1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * MediaTek Pulse Width Modulator driver
4 *
5 * Copyright (C) 2015 John Crispin <blogic@openwrt.org>
6 * Copyright (C) 2017 Zhi Mao <zhi.mao@mediatek.com>
7 *
8 */
9
10 #include <linux/err.h>
11 #include <linux/io.h>
12 #include <linux/ioport.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/clk.h>
16 #include <linux/of.h>
17 #include <linux/platform_device.h>
18 #include <linux/pwm.h>
19 #include <linux/slab.h>
20 #include <linux/types.h>
21
22 /* PWM registers and bits definitions */
23 #define PWMCON 0x00
24 #define PWMHDUR 0x04
25 #define PWMLDUR 0x08
26 #define PWMGDUR 0x0c
27 #define PWMWAVENUM 0x28
28 #define PWMDWIDTH 0x2c
29 #define PWM45DWIDTH_FIXUP 0x30
30 #define PWMTHRES 0x30
31 #define PWM45THRES_FIXUP 0x34
32 #define PWM_CK_26M_SEL 0x210
33
34 #define PWM_CLK_DIV_MAX 7
35
36 struct pwm_mediatek_of_data {
37 unsigned int num_pwms;
38 bool pwm45_fixup;
39 bool has_ck_26m_sel;
40 const unsigned int *reg_offset;
41 };
42
43 /**
44 * struct pwm_mediatek_chip - struct representing PWM chip
45 * @chip: linux PWM chip representation
46 * @regs: base address of PWM chip
47 * @clk_top: the top clock generator
48 * @clk_main: the clock used by PWM core
49 * @clk_pwms: the clock used by each PWM channel
50 * @clk_freq: the fix clock frequency of legacy MIPS SoC
51 * @soc: pointer to chip's platform data
52 */
53 struct pwm_mediatek_chip {
54 struct pwm_chip chip;
55 void __iomem *regs;
56 struct clk *clk_top;
57 struct clk *clk_main;
58 struct clk **clk_pwms;
59 const struct pwm_mediatek_of_data *soc;
60 };
61
62 static const unsigned int mtk_pwm_reg_offset_v1[] = {
63 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
64 };
65
66 static const unsigned int mtk_pwm_reg_offset_v2[] = {
67 0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240
68 };
69
70 static inline struct pwm_mediatek_chip *
to_pwm_mediatek_chip(struct pwm_chip * chip)71 to_pwm_mediatek_chip(struct pwm_chip *chip)
72 {
73 return container_of(chip, struct pwm_mediatek_chip, chip);
74 }
75
pwm_mediatek_clk_enable(struct pwm_chip * chip,struct pwm_device * pwm)76 static int pwm_mediatek_clk_enable(struct pwm_chip *chip,
77 struct pwm_device *pwm)
78 {
79 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
80 int ret;
81
82 ret = clk_prepare_enable(pc->clk_top);
83 if (ret < 0)
84 return ret;
85
86 ret = clk_prepare_enable(pc->clk_main);
87 if (ret < 0)
88 goto disable_clk_top;
89
90 ret = clk_prepare_enable(pc->clk_pwms[pwm->hwpwm]);
91 if (ret < 0)
92 goto disable_clk_main;
93
94 return 0;
95
96 disable_clk_main:
97 clk_disable_unprepare(pc->clk_main);
98 disable_clk_top:
99 clk_disable_unprepare(pc->clk_top);
100
101 return ret;
102 }
103
pwm_mediatek_clk_disable(struct pwm_chip * chip,struct pwm_device * pwm)104 static void pwm_mediatek_clk_disable(struct pwm_chip *chip,
105 struct pwm_device *pwm)
106 {
107 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
108
109 clk_disable_unprepare(pc->clk_pwms[pwm->hwpwm]);
110 clk_disable_unprepare(pc->clk_main);
111 clk_disable_unprepare(pc->clk_top);
112 }
113
pwm_mediatek_writel(struct pwm_mediatek_chip * chip,unsigned int num,unsigned int offset,u32 value)114 static inline void pwm_mediatek_writel(struct pwm_mediatek_chip *chip,
115 unsigned int num, unsigned int offset,
116 u32 value)
117 {
118 writel(value, chip->regs + chip->soc->reg_offset[num] + offset);
119 }
120
pwm_mediatek_config(struct pwm_chip * chip,struct pwm_device * pwm,int duty_ns,int period_ns)121 static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
122 int duty_ns, int period_ns)
123 {
124 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
125 u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH,
126 reg_thres = PWMTHRES;
127 unsigned long clk_rate;
128 u64 resolution;
129 int ret;
130
131 ret = pwm_mediatek_clk_enable(chip, pwm);
132 if (ret < 0)
133 return ret;
134
135 clk_rate = clk_get_rate(pc->clk_pwms[pwm->hwpwm]);
136 if (!clk_rate) {
137 ret = -EINVAL;
138 goto out;
139 }
140
141 /* Make sure we use the bus clock and not the 26MHz clock */
142 if (pc->soc->has_ck_26m_sel)
143 writel(0, pc->regs + PWM_CK_26M_SEL);
144
145 /* Using resolution in picosecond gets accuracy higher */
146 resolution = (u64)NSEC_PER_SEC * 1000;
147 do_div(resolution, clk_rate);
148
149 cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution);
150 while (cnt_period > 8191) {
151 resolution *= 2;
152 clkdiv++;
153 cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000,
154 resolution);
155 }
156
157 if (clkdiv > PWM_CLK_DIV_MAX) {
158 dev_err(chip->dev, "period of %d ns not supported\n", period_ns);
159 ret = -EINVAL;
160 goto out;
161 }
162
163 if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) {
164 /*
165 * PWM[4,5] has distinct offset for PWMDWIDTH and PWMTHRES
166 * from the other PWMs on MT7623.
167 */
168 reg_width = PWM45DWIDTH_FIXUP;
169 reg_thres = PWM45THRES_FIXUP;
170 }
171
172 cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution);
173 pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);
174 pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period);
175 pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty);
176
177 out:
178 pwm_mediatek_clk_disable(chip, pwm);
179
180 return ret;
181 }
182
pwm_mediatek_enable(struct pwm_chip * chip,struct pwm_device * pwm)183 static int pwm_mediatek_enable(struct pwm_chip *chip, struct pwm_device *pwm)
184 {
185 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
186 u32 value;
187 int ret;
188
189 ret = pwm_mediatek_clk_enable(chip, pwm);
190 if (ret < 0)
191 return ret;
192
193 value = readl(pc->regs);
194 value |= BIT(pwm->hwpwm);
195 writel(value, pc->regs);
196
197 return 0;
198 }
199
pwm_mediatek_disable(struct pwm_chip * chip,struct pwm_device * pwm)200 static void pwm_mediatek_disable(struct pwm_chip *chip, struct pwm_device *pwm)
201 {
202 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
203 u32 value;
204
205 value = readl(pc->regs);
206 value &= ~BIT(pwm->hwpwm);
207 writel(value, pc->regs);
208
209 pwm_mediatek_clk_disable(chip, pwm);
210 }
211
pwm_mediatek_apply(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)212 static int pwm_mediatek_apply(struct pwm_chip *chip, struct pwm_device *pwm,
213 const struct pwm_state *state)
214 {
215 int err;
216
217 if (state->polarity != PWM_POLARITY_NORMAL)
218 return -EINVAL;
219
220 if (!state->enabled) {
221 if (pwm->state.enabled)
222 pwm_mediatek_disable(chip, pwm);
223
224 return 0;
225 }
226
227 err = pwm_mediatek_config(pwm->chip, pwm, state->duty_cycle, state->period);
228 if (err)
229 return err;
230
231 if (!pwm->state.enabled)
232 err = pwm_mediatek_enable(chip, pwm);
233
234 return err;
235 }
236
237 static const struct pwm_ops pwm_mediatek_ops = {
238 .apply = pwm_mediatek_apply,
239 .owner = THIS_MODULE,
240 };
241
pwm_mediatek_probe(struct platform_device * pdev)242 static int pwm_mediatek_probe(struct platform_device *pdev)
243 {
244 struct pwm_mediatek_chip *pc;
245 unsigned int i;
246 int ret;
247
248 pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
249 if (!pc)
250 return -ENOMEM;
251
252 pc->soc = of_device_get_match_data(&pdev->dev);
253
254 pc->regs = devm_platform_ioremap_resource(pdev, 0);
255 if (IS_ERR(pc->regs))
256 return PTR_ERR(pc->regs);
257
258 pc->clk_pwms = devm_kmalloc_array(&pdev->dev, pc->soc->num_pwms,
259 sizeof(*pc->clk_pwms), GFP_KERNEL);
260 if (!pc->clk_pwms)
261 return -ENOMEM;
262
263 pc->clk_top = devm_clk_get(&pdev->dev, "top");
264 if (IS_ERR(pc->clk_top))
265 return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_top),
266 "Failed to get top clock\n");
267
268 pc->clk_main = devm_clk_get(&pdev->dev, "main");
269 if (IS_ERR(pc->clk_main))
270 return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_main),
271 "Failed to get main clock\n");
272
273 for (i = 0; i < pc->soc->num_pwms; i++) {
274 char name[8];
275
276 snprintf(name, sizeof(name), "pwm%d", i + 1);
277
278 pc->clk_pwms[i] = devm_clk_get(&pdev->dev, name);
279 if (IS_ERR(pc->clk_pwms[i]))
280 return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_pwms[i]),
281 "Failed to get %s clock\n", name);
282 }
283
284 pc->chip.dev = &pdev->dev;
285 pc->chip.ops = &pwm_mediatek_ops;
286 pc->chip.npwm = pc->soc->num_pwms;
287
288 ret = devm_pwmchip_add(&pdev->dev, &pc->chip);
289 if (ret < 0)
290 return dev_err_probe(&pdev->dev, ret, "pwmchip_add() failed\n");
291
292 return 0;
293 }
294
295 static const struct pwm_mediatek_of_data mt2712_pwm_data = {
296 .num_pwms = 8,
297 .pwm45_fixup = false,
298 .has_ck_26m_sel = false,
299 .reg_offset = mtk_pwm_reg_offset_v1,
300 };
301
302 static const struct pwm_mediatek_of_data mt6795_pwm_data = {
303 .num_pwms = 7,
304 .pwm45_fixup = false,
305 .has_ck_26m_sel = false,
306 .reg_offset = mtk_pwm_reg_offset_v1,
307 };
308
309 static const struct pwm_mediatek_of_data mt7622_pwm_data = {
310 .num_pwms = 6,
311 .pwm45_fixup = false,
312 .has_ck_26m_sel = true,
313 .reg_offset = mtk_pwm_reg_offset_v1,
314 };
315
316 static const struct pwm_mediatek_of_data mt7623_pwm_data = {
317 .num_pwms = 5,
318 .pwm45_fixup = true,
319 .has_ck_26m_sel = false,
320 .reg_offset = mtk_pwm_reg_offset_v1,
321 };
322
323 static const struct pwm_mediatek_of_data mt7628_pwm_data = {
324 .num_pwms = 4,
325 .pwm45_fixup = true,
326 .has_ck_26m_sel = false,
327 .reg_offset = mtk_pwm_reg_offset_v1,
328 };
329
330 static const struct pwm_mediatek_of_data mt7629_pwm_data = {
331 .num_pwms = 1,
332 .pwm45_fixup = false,
333 .has_ck_26m_sel = false,
334 .reg_offset = mtk_pwm_reg_offset_v1,
335 };
336
337 static const struct pwm_mediatek_of_data mt7981_pwm_data = {
338 .num_pwms = 3,
339 .pwm45_fixup = false,
340 .has_ck_26m_sel = true,
341 .reg_offset = mtk_pwm_reg_offset_v2,
342 };
343
344 static const struct pwm_mediatek_of_data mt7986_pwm_data = {
345 .num_pwms = 2,
346 .pwm45_fixup = false,
347 .has_ck_26m_sel = true,
348 .reg_offset = mtk_pwm_reg_offset_v1,
349 };
350
351 static const struct pwm_mediatek_of_data mt8183_pwm_data = {
352 .num_pwms = 4,
353 .pwm45_fixup = false,
354 .has_ck_26m_sel = true,
355 .reg_offset = mtk_pwm_reg_offset_v1,
356 };
357
358 static const struct pwm_mediatek_of_data mt8365_pwm_data = {
359 .num_pwms = 3,
360 .pwm45_fixup = false,
361 .has_ck_26m_sel = true,
362 .reg_offset = mtk_pwm_reg_offset_v1,
363 };
364
365 static const struct pwm_mediatek_of_data mt8516_pwm_data = {
366 .num_pwms = 5,
367 .pwm45_fixup = false,
368 .has_ck_26m_sel = true,
369 .reg_offset = mtk_pwm_reg_offset_v1,
370 };
371
372 static const struct of_device_id pwm_mediatek_of_match[] = {
373 { .compatible = "mediatek,mt2712-pwm", .data = &mt2712_pwm_data },
374 { .compatible = "mediatek,mt6795-pwm", .data = &mt6795_pwm_data },
375 { .compatible = "mediatek,mt7622-pwm", .data = &mt7622_pwm_data },
376 { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
377 { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data },
378 { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
379 { .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data },
380 { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data },
381 { .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data },
382 { .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data },
383 { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data },
384 { },
385 };
386 MODULE_DEVICE_TABLE(of, pwm_mediatek_of_match);
387
388 static struct platform_driver pwm_mediatek_driver = {
389 .driver = {
390 .name = "pwm-mediatek",
391 .of_match_table = pwm_mediatek_of_match,
392 },
393 .probe = pwm_mediatek_probe,
394 };
395 module_platform_driver(pwm_mediatek_driver);
396
397 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
398 MODULE_LICENSE("GPL v2");
399