1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include "amdgpu.h"
24 #include "amdgpu_psp.h"
25 #include "amdgpu_ucode.h"
26 #include "soc15_common.h"
27 #include "psp_v11_0_8.h"
28
29 #include "mp/mp_11_0_8_offset.h"
30
psp_v11_0_8_ring_stop(struct psp_context * psp,enum psp_ring_type ring_type)31 static int psp_v11_0_8_ring_stop(struct psp_context *psp,
32 enum psp_ring_type ring_type)
33 {
34 int ret = 0;
35 struct amdgpu_device *adev = psp->adev;
36
37 if (amdgpu_sriov_vf(adev)) {
38 /* Write the ring destroy command*/
39 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
40 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
41 /* there might be handshake issue with hardware which needs delay */
42 mdelay(20);
43 /* Wait for response flag (bit 31) */
44 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
45 0x80000000, 0x80000000, false);
46 } else {
47 /* Write the ring destroy command*/
48 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
49 GFX_CTRL_CMD_ID_DESTROY_RINGS);
50 /* there might be handshake issue with hardware which needs delay */
51 mdelay(20);
52 /* Wait for response flag (bit 31) */
53 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
54 0x80000000, 0x80000000, false);
55 }
56
57 return ret;
58 }
59
psp_v11_0_8_ring_create(struct psp_context * psp,enum psp_ring_type ring_type)60 static int psp_v11_0_8_ring_create(struct psp_context *psp,
61 enum psp_ring_type ring_type)
62 {
63 int ret = 0;
64 unsigned int psp_ring_reg = 0;
65 struct psp_ring *ring = &psp->km_ring;
66 struct amdgpu_device *adev = psp->adev;
67
68 if (amdgpu_sriov_vf(adev)) {
69 ret = psp_v11_0_8_ring_stop(psp, ring_type);
70 if (ret) {
71 DRM_ERROR("psp_v11_0_8_ring_stop_sriov failed!\n");
72 return ret;
73 }
74
75 /* Write low address of the ring to C2PMSG_102 */
76 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
77 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
78 /* Write high address of the ring to C2PMSG_103 */
79 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
80 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
81
82 /* Write the ring initialization command to C2PMSG_101 */
83 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
84 GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
85
86 /* there might be handshake issue with hardware which needs delay */
87 mdelay(20);
88
89 /* Wait for response flag (bit 31) in C2PMSG_101 */
90 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
91 0x80000000, 0x8000FFFF, false);
92
93 } else {
94 /* Wait for sOS ready for ring creation */
95 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
96 0x80000000, 0x80000000, false);
97 if (ret) {
98 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
99 return ret;
100 }
101
102 /* Write low address of the ring to C2PMSG_69 */
103 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
104 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
105 /* Write high address of the ring to C2PMSG_70 */
106 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
107 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
108 /* Write size of ring to C2PMSG_71 */
109 psp_ring_reg = ring->ring_size;
110 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
111 /* Write the ring initialization command to C2PMSG_64 */
112 psp_ring_reg = ring_type;
113 psp_ring_reg = psp_ring_reg << 16;
114 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
115
116 /* there might be handshake issue with hardware which needs delay */
117 mdelay(20);
118
119 /* Wait for response flag (bit 31) in C2PMSG_64 */
120 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
121 0x80000000, 0x8000FFFF, false);
122 }
123
124 return ret;
125 }
126
psp_v11_0_8_ring_destroy(struct psp_context * psp,enum psp_ring_type ring_type)127 static int psp_v11_0_8_ring_destroy(struct psp_context *psp,
128 enum psp_ring_type ring_type)
129 {
130 int ret = 0;
131 struct psp_ring *ring = &psp->km_ring;
132 struct amdgpu_device *adev = psp->adev;
133
134 ret = psp_v11_0_8_ring_stop(psp, ring_type);
135 if (ret)
136 DRM_ERROR("Fail to stop psp ring\n");
137
138 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
139 &ring->ring_mem_mc_addr,
140 (void **)&ring->ring_mem);
141
142 return ret;
143 }
144
psp_v11_0_8_ring_get_wptr(struct psp_context * psp)145 static uint32_t psp_v11_0_8_ring_get_wptr(struct psp_context *psp)
146 {
147 uint32_t data;
148 struct amdgpu_device *adev = psp->adev;
149
150 if (amdgpu_sriov_vf(adev))
151 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
152 else
153 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
154
155 return data;
156 }
157
psp_v11_0_8_ring_set_wptr(struct psp_context * psp,uint32_t value)158 static void psp_v11_0_8_ring_set_wptr(struct psp_context *psp, uint32_t value)
159 {
160 struct amdgpu_device *adev = psp->adev;
161
162 if (amdgpu_sriov_vf(adev)) {
163 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
164 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
165 GFX_CTRL_CMD_ID_CONSUME_CMD);
166 } else
167 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
168 }
169
170 static const struct psp_funcs psp_v11_0_8_funcs = {
171 .ring_create = psp_v11_0_8_ring_create,
172 .ring_stop = psp_v11_0_8_ring_stop,
173 .ring_destroy = psp_v11_0_8_ring_destroy,
174 .ring_get_wptr = psp_v11_0_8_ring_get_wptr,
175 .ring_set_wptr = psp_v11_0_8_ring_set_wptr,
176 };
177
psp_v11_0_8_set_psp_funcs(struct psp_context * psp)178 void psp_v11_0_8_set_psp_funcs(struct psp_context *psp)
179 {
180 psp->funcs = &psp_v11_0_8_funcs;
181 }
182