1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Author: Huang Rui
23 *
24 */
25
26 #include <linux/firmware.h>
27 #include <linux/module.h>
28 #include <linux/pci.h>
29
30 #include "amdgpu.h"
31 #include "amdgpu_psp.h"
32 #include "amdgpu_ucode.h"
33 #include "soc15_common.h"
34 #include "psp_v10_0.h"
35
36 #include "mp/mp_10_0_offset.h"
37 #include "gc/gc_9_1_offset.h"
38 #include "sdma0/sdma0_4_1_offset.h"
39
40 MODULE_FIRMWARE("amdgpu/raven_asd.bin");
41 MODULE_FIRMWARE("amdgpu/picasso_asd.bin");
42 MODULE_FIRMWARE("amdgpu/raven2_asd.bin");
43 MODULE_FIRMWARE("amdgpu/picasso_ta.bin");
44 MODULE_FIRMWARE("amdgpu/raven2_ta.bin");
45 MODULE_FIRMWARE("amdgpu/raven_ta.bin");
46
psp_v10_0_init_microcode(struct psp_context * psp)47 static int psp_v10_0_init_microcode(struct psp_context *psp)
48 {
49 struct amdgpu_device *adev = psp->adev;
50 char ucode_prefix[30];
51 int err = 0;
52 DRM_DEBUG("\n");
53
54 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
55
56 err = psp_init_asd_microcode(psp, ucode_prefix);
57 if (err)
58 return err;
59
60 err = psp_init_ta_microcode(psp, ucode_prefix);
61 if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 1, 0)) &&
62 (adev->pdev->revision == 0xa1) &&
63 (psp->securedisplay_context.context.bin_desc.fw_version >= 0x27000008)) {
64 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 0;
65 }
66 return err;
67 }
68
psp_v10_0_ring_create(struct psp_context * psp,enum psp_ring_type ring_type)69 static int psp_v10_0_ring_create(struct psp_context *psp,
70 enum psp_ring_type ring_type)
71 {
72 int ret = 0;
73 unsigned int psp_ring_reg = 0;
74 struct psp_ring *ring = &psp->km_ring;
75 struct amdgpu_device *adev = psp->adev;
76
77 /* Write low address of the ring to C2PMSG_69 */
78 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
79 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
80 /* Write high address of the ring to C2PMSG_70 */
81 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
82 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
83 /* Write size of ring to C2PMSG_71 */
84 psp_ring_reg = ring->ring_size;
85 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
86 /* Write the ring initialization command to C2PMSG_64 */
87 psp_ring_reg = ring_type;
88 psp_ring_reg = psp_ring_reg << 16;
89 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
90
91 /* There might be handshake issue with hardware which needs delay */
92 mdelay(20);
93
94 /* Wait for response flag (bit 31) in C2PMSG_64 */
95 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
96 0x80000000, 0x8000FFFF, false);
97
98 return ret;
99 }
100
psp_v10_0_ring_stop(struct psp_context * psp,enum psp_ring_type ring_type)101 static int psp_v10_0_ring_stop(struct psp_context *psp,
102 enum psp_ring_type ring_type)
103 {
104 int ret = 0;
105 unsigned int psp_ring_reg = 0;
106 struct amdgpu_device *adev = psp->adev;
107
108 /* Write the ring destroy command to C2PMSG_64 */
109 psp_ring_reg = 3 << 16;
110 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
111
112 /* There might be handshake issue with hardware which needs delay */
113 mdelay(20);
114
115 /* Wait for response flag (bit 31) in C2PMSG_64 */
116 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
117 0x80000000, 0x80000000, false);
118
119 return ret;
120 }
121
psp_v10_0_ring_destroy(struct psp_context * psp,enum psp_ring_type ring_type)122 static int psp_v10_0_ring_destroy(struct psp_context *psp,
123 enum psp_ring_type ring_type)
124 {
125 int ret = 0;
126 struct psp_ring *ring = &psp->km_ring;
127 struct amdgpu_device *adev = psp->adev;
128
129 ret = psp_v10_0_ring_stop(psp, ring_type);
130 if (ret)
131 DRM_ERROR("Fail to stop psp ring\n");
132
133 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
134 &ring->ring_mem_mc_addr,
135 (void **)&ring->ring_mem);
136
137 return ret;
138 }
139
psp_v10_0_mode1_reset(struct psp_context * psp)140 static int psp_v10_0_mode1_reset(struct psp_context *psp)
141 {
142 DRM_INFO("psp mode 1 reset not supported now! \n");
143 return -EINVAL;
144 }
145
psp_v10_0_ring_get_wptr(struct psp_context * psp)146 static uint32_t psp_v10_0_ring_get_wptr(struct psp_context *psp)
147 {
148 struct amdgpu_device *adev = psp->adev;
149
150 return RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
151 }
152
psp_v10_0_ring_set_wptr(struct psp_context * psp,uint32_t value)153 static void psp_v10_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
154 {
155 struct amdgpu_device *adev = psp->adev;
156
157 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
158 }
159
160 static const struct psp_funcs psp_v10_0_funcs = {
161 .init_microcode = psp_v10_0_init_microcode,
162 .ring_create = psp_v10_0_ring_create,
163 .ring_stop = psp_v10_0_ring_stop,
164 .ring_destroy = psp_v10_0_ring_destroy,
165 .mode1_reset = psp_v10_0_mode1_reset,
166 .ring_get_wptr = psp_v10_0_ring_get_wptr,
167 .ring_set_wptr = psp_v10_0_ring_set_wptr,
168 };
169
psp_v10_0_set_psp_funcs(struct psp_context * psp)170 void psp_v10_0_set_psp_funcs(struct psp_context *psp)
171 {
172 psp->funcs = &psp_v10_0_funcs;
173 }
174