1#!/bin/sh
2
3#
4# helper function to convert from DOS to Unix, if necessary, and handle
5# lines ending in '\'.
6#
7fix_newlines_in_macros() {
8	sed -n ':next;s/\r$//;/[^\\]\\$/ {N;s/\\\n//;b next};p' $1
9}
10
11#
12# Process iocsr_config_*.[ch]
13# $1:	SoC type
14# $2:	Input handoff directory
15# $3:	Input BSP Generated directory
16# $4:	Output directory
17#
18process_iocsr_config() {
19	soc="$1"
20	in_qts_dir="$2"
21	in_bsp_dir="$3"
22	out_dir="$4"
23
24	(
25	cat << EOF
26/* SPDX-License-Identifier: BSD-3-Clause */
27/*
28 * Altera SoCFPGA IOCSR configuration
29 */
30
31#ifndef __SOCFPGA_IOCSR_CONFIG_H__
32#define __SOCFPGA_IOCSR_CONFIG_H__
33
34EOF
35
36	# Retrieve the scan chain lengths
37	fix_newlines_in_macros \
38		${in_bsp_dir}/generated/iocsr_config_${soc}.h |
39	grep 'CONFIG_HPS_IOCSR_SCANCHAIN[0-9]\+_LENGTH'	| tr -d "()"
40
41	echo ""
42
43	# Retrieve the scan chain config and zap the ad-hoc length encoding
44	fix_newlines_in_macros \
45		${in_bsp_dir}/generated/iocsr_config_${soc}.c |
46	sed -n '/^const/ !b; :next {/^const/ s/(.*)//;p;n;b next}'
47
48	cat << EOF
49
50#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
51EOF
52	) > "${out_dir}/iocsr_config.h"
53}
54
55#
56# Process pinmux_config_*.c (and ignore pinmux_config.h)
57# $1:	SoC type
58# $2:	Input directory
59# $3:	Output directory
60#
61process_pinmux_config() {
62	soc="$1"
63	in_qts_dir="$2"
64	in_bsp_dir="$3"
65	out_dir="$4"
66
67	(
68	cat << EOF
69/* SPDX-License-Identifier: BSD-3-Clause */
70/*
71 * Altera SoCFPGA PinMux configuration
72 */
73
74#ifndef __SOCFPGA_PINMUX_CONFIG_H__
75#define __SOCFPGA_PINMUX_CONFIG_H__
76
77EOF
78
79	# Retrieve the pinmux config and zap the ad-hoc length encoding
80	fix_newlines_in_macros \
81		${in_bsp_dir}/generated/pinmux_config_${soc}.c |
82	sed -n '/^unsigned/ !b; :next {/^unsigned/ {s/\[.*\]/[]/;s/unsigned long/const u8/};p;n;b next}'
83
84	cat << EOF
85
86#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
87EOF
88	) > "${out_dir}/pinmux_config.h"
89}
90
91#
92# Process pll_config.h
93# $1:	SoC type (not used)
94# $2:	Input directory
95# $3:	Output directory
96#
97process_pll_config() {
98	soc="$1"
99	in_qts_dir="$2"
100	in_bsp_dir="$3"
101	out_dir="$4"
102
103	(
104	cat << EOF
105/* SPDX-License-Identifier: BSD-3-Clause */
106/*
107 * Altera SoCFPGA Clock and PLL configuration
108 */
109
110#ifndef __SOCFPGA_PLL_CONFIG_H__
111#define __SOCFPGA_PLL_CONFIG_H__
112
113EOF
114
115	# Retrieve the pll config and zap parenthesis
116	fix_newlines_in_macros \
117		${in_bsp_dir}/generated/pll_config.h |
118	sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}'
119
120	cat << EOF
121
122#endif /* __SOCFPGA_PLL_CONFIG_H__ */
123EOF
124	) > "${out_dir}/pll_config.h"
125}
126
127#
128# Filter out only the macros which are actually used by the code
129#
130grep_sdram_config() {
131	egrep "#define (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN|CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA|CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP|CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR|CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN|CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC|CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46|CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4|CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64|RW_MGR_ACTIVATE_0_AND_1|RW_MGR_ACTIVATE_0_AND_1_WAIT1|RW_MGR_ACTIVATE_0_AND_1_WAIT2|RW_MGR_ACTIVATE_1|RW_MGR_CLEAR_DQS_ENABLE|RW_MGR_GUARANTEED_READ|RW_MGR_GUARANTEED_READ_CONT|RW_MGR_GUARANTEED_WRITE|RW_MGR_GUARANTEED_WRITE_WAIT0|RW_MGR_GUARANTEED_WRITE_WAIT1|RW_MGR_GUARANTEED_WRITE_WAIT2|RW_MGR_GUARANTEED_WRITE_WAIT3|RW_MGR_IDLE|RW_MGR_IDLE_LOOP1|RW_MGR_IDLE_LOOP2|RW_MGR_INIT_RESET_0_CKE_0|RW_MGR_INIT_RESET_1_CKE_0|RW_MGR_LFSR_WR_RD_BANK_0|RW_MGR_LFSR_WR_RD_BANK_0_DATA|RW_MGR_LFSR_WR_RD_BANK_0_DQS|RW_MGR_LFSR_WR_RD_BANK_0_NOP|RW_MGR_LFSR_WR_RD_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_BANK_0_WL_1|RW_MGR_LFSR_WR_RD_DM_BANK_0|RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA|RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS|RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP|RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1|RW_MGR_MRS0_DLL_RESET|RW_MGR_MRS0_DLL_RESET_MIRR|RW_MGR_MRS0_USER|RW_MGR_MRS0_USER_MIRR|RW_MGR_MRS1|RW_MGR_MRS1_MIRR|RW_MGR_MRS2|RW_MGR_MRS2_MIRR|RW_MGR_MRS3|RW_MGR_MRS3_MIRR|RW_MGR_PRECHARGE_ALL|RW_MGR_READ_B2B|RW_MGR_READ_B2B_WAIT1|RW_MGR_READ_B2B_WAIT2|RW_MGR_REFRESH_ALL|RW_MGR_RETURN|RW_MGR_SGLE_READ|RW_MGR_ZQCL|RW_MGR_TRUE_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_ADDRESS_MIRRORING|RW_MGR_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_DATA_WIDTH|RW_MGR_MEM_DQ_PER_READ_DQS|RW_MGR_MEM_DQ_PER_WRITE_DQS|RW_MGR_MEM_IF_READ_DQS_WIDTH|RW_MGR_MEM_IF_WRITE_DQS_WIDTH|RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM|RW_MGR_MEM_NUMBER_OF_RANKS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS|IO_DELAY_PER_DCHAIN_TAP|IO_DELAY_PER_DQS_EN_DCHAIN_TAP|IO_DELAY_PER_OPA_TAP|IO_DLL_CHAIN_LENGTH|IO_DQDQS_OUT_PHASE_MAX|IO_DQS_EN_DELAY_MAX|IO_DQS_EN_DELAY_OFFSET|IO_DQS_EN_PHASE_MAX|IO_DQS_IN_DELAY_MAX|IO_DQS_IN_RESERVE|IO_DQS_OUT_RESERVE|IO_IO_IN_DELAY_MAX|IO_IO_OUT1_DELAY_MAX|IO_IO_OUT2_DELAY_MAX|IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS|AFI_RATE_RATIO|CALIB_LFIFO_OFFSET|CALIB_VFIFO_OFFSET|ENABLE_SUPER_QUICK_CALIBRATION|MAX_LATENCY_COUNT_WIDTH|READ_VALID_FIFO_SIZE|REG_FILE_INIT_SEQ_SIGNATURE|TINIT_CNTR0_VAL|TINIT_CNTR1_VAL|TINIT_CNTR2_VAL|TRESET_CNTR0_VAL|TRESET_CNTR1_VAL|TRESET_CNTR2_VAL|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP)[[:space:]]"
132}
133
134#
135# Process sdram_config.h, sequencer_auto*h and sequencer_defines.h
136# $1:	SoC type (not used)
137# $2:	Input directory
138# $3:	Output directory
139#
140process_sdram_config() {
141	soc="$1"
142	in_qts_dir="$2"
143	in_bsp_dir="$3"
144	out_dir="$4"
145
146	(
147	cat << EOF
148/* SPDX-License-Identifier: BSD-3-Clause */
149/*
150 * Altera SoCFPGA SDRAM configuration
151 *
152 */
153
154#ifndef __SOCFPGA_SDRAM_CONFIG_H__
155#define __SOCFPGA_SDRAM_CONFIG_H__
156
157EOF
158
159	echo "/* SDRAM configuration */"
160	# Retrieve the sdram config, zap broken lines and zap parenthesis
161	fix_newlines_in_macros \
162		${in_bsp_dir}/generated/sdram/sdram_config.h |
163	sed -n "/\\\\$/ {N;s/ \\\\\n/\t/};p" |
164	sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}' |
165		sort -u | grep_sdram_config
166
167	echo ""
168	echo "/* Sequencer auto configuration */"
169	fix_newlines_in_macros \
170		${in_qts_dir}/hps_isw_handoff/*/sequencer_auto.h |
171	sed -n "/__RW_MGR/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" |
172		sort -u | grep_sdram_config
173
174	echo ""
175	echo "/* Sequencer defines configuration */"
176	fix_newlines_in_macros \
177		${in_qts_dir}/hps_isw_handoff/*/sequencer_defines.h |
178	sed -n "/^#define [^_]/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" |
179		sort -u | grep_sdram_config
180
181	echo ""
182	echo "/* Sequencer ac_rom_init configuration */"
183	fix_newlines_in_macros \
184		${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_ac_init.c |
185	sed -n '/^const.*\[/ !b; :next {/^const.*\[/ {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'
186
187	echo ""
188	echo "/* Sequencer inst_rom_init configuration */"
189	fix_newlines_in_macros \
190		${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_inst_init.c |
191	sed -n '/^const.*\[/ !b; :next {/^const.*\[/ {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'
192
193	cat << EOF
194
195#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
196EOF
197	) > "${out_dir}/sdram_config.h"
198}
199
200usage() {
201	echo "$0 [soc_type] [input_qts_dir] [input_bsp_dir] [output_dir]"
202	echo "Process QTS-generated headers into U-Boot compatible ones."
203	echo ""
204	echo "  soc_type      - Type of SoC, either 'cyclone5' or 'arria5'."
205	echo "  input_qts_dir - Directory with compiled Quartus project"
206	echo "                  and containing the Quartus project file (QPF)."
207	echo "  input_bsp_dir - Directory with generated bsp containing"
208	echo "                  the settings.bsp file."
209	echo "  output_dir    - Directory to store the U-Boot compatible"
210	echo "                  headers."
211	echo ""
212}
213
214soc="$1"
215in_qts_dir="$2"
216in_bsp_dir="$3"
217out_dir="$4"
218
219if [ "$#" -ne 4 ] ; then
220	usage
221	exit 1
222fi
223
224if [ ! -d "${in_qts_dir}" -o ! -d "${in_bsp_dir}" -o \
225	! -d "${out_dir}" -o -z "${soc}" ] ; then
226	usage
227	exit 3
228fi
229
230process_iocsr_config  "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}"
231process_pinmux_config "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}"
232process_pll_config    "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}"
233process_sdram_config  "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}"
234