1 /* 2 * ARM Versatile Express emulation. 3 * 4 * Copyright (c) 2010 - 2011 B Labs Ltd. 5 * Copyright (c) 2011 Linaro Limited 6 * Written by Bahadir Balban, Amit Mahajan, Peter Maydell 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 * 20 * Contributions after 2012-01-13 are licensed under the terms of the 21 * GNU GPL, version 2 or (at your option) any later version. 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "qemu/datadir.h" 27 #include "hw/sysbus.h" 28 #include "hw/arm/boot.h" 29 #include "hw/arm/primecell.h" 30 #include "hw/arm/machines-qom.h" 31 #include "hw/net/lan9118.h" 32 #include "hw/i2c/i2c.h" 33 #include "net/net.h" 34 #include "system/system.h" 35 #include "hw/boards.h" 36 #include "hw/loader.h" 37 #include "hw/block/flash.h" 38 #include "system/device_tree.h" 39 #include "qemu/error-report.h" 40 #include <libfdt.h> 41 #include "hw/char/pl011.h" 42 #include "hw/cpu/a9mpcore.h" 43 #include "hw/cpu/a15mpcore.h" 44 #include "hw/i2c/arm_sbcon_i2c.h" 45 #include "hw/sd/sd.h" 46 #include "qobject/qlist.h" 47 #include "qom/object.h" 48 #include "qemu/audio.h" 49 #include "target/arm/cpu-qom.h" 50 51 #define VEXPRESS_BOARD_ID 0x8e0 52 #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024) 53 #define VEXPRESS_FLASH_SECT_SIZE (256 * 1024) 54 55 #define GIC_EXT_IRQS 64 /* Versatile Express A9 development board */ 56 57 /* Number of virtio transports to create (0..8; limited by 58 * number of available IRQ lines). 59 */ 60 #define NUM_VIRTIO_TRANSPORTS 4 61 62 /* Address maps for peripherals: 63 * the Versatile Express motherboard has two possible maps, 64 * the "legacy" one (used for A9) and the "Cortex-A Series" 65 * map (used for newer cores). 66 * Individual daughterboards can also have different maps for 67 * their peripherals. 68 */ 69 70 enum { 71 VE_SYSREGS, 72 VE_SP810, 73 VE_SERIALPCI, 74 VE_PL041, 75 VE_MMCI, 76 VE_KMI0, 77 VE_KMI1, 78 VE_UART0, 79 VE_UART1, 80 VE_UART2, 81 VE_UART3, 82 VE_WDT, 83 VE_TIMER01, 84 VE_TIMER23, 85 VE_SERIALDVI, 86 VE_RTC, 87 VE_COMPACTFLASH, 88 VE_CLCD, 89 VE_NORFLASH0, 90 VE_NORFLASH1, 91 VE_NORFLASHALIAS, 92 VE_SRAM, 93 VE_VIDEORAM, 94 VE_ETHERNET, 95 VE_USB, 96 VE_DAPROM, 97 VE_VIRTIO, 98 }; 99 100 static hwaddr motherboard_legacy_map[] = { 101 [VE_NORFLASHALIAS] = 0, 102 /* CS7: 0x10000000 .. 0x10020000 */ 103 [VE_SYSREGS] = 0x10000000, 104 [VE_SP810] = 0x10001000, 105 [VE_SERIALPCI] = 0x10002000, 106 [VE_PL041] = 0x10004000, 107 [VE_MMCI] = 0x10005000, 108 [VE_KMI0] = 0x10006000, 109 [VE_KMI1] = 0x10007000, 110 [VE_UART0] = 0x10009000, 111 [VE_UART1] = 0x1000a000, 112 [VE_UART2] = 0x1000b000, 113 [VE_UART3] = 0x1000c000, 114 [VE_WDT] = 0x1000f000, 115 [VE_TIMER01] = 0x10011000, 116 [VE_TIMER23] = 0x10012000, 117 [VE_VIRTIO] = 0x10013000, 118 [VE_SERIALDVI] = 0x10016000, 119 [VE_RTC] = 0x10017000, 120 [VE_COMPACTFLASH] = 0x1001a000, 121 [VE_CLCD] = 0x1001f000, 122 /* CS0: 0x40000000 .. 0x44000000 */ 123 [VE_NORFLASH0] = 0x40000000, 124 /* CS1: 0x44000000 .. 0x48000000 */ 125 [VE_NORFLASH1] = 0x44000000, 126 /* CS2: 0x48000000 .. 0x4a000000 */ 127 [VE_SRAM] = 0x48000000, 128 /* CS3: 0x4c000000 .. 0x50000000 */ 129 [VE_VIDEORAM] = 0x4c000000, 130 [VE_ETHERNET] = 0x4e000000, 131 [VE_USB] = 0x4f000000, 132 }; 133 134 static hwaddr motherboard_aseries_map[] = { 135 [VE_NORFLASHALIAS] = 0, 136 /* CS0: 0x08000000 .. 0x0c000000 */ 137 [VE_NORFLASH0] = 0x08000000, 138 /* CS4: 0x0c000000 .. 0x10000000 */ 139 [VE_NORFLASH1] = 0x0c000000, 140 /* CS5: 0x10000000 .. 0x14000000 */ 141 /* CS1: 0x14000000 .. 0x18000000 */ 142 [VE_SRAM] = 0x14000000, 143 /* CS2: 0x18000000 .. 0x1c000000 */ 144 [VE_VIDEORAM] = 0x18000000, 145 [VE_ETHERNET] = 0x1a000000, 146 [VE_USB] = 0x1b000000, 147 /* CS3: 0x1c000000 .. 0x20000000 */ 148 [VE_DAPROM] = 0x1c000000, 149 [VE_SYSREGS] = 0x1c010000, 150 [VE_SP810] = 0x1c020000, 151 [VE_SERIALPCI] = 0x1c030000, 152 [VE_PL041] = 0x1c040000, 153 [VE_MMCI] = 0x1c050000, 154 [VE_KMI0] = 0x1c060000, 155 [VE_KMI1] = 0x1c070000, 156 [VE_UART0] = 0x1c090000, 157 [VE_UART1] = 0x1c0a0000, 158 [VE_UART2] = 0x1c0b0000, 159 [VE_UART3] = 0x1c0c0000, 160 [VE_WDT] = 0x1c0f0000, 161 [VE_TIMER01] = 0x1c110000, 162 [VE_TIMER23] = 0x1c120000, 163 [VE_VIRTIO] = 0x1c130000, 164 [VE_SERIALDVI] = 0x1c160000, 165 [VE_RTC] = 0x1c170000, 166 [VE_COMPACTFLASH] = 0x1c1a0000, 167 [VE_CLCD] = 0x1c1f0000, 168 }; 169 170 /* Structure defining the peculiarities of a specific daughterboard */ 171 172 typedef struct VEDBoardInfo VEDBoardInfo; 173 174 struct VexpressMachineClass { 175 MachineClass parent; 176 VEDBoardInfo *daughterboard; 177 }; 178 179 struct VexpressMachineState { 180 MachineState parent; 181 MemoryRegion vram; 182 MemoryRegion sram; 183 MemoryRegion flashalias; 184 MemoryRegion a15sram; 185 bool secure; 186 bool virt; 187 }; 188 189 #define TYPE_VEXPRESS_MACHINE "vexpress" 190 #define TYPE_VEXPRESS_A9_MACHINE MACHINE_TYPE_NAME("vexpress-a9") 191 #define TYPE_VEXPRESS_A15_MACHINE MACHINE_TYPE_NAME("vexpress-a15") 192 OBJECT_DECLARE_TYPE(VexpressMachineState, VexpressMachineClass, VEXPRESS_MACHINE) 193 194 typedef void DBoardInitFn(VexpressMachineState *machine, 195 ram_addr_t ram_size, 196 const char *cpu_type, 197 qemu_irq *pic); 198 199 struct VEDBoardInfo { 200 struct arm_boot_info bootinfo; 201 const hwaddr *motherboard_map; 202 hwaddr loader_start; 203 const hwaddr gic_cpu_if_addr; 204 uint32_t proc_id; 205 uint32_t num_voltage_sensors; 206 const uint32_t *voltages; 207 uint32_t num_clocks; 208 const uint32_t *clocks; 209 DBoardInitFn *init; 210 }; 211 212 static void init_cpus(MachineState *ms, const char *cpu_type, 213 const char *privdev, hwaddr periphbase, 214 qemu_irq *pic, bool secure, bool virt) 215 { 216 DeviceState *dev; 217 SysBusDevice *busdev; 218 int n; 219 unsigned int smp_cpus = ms->smp.cpus; 220 221 /* Create the actual CPUs */ 222 for (n = 0; n < smp_cpus; n++) { 223 Object *cpuobj = object_new(cpu_type); 224 225 if (!secure) { 226 object_property_set_bool(cpuobj, "has_el3", false, NULL); 227 } 228 if (!virt) { 229 if (object_property_find(cpuobj, "has_el2")) { 230 object_property_set_bool(cpuobj, "has_el2", false, NULL); 231 } 232 } 233 234 if (object_property_find(cpuobj, "reset-cbar")) { 235 object_property_set_int(cpuobj, "reset-cbar", periphbase, 236 &error_abort); 237 } 238 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 239 } 240 241 /* Create the private peripheral devices (including the GIC); 242 * this must happen after the CPUs are created because a15mpcore_priv 243 * wires itself up to the CPU's generic_timer gpio out lines. 244 */ 245 dev = qdev_new(privdev); 246 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); 247 qdev_prop_set_uint32(dev, "num-irq", GIC_EXT_IRQS + GIC_INTERNAL); 248 busdev = SYS_BUS_DEVICE(dev); 249 sysbus_realize_and_unref(busdev, &error_fatal); 250 sysbus_mmio_map(busdev, 0, periphbase); 251 252 /* Interrupts [42:0] are from the motherboard; 253 * [47:43] are reserved; [63:48] are daughterboard 254 * peripherals. Note that some documentation numbers 255 * external interrupts starting from 32 (because there 256 * are internal interrupts 0..31). 257 */ 258 for (n = 0; n < GIC_EXT_IRQS; n++) { 259 pic[n] = qdev_get_gpio_in(dev, n); 260 } 261 262 /* Connect the CPUs to the GIC */ 263 for (n = 0; n < smp_cpus; n++) { 264 DeviceState *cpudev = DEVICE(qemu_get_cpu(n)); 265 266 sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 267 sysbus_connect_irq(busdev, n + smp_cpus, 268 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 269 sysbus_connect_irq(busdev, n + 2 * smp_cpus, 270 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 271 sysbus_connect_irq(busdev, n + 3 * smp_cpus, 272 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 273 } 274 } 275 276 static void a9_daughterboard_init(VexpressMachineState *vms, 277 ram_addr_t ram_size, 278 const char *cpu_type, 279 qemu_irq *pic) 280 { 281 MachineState *machine = MACHINE(vms); 282 MemoryRegion *sysmem = get_system_memory(); 283 DeviceState *dev; 284 285 if (ram_size > 0x40000000) { 286 /* 1GB is the maximum the address space permits */ 287 error_report("vexpress-a9: cannot model more than 1GB RAM"); 288 exit(1); 289 } 290 291 /* 292 * RAM is from 0x60000000 upwards. The bottom 64MB of the 293 * address space should in theory be remappable to various 294 * things including ROM or RAM; we always map the flash there. 295 */ 296 memory_region_add_subregion(sysmem, 0x60000000, machine->ram); 297 298 /* 0x1e000000 A9MPCore (SCU) private memory region */ 299 init_cpus(machine, cpu_type, TYPE_A9MPCORE_PRIV, 0x1e000000, pic, 300 vms->secure, vms->virt); 301 302 /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */ 303 304 /* 0x10020000 PL111 CLCD (daughterboard) */ 305 dev = qdev_new("pl111"); 306 object_property_set_link(OBJECT(dev), "framebuffer-memory", 307 OBJECT(sysmem), &error_fatal); 308 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 309 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x10020000); 310 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[44]); 311 312 /* 0x10060000 AXI RAM */ 313 /* 0x100e0000 PL341 Dynamic Memory Controller */ 314 /* 0x100e1000 PL354 Static Memory Controller */ 315 /* 0x100e2000 System Configuration Controller */ 316 317 sysbus_create_simple("sp804", 0x100e4000, pic[48]); 318 /* 0x100e5000 SP805 Watchdog module */ 319 /* 0x100e6000 BP147 TrustZone Protection Controller */ 320 /* 0x100e9000 PL301 'Fast' AXI matrix */ 321 /* 0x100ea000 PL301 'Slow' AXI matrix */ 322 /* 0x100ec000 TrustZone Address Space Controller */ 323 /* 0x10200000 CoreSight debug APB */ 324 /* 0x1e00a000 PL310 L2 Cache Controller */ 325 sysbus_create_varargs("l2x0", 0x1e00a000, NULL); 326 } 327 328 /* Voltage values for SYS_CFG_VOLT daughterboard registers; 329 * values are in microvolts. 330 */ 331 static const uint32_t a9_voltages[] = { 332 1000000, /* VD10 : 1.0V : SoC internal logic voltage */ 333 1000000, /* VD10_S2 : 1.0V : PL310, L2 cache, RAM, non-PL310 logic */ 334 1000000, /* VD10_S3 : 1.0V : Cortex-A9, cores, MPEs, SCU, PL310 logic */ 335 1800000, /* VCC1V8 : 1.8V : DDR2 SDRAM, test chip DDR2 I/O supply */ 336 900000, /* DDR2VTT : 0.9V : DDR2 SDRAM VTT termination voltage */ 337 3300000, /* VCC3V3 : 3.3V : local board supply for misc external logic */ 338 }; 339 340 /* Reset values for daughterboard oscillators (in Hz) */ 341 static const uint32_t a9_clocks[] = { 342 45000000, /* AMBA AXI ACLK: 45MHz */ 343 23750000, /* daughterboard CLCD clock: 23.75MHz */ 344 66670000, /* Test chip reference clock: 66.67MHz */ 345 }; 346 347 static VEDBoardInfo a9_daughterboard = { 348 .motherboard_map = motherboard_legacy_map, 349 .loader_start = 0x60000000, 350 .gic_cpu_if_addr = 0x1e000100, 351 .proc_id = 0x0c000191, 352 .num_voltage_sensors = ARRAY_SIZE(a9_voltages), 353 .voltages = a9_voltages, 354 .num_clocks = ARRAY_SIZE(a9_clocks), 355 .clocks = a9_clocks, 356 .init = a9_daughterboard_init, 357 }; 358 359 static void a15_daughterboard_init(VexpressMachineState *vms, 360 ram_addr_t ram_size, 361 const char *cpu_type, 362 qemu_irq *pic) 363 { 364 MachineState *machine = MACHINE(vms); 365 MemoryRegion *sysmem = get_system_memory(); 366 367 { 368 /* We have to use a separate 64 bit variable here to avoid the gcc 369 * "comparison is always false due to limited range of data type" 370 * warning if we are on a host where ram_addr_t is 32 bits. 371 */ 372 uint64_t rsz = ram_size; 373 if (rsz > (30ULL * 1024 * 1024 * 1024)) { 374 error_report("vexpress-a15: cannot model more than 30GB RAM"); 375 exit(1); 376 } 377 } 378 379 /* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */ 380 memory_region_add_subregion(sysmem, 0x80000000, machine->ram); 381 382 /* 0x2c000000 A15MPCore private memory region (GIC) */ 383 init_cpus(machine, cpu_type, TYPE_A15MPCORE_PRIV, 384 0x2c000000, pic, vms->secure, vms->virt); 385 386 /* A15 daughterboard peripherals: */ 387 388 /* 0x20000000: CoreSight interfaces: not modelled */ 389 /* 0x2a000000: PL301 AXI interconnect: not modelled */ 390 /* 0x2a420000: SCC: not modelled */ 391 /* 0x2a430000: system counter: not modelled */ 392 /* 0x2b000000: HDLCD controller: not modelled */ 393 /* 0x2b060000: SP805 watchdog: not modelled */ 394 /* 0x2b0a0000: PL341 dynamic memory controller: not modelled */ 395 /* 0x2e000000: system SRAM */ 396 memory_region_init_ram(&vms->a15sram, NULL, "vexpress.a15sram", 0x10000, 397 &error_fatal); 398 memory_region_add_subregion(sysmem, 0x2e000000, &vms->a15sram); 399 400 /* 0x7ffb0000: DMA330 DMA controller: not modelled */ 401 /* 0x7ffd0000: PL354 static memory controller: not modelled */ 402 } 403 404 static const uint32_t a15_voltages[] = { 405 900000, /* Vcore: 0.9V : CPU core voltage */ 406 }; 407 408 static const uint32_t a15_clocks[] = { 409 60000000, /* OSCCLK0: 60MHz : CPU_CLK reference */ 410 0, /* OSCCLK1: reserved */ 411 0, /* OSCCLK2: reserved */ 412 0, /* OSCCLK3: reserved */ 413 40000000, /* OSCCLK4: 40MHz : external AXI master clock */ 414 23750000, /* OSCCLK5: 23.75MHz : HDLCD PLL reference */ 415 50000000, /* OSCCLK6: 50MHz : static memory controller clock */ 416 60000000, /* OSCCLK7: 60MHz : SYSCLK reference */ 417 40000000, /* OSCCLK8: 40MHz : DDR2 PLL reference */ 418 }; 419 420 static VEDBoardInfo a15_daughterboard = { 421 .motherboard_map = motherboard_aseries_map, 422 .loader_start = 0x80000000, 423 .gic_cpu_if_addr = 0x2c002000, 424 .proc_id = 0x14000237, 425 .num_voltage_sensors = ARRAY_SIZE(a15_voltages), 426 .voltages = a15_voltages, 427 .num_clocks = ARRAY_SIZE(a15_clocks), 428 .clocks = a15_clocks, 429 .init = a15_daughterboard_init, 430 }; 431 432 static int add_virtio_mmio_node(void *fdt, uint32_t acells, uint32_t scells, 433 hwaddr addr, hwaddr size, uint32_t intc, 434 int irq) 435 { 436 /* Add a virtio_mmio node to the device tree blob: 437 * virtio_mmio@ADDRESS { 438 * compatible = "virtio,mmio"; 439 * reg = <ADDRESS, SIZE>; 440 * interrupt-parent = <&intc>; 441 * interrupts = <0, irq, 1>; 442 * } 443 * (Note that the format of the interrupts property is dependent on the 444 * interrupt controller that interrupt-parent points to; these are for 445 * the ARM GIC and indicate an SPI interrupt, rising-edge-triggered.) 446 */ 447 int rc; 448 char *nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, addr); 449 450 rc = qemu_fdt_add_subnode(fdt, nodename); 451 rc |= qemu_fdt_setprop_string(fdt, nodename, 452 "compatible", "virtio,mmio"); 453 rc |= qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", 454 acells, addr, scells, size); 455 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", intc); 456 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 0, irq, 1); 457 qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0); 458 g_free(nodename); 459 if (rc) { 460 return -1; 461 } 462 return 0; 463 } 464 465 static uint32_t find_int_controller(void *fdt) 466 { 467 /* Find the FDT node corresponding to the interrupt controller 468 * for virtio-mmio devices. We do this by scanning the fdt for 469 * a node with the right compatibility, since we know there is 470 * only one GIC on a vexpress board. 471 * We return the phandle of the node, or 0 if none was found. 472 */ 473 const char *compat = "arm,cortex-a9-gic"; 474 int offset; 475 476 offset = fdt_node_offset_by_compatible(fdt, -1, compat); 477 if (offset >= 0) { 478 return fdt_get_phandle(fdt, offset); 479 } 480 return 0; 481 } 482 483 static void vexpress_modify_dtb(const struct arm_boot_info *info, void *fdt) 484 { 485 uint32_t acells, scells, intc; 486 const VEDBoardInfo *daughterboard = (const VEDBoardInfo *)info; 487 488 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells", 489 NULL, &error_fatal); 490 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells", 491 NULL, &error_fatal); 492 intc = find_int_controller(fdt); 493 if (!intc) { 494 /* Not fatal, we just won't provide virtio. This will 495 * happen with older device tree blobs. 496 */ 497 warn_report("couldn't find interrupt controller in " 498 "dtb; will not include virtio-mmio devices in the dtb"); 499 } else { 500 int i; 501 const hwaddr *map = daughterboard->motherboard_map; 502 503 /* We iterate backwards here because adding nodes 504 * to the dtb puts them in last-first. 505 */ 506 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 507 add_virtio_mmio_node(fdt, acells, scells, 508 map[VE_VIRTIO] + 0x200 * i, 509 0x200, intc, 40 + i); 510 } 511 } 512 } 513 514 515 /* Open code a private version of pflash registration since we 516 * need to set non-default device width for VExpress platform. 517 */ 518 static PFlashCFI01 *ve_pflash_cfi01_register(hwaddr base, const char *name, 519 DriveInfo *di) 520 { 521 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 522 523 if (di) { 524 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(di)); 525 } 526 527 qdev_prop_set_uint32(dev, "num-blocks", 528 VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE); 529 qdev_prop_set_uint64(dev, "sector-length", VEXPRESS_FLASH_SECT_SIZE); 530 qdev_prop_set_uint8(dev, "width", 4); 531 qdev_prop_set_uint8(dev, "device-width", 2); 532 qdev_prop_set_bit(dev, "big-endian", false); 533 qdev_prop_set_uint16(dev, "id0", 0x89); 534 qdev_prop_set_uint16(dev, "id1", 0x18); 535 qdev_prop_set_uint16(dev, "id2", 0x00); 536 qdev_prop_set_uint16(dev, "id3", 0x00); 537 qdev_prop_set_string(dev, "name", name); 538 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 539 540 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 541 return PFLASH_CFI01(dev); 542 } 543 544 static void vexpress_common_init(MachineState *machine) 545 { 546 VexpressMachineState *vms = VEXPRESS_MACHINE(machine); 547 VexpressMachineClass *vmc = VEXPRESS_MACHINE_GET_CLASS(machine); 548 VEDBoardInfo *daughterboard = vmc->daughterboard; 549 DeviceState *dev, *sysctl, *pl041; 550 qemu_irq pic[GIC_EXT_IRQS]; 551 uint32_t sys_id; 552 DriveInfo *dinfo; 553 PFlashCFI01 *pflash0; 554 I2CBus *i2c; 555 ram_addr_t vram_size, sram_size; 556 MemoryRegion *sysmem = get_system_memory(); 557 const hwaddr *map = daughterboard->motherboard_map; 558 QList *db_voltage, *db_clock; 559 int i; 560 561 daughterboard->init(vms, machine->ram_size, machine->cpu_type, pic); 562 563 /* 564 * If a bios file was provided, attempt to map it into memory 565 */ 566 if (machine->firmware) { 567 char *fn; 568 int image_size; 569 570 if (drive_get(IF_PFLASH, 0, 0)) { 571 error_report("The contents of the first flash device may be " 572 "specified with -bios or with -drive if=pflash... " 573 "but you cannot use both options at once"); 574 exit(1); 575 } 576 fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware); 577 if (!fn) { 578 error_report("Could not find ROM image '%s'", machine->firmware); 579 exit(1); 580 } 581 image_size = load_image_targphys(fn, map[VE_NORFLASH0], 582 VEXPRESS_FLASH_SIZE, NULL); 583 g_free(fn); 584 if (image_size < 0) { 585 error_report("Could not load ROM image '%s'", machine->firmware); 586 exit(1); 587 } 588 } 589 590 /* Motherboard peripherals: the wiring is the same but the 591 * addresses vary between the legacy and A-Series memory maps. 592 */ 593 594 sys_id = 0x1190f500; 595 596 sysctl = qdev_new("realview_sysctl"); 597 qdev_prop_set_uint32(sysctl, "sys_id", sys_id); 598 qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id); 599 600 db_voltage = qlist_new(); 601 for (i = 0; i < daughterboard->num_voltage_sensors; i++) { 602 qlist_append_int(db_voltage, daughterboard->voltages[i]); 603 } 604 qdev_prop_set_array(sysctl, "db-voltage", db_voltage); 605 606 db_clock = qlist_new(); 607 for (i = 0; i < daughterboard->num_clocks; i++) { 608 qlist_append_int(db_clock, daughterboard->clocks[i]); 609 } 610 qdev_prop_set_array(sysctl, "db-clock", db_clock); 611 612 sysbus_realize_and_unref(SYS_BUS_DEVICE(sysctl), &error_fatal); 613 sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]); 614 615 /* VE_SP810: not modelled */ 616 /* VE_SERIALPCI: not modelled */ 617 618 pl041 = qdev_new("pl041"); 619 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); 620 if (machine->audiodev) { 621 qdev_prop_set_string(pl041, "audiodev", machine->audiodev); 622 } 623 sysbus_realize_and_unref(SYS_BUS_DEVICE(pl041), &error_fatal); 624 sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]); 625 sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]); 626 627 dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL); 628 /* Wire up MMC card detect and read-only signals */ 629 qdev_connect_gpio_out_named(dev, "card-read-only", 0, 630 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT)); 631 qdev_connect_gpio_out_named(dev, "card-inserted", 0, 632 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN)); 633 dinfo = drive_get(IF_SD, 0, 0); 634 if (dinfo) { 635 DeviceState *card; 636 637 card = qdev_new(TYPE_SD_CARD); 638 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 639 &error_fatal); 640 qdev_realize_and_unref(card, qdev_get_child_bus(dev, "sd-bus"), 641 &error_fatal); 642 } 643 644 sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]); 645 sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]); 646 647 pl011_create(map[VE_UART0], pic[5], serial_hd(0)); 648 pl011_create(map[VE_UART1], pic[6], serial_hd(1)); 649 pl011_create(map[VE_UART2], pic[7], serial_hd(2)); 650 pl011_create(map[VE_UART3], pic[8], serial_hd(3)); 651 652 sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]); 653 sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]); 654 655 dev = sysbus_create_simple(TYPE_ARM_SBCON_I2C, map[VE_SERIALDVI], NULL); 656 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 657 i2c_slave_create_simple(i2c, "sii9022", 0x39); 658 659 sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */ 660 661 /* VE_COMPACTFLASH: not modelled */ 662 663 dev = qdev_new("pl111"); 664 object_property_set_link(OBJECT(dev), "framebuffer-memory", 665 OBJECT(sysmem), &error_fatal); 666 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 667 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, map[VE_CLCD]); 668 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[14]); 669 670 dinfo = drive_get(IF_PFLASH, 0, 0); 671 pflash0 = ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flash0", 672 dinfo); 673 674 if (map[VE_NORFLASHALIAS] != -1) { 675 /* Map flash 0 as an alias into low memory */ 676 MemoryRegion *flash0mem; 677 flash0mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(pflash0), 0); 678 memory_region_init_alias(&vms->flashalias, NULL, "vexpress.flashalias", 679 flash0mem, 0, VEXPRESS_FLASH_SIZE); 680 memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], &vms->flashalias); 681 } 682 683 dinfo = drive_get(IF_PFLASH, 0, 1); 684 ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1", dinfo); 685 686 sram_size = 0x2000000; 687 memory_region_init_ram(&vms->sram, NULL, "vexpress.sram", sram_size, 688 &error_fatal); 689 memory_region_add_subregion(sysmem, map[VE_SRAM], &vms->sram); 690 691 vram_size = 0x800000; 692 memory_region_init_ram(&vms->vram, NULL, "vexpress.vram", vram_size, 693 &error_fatal); 694 memory_region_add_subregion(sysmem, map[VE_VIDEORAM], &vms->vram); 695 696 /* 0x4e000000 LAN9118 Ethernet */ 697 if (qemu_find_nic_info("lan9118", true, NULL)) { 698 lan9118_init(map[VE_ETHERNET], pic[15]); 699 } 700 701 /* VE_USB: not modelled */ 702 703 /* VE_DAPROM: not modelled */ 704 705 /* Create mmio transports, so the user can create virtio backends 706 * (which will be automatically plugged in to the transports). If 707 * no backend is created the transport will just sit harmlessly idle. 708 */ 709 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 710 sysbus_create_simple("virtio-mmio", map[VE_VIRTIO] + 0x200 * i, 711 pic[40 + i]); 712 } 713 714 daughterboard->bootinfo.ram_size = machine->ram_size; 715 daughterboard->bootinfo.board_id = VEXPRESS_BOARD_ID; 716 daughterboard->bootinfo.loader_start = daughterboard->loader_start; 717 daughterboard->bootinfo.smp_loader_start = map[VE_SRAM]; 718 daughterboard->bootinfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30; 719 daughterboard->bootinfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr; 720 daughterboard->bootinfo.modify_dtb = vexpress_modify_dtb; 721 /* When booting Linux we should be in secure state if the CPU has one. */ 722 daughterboard->bootinfo.secure_boot = vms->secure; 723 arm_load_kernel(ARM_CPU(first_cpu), machine, &daughterboard->bootinfo); 724 } 725 726 static bool vexpress_get_secure(Object *obj, Error **errp) 727 { 728 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 729 730 return vms->secure; 731 } 732 733 static void vexpress_set_secure(Object *obj, bool value, Error **errp) 734 { 735 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 736 737 vms->secure = value; 738 } 739 740 static bool vexpress_get_virt(Object *obj, Error **errp) 741 { 742 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 743 744 return vms->virt; 745 } 746 747 static void vexpress_set_virt(Object *obj, bool value, Error **errp) 748 { 749 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 750 751 vms->virt = value; 752 } 753 754 static void vexpress_instance_init(Object *obj) 755 { 756 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 757 758 /* EL3 is enabled by default on vexpress */ 759 vms->secure = true; 760 } 761 762 static void vexpress_a15_instance_init(Object *obj) 763 { 764 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 765 766 /* 767 * For the vexpress-a15, EL2 is by default enabled if EL3 is, 768 * but can also be specifically set to on or off. 769 */ 770 vms->virt = true; 771 } 772 773 static void vexpress_a9_instance_init(Object *obj) 774 { 775 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 776 777 /* The A9 doesn't have the virt extensions */ 778 vms->virt = false; 779 } 780 781 static void vexpress_class_init(ObjectClass *oc, const void *data) 782 { 783 MachineClass *mc = MACHINE_CLASS(oc); 784 785 mc->desc = "ARM Versatile Express"; 786 mc->init = vexpress_common_init; 787 mc->max_cpus = 4; 788 mc->ignore_memory_transaction_failures = true; 789 mc->default_ram_id = "vexpress.highmem"; 790 791 machine_add_audiodev_property(mc); 792 object_class_property_add_bool(oc, "secure", vexpress_get_secure, 793 vexpress_set_secure); 794 object_class_property_set_description(oc, "secure", 795 "Set on/off to enable/disable the ARM " 796 "Security Extensions (TrustZone)"); 797 } 798 799 static void vexpress_a9_class_init(ObjectClass *oc, const void *data) 800 { 801 static const char * const valid_cpu_types[] = { 802 ARM_CPU_TYPE_NAME("cortex-a9"), 803 NULL 804 }; 805 MachineClass *mc = MACHINE_CLASS(oc); 806 VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc); 807 808 mc->desc = "ARM Versatile Express for Cortex-A9"; 809 mc->valid_cpu_types = valid_cpu_types; 810 mc->auto_create_sdcard = true; 811 812 vmc->daughterboard = &a9_daughterboard; 813 } 814 815 static void vexpress_a15_class_init(ObjectClass *oc, const void *data) 816 { 817 static const char * const valid_cpu_types[] = { 818 ARM_CPU_TYPE_NAME("cortex-a15"), 819 NULL 820 }; 821 MachineClass *mc = MACHINE_CLASS(oc); 822 VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc); 823 824 mc->desc = "ARM Versatile Express for Cortex-A15"; 825 mc->valid_cpu_types = valid_cpu_types; 826 mc->auto_create_sdcard = true; 827 828 vmc->daughterboard = &a15_daughterboard; 829 830 object_class_property_add_bool(oc, "virtualization", vexpress_get_virt, 831 vexpress_set_virt); 832 object_class_property_set_description(oc, "virtualization", 833 "Set on/off to enable/disable the ARM " 834 "Virtualization Extensions " 835 "(defaults to same as 'secure')"); 836 837 } 838 839 static const TypeInfo vexpress_info = { 840 .name = TYPE_VEXPRESS_MACHINE, 841 .parent = TYPE_MACHINE, 842 .abstract = true, 843 .instance_size = sizeof(VexpressMachineState), 844 .instance_init = vexpress_instance_init, 845 .class_size = sizeof(VexpressMachineClass), 846 .class_init = vexpress_class_init, 847 }; 848 849 static const TypeInfo vexpress_a9_info = { 850 .name = TYPE_VEXPRESS_A9_MACHINE, 851 .parent = TYPE_VEXPRESS_MACHINE, 852 .class_init = vexpress_a9_class_init, 853 .instance_init = vexpress_a9_instance_init, 854 .interfaces = arm_machine_interfaces, 855 }; 856 857 static const TypeInfo vexpress_a15_info = { 858 .name = TYPE_VEXPRESS_A15_MACHINE, 859 .parent = TYPE_VEXPRESS_MACHINE, 860 .class_init = vexpress_a15_class_init, 861 .instance_init = vexpress_a15_instance_init, 862 .interfaces = arm_machine_interfaces, 863 }; 864 865 static void vexpress_machine_init(void) 866 { 867 type_register_static(&vexpress_info); 868 type_register_static(&vexpress_a9_info); 869 type_register_static(&vexpress_a15_info); 870 } 871 872 type_init(vexpress_machine_init); 873