1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Hantro VPU HEVC codec driver
4  *
5  * Copyright (C) 2020 Safran Passenger Innovations LLC
6  */
7 
8 #include "hantro_hw.h"
9 #include "hantro_g2_regs.h"
10 
11 #define G2_ALIGN	16
12 
hantro_hevc_chroma_offset(struct hantro_ctx * ctx)13 static size_t hantro_hevc_chroma_offset(struct hantro_ctx *ctx)
14 {
15 	return ctx->dst_fmt.width * ctx->dst_fmt.height * ctx->bit_depth / 8;
16 }
17 
hantro_hevc_motion_vectors_offset(struct hantro_ctx * ctx)18 static size_t hantro_hevc_motion_vectors_offset(struct hantro_ctx *ctx)
19 {
20 	size_t cr_offset = hantro_hevc_chroma_offset(ctx);
21 
22 	return ALIGN((cr_offset * 3) / 2, G2_ALIGN);
23 }
24 
prepare_tile_info_buffer(struct hantro_ctx * ctx)25 static void prepare_tile_info_buffer(struct hantro_ctx *ctx)
26 {
27 	struct hantro_dev *vpu = ctx->dev;
28 	const struct hantro_hevc_dec_ctrls *ctrls = &ctx->hevc_dec.ctrls;
29 	const struct v4l2_ctrl_hevc_pps *pps = ctrls->pps;
30 	const struct v4l2_ctrl_hevc_sps *sps = ctrls->sps;
31 	u16 *p = (u16 *)((u8 *)ctx->hevc_dec.tile_sizes.cpu);
32 	unsigned int num_tile_rows = pps->num_tile_rows_minus1 + 1;
33 	unsigned int num_tile_cols = pps->num_tile_columns_minus1 + 1;
34 	unsigned int pic_width_in_ctbs, pic_height_in_ctbs;
35 	unsigned int max_log2_ctb_size, ctb_size;
36 	bool tiles_enabled, uniform_spacing;
37 	u32 no_chroma = 0;
38 
39 	tiles_enabled = !!(pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED);
40 	uniform_spacing = !!(pps->flags & V4L2_HEVC_PPS_FLAG_UNIFORM_SPACING);
41 
42 	hantro_reg_write(vpu, &g2_tile_e, tiles_enabled);
43 
44 	max_log2_ctb_size = sps->log2_min_luma_coding_block_size_minus3 + 3 +
45 			    sps->log2_diff_max_min_luma_coding_block_size;
46 	pic_width_in_ctbs = (sps->pic_width_in_luma_samples +
47 			    (1 << max_log2_ctb_size) - 1) >> max_log2_ctb_size;
48 	pic_height_in_ctbs = (sps->pic_height_in_luma_samples + (1 << max_log2_ctb_size) - 1)
49 			     >> max_log2_ctb_size;
50 	ctb_size = 1 << max_log2_ctb_size;
51 
52 	vpu_debug(1, "Preparing tile sizes buffer for %dx%d CTBs (CTB size %d)\n",
53 		  pic_width_in_ctbs, pic_height_in_ctbs, ctb_size);
54 
55 	if (tiles_enabled) {
56 		unsigned int i, j, h;
57 
58 		vpu_debug(1, "Tiles enabled! %dx%d\n", num_tile_cols, num_tile_rows);
59 
60 		hantro_reg_write(vpu, &g2_num_tile_rows, num_tile_rows);
61 		hantro_reg_write(vpu, &g2_num_tile_cols, num_tile_cols);
62 
63 		/* write width + height for each tile in pic */
64 		if (!uniform_spacing) {
65 			u32 tmp_w = 0, tmp_h = 0;
66 
67 			for (i = 0; i < num_tile_rows; i++) {
68 				if (i == num_tile_rows - 1)
69 					h = pic_height_in_ctbs - tmp_h;
70 				else
71 					h = pps->row_height_minus1[i] + 1;
72 				tmp_h += h;
73 				if (i == 0 && h == 1 && ctb_size == 16)
74 					no_chroma = 1;
75 				for (j = 0, tmp_w = 0; j < num_tile_cols - 1; j++) {
76 					tmp_w += pps->column_width_minus1[j] + 1;
77 					*p++ = pps->column_width_minus1[j] + 1;
78 					*p++ = h;
79 					if (i == 0 && h == 1 && ctb_size == 16)
80 						no_chroma = 1;
81 				}
82 				/* last column */
83 				*p++ = pic_width_in_ctbs - tmp_w;
84 				*p++ = h;
85 			}
86 		} else { /* uniform spacing */
87 			u32 tmp, prev_h, prev_w;
88 
89 			for (i = 0, prev_h = 0; i < num_tile_rows; i++) {
90 				tmp = (i + 1) * pic_height_in_ctbs / num_tile_rows;
91 				h = tmp - prev_h;
92 				prev_h = tmp;
93 				if (i == 0 && h == 1 && ctb_size == 16)
94 					no_chroma = 1;
95 				for (j = 0, prev_w = 0; j < num_tile_cols; j++) {
96 					tmp = (j + 1) * pic_width_in_ctbs / num_tile_cols;
97 					*p++ = tmp - prev_w;
98 					*p++ = h;
99 					if (j == 0 &&
100 					    (pps->column_width_minus1[0] + 1) == 1 &&
101 					    ctb_size == 16)
102 						no_chroma = 1;
103 					prev_w = tmp;
104 				}
105 			}
106 		}
107 	} else {
108 		hantro_reg_write(vpu, &g2_num_tile_rows, 1);
109 		hantro_reg_write(vpu, &g2_num_tile_cols, 1);
110 
111 		/* There's one tile, with dimensions equal to pic size. */
112 		p[0] = pic_width_in_ctbs;
113 		p[1] = pic_height_in_ctbs;
114 	}
115 
116 	if (no_chroma)
117 		vpu_debug(1, "%s: no chroma!\n", __func__);
118 }
119 
compute_header_skip_length(struct hantro_ctx * ctx)120 static int compute_header_skip_length(struct hantro_ctx *ctx)
121 {
122 	const struct hantro_hevc_dec_ctrls *ctrls = &ctx->hevc_dec.ctrls;
123 	const struct v4l2_ctrl_hevc_decode_params *decode_params = ctrls->decode_params;
124 	const struct v4l2_ctrl_hevc_sps *sps = ctrls->sps;
125 	const struct v4l2_ctrl_hevc_pps *pps = ctrls->pps;
126 	int skip = 0;
127 
128 	if (pps->flags & V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT)
129 		/* size of pic_output_flag */
130 		skip++;
131 
132 	if (sps->flags & V4L2_HEVC_SPS_FLAG_SEPARATE_COLOUR_PLANE)
133 		/* size of pic_order_cnt_lsb */
134 		skip += 2;
135 
136 	if (!(decode_params->flags & V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC)) {
137 		/* size of pic_order_cnt_lsb */
138 		skip += sps->log2_max_pic_order_cnt_lsb_minus4 + 4;
139 
140 		/* size of short_term_ref_pic_set_sps_flag */
141 		skip++;
142 
143 		if (decode_params->short_term_ref_pic_set_size)
144 			/* size of st_ref_pic_set( num_short_term_ref_pic_sets ) */
145 			skip += decode_params->short_term_ref_pic_set_size;
146 		else if (sps->num_short_term_ref_pic_sets > 1)
147 			skip += fls(sps->num_short_term_ref_pic_sets - 1);
148 
149 		skip += decode_params->long_term_ref_pic_set_size;
150 	}
151 
152 	return skip;
153 }
154 
set_params(struct hantro_ctx * ctx)155 static void set_params(struct hantro_ctx *ctx)
156 {
157 	const struct hantro_hevc_dec_ctrls *ctrls = &ctx->hevc_dec.ctrls;
158 	const struct v4l2_ctrl_hevc_sps *sps = ctrls->sps;
159 	const struct v4l2_ctrl_hevc_pps *pps = ctrls->pps;
160 	const struct v4l2_ctrl_hevc_decode_params *decode_params = ctrls->decode_params;
161 	struct hantro_dev *vpu = ctx->dev;
162 	u32 min_log2_cb_size, max_log2_ctb_size, min_cb_size, max_ctb_size;
163 	u32 pic_width_in_min_cbs, pic_height_in_min_cbs;
164 	u32 pic_width_aligned, pic_height_aligned;
165 	u32 partial_ctb_x, partial_ctb_y;
166 
167 	hantro_reg_write(vpu, &g2_bit_depth_y_minus8, sps->bit_depth_luma_minus8);
168 	hantro_reg_write(vpu, &g2_bit_depth_c_minus8, sps->bit_depth_chroma_minus8);
169 
170 	hantro_reg_write(vpu, &g2_hdr_skip_length, compute_header_skip_length(ctx));
171 
172 	min_log2_cb_size = sps->log2_min_luma_coding_block_size_minus3 + 3;
173 	max_log2_ctb_size = min_log2_cb_size + sps->log2_diff_max_min_luma_coding_block_size;
174 
175 	hantro_reg_write(vpu, &g2_min_cb_size, min_log2_cb_size);
176 	hantro_reg_write(vpu, &g2_max_cb_size, max_log2_ctb_size);
177 
178 	min_cb_size = 1 << min_log2_cb_size;
179 	max_ctb_size = 1 << max_log2_ctb_size;
180 
181 	pic_width_in_min_cbs = sps->pic_width_in_luma_samples / min_cb_size;
182 	pic_height_in_min_cbs = sps->pic_height_in_luma_samples / min_cb_size;
183 	pic_width_aligned = ALIGN(sps->pic_width_in_luma_samples, max_ctb_size);
184 	pic_height_aligned = ALIGN(sps->pic_height_in_luma_samples, max_ctb_size);
185 
186 	partial_ctb_x = !!(sps->pic_width_in_luma_samples != pic_width_aligned);
187 	partial_ctb_y = !!(sps->pic_height_in_luma_samples != pic_height_aligned);
188 
189 	hantro_reg_write(vpu, &g2_partial_ctb_x, partial_ctb_x);
190 	hantro_reg_write(vpu, &g2_partial_ctb_y, partial_ctb_y);
191 
192 	hantro_reg_write(vpu, &g2_pic_width_in_cbs, pic_width_in_min_cbs);
193 	hantro_reg_write(vpu, &g2_pic_height_in_cbs, pic_height_in_min_cbs);
194 
195 	hantro_reg_write(vpu, &g2_pic_width_4x4,
196 			 (pic_width_in_min_cbs * min_cb_size) / 4);
197 	hantro_reg_write(vpu, &g2_pic_height_4x4,
198 			 (pic_height_in_min_cbs * min_cb_size) / 4);
199 
200 	hantro_reg_write(vpu, &hevc_max_inter_hierdepth,
201 			 sps->max_transform_hierarchy_depth_inter);
202 	hantro_reg_write(vpu, &hevc_max_intra_hierdepth,
203 			 sps->max_transform_hierarchy_depth_intra);
204 	hantro_reg_write(vpu, &hevc_min_trb_size,
205 			 sps->log2_min_luma_transform_block_size_minus2 + 2);
206 	hantro_reg_write(vpu, &hevc_max_trb_size,
207 			 sps->log2_min_luma_transform_block_size_minus2 + 2 +
208 			 sps->log2_diff_max_min_luma_transform_block_size);
209 
210 	hantro_reg_write(vpu, &g2_tempor_mvp_e,
211 			 !!(sps->flags & V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED) &&
212 			 !(decode_params->flags & V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC));
213 	hantro_reg_write(vpu, &g2_strong_smooth_e,
214 			 !!(sps->flags & V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED));
215 	hantro_reg_write(vpu, &g2_asym_pred_e,
216 			 !!(sps->flags & V4L2_HEVC_SPS_FLAG_AMP_ENABLED));
217 	hantro_reg_write(vpu, &g2_sao_e,
218 			 !!(sps->flags & V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET));
219 	hantro_reg_write(vpu, &g2_sign_data_hide,
220 			 !!(pps->flags & V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED));
221 
222 	if (pps->flags & V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED) {
223 		hantro_reg_write(vpu, &g2_cu_qpd_e, 1);
224 		hantro_reg_write(vpu, &g2_max_cu_qpd_depth, pps->diff_cu_qp_delta_depth);
225 	} else {
226 		hantro_reg_write(vpu, &g2_cu_qpd_e, 0);
227 		hantro_reg_write(vpu, &g2_max_cu_qpd_depth, 0);
228 	}
229 
230 	hantro_reg_write(vpu, &g2_cb_qp_offset, pps->pps_cb_qp_offset);
231 	hantro_reg_write(vpu, &g2_cr_qp_offset, pps->pps_cr_qp_offset);
232 
233 	hantro_reg_write(vpu, &g2_filt_offset_beta, pps->pps_beta_offset_div2);
234 	hantro_reg_write(vpu, &g2_filt_offset_tc, pps->pps_tc_offset_div2);
235 	hantro_reg_write(vpu, &g2_slice_hdr_ext_e,
236 			 !!(pps->flags & V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT));
237 	hantro_reg_write(vpu, &g2_slice_hdr_ext_bits, pps->num_extra_slice_header_bits);
238 	hantro_reg_write(vpu, &g2_slice_chqp_present,
239 			 !!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT));
240 	hantro_reg_write(vpu, &g2_weight_bipr_idc,
241 			 !!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED));
242 	hantro_reg_write(vpu, &g2_transq_bypass,
243 			 !!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED));
244 	hantro_reg_write(vpu, &g2_list_mod_e,
245 			 !!(pps->flags & V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT));
246 	hantro_reg_write(vpu, &g2_entropy_sync_e,
247 			 !!(pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED));
248 	hantro_reg_write(vpu, &g2_cabac_init_present,
249 			 !!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT));
250 	hantro_reg_write(vpu, &g2_idr_pic_e,
251 			 !!(decode_params->flags & V4L2_HEVC_DECODE_PARAM_FLAG_IRAP_PIC));
252 	hantro_reg_write(vpu, &hevc_parallel_merge,
253 			 pps->log2_parallel_merge_level_minus2 + 2);
254 	hantro_reg_write(vpu, &g2_pcm_filt_d,
255 			 !!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED));
256 	hantro_reg_write(vpu, &g2_pcm_e,
257 			 !!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_ENABLED));
258 	if (sps->flags & V4L2_HEVC_SPS_FLAG_PCM_ENABLED) {
259 		hantro_reg_write(vpu, &g2_max_pcm_size,
260 				 sps->log2_diff_max_min_pcm_luma_coding_block_size +
261 				 sps->log2_min_pcm_luma_coding_block_size_minus3 + 3);
262 		hantro_reg_write(vpu, &g2_min_pcm_size,
263 				 sps->log2_min_pcm_luma_coding_block_size_minus3 + 3);
264 		hantro_reg_write(vpu, &g2_bit_depth_pcm_y,
265 				 sps->pcm_sample_bit_depth_luma_minus1 + 1);
266 		hantro_reg_write(vpu, &g2_bit_depth_pcm_c,
267 				 sps->pcm_sample_bit_depth_chroma_minus1 + 1);
268 	} else {
269 		hantro_reg_write(vpu, &g2_max_pcm_size, 0);
270 		hantro_reg_write(vpu, &g2_min_pcm_size, 0);
271 		hantro_reg_write(vpu, &g2_bit_depth_pcm_y, 0);
272 		hantro_reg_write(vpu, &g2_bit_depth_pcm_c, 0);
273 	}
274 
275 	hantro_reg_write(vpu, &g2_start_code_e, 1);
276 	hantro_reg_write(vpu, &g2_init_qp, pps->init_qp_minus26 + 26);
277 	hantro_reg_write(vpu, &g2_weight_pred_e,
278 			 !!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED));
279 	hantro_reg_write(vpu, &g2_cabac_init_present,
280 			 !!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT));
281 	hantro_reg_write(vpu, &g2_const_intra_e,
282 			 !!(pps->flags & V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED));
283 	hantro_reg_write(vpu, &g2_transform_skip,
284 			 !!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED));
285 	hantro_reg_write(vpu, &g2_out_filtering_dis,
286 			 !!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER));
287 	hantro_reg_write(vpu, &g2_filt_ctrl_pres,
288 			 !!(pps->flags & V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT));
289 	hantro_reg_write(vpu, &g2_dependent_slice,
290 			 !!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED));
291 	hantro_reg_write(vpu, &g2_filter_override,
292 			 !!(pps->flags & V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED));
293 	hantro_reg_write(vpu, &g2_refidx0_active,
294 			 pps->num_ref_idx_l0_default_active_minus1 + 1);
295 	hantro_reg_write(vpu, &g2_refidx1_active,
296 			 pps->num_ref_idx_l1_default_active_minus1 + 1);
297 	hantro_reg_write(vpu, &g2_apf_threshold, 8);
298 }
299 
set_ref_pic_list(struct hantro_ctx * ctx)300 static void set_ref_pic_list(struct hantro_ctx *ctx)
301 {
302 	const struct hantro_hevc_dec_ctrls *ctrls = &ctx->hevc_dec.ctrls;
303 	struct hantro_dev *vpu = ctx->dev;
304 	const struct v4l2_ctrl_hevc_decode_params *decode_params = ctrls->decode_params;
305 	u32 list0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX] = {};
306 	u32 list1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX] = {};
307 	static const struct hantro_reg ref_pic_regs0[] = {
308 		hevc_rlist_f0,
309 		hevc_rlist_f1,
310 		hevc_rlist_f2,
311 		hevc_rlist_f3,
312 		hevc_rlist_f4,
313 		hevc_rlist_f5,
314 		hevc_rlist_f6,
315 		hevc_rlist_f7,
316 		hevc_rlist_f8,
317 		hevc_rlist_f9,
318 		hevc_rlist_f10,
319 		hevc_rlist_f11,
320 		hevc_rlist_f12,
321 		hevc_rlist_f13,
322 		hevc_rlist_f14,
323 		hevc_rlist_f15,
324 	};
325 	static const struct hantro_reg ref_pic_regs1[] = {
326 		hevc_rlist_b0,
327 		hevc_rlist_b1,
328 		hevc_rlist_b2,
329 		hevc_rlist_b3,
330 		hevc_rlist_b4,
331 		hevc_rlist_b5,
332 		hevc_rlist_b6,
333 		hevc_rlist_b7,
334 		hevc_rlist_b8,
335 		hevc_rlist_b9,
336 		hevc_rlist_b10,
337 		hevc_rlist_b11,
338 		hevc_rlist_b12,
339 		hevc_rlist_b13,
340 		hevc_rlist_b14,
341 		hevc_rlist_b15,
342 	};
343 	unsigned int i, j;
344 
345 	/* List 0 contains: short term before, short term after and long term */
346 	j = 0;
347 	for (i = 0; i < decode_params->num_poc_st_curr_before && j < ARRAY_SIZE(list0); i++)
348 		list0[j++] = decode_params->poc_st_curr_before[i];
349 	for (i = 0; i < decode_params->num_poc_st_curr_after && j < ARRAY_SIZE(list0); i++)
350 		list0[j++] = decode_params->poc_st_curr_after[i];
351 	for (i = 0; i < decode_params->num_poc_lt_curr && j < ARRAY_SIZE(list0); i++)
352 		list0[j++] = decode_params->poc_lt_curr[i];
353 
354 	/* Fill the list, copying over and over */
355 	i = 0;
356 	while (j < ARRAY_SIZE(list0))
357 		list0[j++] = list0[i++];
358 
359 	j = 0;
360 	for (i = 0; i < decode_params->num_poc_st_curr_after && j < ARRAY_SIZE(list1); i++)
361 		list1[j++] = decode_params->poc_st_curr_after[i];
362 	for (i = 0; i < decode_params->num_poc_st_curr_before && j < ARRAY_SIZE(list1); i++)
363 		list1[j++] = decode_params->poc_st_curr_before[i];
364 	for (i = 0; i < decode_params->num_poc_lt_curr && j < ARRAY_SIZE(list1); i++)
365 		list1[j++] = decode_params->poc_lt_curr[i];
366 
367 	i = 0;
368 	while (j < ARRAY_SIZE(list1))
369 		list1[j++] = list1[i++];
370 
371 	for (i = 0; i < V4L2_HEVC_DPB_ENTRIES_NUM_MAX; i++) {
372 		hantro_reg_write(vpu, &ref_pic_regs0[i], list0[i]);
373 		hantro_reg_write(vpu, &ref_pic_regs1[i], list1[i]);
374 	}
375 }
376 
set_ref(struct hantro_ctx * ctx)377 static int set_ref(struct hantro_ctx *ctx)
378 {
379 	const struct hantro_hevc_dec_ctrls *ctrls = &ctx->hevc_dec.ctrls;
380 	const struct v4l2_ctrl_hevc_pps *pps = ctrls->pps;
381 	const struct v4l2_ctrl_hevc_decode_params *decode_params = ctrls->decode_params;
382 	const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb;
383 	dma_addr_t luma_addr, chroma_addr, mv_addr = 0;
384 	struct hantro_dev *vpu = ctx->dev;
385 	struct vb2_v4l2_buffer *vb2_dst;
386 	struct hantro_decoded_buffer *dst;
387 	size_t cr_offset = hantro_hevc_chroma_offset(ctx);
388 	size_t mv_offset = hantro_hevc_motion_vectors_offset(ctx);
389 	u32 max_ref_frames;
390 	u16 dpb_longterm_e;
391 	static const struct hantro_reg cur_poc[] = {
392 		hevc_cur_poc_00,
393 		hevc_cur_poc_01,
394 		hevc_cur_poc_02,
395 		hevc_cur_poc_03,
396 		hevc_cur_poc_04,
397 		hevc_cur_poc_05,
398 		hevc_cur_poc_06,
399 		hevc_cur_poc_07,
400 		hevc_cur_poc_08,
401 		hevc_cur_poc_09,
402 		hevc_cur_poc_10,
403 		hevc_cur_poc_11,
404 		hevc_cur_poc_12,
405 		hevc_cur_poc_13,
406 		hevc_cur_poc_14,
407 		hevc_cur_poc_15,
408 	};
409 	unsigned int i;
410 
411 	max_ref_frames = decode_params->num_poc_lt_curr +
412 		decode_params->num_poc_st_curr_before +
413 		decode_params->num_poc_st_curr_after;
414 	/*
415 	 * Set max_ref_frames to non-zero to avoid HW hang when decoding
416 	 * badly marked I-frames.
417 	 */
418 	max_ref_frames = max_ref_frames ? max_ref_frames : 1;
419 	hantro_reg_write(vpu, &g2_num_ref_frames, max_ref_frames);
420 	hantro_reg_write(vpu, &g2_filter_over_slices,
421 			 !!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED));
422 	hantro_reg_write(vpu, &g2_filter_over_tiles,
423 			 !!(pps->flags & V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED));
424 
425 	/*
426 	 * Write POC count diff from current pic.
427 	 */
428 	for (i = 0; i < decode_params->num_active_dpb_entries && i < ARRAY_SIZE(cur_poc); i++) {
429 		char poc_diff = decode_params->pic_order_cnt_val - dpb[i].pic_order_cnt_val;
430 
431 		hantro_reg_write(vpu, &cur_poc[i], poc_diff);
432 	}
433 
434 	if (i < ARRAY_SIZE(cur_poc)) {
435 		/*
436 		 * After the references, fill one entry pointing to itself,
437 		 * i.e. difference is zero.
438 		 */
439 		hantro_reg_write(vpu, &cur_poc[i], 0);
440 		i++;
441 	}
442 
443 	/* Fill the rest with the current picture */
444 	for (; i < ARRAY_SIZE(cur_poc); i++)
445 		hantro_reg_write(vpu, &cur_poc[i], decode_params->pic_order_cnt_val);
446 
447 	set_ref_pic_list(ctx);
448 
449 	/* We will only keep the reference pictures that are still used */
450 	hantro_hevc_ref_init(ctx);
451 
452 	/* Set up addresses of DPB buffers */
453 	dpb_longterm_e = 0;
454 	for (i = 0; i < decode_params->num_active_dpb_entries &&
455 	     i < (V4L2_HEVC_DPB_ENTRIES_NUM_MAX - 1); i++) {
456 		luma_addr = hantro_hevc_get_ref_buf(ctx, dpb[i].pic_order_cnt_val);
457 		if (!luma_addr)
458 			return -ENOMEM;
459 
460 		chroma_addr = luma_addr + cr_offset;
461 		mv_addr = luma_addr + mv_offset;
462 
463 		if (dpb[i].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE)
464 			dpb_longterm_e |= BIT(V4L2_HEVC_DPB_ENTRIES_NUM_MAX - 1 - i);
465 
466 		hantro_write_addr(vpu, G2_REF_LUMA_ADDR(i), luma_addr);
467 		hantro_write_addr(vpu, G2_REF_CHROMA_ADDR(i), chroma_addr);
468 		hantro_write_addr(vpu, G2_REF_MV_ADDR(i), mv_addr);
469 	}
470 
471 	vb2_dst = hantro_get_dst_buf(ctx);
472 	dst = vb2_to_hantro_decoded_buf(&vb2_dst->vb2_buf);
473 	luma_addr = hantro_get_dec_buf_addr(ctx, &dst->base.vb.vb2_buf);
474 	if (!luma_addr)
475 		return -ENOMEM;
476 
477 	if (hantro_hevc_add_ref_buf(ctx, decode_params->pic_order_cnt_val, luma_addr))
478 		return -EINVAL;
479 
480 	chroma_addr = luma_addr + cr_offset;
481 	mv_addr = luma_addr + mv_offset;
482 
483 	hantro_write_addr(vpu, G2_REF_LUMA_ADDR(i), luma_addr);
484 	hantro_write_addr(vpu, G2_REF_CHROMA_ADDR(i), chroma_addr);
485 	hantro_write_addr(vpu, G2_REF_MV_ADDR(i++), mv_addr);
486 
487 	hantro_write_addr(vpu, G2_OUT_LUMA_ADDR, luma_addr);
488 	hantro_write_addr(vpu, G2_OUT_CHROMA_ADDR, chroma_addr);
489 	hantro_write_addr(vpu, G2_OUT_MV_ADDR, mv_addr);
490 
491 	for (; i < V4L2_HEVC_DPB_ENTRIES_NUM_MAX; i++) {
492 		hantro_write_addr(vpu, G2_REF_LUMA_ADDR(i), 0);
493 		hantro_write_addr(vpu, G2_REF_CHROMA_ADDR(i), 0);
494 		hantro_write_addr(vpu, G2_REF_MV_ADDR(i), 0);
495 	}
496 
497 	hantro_reg_write(vpu, &g2_refer_lterm_e, dpb_longterm_e);
498 
499 	return 0;
500 }
501 
set_buffers(struct hantro_ctx * ctx)502 static void set_buffers(struct hantro_ctx *ctx)
503 {
504 	struct vb2_v4l2_buffer *src_buf;
505 	struct hantro_dev *vpu = ctx->dev;
506 	dma_addr_t src_dma;
507 	u32 src_len, src_buf_len;
508 
509 	src_buf = hantro_get_src_buf(ctx);
510 
511 	/* Source (stream) buffer. */
512 	src_dma = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0);
513 	src_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0);
514 	src_buf_len = vb2_plane_size(&src_buf->vb2_buf, 0);
515 
516 	hantro_write_addr(vpu, G2_STREAM_ADDR, src_dma);
517 	hantro_reg_write(vpu, &g2_stream_len, src_len);
518 	hantro_reg_write(vpu, &g2_strm_buffer_len, src_buf_len);
519 	hantro_reg_write(vpu, &g2_strm_start_offset, 0);
520 	hantro_reg_write(vpu, &g2_write_mvs_e, 1);
521 
522 	hantro_write_addr(vpu, G2_TILE_SIZES_ADDR, ctx->hevc_dec.tile_sizes.dma);
523 	hantro_write_addr(vpu, G2_TILE_FILTER_ADDR, ctx->hevc_dec.tile_filter.dma);
524 	hantro_write_addr(vpu, G2_TILE_SAO_ADDR, ctx->hevc_dec.tile_sao.dma);
525 	hantro_write_addr(vpu, G2_TILE_BSD_ADDR, ctx->hevc_dec.tile_bsd.dma);
526 }
527 
prepare_scaling_list_buffer(struct hantro_ctx * ctx)528 static void prepare_scaling_list_buffer(struct hantro_ctx *ctx)
529 {
530 	struct hantro_dev *vpu = ctx->dev;
531 	const struct hantro_hevc_dec_ctrls *ctrls = &ctx->hevc_dec.ctrls;
532 	const struct v4l2_ctrl_hevc_scaling_matrix *sc = ctrls->scaling;
533 	const struct v4l2_ctrl_hevc_sps *sps = ctrls->sps;
534 	u8 *p = ((u8 *)ctx->hevc_dec.scaling_lists.cpu);
535 	unsigned int scaling_list_enabled;
536 	unsigned int i, j, k;
537 
538 	scaling_list_enabled = !!(sps->flags & V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED);
539 	hantro_reg_write(vpu, &g2_scaling_list_e, scaling_list_enabled);
540 
541 	if (!scaling_list_enabled)
542 		return;
543 
544 	for (i = 0; i < ARRAY_SIZE(sc->scaling_list_dc_coef_16x16); i++)
545 		*p++ = sc->scaling_list_dc_coef_16x16[i];
546 
547 	for (i = 0; i < ARRAY_SIZE(sc->scaling_list_dc_coef_32x32); i++)
548 		*p++ = sc->scaling_list_dc_coef_32x32[i];
549 
550 	/* 128-bit boundary */
551 	p += 8;
552 
553 	/* write scaling lists column by column */
554 
555 	for (i = 0; i < 6; i++)
556 		for (j = 0; j < 4; j++)
557 			for (k = 0; k < 4; k++)
558 				*p++ = sc->scaling_list_4x4[i][4 * k + j];
559 
560 	for (i = 0; i < 6; i++)
561 		for (j = 0; j < 8; j++)
562 			for (k = 0; k < 8; k++)
563 				*p++ = sc->scaling_list_8x8[i][8 * k + j];
564 
565 	for (i = 0; i < 6; i++)
566 		for (j = 0; j < 8; j++)
567 			for (k = 0; k < 8; k++)
568 				*p++ = sc->scaling_list_16x16[i][8 * k + j];
569 
570 	for (i = 0; i < 2; i++)
571 		for (j = 0; j < 8; j++)
572 			for (k = 0; k < 8; k++)
573 				*p++ = sc->scaling_list_32x32[i][8 * k + j];
574 
575 	hantro_write_addr(vpu, G2_HEVC_SCALING_LIST_ADDR, ctx->hevc_dec.scaling_lists.dma);
576 }
577 
hantro_g2_hevc_dec_run(struct hantro_ctx * ctx)578 int hantro_g2_hevc_dec_run(struct hantro_ctx *ctx)
579 {
580 	struct hantro_dev *vpu = ctx->dev;
581 	int ret;
582 
583 	hantro_g2_check_idle(vpu);
584 
585 	/* Prepare HEVC decoder context. */
586 	ret = hantro_hevc_dec_prepare_run(ctx);
587 	if (ret)
588 		return ret;
589 
590 	/* Configure hardware registers. */
591 	set_params(ctx);
592 
593 	/* set reference pictures */
594 	ret = set_ref(ctx);
595 	if (ret)
596 		return ret;
597 
598 	set_buffers(ctx);
599 	prepare_tile_info_buffer(ctx);
600 
601 	prepare_scaling_list_buffer(ctx);
602 
603 	hantro_end_prepare_run(ctx);
604 
605 	hantro_reg_write(vpu, &g2_mode, HEVC_DEC_MODE);
606 	hantro_reg_write(vpu, &g2_clk_gate_e, 1);
607 
608 	/* Don't disable output */
609 	hantro_reg_write(vpu, &g2_out_dis, 0);
610 
611 	/* Don't compress buffers */
612 	hantro_reg_write(vpu, &g2_ref_compress_bypass, 1);
613 
614 	/* Bus width and max burst */
615 	hantro_reg_write(vpu, &g2_buswidth, BUS_WIDTH_128);
616 	hantro_reg_write(vpu, &g2_max_burst, 16);
617 
618 	/* Swap */
619 	hantro_reg_write(vpu, &g2_strm_swap, 0xf);
620 	hantro_reg_write(vpu, &g2_dirmv_swap, 0xf);
621 	hantro_reg_write(vpu, &g2_compress_swap, 0xf);
622 
623 	/* Start decoding! */
624 	vdpu_write(vpu, G2_REG_INTERRUPT_DEC_E, G2_REG_INTERRUPT);
625 
626 	return 0;
627 }
628