1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /*
3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 */
24
25 #include <linux/ratelimit.h>
26 #include <linux/printk.h>
27 #include <linux/slab.h>
28 #include <linux/list.h>
29 #include <linux/types.h>
30 #include <linux/bitops.h>
31 #include <linux/sched.h>
32 #include "kfd_priv.h"
33 #include "kfd_device_queue_manager.h"
34 #include "kfd_mqd_manager.h"
35 #include "cik_regs.h"
36 #include "kfd_kernel_queue.h"
37 #include "amdgpu_amdkfd.h"
38 #include "mes_api_def.h"
39 #include "kfd_debug.h"
40
41 /* Size of the per-pipe EOP queue */
42 #define CIK_HPD_EOP_BYTES_LOG2 11
43 #define CIK_HPD_EOP_BYTES (1U << CIK_HPD_EOP_BYTES_LOG2)
44
45 static int set_pasid_vmid_mapping(struct device_queue_manager *dqm,
46 u32 pasid, unsigned int vmid);
47
48 static int execute_queues_cpsch(struct device_queue_manager *dqm,
49 enum kfd_unmap_queues_filter filter,
50 uint32_t filter_param,
51 uint32_t grace_period);
52 static int unmap_queues_cpsch(struct device_queue_manager *dqm,
53 enum kfd_unmap_queues_filter filter,
54 uint32_t filter_param,
55 uint32_t grace_period,
56 bool reset);
57
58 static int map_queues_cpsch(struct device_queue_manager *dqm);
59
60 static void deallocate_sdma_queue(struct device_queue_manager *dqm,
61 struct queue *q);
62
63 static inline void deallocate_hqd(struct device_queue_manager *dqm,
64 struct queue *q);
65 static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q);
66 static int allocate_sdma_queue(struct device_queue_manager *dqm,
67 struct queue *q, const uint32_t *restore_sdma_id);
68 static void kfd_process_hw_exception(struct work_struct *work);
69
70 static inline
get_mqd_type_from_queue_type(enum kfd_queue_type type)71 enum KFD_MQD_TYPE get_mqd_type_from_queue_type(enum kfd_queue_type type)
72 {
73 if (type == KFD_QUEUE_TYPE_SDMA || type == KFD_QUEUE_TYPE_SDMA_XGMI)
74 return KFD_MQD_TYPE_SDMA;
75 return KFD_MQD_TYPE_CP;
76 }
77
is_pipe_enabled(struct device_queue_manager * dqm,int mec,int pipe)78 static bool is_pipe_enabled(struct device_queue_manager *dqm, int mec, int pipe)
79 {
80 int i;
81 int pipe_offset = (mec * dqm->dev->kfd->shared_resources.num_pipe_per_mec
82 + pipe) * dqm->dev->kfd->shared_resources.num_queue_per_pipe;
83
84 /* queue is available for KFD usage if bit is 1 */
85 for (i = 0; i < dqm->dev->kfd->shared_resources.num_queue_per_pipe; ++i)
86 if (test_bit(pipe_offset + i,
87 dqm->dev->kfd->shared_resources.cp_queue_bitmap))
88 return true;
89 return false;
90 }
91
get_cp_queues_num(struct device_queue_manager * dqm)92 unsigned int get_cp_queues_num(struct device_queue_manager *dqm)
93 {
94 return bitmap_weight(dqm->dev->kfd->shared_resources.cp_queue_bitmap,
95 KGD_MAX_QUEUES);
96 }
97
get_queues_per_pipe(struct device_queue_manager * dqm)98 unsigned int get_queues_per_pipe(struct device_queue_manager *dqm)
99 {
100 return dqm->dev->kfd->shared_resources.num_queue_per_pipe;
101 }
102
get_pipes_per_mec(struct device_queue_manager * dqm)103 unsigned int get_pipes_per_mec(struct device_queue_manager *dqm)
104 {
105 return dqm->dev->kfd->shared_resources.num_pipe_per_mec;
106 }
107
get_num_all_sdma_engines(struct device_queue_manager * dqm)108 static unsigned int get_num_all_sdma_engines(struct device_queue_manager *dqm)
109 {
110 return kfd_get_num_sdma_engines(dqm->dev) +
111 kfd_get_num_xgmi_sdma_engines(dqm->dev);
112 }
113
get_num_sdma_queues(struct device_queue_manager * dqm)114 unsigned int get_num_sdma_queues(struct device_queue_manager *dqm)
115 {
116 return kfd_get_num_sdma_engines(dqm->dev) *
117 dqm->dev->kfd->device_info.num_sdma_queues_per_engine;
118 }
119
get_num_xgmi_sdma_queues(struct device_queue_manager * dqm)120 unsigned int get_num_xgmi_sdma_queues(struct device_queue_manager *dqm)
121 {
122 return kfd_get_num_xgmi_sdma_engines(dqm->dev) *
123 dqm->dev->kfd->device_info.num_sdma_queues_per_engine;
124 }
125
init_sdma_bitmaps(struct device_queue_manager * dqm)126 static void init_sdma_bitmaps(struct device_queue_manager *dqm)
127 {
128 bitmap_zero(dqm->sdma_bitmap, KFD_MAX_SDMA_QUEUES);
129 bitmap_set(dqm->sdma_bitmap, 0, get_num_sdma_queues(dqm));
130
131 bitmap_zero(dqm->xgmi_sdma_bitmap, KFD_MAX_SDMA_QUEUES);
132 bitmap_set(dqm->xgmi_sdma_bitmap, 0, get_num_xgmi_sdma_queues(dqm));
133
134 /* Mask out the reserved queues */
135 bitmap_andnot(dqm->sdma_bitmap, dqm->sdma_bitmap,
136 dqm->dev->kfd->device_info.reserved_sdma_queues_bitmap,
137 KFD_MAX_SDMA_QUEUES);
138 }
139
program_sh_mem_settings(struct device_queue_manager * dqm,struct qcm_process_device * qpd)140 void program_sh_mem_settings(struct device_queue_manager *dqm,
141 struct qcm_process_device *qpd)
142 {
143 uint32_t xcc_mask = dqm->dev->xcc_mask;
144 int xcc_id;
145
146 for_each_inst(xcc_id, xcc_mask)
147 dqm->dev->kfd2kgd->program_sh_mem_settings(
148 dqm->dev->adev, qpd->vmid, qpd->sh_mem_config,
149 qpd->sh_mem_ape1_base, qpd->sh_mem_ape1_limit,
150 qpd->sh_mem_bases, xcc_id);
151 }
152
kfd_hws_hang(struct device_queue_manager * dqm)153 static void kfd_hws_hang(struct device_queue_manager *dqm)
154 {
155 /*
156 * Issue a GPU reset if HWS is unresponsive
157 */
158 dqm->is_hws_hang = true;
159
160 /* It's possible we're detecting a HWS hang in the
161 * middle of a GPU reset. No need to schedule another
162 * reset in this case.
163 */
164 if (!dqm->is_resetting)
165 schedule_work(&dqm->hw_exception_work);
166 }
167
convert_to_mes_queue_type(int queue_type)168 static int convert_to_mes_queue_type(int queue_type)
169 {
170 int mes_queue_type;
171
172 switch (queue_type) {
173 case KFD_QUEUE_TYPE_COMPUTE:
174 mes_queue_type = MES_QUEUE_TYPE_COMPUTE;
175 break;
176 case KFD_QUEUE_TYPE_SDMA:
177 mes_queue_type = MES_QUEUE_TYPE_SDMA;
178 break;
179 default:
180 WARN(1, "Invalid queue type %d", queue_type);
181 mes_queue_type = -EINVAL;
182 break;
183 }
184
185 return mes_queue_type;
186 }
187
add_queue_mes(struct device_queue_manager * dqm,struct queue * q,struct qcm_process_device * qpd)188 static int add_queue_mes(struct device_queue_manager *dqm, struct queue *q,
189 struct qcm_process_device *qpd)
190 {
191 struct amdgpu_device *adev = (struct amdgpu_device *)dqm->dev->adev;
192 struct kfd_process_device *pdd = qpd_to_pdd(qpd);
193 struct mes_add_queue_input queue_input;
194 int r, queue_type;
195 uint64_t wptr_addr_off;
196
197 if (dqm->is_hws_hang)
198 return -EIO;
199
200 if (!pdd->proc_ctx_cpu_ptr) {
201 r = amdgpu_amdkfd_alloc_gtt_mem(adev,
202 AMDGPU_MES_PROC_CTX_SIZE,
203 &pdd->proc_ctx_bo,
204 &pdd->proc_ctx_gpu_addr,
205 &pdd->proc_ctx_cpu_ptr,
206 false);
207 if (r) {
208 dev_err(adev->dev,
209 "failed to allocate process context bo\n");
210 return r;
211 }
212 memset(pdd->proc_ctx_cpu_ptr, 0, AMDGPU_MES_PROC_CTX_SIZE);
213 }
214
215 memset(&queue_input, 0x0, sizeof(struct mes_add_queue_input));
216 queue_input.process_id = qpd->pqm->process->pasid;
217 queue_input.page_table_base_addr = qpd->page_table_base;
218 queue_input.process_va_start = 0;
219 queue_input.process_va_end = adev->vm_manager.max_pfn - 1;
220 /* MES unit for quantum is 100ns */
221 queue_input.process_quantum = KFD_MES_PROCESS_QUANTUM; /* Equivalent to 10ms. */
222 queue_input.process_context_addr = pdd->proc_ctx_gpu_addr;
223 queue_input.gang_quantum = KFD_MES_GANG_QUANTUM; /* Equivalent to 1ms */
224 queue_input.gang_context_addr = q->gang_ctx_gpu_addr;
225 queue_input.inprocess_gang_priority = q->properties.priority;
226 queue_input.gang_global_priority_level =
227 AMDGPU_MES_PRIORITY_LEVEL_NORMAL;
228 queue_input.doorbell_offset = q->properties.doorbell_off;
229 queue_input.mqd_addr = q->gart_mqd_addr;
230 queue_input.wptr_addr = (uint64_t)q->properties.write_ptr;
231
232 if (q->wptr_bo) {
233 wptr_addr_off = (uint64_t)q->properties.write_ptr & (PAGE_SIZE - 1);
234 queue_input.wptr_mc_addr = amdgpu_bo_gpu_offset(q->wptr_bo) + wptr_addr_off;
235 }
236
237 queue_input.is_kfd_process = 1;
238 queue_input.is_aql_queue = (q->properties.format == KFD_QUEUE_FORMAT_AQL);
239 queue_input.queue_size = q->properties.queue_size >> 2;
240
241 queue_input.paging = false;
242 queue_input.tba_addr = qpd->tba_addr;
243 queue_input.tma_addr = qpd->tma_addr;
244 queue_input.trap_en = !kfd_dbg_has_cwsr_workaround(q->device);
245 queue_input.skip_process_ctx_clear = qpd->pqm->process->debug_trap_enabled ||
246 kfd_dbg_has_ttmps_always_setup(q->device);
247
248 queue_type = convert_to_mes_queue_type(q->properties.type);
249 if (queue_type < 0) {
250 pr_err("Queue type not supported with MES, queue:%d\n",
251 q->properties.type);
252 return -EINVAL;
253 }
254 queue_input.queue_type = (uint32_t)queue_type;
255
256 queue_input.exclusively_scheduled = q->properties.is_gws;
257
258 amdgpu_mes_lock(&adev->mes);
259 r = adev->mes.funcs->add_hw_queue(&adev->mes, &queue_input);
260 amdgpu_mes_unlock(&adev->mes);
261 if (r) {
262 pr_err("failed to add hardware queue to MES, doorbell=0x%x\n",
263 q->properties.doorbell_off);
264 pr_err("MES might be in unrecoverable state, issue a GPU reset\n");
265 kfd_hws_hang(dqm);
266 }
267
268 return r;
269 }
270
remove_queue_mes(struct device_queue_manager * dqm,struct queue * q,struct qcm_process_device * qpd)271 static int remove_queue_mes(struct device_queue_manager *dqm, struct queue *q,
272 struct qcm_process_device *qpd)
273 {
274 struct amdgpu_device *adev = (struct amdgpu_device *)dqm->dev->adev;
275 int r;
276 struct mes_remove_queue_input queue_input;
277
278 if (dqm->is_hws_hang)
279 return -EIO;
280
281 memset(&queue_input, 0x0, sizeof(struct mes_remove_queue_input));
282 queue_input.doorbell_offset = q->properties.doorbell_off;
283 queue_input.gang_context_addr = q->gang_ctx_gpu_addr;
284
285 amdgpu_mes_lock(&adev->mes);
286 r = adev->mes.funcs->remove_hw_queue(&adev->mes, &queue_input);
287 amdgpu_mes_unlock(&adev->mes);
288
289 if (r) {
290 pr_err("failed to remove hardware queue from MES, doorbell=0x%x\n",
291 q->properties.doorbell_off);
292 pr_err("MES might be in unrecoverable state, issue a GPU reset\n");
293 kfd_hws_hang(dqm);
294 }
295
296 return r;
297 }
298
remove_all_queues_mes(struct device_queue_manager * dqm)299 static int remove_all_queues_mes(struct device_queue_manager *dqm)
300 {
301 struct device_process_node *cur;
302 struct qcm_process_device *qpd;
303 struct queue *q;
304 int retval = 0;
305
306 list_for_each_entry(cur, &dqm->queues, list) {
307 qpd = cur->qpd;
308 list_for_each_entry(q, &qpd->queues_list, list) {
309 if (q->properties.is_active) {
310 retval = remove_queue_mes(dqm, q, qpd);
311 if (retval) {
312 pr_err("%s: Failed to remove queue %d for dev %d",
313 __func__,
314 q->properties.queue_id,
315 dqm->dev->id);
316 return retval;
317 }
318 }
319 }
320 }
321
322 return retval;
323 }
324
increment_queue_count(struct device_queue_manager * dqm,struct qcm_process_device * qpd,struct queue * q)325 static void increment_queue_count(struct device_queue_manager *dqm,
326 struct qcm_process_device *qpd,
327 struct queue *q)
328 {
329 dqm->active_queue_count++;
330 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
331 q->properties.type == KFD_QUEUE_TYPE_DIQ)
332 dqm->active_cp_queue_count++;
333
334 if (q->properties.is_gws) {
335 dqm->gws_queue_count++;
336 qpd->mapped_gws_queue = true;
337 }
338 }
339
decrement_queue_count(struct device_queue_manager * dqm,struct qcm_process_device * qpd,struct queue * q)340 static void decrement_queue_count(struct device_queue_manager *dqm,
341 struct qcm_process_device *qpd,
342 struct queue *q)
343 {
344 dqm->active_queue_count--;
345 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
346 q->properties.type == KFD_QUEUE_TYPE_DIQ)
347 dqm->active_cp_queue_count--;
348
349 if (q->properties.is_gws) {
350 dqm->gws_queue_count--;
351 qpd->mapped_gws_queue = false;
352 }
353 }
354
355 /*
356 * Allocate a doorbell ID to this queue.
357 * If doorbell_id is passed in, make sure requested ID is valid then allocate it.
358 */
allocate_doorbell(struct qcm_process_device * qpd,struct queue * q,uint32_t const * restore_id)359 static int allocate_doorbell(struct qcm_process_device *qpd,
360 struct queue *q,
361 uint32_t const *restore_id)
362 {
363 struct kfd_node *dev = qpd->dqm->dev;
364
365 if (!KFD_IS_SOC15(dev)) {
366 /* On pre-SOC15 chips we need to use the queue ID to
367 * preserve the user mode ABI.
368 */
369
370 if (restore_id && *restore_id != q->properties.queue_id)
371 return -EINVAL;
372
373 q->doorbell_id = q->properties.queue_id;
374 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
375 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
376 /* For SDMA queues on SOC15 with 8-byte doorbell, use static
377 * doorbell assignments based on the engine and queue id.
378 * The doobell index distance between RLC (2*i) and (2*i+1)
379 * for a SDMA engine is 512.
380 */
381
382 uint32_t *idx_offset = dev->kfd->shared_resources.sdma_doorbell_idx;
383
384 /*
385 * q->properties.sdma_engine_id corresponds to the virtual
386 * sdma engine number. However, for doorbell allocation,
387 * we need the physical sdma engine id in order to get the
388 * correct doorbell offset.
389 */
390 uint32_t valid_id = idx_offset[qpd->dqm->dev->node_id *
391 get_num_all_sdma_engines(qpd->dqm) +
392 q->properties.sdma_engine_id]
393 + (q->properties.sdma_queue_id & 1)
394 * KFD_QUEUE_DOORBELL_MIRROR_OFFSET
395 + (q->properties.sdma_queue_id >> 1);
396
397 if (restore_id && *restore_id != valid_id)
398 return -EINVAL;
399 q->doorbell_id = valid_id;
400 } else {
401 /* For CP queues on SOC15 */
402 if (restore_id) {
403 /* make sure that ID is free */
404 if (__test_and_set_bit(*restore_id, qpd->doorbell_bitmap))
405 return -EINVAL;
406
407 q->doorbell_id = *restore_id;
408 } else {
409 /* or reserve a free doorbell ID */
410 unsigned int found;
411
412 found = find_first_zero_bit(qpd->doorbell_bitmap,
413 KFD_MAX_NUM_OF_QUEUES_PER_PROCESS);
414 if (found >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) {
415 pr_debug("No doorbells available");
416 return -EBUSY;
417 }
418 set_bit(found, qpd->doorbell_bitmap);
419 q->doorbell_id = found;
420 }
421 }
422
423 q->properties.doorbell_off = amdgpu_doorbell_index_on_bar(dev->adev,
424 qpd->proc_doorbells,
425 q->doorbell_id,
426 dev->kfd->device_info.doorbell_size);
427 return 0;
428 }
429
deallocate_doorbell(struct qcm_process_device * qpd,struct queue * q)430 static void deallocate_doorbell(struct qcm_process_device *qpd,
431 struct queue *q)
432 {
433 unsigned int old;
434 struct kfd_node *dev = qpd->dqm->dev;
435
436 if (!KFD_IS_SOC15(dev) ||
437 q->properties.type == KFD_QUEUE_TYPE_SDMA ||
438 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
439 return;
440
441 old = test_and_clear_bit(q->doorbell_id, qpd->doorbell_bitmap);
442 WARN_ON(!old);
443 }
444
program_trap_handler_settings(struct device_queue_manager * dqm,struct qcm_process_device * qpd)445 static void program_trap_handler_settings(struct device_queue_manager *dqm,
446 struct qcm_process_device *qpd)
447 {
448 uint32_t xcc_mask = dqm->dev->xcc_mask;
449 int xcc_id;
450
451 if (dqm->dev->kfd2kgd->program_trap_handler_settings)
452 for_each_inst(xcc_id, xcc_mask)
453 dqm->dev->kfd2kgd->program_trap_handler_settings(
454 dqm->dev->adev, qpd->vmid, qpd->tba_addr,
455 qpd->tma_addr, xcc_id);
456 }
457
allocate_vmid(struct device_queue_manager * dqm,struct qcm_process_device * qpd,struct queue * q)458 static int allocate_vmid(struct device_queue_manager *dqm,
459 struct qcm_process_device *qpd,
460 struct queue *q)
461 {
462 int allocated_vmid = -1, i;
463
464 for (i = dqm->dev->vm_info.first_vmid_kfd;
465 i <= dqm->dev->vm_info.last_vmid_kfd; i++) {
466 if (!dqm->vmid_pasid[i]) {
467 allocated_vmid = i;
468 break;
469 }
470 }
471
472 if (allocated_vmid < 0) {
473 pr_err("no more vmid to allocate\n");
474 return -ENOSPC;
475 }
476
477 pr_debug("vmid allocated: %d\n", allocated_vmid);
478
479 dqm->vmid_pasid[allocated_vmid] = q->process->pasid;
480
481 set_pasid_vmid_mapping(dqm, q->process->pasid, allocated_vmid);
482
483 qpd->vmid = allocated_vmid;
484 q->properties.vmid = allocated_vmid;
485
486 program_sh_mem_settings(dqm, qpd);
487
488 if (KFD_IS_SOC15(dqm->dev) && dqm->dev->kfd->cwsr_enabled)
489 program_trap_handler_settings(dqm, qpd);
490
491 /* qpd->page_table_base is set earlier when register_process()
492 * is called, i.e. when the first queue is created.
493 */
494 dqm->dev->kfd2kgd->set_vm_context_page_table_base(dqm->dev->adev,
495 qpd->vmid,
496 qpd->page_table_base);
497 /* invalidate the VM context after pasid and vmid mapping is set up */
498 kfd_flush_tlb(qpd_to_pdd(qpd), TLB_FLUSH_LEGACY);
499
500 if (dqm->dev->kfd2kgd->set_scratch_backing_va)
501 dqm->dev->kfd2kgd->set_scratch_backing_va(dqm->dev->adev,
502 qpd->sh_hidden_private_base, qpd->vmid);
503
504 return 0;
505 }
506
flush_texture_cache_nocpsch(struct kfd_node * kdev,struct qcm_process_device * qpd)507 static int flush_texture_cache_nocpsch(struct kfd_node *kdev,
508 struct qcm_process_device *qpd)
509 {
510 const struct packet_manager_funcs *pmf = qpd->dqm->packet_mgr.pmf;
511 int ret;
512
513 if (!qpd->ib_kaddr)
514 return -ENOMEM;
515
516 ret = pmf->release_mem(qpd->ib_base, (uint32_t *)qpd->ib_kaddr);
517 if (ret)
518 return ret;
519
520 return amdgpu_amdkfd_submit_ib(kdev->adev, KGD_ENGINE_MEC1, qpd->vmid,
521 qpd->ib_base, (uint32_t *)qpd->ib_kaddr,
522 pmf->release_mem_size / sizeof(uint32_t));
523 }
524
deallocate_vmid(struct device_queue_manager * dqm,struct qcm_process_device * qpd,struct queue * q)525 static void deallocate_vmid(struct device_queue_manager *dqm,
526 struct qcm_process_device *qpd,
527 struct queue *q)
528 {
529 /* On GFX v7, CP doesn't flush TC at dequeue */
530 if (q->device->adev->asic_type == CHIP_HAWAII)
531 if (flush_texture_cache_nocpsch(q->device, qpd))
532 pr_err("Failed to flush TC\n");
533
534 kfd_flush_tlb(qpd_to_pdd(qpd), TLB_FLUSH_LEGACY);
535
536 /* Release the vmid mapping */
537 set_pasid_vmid_mapping(dqm, 0, qpd->vmid);
538 dqm->vmid_pasid[qpd->vmid] = 0;
539
540 qpd->vmid = 0;
541 q->properties.vmid = 0;
542 }
543
create_queue_nocpsch(struct device_queue_manager * dqm,struct queue * q,struct qcm_process_device * qpd,const struct kfd_criu_queue_priv_data * qd,const void * restore_mqd,const void * restore_ctl_stack)544 static int create_queue_nocpsch(struct device_queue_manager *dqm,
545 struct queue *q,
546 struct qcm_process_device *qpd,
547 const struct kfd_criu_queue_priv_data *qd,
548 const void *restore_mqd, const void *restore_ctl_stack)
549 {
550 struct mqd_manager *mqd_mgr;
551 int retval;
552
553 dqm_lock(dqm);
554
555 if (dqm->total_queue_count >= max_num_of_queues_per_device) {
556 pr_warn("Can't create new usermode queue because %d queues were already created\n",
557 dqm->total_queue_count);
558 retval = -EPERM;
559 goto out_unlock;
560 }
561
562 if (list_empty(&qpd->queues_list)) {
563 retval = allocate_vmid(dqm, qpd, q);
564 if (retval)
565 goto out_unlock;
566 }
567 q->properties.vmid = qpd->vmid;
568 /*
569 * Eviction state logic: mark all queues as evicted, even ones
570 * not currently active. Restoring inactive queues later only
571 * updates the is_evicted flag but is a no-op otherwise.
572 */
573 q->properties.is_evicted = !!qpd->evicted;
574
575 q->properties.tba_addr = qpd->tba_addr;
576 q->properties.tma_addr = qpd->tma_addr;
577
578 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
579 q->properties.type)];
580 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) {
581 retval = allocate_hqd(dqm, q);
582 if (retval)
583 goto deallocate_vmid;
584 pr_debug("Loading mqd to hqd on pipe %d, queue %d\n",
585 q->pipe, q->queue);
586 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
587 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
588 retval = allocate_sdma_queue(dqm, q, qd ? &qd->sdma_id : NULL);
589 if (retval)
590 goto deallocate_vmid;
591 dqm->asic_ops.init_sdma_vm(dqm, q, qpd);
592 }
593
594 retval = allocate_doorbell(qpd, q, qd ? &qd->doorbell_id : NULL);
595 if (retval)
596 goto out_deallocate_hqd;
597
598 /* Temporarily release dqm lock to avoid a circular lock dependency */
599 dqm_unlock(dqm);
600 q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr->dev, &q->properties);
601 dqm_lock(dqm);
602
603 if (!q->mqd_mem_obj) {
604 retval = -ENOMEM;
605 goto out_deallocate_doorbell;
606 }
607
608 if (qd)
609 mqd_mgr->restore_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj, &q->gart_mqd_addr,
610 &q->properties, restore_mqd, restore_ctl_stack,
611 qd->ctl_stack_size);
612 else
613 mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj,
614 &q->gart_mqd_addr, &q->properties);
615
616 if (q->properties.is_active) {
617 if (!dqm->sched_running) {
618 WARN_ONCE(1, "Load non-HWS mqd while stopped\n");
619 goto add_queue_to_list;
620 }
621
622 if (WARN(q->process->mm != current->mm,
623 "should only run in user thread"))
624 retval = -EFAULT;
625 else
626 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe,
627 q->queue, &q->properties, current->mm);
628 if (retval)
629 goto out_free_mqd;
630 }
631
632 add_queue_to_list:
633 list_add(&q->list, &qpd->queues_list);
634 qpd->queue_count++;
635 if (q->properties.is_active)
636 increment_queue_count(dqm, qpd, q);
637
638 /*
639 * Unconditionally increment this counter, regardless of the queue's
640 * type or whether the queue is active.
641 */
642 dqm->total_queue_count++;
643 pr_debug("Total of %d queues are accountable so far\n",
644 dqm->total_queue_count);
645 goto out_unlock;
646
647 out_free_mqd:
648 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
649 out_deallocate_doorbell:
650 deallocate_doorbell(qpd, q);
651 out_deallocate_hqd:
652 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE)
653 deallocate_hqd(dqm, q);
654 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
655 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
656 deallocate_sdma_queue(dqm, q);
657 deallocate_vmid:
658 if (list_empty(&qpd->queues_list))
659 deallocate_vmid(dqm, qpd, q);
660 out_unlock:
661 dqm_unlock(dqm);
662 return retval;
663 }
664
allocate_hqd(struct device_queue_manager * dqm,struct queue * q)665 static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q)
666 {
667 bool set;
668 int pipe, bit, i;
669
670 set = false;
671
672 for (pipe = dqm->next_pipe_to_allocate, i = 0;
673 i < get_pipes_per_mec(dqm);
674 pipe = ((pipe + 1) % get_pipes_per_mec(dqm)), ++i) {
675
676 if (!is_pipe_enabled(dqm, 0, pipe))
677 continue;
678
679 if (dqm->allocated_queues[pipe] != 0) {
680 bit = ffs(dqm->allocated_queues[pipe]) - 1;
681 dqm->allocated_queues[pipe] &= ~(1 << bit);
682 q->pipe = pipe;
683 q->queue = bit;
684 set = true;
685 break;
686 }
687 }
688
689 if (!set)
690 return -EBUSY;
691
692 pr_debug("hqd slot - pipe %d, queue %d\n", q->pipe, q->queue);
693 /* horizontal hqd allocation */
694 dqm->next_pipe_to_allocate = (pipe + 1) % get_pipes_per_mec(dqm);
695
696 return 0;
697 }
698
deallocate_hqd(struct device_queue_manager * dqm,struct queue * q)699 static inline void deallocate_hqd(struct device_queue_manager *dqm,
700 struct queue *q)
701 {
702 dqm->allocated_queues[q->pipe] |= (1 << q->queue);
703 }
704
705 #define SQ_IND_CMD_CMD_KILL 0x00000003
706 #define SQ_IND_CMD_MODE_BROADCAST 0x00000001
707
dbgdev_wave_reset_wavefronts(struct kfd_node * dev,struct kfd_process * p)708 static int dbgdev_wave_reset_wavefronts(struct kfd_node *dev, struct kfd_process *p)
709 {
710 int status = 0;
711 unsigned int vmid;
712 uint16_t queried_pasid;
713 union SQ_CMD_BITS reg_sq_cmd;
714 union GRBM_GFX_INDEX_BITS reg_gfx_index;
715 struct kfd_process_device *pdd;
716 int first_vmid_to_scan = dev->vm_info.first_vmid_kfd;
717 int last_vmid_to_scan = dev->vm_info.last_vmid_kfd;
718 uint32_t xcc_mask = dev->xcc_mask;
719 int xcc_id;
720
721 reg_sq_cmd.u32All = 0;
722 reg_gfx_index.u32All = 0;
723
724 pr_debug("Killing all process wavefronts\n");
725
726 if (!dev->kfd2kgd->get_atc_vmid_pasid_mapping_info) {
727 pr_err("no vmid pasid mapping supported \n");
728 return -EOPNOTSUPP;
729 }
730
731 /* Scan all registers in the range ATC_VMID8_PASID_MAPPING ..
732 * ATC_VMID15_PASID_MAPPING
733 * to check which VMID the current process is mapped to.
734 */
735
736 for (vmid = first_vmid_to_scan; vmid <= last_vmid_to_scan; vmid++) {
737 status = dev->kfd2kgd->get_atc_vmid_pasid_mapping_info
738 (dev->adev, vmid, &queried_pasid);
739
740 if (status && queried_pasid == p->pasid) {
741 pr_debug("Killing wave fronts of vmid %d and pasid 0x%x\n",
742 vmid, p->pasid);
743 break;
744 }
745 }
746
747 if (vmid > last_vmid_to_scan) {
748 pr_err("Didn't find vmid for pasid 0x%x\n", p->pasid);
749 return -EFAULT;
750 }
751
752 /* taking the VMID for that process on the safe way using PDD */
753 pdd = kfd_get_process_device_data(dev, p);
754 if (!pdd)
755 return -EFAULT;
756
757 reg_gfx_index.bits.sh_broadcast_writes = 1;
758 reg_gfx_index.bits.se_broadcast_writes = 1;
759 reg_gfx_index.bits.instance_broadcast_writes = 1;
760 reg_sq_cmd.bits.mode = SQ_IND_CMD_MODE_BROADCAST;
761 reg_sq_cmd.bits.cmd = SQ_IND_CMD_CMD_KILL;
762 reg_sq_cmd.bits.vm_id = vmid;
763
764 for_each_inst(xcc_id, xcc_mask)
765 dev->kfd2kgd->wave_control_execute(
766 dev->adev, reg_gfx_index.u32All,
767 reg_sq_cmd.u32All, xcc_id);
768
769 return 0;
770 }
771
772 /* Access to DQM has to be locked before calling destroy_queue_nocpsch_locked
773 * to avoid asynchronized access
774 */
destroy_queue_nocpsch_locked(struct device_queue_manager * dqm,struct qcm_process_device * qpd,struct queue * q)775 static int destroy_queue_nocpsch_locked(struct device_queue_manager *dqm,
776 struct qcm_process_device *qpd,
777 struct queue *q)
778 {
779 int retval;
780 struct mqd_manager *mqd_mgr;
781
782 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
783 q->properties.type)];
784
785 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE)
786 deallocate_hqd(dqm, q);
787 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
788 deallocate_sdma_queue(dqm, q);
789 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
790 deallocate_sdma_queue(dqm, q);
791 else {
792 pr_debug("q->properties.type %d is invalid\n",
793 q->properties.type);
794 return -EINVAL;
795 }
796 dqm->total_queue_count--;
797
798 deallocate_doorbell(qpd, q);
799
800 if (!dqm->sched_running) {
801 WARN_ONCE(1, "Destroy non-HWS queue while stopped\n");
802 return 0;
803 }
804
805 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd,
806 KFD_PREEMPT_TYPE_WAVEFRONT_RESET,
807 KFD_UNMAP_LATENCY_MS,
808 q->pipe, q->queue);
809 if (retval == -ETIME)
810 qpd->reset_wavefronts = true;
811
812 list_del(&q->list);
813 if (list_empty(&qpd->queues_list)) {
814 if (qpd->reset_wavefronts) {
815 pr_warn("Resetting wave fronts (nocpsch) on dev %p\n",
816 dqm->dev);
817 /* dbgdev_wave_reset_wavefronts has to be called before
818 * deallocate_vmid(), i.e. when vmid is still in use.
819 */
820 dbgdev_wave_reset_wavefronts(dqm->dev,
821 qpd->pqm->process);
822 qpd->reset_wavefronts = false;
823 }
824
825 deallocate_vmid(dqm, qpd, q);
826 }
827 qpd->queue_count--;
828 if (q->properties.is_active)
829 decrement_queue_count(dqm, qpd, q);
830
831 return retval;
832 }
833
destroy_queue_nocpsch(struct device_queue_manager * dqm,struct qcm_process_device * qpd,struct queue * q)834 static int destroy_queue_nocpsch(struct device_queue_manager *dqm,
835 struct qcm_process_device *qpd,
836 struct queue *q)
837 {
838 int retval;
839 uint64_t sdma_val = 0;
840 struct kfd_process_device *pdd = qpd_to_pdd(qpd);
841 struct mqd_manager *mqd_mgr =
842 dqm->mqd_mgrs[get_mqd_type_from_queue_type(q->properties.type)];
843
844 /* Get the SDMA queue stats */
845 if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) ||
846 (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) {
847 retval = read_sdma_queue_counter((uint64_t __user *)q->properties.read_ptr,
848 &sdma_val);
849 if (retval)
850 pr_err("Failed to read SDMA queue counter for queue: %d\n",
851 q->properties.queue_id);
852 }
853
854 dqm_lock(dqm);
855 retval = destroy_queue_nocpsch_locked(dqm, qpd, q);
856 if (!retval)
857 pdd->sdma_past_activity_counter += sdma_val;
858 dqm_unlock(dqm);
859
860 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
861
862 return retval;
863 }
864
update_queue(struct device_queue_manager * dqm,struct queue * q,struct mqd_update_info * minfo)865 static int update_queue(struct device_queue_manager *dqm, struct queue *q,
866 struct mqd_update_info *minfo)
867 {
868 int retval = 0;
869 struct mqd_manager *mqd_mgr;
870 struct kfd_process_device *pdd;
871 bool prev_active = false;
872
873 dqm_lock(dqm);
874 pdd = kfd_get_process_device_data(q->device, q->process);
875 if (!pdd) {
876 retval = -ENODEV;
877 goto out_unlock;
878 }
879 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
880 q->properties.type)];
881
882 /* Save previous activity state for counters */
883 prev_active = q->properties.is_active;
884
885 /* Make sure the queue is unmapped before updating the MQD */
886 if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) {
887 if (!dqm->dev->kfd->shared_resources.enable_mes)
888 retval = unmap_queues_cpsch(dqm,
889 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD, false);
890 else if (prev_active)
891 retval = remove_queue_mes(dqm, q, &pdd->qpd);
892
893 if (retval) {
894 pr_err("unmap queue failed\n");
895 goto out_unlock;
896 }
897 } else if (prev_active &&
898 (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
899 q->properties.type == KFD_QUEUE_TYPE_SDMA ||
900 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) {
901
902 if (!dqm->sched_running) {
903 WARN_ONCE(1, "Update non-HWS queue while stopped\n");
904 goto out_unlock;
905 }
906
907 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd,
908 (dqm->dev->kfd->cwsr_enabled ?
909 KFD_PREEMPT_TYPE_WAVEFRONT_SAVE :
910 KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN),
911 KFD_UNMAP_LATENCY_MS, q->pipe, q->queue);
912 if (retval) {
913 pr_err("destroy mqd failed\n");
914 goto out_unlock;
915 }
916 }
917
918 mqd_mgr->update_mqd(mqd_mgr, q->mqd, &q->properties, minfo);
919
920 /*
921 * check active state vs. the previous state and modify
922 * counter accordingly. map_queues_cpsch uses the
923 * dqm->active_queue_count to determine whether a new runlist must be
924 * uploaded.
925 */
926 if (q->properties.is_active && !prev_active) {
927 increment_queue_count(dqm, &pdd->qpd, q);
928 } else if (!q->properties.is_active && prev_active) {
929 decrement_queue_count(dqm, &pdd->qpd, q);
930 } else if (q->gws && !q->properties.is_gws) {
931 if (q->properties.is_active) {
932 dqm->gws_queue_count++;
933 pdd->qpd.mapped_gws_queue = true;
934 }
935 q->properties.is_gws = true;
936 } else if (!q->gws && q->properties.is_gws) {
937 if (q->properties.is_active) {
938 dqm->gws_queue_count--;
939 pdd->qpd.mapped_gws_queue = false;
940 }
941 q->properties.is_gws = false;
942 }
943
944 if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) {
945 if (!dqm->dev->kfd->shared_resources.enable_mes)
946 retval = map_queues_cpsch(dqm);
947 else if (q->properties.is_active)
948 retval = add_queue_mes(dqm, q, &pdd->qpd);
949 } else if (q->properties.is_active &&
950 (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
951 q->properties.type == KFD_QUEUE_TYPE_SDMA ||
952 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) {
953 if (WARN(q->process->mm != current->mm,
954 "should only run in user thread"))
955 retval = -EFAULT;
956 else
957 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd,
958 q->pipe, q->queue,
959 &q->properties, current->mm);
960 }
961
962 out_unlock:
963 dqm_unlock(dqm);
964 return retval;
965 }
966
967 /* suspend_single_queue does not lock the dqm like the
968 * evict_process_queues_cpsch or evict_process_queues_nocpsch. You should
969 * lock the dqm before calling, and unlock after calling.
970 *
971 * The reason we don't lock the dqm is because this function may be
972 * called on multiple queues in a loop, so rather than locking/unlocking
973 * multiple times, we will just keep the dqm locked for all of the calls.
974 */
suspend_single_queue(struct device_queue_manager * dqm,struct kfd_process_device * pdd,struct queue * q)975 static int suspend_single_queue(struct device_queue_manager *dqm,
976 struct kfd_process_device *pdd,
977 struct queue *q)
978 {
979 bool is_new;
980
981 if (q->properties.is_suspended)
982 return 0;
983
984 pr_debug("Suspending PASID %u queue [%i]\n",
985 pdd->process->pasid,
986 q->properties.queue_id);
987
988 is_new = q->properties.exception_status & KFD_EC_MASK(EC_QUEUE_NEW);
989
990 if (is_new || q->properties.is_being_destroyed) {
991 pr_debug("Suspend: skip %s queue id %i\n",
992 is_new ? "new" : "destroyed",
993 q->properties.queue_id);
994 return -EBUSY;
995 }
996
997 q->properties.is_suspended = true;
998 if (q->properties.is_active) {
999 if (dqm->dev->kfd->shared_resources.enable_mes) {
1000 int r = remove_queue_mes(dqm, q, &pdd->qpd);
1001
1002 if (r)
1003 return r;
1004 }
1005
1006 decrement_queue_count(dqm, &pdd->qpd, q);
1007 q->properties.is_active = false;
1008 }
1009
1010 return 0;
1011 }
1012
1013 /* resume_single_queue does not lock the dqm like the functions
1014 * restore_process_queues_cpsch or restore_process_queues_nocpsch. You should
1015 * lock the dqm before calling, and unlock after calling.
1016 *
1017 * The reason we don't lock the dqm is because this function may be
1018 * called on multiple queues in a loop, so rather than locking/unlocking
1019 * multiple times, we will just keep the dqm locked for all of the calls.
1020 */
resume_single_queue(struct device_queue_manager * dqm,struct qcm_process_device * qpd,struct queue * q)1021 static int resume_single_queue(struct device_queue_manager *dqm,
1022 struct qcm_process_device *qpd,
1023 struct queue *q)
1024 {
1025 struct kfd_process_device *pdd;
1026
1027 if (!q->properties.is_suspended)
1028 return 0;
1029
1030 pdd = qpd_to_pdd(qpd);
1031
1032 pr_debug("Restoring from suspend PASID %u queue [%i]\n",
1033 pdd->process->pasid,
1034 q->properties.queue_id);
1035
1036 q->properties.is_suspended = false;
1037
1038 if (QUEUE_IS_ACTIVE(q->properties)) {
1039 if (dqm->dev->kfd->shared_resources.enable_mes) {
1040 int r = add_queue_mes(dqm, q, &pdd->qpd);
1041
1042 if (r)
1043 return r;
1044 }
1045
1046 q->properties.is_active = true;
1047 increment_queue_count(dqm, qpd, q);
1048 }
1049
1050 return 0;
1051 }
1052
evict_process_queues_nocpsch(struct device_queue_manager * dqm,struct qcm_process_device * qpd)1053 static int evict_process_queues_nocpsch(struct device_queue_manager *dqm,
1054 struct qcm_process_device *qpd)
1055 {
1056 struct queue *q;
1057 struct mqd_manager *mqd_mgr;
1058 struct kfd_process_device *pdd;
1059 int retval, ret = 0;
1060
1061 dqm_lock(dqm);
1062 if (qpd->evicted++ > 0) /* already evicted, do nothing */
1063 goto out;
1064
1065 pdd = qpd_to_pdd(qpd);
1066 pr_debug_ratelimited("Evicting PASID 0x%x queues\n",
1067 pdd->process->pasid);
1068
1069 pdd->last_evict_timestamp = get_jiffies_64();
1070 /* Mark all queues as evicted. Deactivate all active queues on
1071 * the qpd.
1072 */
1073 list_for_each_entry(q, &qpd->queues_list, list) {
1074 q->properties.is_evicted = true;
1075 if (!q->properties.is_active)
1076 continue;
1077
1078 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
1079 q->properties.type)];
1080 q->properties.is_active = false;
1081 decrement_queue_count(dqm, qpd, q);
1082
1083 if (WARN_ONCE(!dqm->sched_running, "Evict when stopped\n"))
1084 continue;
1085
1086 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd,
1087 (dqm->dev->kfd->cwsr_enabled ?
1088 KFD_PREEMPT_TYPE_WAVEFRONT_SAVE :
1089 KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN),
1090 KFD_UNMAP_LATENCY_MS, q->pipe, q->queue);
1091 if (retval && !ret)
1092 /* Return the first error, but keep going to
1093 * maintain a consistent eviction state
1094 */
1095 ret = retval;
1096 }
1097
1098 out:
1099 dqm_unlock(dqm);
1100 return ret;
1101 }
1102
evict_process_queues_cpsch(struct device_queue_manager * dqm,struct qcm_process_device * qpd)1103 static int evict_process_queues_cpsch(struct device_queue_manager *dqm,
1104 struct qcm_process_device *qpd)
1105 {
1106 struct queue *q;
1107 struct kfd_process_device *pdd;
1108 int retval = 0;
1109
1110 dqm_lock(dqm);
1111 if (qpd->evicted++ > 0) /* already evicted, do nothing */
1112 goto out;
1113
1114 pdd = qpd_to_pdd(qpd);
1115
1116 /* The debugger creates processes that temporarily have not acquired
1117 * all VMs for all devices and has no VMs itself.
1118 * Skip queue eviction on process eviction.
1119 */
1120 if (!pdd->drm_priv)
1121 goto out;
1122
1123 pr_debug_ratelimited("Evicting PASID 0x%x queues\n",
1124 pdd->process->pasid);
1125
1126 /* Mark all queues as evicted. Deactivate all active queues on
1127 * the qpd.
1128 */
1129 list_for_each_entry(q, &qpd->queues_list, list) {
1130 q->properties.is_evicted = true;
1131 if (!q->properties.is_active)
1132 continue;
1133
1134 q->properties.is_active = false;
1135 decrement_queue_count(dqm, qpd, q);
1136
1137 if (dqm->dev->kfd->shared_resources.enable_mes) {
1138 retval = remove_queue_mes(dqm, q, qpd);
1139 if (retval) {
1140 pr_err("Failed to evict queue %d\n",
1141 q->properties.queue_id);
1142 goto out;
1143 }
1144 }
1145 }
1146 pdd->last_evict_timestamp = get_jiffies_64();
1147 if (!dqm->dev->kfd->shared_resources.enable_mes)
1148 retval = execute_queues_cpsch(dqm,
1149 qpd->is_debug ?
1150 KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES :
1151 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0,
1152 USE_DEFAULT_GRACE_PERIOD);
1153
1154 out:
1155 dqm_unlock(dqm);
1156 return retval;
1157 }
1158
restore_process_queues_nocpsch(struct device_queue_manager * dqm,struct qcm_process_device * qpd)1159 static int restore_process_queues_nocpsch(struct device_queue_manager *dqm,
1160 struct qcm_process_device *qpd)
1161 {
1162 struct mm_struct *mm = NULL;
1163 struct queue *q;
1164 struct mqd_manager *mqd_mgr;
1165 struct kfd_process_device *pdd;
1166 uint64_t pd_base;
1167 uint64_t eviction_duration;
1168 int retval, ret = 0;
1169
1170 pdd = qpd_to_pdd(qpd);
1171 /* Retrieve PD base */
1172 pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv);
1173
1174 dqm_lock(dqm);
1175 if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */
1176 goto out;
1177 if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */
1178 qpd->evicted--;
1179 goto out;
1180 }
1181
1182 pr_debug_ratelimited("Restoring PASID 0x%x queues\n",
1183 pdd->process->pasid);
1184
1185 /* Update PD Base in QPD */
1186 qpd->page_table_base = pd_base;
1187 pr_debug("Updated PD address to 0x%llx\n", pd_base);
1188
1189 if (!list_empty(&qpd->queues_list)) {
1190 dqm->dev->kfd2kgd->set_vm_context_page_table_base(
1191 dqm->dev->adev,
1192 qpd->vmid,
1193 qpd->page_table_base);
1194 kfd_flush_tlb(pdd, TLB_FLUSH_LEGACY);
1195 }
1196
1197 /* Take a safe reference to the mm_struct, which may otherwise
1198 * disappear even while the kfd_process is still referenced.
1199 */
1200 mm = get_task_mm(pdd->process->lead_thread);
1201 if (!mm) {
1202 ret = -EFAULT;
1203 goto out;
1204 }
1205
1206 /* Remove the eviction flags. Activate queues that are not
1207 * inactive for other reasons.
1208 */
1209 list_for_each_entry(q, &qpd->queues_list, list) {
1210 q->properties.is_evicted = false;
1211 if (!QUEUE_IS_ACTIVE(q->properties))
1212 continue;
1213
1214 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
1215 q->properties.type)];
1216 q->properties.is_active = true;
1217 increment_queue_count(dqm, qpd, q);
1218
1219 if (WARN_ONCE(!dqm->sched_running, "Restore when stopped\n"))
1220 continue;
1221
1222 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe,
1223 q->queue, &q->properties, mm);
1224 if (retval && !ret)
1225 /* Return the first error, but keep going to
1226 * maintain a consistent eviction state
1227 */
1228 ret = retval;
1229 }
1230 qpd->evicted = 0;
1231 eviction_duration = get_jiffies_64() - pdd->last_evict_timestamp;
1232 atomic64_add(eviction_duration, &pdd->evict_duration_counter);
1233 out:
1234 if (mm)
1235 mmput(mm);
1236 dqm_unlock(dqm);
1237 return ret;
1238 }
1239
restore_process_queues_cpsch(struct device_queue_manager * dqm,struct qcm_process_device * qpd)1240 static int restore_process_queues_cpsch(struct device_queue_manager *dqm,
1241 struct qcm_process_device *qpd)
1242 {
1243 struct queue *q;
1244 struct kfd_process_device *pdd;
1245 uint64_t eviction_duration;
1246 int retval = 0;
1247
1248 pdd = qpd_to_pdd(qpd);
1249
1250 dqm_lock(dqm);
1251 if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */
1252 goto out;
1253 if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */
1254 qpd->evicted--;
1255 goto out;
1256 }
1257
1258 /* The debugger creates processes that temporarily have not acquired
1259 * all VMs for all devices and has no VMs itself.
1260 * Skip queue restore on process restore.
1261 */
1262 if (!pdd->drm_priv)
1263 goto vm_not_acquired;
1264
1265 pr_debug_ratelimited("Restoring PASID 0x%x queues\n",
1266 pdd->process->pasid);
1267
1268 /* Update PD Base in QPD */
1269 qpd->page_table_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv);
1270 pr_debug("Updated PD address to 0x%llx\n", qpd->page_table_base);
1271
1272 /* activate all active queues on the qpd */
1273 list_for_each_entry(q, &qpd->queues_list, list) {
1274 q->properties.is_evicted = false;
1275 if (!QUEUE_IS_ACTIVE(q->properties))
1276 continue;
1277
1278 q->properties.is_active = true;
1279 increment_queue_count(dqm, &pdd->qpd, q);
1280
1281 if (dqm->dev->kfd->shared_resources.enable_mes) {
1282 retval = add_queue_mes(dqm, q, qpd);
1283 if (retval) {
1284 pr_err("Failed to restore queue %d\n",
1285 q->properties.queue_id);
1286 goto out;
1287 }
1288 }
1289 }
1290 if (!dqm->dev->kfd->shared_resources.enable_mes)
1291 retval = execute_queues_cpsch(dqm,
1292 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD);
1293 eviction_duration = get_jiffies_64() - pdd->last_evict_timestamp;
1294 atomic64_add(eviction_duration, &pdd->evict_duration_counter);
1295 vm_not_acquired:
1296 qpd->evicted = 0;
1297 out:
1298 dqm_unlock(dqm);
1299 return retval;
1300 }
1301
register_process(struct device_queue_manager * dqm,struct qcm_process_device * qpd)1302 static int register_process(struct device_queue_manager *dqm,
1303 struct qcm_process_device *qpd)
1304 {
1305 struct device_process_node *n;
1306 struct kfd_process_device *pdd;
1307 uint64_t pd_base;
1308 int retval;
1309
1310 n = kzalloc(sizeof(*n), GFP_KERNEL);
1311 if (!n)
1312 return -ENOMEM;
1313
1314 n->qpd = qpd;
1315
1316 pdd = qpd_to_pdd(qpd);
1317 /* Retrieve PD base */
1318 pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv);
1319
1320 dqm_lock(dqm);
1321 list_add(&n->list, &dqm->queues);
1322
1323 /* Update PD Base in QPD */
1324 qpd->page_table_base = pd_base;
1325 pr_debug("Updated PD address to 0x%llx\n", pd_base);
1326
1327 retval = dqm->asic_ops.update_qpd(dqm, qpd);
1328
1329 dqm->processes_count++;
1330
1331 dqm_unlock(dqm);
1332
1333 /* Outside the DQM lock because under the DQM lock we can't do
1334 * reclaim or take other locks that others hold while reclaiming.
1335 */
1336 kfd_inc_compute_active(dqm->dev);
1337
1338 return retval;
1339 }
1340
unregister_process(struct device_queue_manager * dqm,struct qcm_process_device * qpd)1341 static int unregister_process(struct device_queue_manager *dqm,
1342 struct qcm_process_device *qpd)
1343 {
1344 int retval;
1345 struct device_process_node *cur, *next;
1346
1347 pr_debug("qpd->queues_list is %s\n",
1348 list_empty(&qpd->queues_list) ? "empty" : "not empty");
1349
1350 retval = 0;
1351 dqm_lock(dqm);
1352
1353 list_for_each_entry_safe(cur, next, &dqm->queues, list) {
1354 if (qpd == cur->qpd) {
1355 list_del(&cur->list);
1356 kfree(cur);
1357 dqm->processes_count--;
1358 goto out;
1359 }
1360 }
1361 /* qpd not found in dqm list */
1362 retval = 1;
1363 out:
1364 dqm_unlock(dqm);
1365
1366 /* Outside the DQM lock because under the DQM lock we can't do
1367 * reclaim or take other locks that others hold while reclaiming.
1368 */
1369 if (!retval)
1370 kfd_dec_compute_active(dqm->dev);
1371
1372 return retval;
1373 }
1374
1375 static int
set_pasid_vmid_mapping(struct device_queue_manager * dqm,u32 pasid,unsigned int vmid)1376 set_pasid_vmid_mapping(struct device_queue_manager *dqm, u32 pasid,
1377 unsigned int vmid)
1378 {
1379 uint32_t xcc_mask = dqm->dev->xcc_mask;
1380 int xcc_id, ret;
1381
1382 for_each_inst(xcc_id, xcc_mask) {
1383 ret = dqm->dev->kfd2kgd->set_pasid_vmid_mapping(
1384 dqm->dev->adev, pasid, vmid, xcc_id);
1385 if (ret)
1386 break;
1387 }
1388
1389 return ret;
1390 }
1391
init_interrupts(struct device_queue_manager * dqm)1392 static void init_interrupts(struct device_queue_manager *dqm)
1393 {
1394 uint32_t xcc_mask = dqm->dev->xcc_mask;
1395 unsigned int i, xcc_id;
1396
1397 for_each_inst(xcc_id, xcc_mask) {
1398 for (i = 0 ; i < get_pipes_per_mec(dqm) ; i++) {
1399 if (is_pipe_enabled(dqm, 0, i)) {
1400 dqm->dev->kfd2kgd->init_interrupts(
1401 dqm->dev->adev, i, xcc_id);
1402 }
1403 }
1404 }
1405 }
1406
initialize_nocpsch(struct device_queue_manager * dqm)1407 static int initialize_nocpsch(struct device_queue_manager *dqm)
1408 {
1409 int pipe, queue;
1410
1411 pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm));
1412
1413 dqm->allocated_queues = kcalloc(get_pipes_per_mec(dqm),
1414 sizeof(unsigned int), GFP_KERNEL);
1415 if (!dqm->allocated_queues)
1416 return -ENOMEM;
1417
1418 mutex_init(&dqm->lock_hidden);
1419 INIT_LIST_HEAD(&dqm->queues);
1420 dqm->active_queue_count = dqm->next_pipe_to_allocate = 0;
1421 dqm->active_cp_queue_count = 0;
1422 dqm->gws_queue_count = 0;
1423
1424 for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) {
1425 int pipe_offset = pipe * get_queues_per_pipe(dqm);
1426
1427 for (queue = 0; queue < get_queues_per_pipe(dqm); queue++)
1428 if (test_bit(pipe_offset + queue,
1429 dqm->dev->kfd->shared_resources.cp_queue_bitmap))
1430 dqm->allocated_queues[pipe] |= 1 << queue;
1431 }
1432
1433 memset(dqm->vmid_pasid, 0, sizeof(dqm->vmid_pasid));
1434
1435 init_sdma_bitmaps(dqm);
1436
1437 return 0;
1438 }
1439
uninitialize(struct device_queue_manager * dqm)1440 static void uninitialize(struct device_queue_manager *dqm)
1441 {
1442 int i;
1443
1444 WARN_ON(dqm->active_queue_count > 0 || dqm->processes_count > 0);
1445
1446 kfree(dqm->allocated_queues);
1447 for (i = 0 ; i < KFD_MQD_TYPE_MAX ; i++)
1448 kfree(dqm->mqd_mgrs[i]);
1449 mutex_destroy(&dqm->lock_hidden);
1450 }
1451
start_nocpsch(struct device_queue_manager * dqm)1452 static int start_nocpsch(struct device_queue_manager *dqm)
1453 {
1454 int r = 0;
1455
1456 pr_info("SW scheduler is used");
1457 init_interrupts(dqm);
1458
1459 if (dqm->dev->adev->asic_type == CHIP_HAWAII)
1460 r = pm_init(&dqm->packet_mgr, dqm);
1461 if (!r)
1462 dqm->sched_running = true;
1463
1464 return r;
1465 }
1466
stop_nocpsch(struct device_queue_manager * dqm)1467 static int stop_nocpsch(struct device_queue_manager *dqm)
1468 {
1469 dqm_lock(dqm);
1470 if (!dqm->sched_running) {
1471 dqm_unlock(dqm);
1472 return 0;
1473 }
1474
1475 if (dqm->dev->adev->asic_type == CHIP_HAWAII)
1476 pm_uninit(&dqm->packet_mgr, false);
1477 dqm->sched_running = false;
1478 dqm_unlock(dqm);
1479
1480 return 0;
1481 }
1482
pre_reset(struct device_queue_manager * dqm)1483 static void pre_reset(struct device_queue_manager *dqm)
1484 {
1485 dqm_lock(dqm);
1486 dqm->is_resetting = true;
1487 dqm_unlock(dqm);
1488 }
1489
allocate_sdma_queue(struct device_queue_manager * dqm,struct queue * q,const uint32_t * restore_sdma_id)1490 static int allocate_sdma_queue(struct device_queue_manager *dqm,
1491 struct queue *q, const uint32_t *restore_sdma_id)
1492 {
1493 int bit;
1494
1495 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
1496 if (bitmap_empty(dqm->sdma_bitmap, KFD_MAX_SDMA_QUEUES)) {
1497 pr_err("No more SDMA queue to allocate\n");
1498 return -ENOMEM;
1499 }
1500
1501 if (restore_sdma_id) {
1502 /* Re-use existing sdma_id */
1503 if (!test_bit(*restore_sdma_id, dqm->sdma_bitmap)) {
1504 pr_err("SDMA queue already in use\n");
1505 return -EBUSY;
1506 }
1507 clear_bit(*restore_sdma_id, dqm->sdma_bitmap);
1508 q->sdma_id = *restore_sdma_id;
1509 } else {
1510 /* Find first available sdma_id */
1511 bit = find_first_bit(dqm->sdma_bitmap,
1512 get_num_sdma_queues(dqm));
1513 clear_bit(bit, dqm->sdma_bitmap);
1514 q->sdma_id = bit;
1515 }
1516
1517 q->properties.sdma_engine_id =
1518 q->sdma_id % kfd_get_num_sdma_engines(dqm->dev);
1519 q->properties.sdma_queue_id = q->sdma_id /
1520 kfd_get_num_sdma_engines(dqm->dev);
1521 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
1522 if (bitmap_empty(dqm->xgmi_sdma_bitmap, KFD_MAX_SDMA_QUEUES)) {
1523 pr_err("No more XGMI SDMA queue to allocate\n");
1524 return -ENOMEM;
1525 }
1526 if (restore_sdma_id) {
1527 /* Re-use existing sdma_id */
1528 if (!test_bit(*restore_sdma_id, dqm->xgmi_sdma_bitmap)) {
1529 pr_err("SDMA queue already in use\n");
1530 return -EBUSY;
1531 }
1532 clear_bit(*restore_sdma_id, dqm->xgmi_sdma_bitmap);
1533 q->sdma_id = *restore_sdma_id;
1534 } else {
1535 bit = find_first_bit(dqm->xgmi_sdma_bitmap,
1536 get_num_xgmi_sdma_queues(dqm));
1537 clear_bit(bit, dqm->xgmi_sdma_bitmap);
1538 q->sdma_id = bit;
1539 }
1540 /* sdma_engine_id is sdma id including
1541 * both PCIe-optimized SDMAs and XGMI-
1542 * optimized SDMAs. The calculation below
1543 * assumes the first N engines are always
1544 * PCIe-optimized ones
1545 */
1546 q->properties.sdma_engine_id =
1547 kfd_get_num_sdma_engines(dqm->dev) +
1548 q->sdma_id % kfd_get_num_xgmi_sdma_engines(dqm->dev);
1549 q->properties.sdma_queue_id = q->sdma_id /
1550 kfd_get_num_xgmi_sdma_engines(dqm->dev);
1551 }
1552
1553 pr_debug("SDMA engine id: %d\n", q->properties.sdma_engine_id);
1554 pr_debug("SDMA queue id: %d\n", q->properties.sdma_queue_id);
1555
1556 return 0;
1557 }
1558
deallocate_sdma_queue(struct device_queue_manager * dqm,struct queue * q)1559 static void deallocate_sdma_queue(struct device_queue_manager *dqm,
1560 struct queue *q)
1561 {
1562 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
1563 if (q->sdma_id >= get_num_sdma_queues(dqm))
1564 return;
1565 set_bit(q->sdma_id, dqm->sdma_bitmap);
1566 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
1567 if (q->sdma_id >= get_num_xgmi_sdma_queues(dqm))
1568 return;
1569 set_bit(q->sdma_id, dqm->xgmi_sdma_bitmap);
1570 }
1571 }
1572
1573 /*
1574 * Device Queue Manager implementation for cp scheduler
1575 */
1576
set_sched_resources(struct device_queue_manager * dqm)1577 static int set_sched_resources(struct device_queue_manager *dqm)
1578 {
1579 int i, mec;
1580 struct scheduling_resources res;
1581
1582 res.vmid_mask = dqm->dev->compute_vmid_bitmap;
1583
1584 res.queue_mask = 0;
1585 for (i = 0; i < KGD_MAX_QUEUES; ++i) {
1586 mec = (i / dqm->dev->kfd->shared_resources.num_queue_per_pipe)
1587 / dqm->dev->kfd->shared_resources.num_pipe_per_mec;
1588
1589 if (!test_bit(i, dqm->dev->kfd->shared_resources.cp_queue_bitmap))
1590 continue;
1591
1592 /* only acquire queues from the first MEC */
1593 if (mec > 0)
1594 continue;
1595
1596 /* This situation may be hit in the future if a new HW
1597 * generation exposes more than 64 queues. If so, the
1598 * definition of res.queue_mask needs updating
1599 */
1600 if (WARN_ON(i >= (sizeof(res.queue_mask)*8))) {
1601 pr_err("Invalid queue enabled by amdgpu: %d\n", i);
1602 break;
1603 }
1604
1605 res.queue_mask |= 1ull
1606 << amdgpu_queue_mask_bit_to_set_resource_bit(
1607 dqm->dev->adev, i);
1608 }
1609 res.gws_mask = ~0ull;
1610 res.oac_mask = res.gds_heap_base = res.gds_heap_size = 0;
1611
1612 pr_debug("Scheduling resources:\n"
1613 "vmid mask: 0x%8X\n"
1614 "queue mask: 0x%8llX\n",
1615 res.vmid_mask, res.queue_mask);
1616
1617 return pm_send_set_resources(&dqm->packet_mgr, &res);
1618 }
1619
initialize_cpsch(struct device_queue_manager * dqm)1620 static int initialize_cpsch(struct device_queue_manager *dqm)
1621 {
1622 pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm));
1623
1624 mutex_init(&dqm->lock_hidden);
1625 INIT_LIST_HEAD(&dqm->queues);
1626 dqm->active_queue_count = dqm->processes_count = 0;
1627 dqm->active_cp_queue_count = 0;
1628 dqm->gws_queue_count = 0;
1629 dqm->active_runlist = false;
1630 INIT_WORK(&dqm->hw_exception_work, kfd_process_hw_exception);
1631 dqm->trap_debug_vmid = 0;
1632
1633 init_sdma_bitmaps(dqm);
1634
1635 if (dqm->dev->kfd2kgd->get_iq_wait_times)
1636 dqm->dev->kfd2kgd->get_iq_wait_times(dqm->dev->adev,
1637 &dqm->wait_times,
1638 ffs(dqm->dev->xcc_mask) - 1);
1639 return 0;
1640 }
1641
start_cpsch(struct device_queue_manager * dqm)1642 static int start_cpsch(struct device_queue_manager *dqm)
1643 {
1644 int retval;
1645
1646 retval = 0;
1647
1648 dqm_lock(dqm);
1649
1650 if (!dqm->dev->kfd->shared_resources.enable_mes) {
1651 retval = pm_init(&dqm->packet_mgr, dqm);
1652 if (retval)
1653 goto fail_packet_manager_init;
1654
1655 retval = set_sched_resources(dqm);
1656 if (retval)
1657 goto fail_set_sched_resources;
1658 }
1659 pr_debug("Allocating fence memory\n");
1660
1661 /* allocate fence memory on the gart */
1662 retval = kfd_gtt_sa_allocate(dqm->dev, sizeof(*dqm->fence_addr),
1663 &dqm->fence_mem);
1664
1665 if (retval)
1666 goto fail_allocate_vidmem;
1667
1668 dqm->fence_addr = (uint64_t *)dqm->fence_mem->cpu_ptr;
1669 dqm->fence_gpu_addr = dqm->fence_mem->gpu_addr;
1670
1671 init_interrupts(dqm);
1672
1673 /* clear hang status when driver try to start the hw scheduler */
1674 dqm->is_hws_hang = false;
1675 dqm->is_resetting = false;
1676 dqm->sched_running = true;
1677
1678 if (!dqm->dev->kfd->shared_resources.enable_mes)
1679 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD);
1680
1681 /* Set CWSR grace period to 1x1000 cycle for GFX9.4.3 APU */
1682 if (amdgpu_emu_mode == 0 && dqm->dev->adev->gmc.is_app_apu &&
1683 (KFD_GC_VERSION(dqm->dev) == IP_VERSION(9, 4, 3))) {
1684 uint32_t reg_offset = 0;
1685 uint32_t grace_period = 1;
1686
1687 retval = pm_update_grace_period(&dqm->packet_mgr,
1688 grace_period);
1689 if (retval)
1690 pr_err("Setting grace timeout failed\n");
1691 else if (dqm->dev->kfd2kgd->build_grace_period_packet_info)
1692 /* Update dqm->wait_times maintained in software */
1693 dqm->dev->kfd2kgd->build_grace_period_packet_info(
1694 dqm->dev->adev, dqm->wait_times,
1695 grace_period, ®_offset,
1696 &dqm->wait_times);
1697 }
1698
1699 dqm_unlock(dqm);
1700
1701 return 0;
1702 fail_allocate_vidmem:
1703 fail_set_sched_resources:
1704 if (!dqm->dev->kfd->shared_resources.enable_mes)
1705 pm_uninit(&dqm->packet_mgr, false);
1706 fail_packet_manager_init:
1707 dqm_unlock(dqm);
1708 return retval;
1709 }
1710
stop_cpsch(struct device_queue_manager * dqm)1711 static int stop_cpsch(struct device_queue_manager *dqm)
1712 {
1713 bool hanging;
1714
1715 dqm_lock(dqm);
1716 if (!dqm->sched_running) {
1717 dqm_unlock(dqm);
1718 return 0;
1719 }
1720
1721 if (!dqm->is_hws_hang) {
1722 if (!dqm->dev->kfd->shared_resources.enable_mes)
1723 unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD, false);
1724 else
1725 remove_all_queues_mes(dqm);
1726 }
1727
1728 hanging = dqm->is_hws_hang || dqm->is_resetting;
1729 dqm->sched_running = false;
1730
1731 if (!dqm->dev->kfd->shared_resources.enable_mes)
1732 pm_release_ib(&dqm->packet_mgr);
1733
1734 kfd_gtt_sa_free(dqm->dev, dqm->fence_mem);
1735 if (!dqm->dev->kfd->shared_resources.enable_mes)
1736 pm_uninit(&dqm->packet_mgr, hanging);
1737 dqm_unlock(dqm);
1738
1739 return 0;
1740 }
1741
create_kernel_queue_cpsch(struct device_queue_manager * dqm,struct kernel_queue * kq,struct qcm_process_device * qpd)1742 static int create_kernel_queue_cpsch(struct device_queue_manager *dqm,
1743 struct kernel_queue *kq,
1744 struct qcm_process_device *qpd)
1745 {
1746 dqm_lock(dqm);
1747 if (dqm->total_queue_count >= max_num_of_queues_per_device) {
1748 pr_warn("Can't create new kernel queue because %d queues were already created\n",
1749 dqm->total_queue_count);
1750 dqm_unlock(dqm);
1751 return -EPERM;
1752 }
1753
1754 /*
1755 * Unconditionally increment this counter, regardless of the queue's
1756 * type or whether the queue is active.
1757 */
1758 dqm->total_queue_count++;
1759 pr_debug("Total of %d queues are accountable so far\n",
1760 dqm->total_queue_count);
1761
1762 list_add(&kq->list, &qpd->priv_queue_list);
1763 increment_queue_count(dqm, qpd, kq->queue);
1764 qpd->is_debug = true;
1765 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0,
1766 USE_DEFAULT_GRACE_PERIOD);
1767 dqm_unlock(dqm);
1768
1769 return 0;
1770 }
1771
destroy_kernel_queue_cpsch(struct device_queue_manager * dqm,struct kernel_queue * kq,struct qcm_process_device * qpd)1772 static void destroy_kernel_queue_cpsch(struct device_queue_manager *dqm,
1773 struct kernel_queue *kq,
1774 struct qcm_process_device *qpd)
1775 {
1776 dqm_lock(dqm);
1777 list_del(&kq->list);
1778 decrement_queue_count(dqm, qpd, kq->queue);
1779 qpd->is_debug = false;
1780 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0,
1781 USE_DEFAULT_GRACE_PERIOD);
1782 /*
1783 * Unconditionally decrement this counter, regardless of the queue's
1784 * type.
1785 */
1786 dqm->total_queue_count--;
1787 pr_debug("Total of %d queues are accountable so far\n",
1788 dqm->total_queue_count);
1789 dqm_unlock(dqm);
1790 }
1791
create_queue_cpsch(struct device_queue_manager * dqm,struct queue * q,struct qcm_process_device * qpd,const struct kfd_criu_queue_priv_data * qd,const void * restore_mqd,const void * restore_ctl_stack)1792 static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q,
1793 struct qcm_process_device *qpd,
1794 const struct kfd_criu_queue_priv_data *qd,
1795 const void *restore_mqd, const void *restore_ctl_stack)
1796 {
1797 int retval;
1798 struct mqd_manager *mqd_mgr;
1799
1800 if (dqm->total_queue_count >= max_num_of_queues_per_device) {
1801 pr_warn("Can't create new usermode queue because %d queues were already created\n",
1802 dqm->total_queue_count);
1803 retval = -EPERM;
1804 goto out;
1805 }
1806
1807 if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
1808 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
1809 dqm_lock(dqm);
1810 retval = allocate_sdma_queue(dqm, q, qd ? &qd->sdma_id : NULL);
1811 dqm_unlock(dqm);
1812 if (retval)
1813 goto out;
1814 }
1815
1816 retval = allocate_doorbell(qpd, q, qd ? &qd->doorbell_id : NULL);
1817 if (retval)
1818 goto out_deallocate_sdma_queue;
1819
1820 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
1821 q->properties.type)];
1822
1823 if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
1824 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
1825 dqm->asic_ops.init_sdma_vm(dqm, q, qpd);
1826 q->properties.tba_addr = qpd->tba_addr;
1827 q->properties.tma_addr = qpd->tma_addr;
1828 q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr->dev, &q->properties);
1829 if (!q->mqd_mem_obj) {
1830 retval = -ENOMEM;
1831 goto out_deallocate_doorbell;
1832 }
1833
1834 dqm_lock(dqm);
1835 /*
1836 * Eviction state logic: mark all queues as evicted, even ones
1837 * not currently active. Restoring inactive queues later only
1838 * updates the is_evicted flag but is a no-op otherwise.
1839 */
1840 q->properties.is_evicted = !!qpd->evicted;
1841 q->properties.is_dbg_wa = qpd->pqm->process->debug_trap_enabled &&
1842 kfd_dbg_has_cwsr_workaround(q->device);
1843
1844 if (qd)
1845 mqd_mgr->restore_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj, &q->gart_mqd_addr,
1846 &q->properties, restore_mqd, restore_ctl_stack,
1847 qd->ctl_stack_size);
1848 else
1849 mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj,
1850 &q->gart_mqd_addr, &q->properties);
1851
1852 list_add(&q->list, &qpd->queues_list);
1853 qpd->queue_count++;
1854
1855 if (q->properties.is_active) {
1856 increment_queue_count(dqm, qpd, q);
1857
1858 if (!dqm->dev->kfd->shared_resources.enable_mes)
1859 retval = execute_queues_cpsch(dqm,
1860 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD);
1861 else
1862 retval = add_queue_mes(dqm, q, qpd);
1863 if (retval)
1864 goto cleanup_queue;
1865 }
1866
1867 /*
1868 * Unconditionally increment this counter, regardless of the queue's
1869 * type or whether the queue is active.
1870 */
1871 dqm->total_queue_count++;
1872
1873 pr_debug("Total of %d queues are accountable so far\n",
1874 dqm->total_queue_count);
1875
1876 dqm_unlock(dqm);
1877 return retval;
1878
1879 cleanup_queue:
1880 qpd->queue_count--;
1881 list_del(&q->list);
1882 if (q->properties.is_active)
1883 decrement_queue_count(dqm, qpd, q);
1884 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
1885 dqm_unlock(dqm);
1886 out_deallocate_doorbell:
1887 deallocate_doorbell(qpd, q);
1888 out_deallocate_sdma_queue:
1889 if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
1890 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
1891 dqm_lock(dqm);
1892 deallocate_sdma_queue(dqm, q);
1893 dqm_unlock(dqm);
1894 }
1895 out:
1896 return retval;
1897 }
1898
amdkfd_fence_wait_timeout(uint64_t * fence_addr,uint64_t fence_value,unsigned int timeout_ms)1899 int amdkfd_fence_wait_timeout(uint64_t *fence_addr,
1900 uint64_t fence_value,
1901 unsigned int timeout_ms)
1902 {
1903 unsigned long end_jiffies = msecs_to_jiffies(timeout_ms) + jiffies;
1904
1905 while (*fence_addr != fence_value) {
1906 if (time_after(jiffies, end_jiffies)) {
1907 pr_err("qcm fence wait loop timeout expired\n");
1908 /* In HWS case, this is used to halt the driver thread
1909 * in order not to mess up CP states before doing
1910 * scandumps for FW debugging.
1911 */
1912 while (halt_if_hws_hang)
1913 schedule();
1914
1915 return -ETIME;
1916 }
1917 schedule();
1918 }
1919
1920 return 0;
1921 }
1922
1923 /* dqm->lock mutex has to be locked before calling this function */
map_queues_cpsch(struct device_queue_manager * dqm)1924 static int map_queues_cpsch(struct device_queue_manager *dqm)
1925 {
1926 int retval;
1927
1928 if (!dqm->sched_running)
1929 return 0;
1930 if (dqm->active_queue_count <= 0 || dqm->processes_count <= 0)
1931 return 0;
1932 if (dqm->active_runlist)
1933 return 0;
1934
1935 retval = pm_send_runlist(&dqm->packet_mgr, &dqm->queues);
1936 pr_debug("%s sent runlist\n", __func__);
1937 if (retval) {
1938 pr_err("failed to execute runlist\n");
1939 return retval;
1940 }
1941 dqm->active_runlist = true;
1942
1943 return retval;
1944 }
1945
1946 /* dqm->lock mutex has to be locked before calling this function */
unmap_queues_cpsch(struct device_queue_manager * dqm,enum kfd_unmap_queues_filter filter,uint32_t filter_param,uint32_t grace_period,bool reset)1947 static int unmap_queues_cpsch(struct device_queue_manager *dqm,
1948 enum kfd_unmap_queues_filter filter,
1949 uint32_t filter_param,
1950 uint32_t grace_period,
1951 bool reset)
1952 {
1953 int retval = 0;
1954 struct mqd_manager *mqd_mgr;
1955
1956 if (!dqm->sched_running)
1957 return 0;
1958 if (dqm->is_hws_hang || dqm->is_resetting)
1959 return -EIO;
1960 if (!dqm->active_runlist)
1961 return retval;
1962
1963 if (grace_period != USE_DEFAULT_GRACE_PERIOD) {
1964 retval = pm_update_grace_period(&dqm->packet_mgr, grace_period);
1965 if (retval)
1966 return retval;
1967 }
1968
1969 retval = pm_send_unmap_queue(&dqm->packet_mgr, filter, filter_param, reset);
1970 if (retval)
1971 return retval;
1972
1973 *dqm->fence_addr = KFD_FENCE_INIT;
1974 pm_send_query_status(&dqm->packet_mgr, dqm->fence_gpu_addr,
1975 KFD_FENCE_COMPLETED);
1976 /* should be timed out */
1977 retval = amdkfd_fence_wait_timeout(dqm->fence_addr, KFD_FENCE_COMPLETED,
1978 queue_preemption_timeout_ms);
1979 if (retval) {
1980 pr_err("The cp might be in an unrecoverable state due to an unsuccessful queues preemption\n");
1981 kfd_hws_hang(dqm);
1982 return retval;
1983 }
1984
1985 /* In the current MEC firmware implementation, if compute queue
1986 * doesn't response to the preemption request in time, HIQ will
1987 * abandon the unmap request without returning any timeout error
1988 * to driver. Instead, MEC firmware will log the doorbell of the
1989 * unresponding compute queue to HIQ.MQD.queue_doorbell_id fields.
1990 * To make sure the queue unmap was successful, driver need to
1991 * check those fields
1992 */
1993 mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ];
1994 if (mqd_mgr->read_doorbell_id(dqm->packet_mgr.priv_queue->queue->mqd)) {
1995 pr_err("HIQ MQD's queue_doorbell_id0 is not 0, Queue preemption time out\n");
1996 while (halt_if_hws_hang)
1997 schedule();
1998 kfd_hws_hang(dqm);
1999 return -ETIME;
2000 }
2001
2002 /* We need to reset the grace period value for this device */
2003 if (grace_period != USE_DEFAULT_GRACE_PERIOD) {
2004 if (pm_update_grace_period(&dqm->packet_mgr,
2005 USE_DEFAULT_GRACE_PERIOD))
2006 pr_err("Failed to reset grace period\n");
2007 }
2008
2009 pm_release_ib(&dqm->packet_mgr);
2010 dqm->active_runlist = false;
2011
2012 return retval;
2013 }
2014
2015 /* only for compute queue */
reset_queues_cpsch(struct device_queue_manager * dqm,uint16_t pasid)2016 static int reset_queues_cpsch(struct device_queue_manager *dqm,
2017 uint16_t pasid)
2018 {
2019 int retval;
2020
2021 dqm_lock(dqm);
2022
2023 retval = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_BY_PASID,
2024 pasid, USE_DEFAULT_GRACE_PERIOD, true);
2025
2026 dqm_unlock(dqm);
2027 return retval;
2028 }
2029
2030 /* dqm->lock mutex has to be locked before calling this function */
execute_queues_cpsch(struct device_queue_manager * dqm,enum kfd_unmap_queues_filter filter,uint32_t filter_param,uint32_t grace_period)2031 static int execute_queues_cpsch(struct device_queue_manager *dqm,
2032 enum kfd_unmap_queues_filter filter,
2033 uint32_t filter_param,
2034 uint32_t grace_period)
2035 {
2036 int retval;
2037
2038 if (dqm->is_hws_hang)
2039 return -EIO;
2040 retval = unmap_queues_cpsch(dqm, filter, filter_param, grace_period, false);
2041 if (retval)
2042 return retval;
2043
2044 return map_queues_cpsch(dqm);
2045 }
2046
wait_on_destroy_queue(struct device_queue_manager * dqm,struct queue * q)2047 static int wait_on_destroy_queue(struct device_queue_manager *dqm,
2048 struct queue *q)
2049 {
2050 struct kfd_process_device *pdd = kfd_get_process_device_data(q->device,
2051 q->process);
2052 int ret = 0;
2053
2054 if (pdd->qpd.is_debug)
2055 return ret;
2056
2057 q->properties.is_being_destroyed = true;
2058
2059 if (pdd->process->debug_trap_enabled && q->properties.is_suspended) {
2060 dqm_unlock(dqm);
2061 mutex_unlock(&q->process->mutex);
2062 ret = wait_event_interruptible(dqm->destroy_wait,
2063 !q->properties.is_suspended);
2064
2065 mutex_lock(&q->process->mutex);
2066 dqm_lock(dqm);
2067 }
2068
2069 return ret;
2070 }
2071
destroy_queue_cpsch(struct device_queue_manager * dqm,struct qcm_process_device * qpd,struct queue * q)2072 static int destroy_queue_cpsch(struct device_queue_manager *dqm,
2073 struct qcm_process_device *qpd,
2074 struct queue *q)
2075 {
2076 int retval;
2077 struct mqd_manager *mqd_mgr;
2078 uint64_t sdma_val = 0;
2079 struct kfd_process_device *pdd = qpd_to_pdd(qpd);
2080
2081 /* Get the SDMA queue stats */
2082 if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) ||
2083 (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) {
2084 retval = read_sdma_queue_counter((uint64_t __user *)q->properties.read_ptr,
2085 &sdma_val);
2086 if (retval)
2087 pr_err("Failed to read SDMA queue counter for queue: %d\n",
2088 q->properties.queue_id);
2089 }
2090
2091 /* remove queue from list to prevent rescheduling after preemption */
2092 dqm_lock(dqm);
2093
2094 retval = wait_on_destroy_queue(dqm, q);
2095
2096 if (retval) {
2097 dqm_unlock(dqm);
2098 return retval;
2099 }
2100
2101 if (qpd->is_debug) {
2102 /*
2103 * error, currently we do not allow to destroy a queue
2104 * of a currently debugged process
2105 */
2106 retval = -EBUSY;
2107 goto failed_try_destroy_debugged_queue;
2108
2109 }
2110
2111 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
2112 q->properties.type)];
2113
2114 deallocate_doorbell(qpd, q);
2115
2116 if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) ||
2117 (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) {
2118 deallocate_sdma_queue(dqm, q);
2119 pdd->sdma_past_activity_counter += sdma_val;
2120 }
2121
2122 list_del(&q->list);
2123 qpd->queue_count--;
2124 if (q->properties.is_active) {
2125 decrement_queue_count(dqm, qpd, q);
2126 if (!dqm->dev->kfd->shared_resources.enable_mes) {
2127 retval = execute_queues_cpsch(dqm,
2128 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0,
2129 USE_DEFAULT_GRACE_PERIOD);
2130 if (retval == -ETIME)
2131 qpd->reset_wavefronts = true;
2132 } else {
2133 retval = remove_queue_mes(dqm, q, qpd);
2134 }
2135 }
2136
2137 /*
2138 * Unconditionally decrement this counter, regardless of the queue's
2139 * type
2140 */
2141 dqm->total_queue_count--;
2142 pr_debug("Total of %d queues are accountable so far\n",
2143 dqm->total_queue_count);
2144
2145 dqm_unlock(dqm);
2146
2147 /*
2148 * Do free_mqd and raise delete event after dqm_unlock(dqm) to avoid
2149 * circular locking
2150 */
2151 kfd_dbg_ev_raise(KFD_EC_MASK(EC_DEVICE_QUEUE_DELETE),
2152 qpd->pqm->process, q->device,
2153 -1, false, NULL, 0);
2154
2155 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
2156
2157 return retval;
2158
2159 failed_try_destroy_debugged_queue:
2160
2161 dqm_unlock(dqm);
2162 return retval;
2163 }
2164
2165 /*
2166 * Low bits must be 0000/FFFF as required by HW, high bits must be 0 to
2167 * stay in user mode.
2168 */
2169 #define APE1_FIXED_BITS_MASK 0xFFFF80000000FFFFULL
2170 /* APE1 limit is inclusive and 64K aligned. */
2171 #define APE1_LIMIT_ALIGNMENT 0xFFFF
2172
set_cache_memory_policy(struct device_queue_manager * dqm,struct qcm_process_device * qpd,enum cache_policy default_policy,enum cache_policy alternate_policy,void __user * alternate_aperture_base,uint64_t alternate_aperture_size)2173 static bool set_cache_memory_policy(struct device_queue_manager *dqm,
2174 struct qcm_process_device *qpd,
2175 enum cache_policy default_policy,
2176 enum cache_policy alternate_policy,
2177 void __user *alternate_aperture_base,
2178 uint64_t alternate_aperture_size)
2179 {
2180 bool retval = true;
2181
2182 if (!dqm->asic_ops.set_cache_memory_policy)
2183 return retval;
2184
2185 dqm_lock(dqm);
2186
2187 if (alternate_aperture_size == 0) {
2188 /* base > limit disables APE1 */
2189 qpd->sh_mem_ape1_base = 1;
2190 qpd->sh_mem_ape1_limit = 0;
2191 } else {
2192 /*
2193 * In FSA64, APE1_Base[63:0] = { 16{SH_MEM_APE1_BASE[31]},
2194 * SH_MEM_APE1_BASE[31:0], 0x0000 }
2195 * APE1_Limit[63:0] = { 16{SH_MEM_APE1_LIMIT[31]},
2196 * SH_MEM_APE1_LIMIT[31:0], 0xFFFF }
2197 * Verify that the base and size parameters can be
2198 * represented in this format and convert them.
2199 * Additionally restrict APE1 to user-mode addresses.
2200 */
2201
2202 uint64_t base = (uintptr_t)alternate_aperture_base;
2203 uint64_t limit = base + alternate_aperture_size - 1;
2204
2205 if (limit <= base || (base & APE1_FIXED_BITS_MASK) != 0 ||
2206 (limit & APE1_FIXED_BITS_MASK) != APE1_LIMIT_ALIGNMENT) {
2207 retval = false;
2208 goto out;
2209 }
2210
2211 qpd->sh_mem_ape1_base = base >> 16;
2212 qpd->sh_mem_ape1_limit = limit >> 16;
2213 }
2214
2215 retval = dqm->asic_ops.set_cache_memory_policy(
2216 dqm,
2217 qpd,
2218 default_policy,
2219 alternate_policy,
2220 alternate_aperture_base,
2221 alternate_aperture_size);
2222
2223 if ((dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) && (qpd->vmid != 0))
2224 program_sh_mem_settings(dqm, qpd);
2225
2226 pr_debug("sh_mem_config: 0x%x, ape1_base: 0x%x, ape1_limit: 0x%x\n",
2227 qpd->sh_mem_config, qpd->sh_mem_ape1_base,
2228 qpd->sh_mem_ape1_limit);
2229
2230 out:
2231 dqm_unlock(dqm);
2232 return retval;
2233 }
2234
process_termination_nocpsch(struct device_queue_manager * dqm,struct qcm_process_device * qpd)2235 static int process_termination_nocpsch(struct device_queue_manager *dqm,
2236 struct qcm_process_device *qpd)
2237 {
2238 struct queue *q;
2239 struct device_process_node *cur, *next_dpn;
2240 int retval = 0;
2241 bool found = false;
2242
2243 dqm_lock(dqm);
2244
2245 /* Clear all user mode queues */
2246 while (!list_empty(&qpd->queues_list)) {
2247 struct mqd_manager *mqd_mgr;
2248 int ret;
2249
2250 q = list_first_entry(&qpd->queues_list, struct queue, list);
2251 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
2252 q->properties.type)];
2253 ret = destroy_queue_nocpsch_locked(dqm, qpd, q);
2254 if (ret)
2255 retval = ret;
2256 dqm_unlock(dqm);
2257 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
2258 dqm_lock(dqm);
2259 }
2260
2261 /* Unregister process */
2262 list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) {
2263 if (qpd == cur->qpd) {
2264 list_del(&cur->list);
2265 kfree(cur);
2266 dqm->processes_count--;
2267 found = true;
2268 break;
2269 }
2270 }
2271
2272 dqm_unlock(dqm);
2273
2274 /* Outside the DQM lock because under the DQM lock we can't do
2275 * reclaim or take other locks that others hold while reclaiming.
2276 */
2277 if (found)
2278 kfd_dec_compute_active(dqm->dev);
2279
2280 return retval;
2281 }
2282
get_wave_state(struct device_queue_manager * dqm,struct queue * q,void __user * ctl_stack,u32 * ctl_stack_used_size,u32 * save_area_used_size)2283 static int get_wave_state(struct device_queue_manager *dqm,
2284 struct queue *q,
2285 void __user *ctl_stack,
2286 u32 *ctl_stack_used_size,
2287 u32 *save_area_used_size)
2288 {
2289 struct mqd_manager *mqd_mgr;
2290
2291 dqm_lock(dqm);
2292
2293 mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_CP];
2294
2295 if (q->properties.type != KFD_QUEUE_TYPE_COMPUTE ||
2296 q->properties.is_active || !q->device->kfd->cwsr_enabled ||
2297 !mqd_mgr->get_wave_state) {
2298 dqm_unlock(dqm);
2299 return -EINVAL;
2300 }
2301
2302 dqm_unlock(dqm);
2303
2304 /*
2305 * get_wave_state is outside the dqm lock to prevent circular locking
2306 * and the queue should be protected against destruction by the process
2307 * lock.
2308 */
2309 return mqd_mgr->get_wave_state(mqd_mgr, q->mqd, &q->properties,
2310 ctl_stack, ctl_stack_used_size, save_area_used_size);
2311 }
2312
get_queue_checkpoint_info(struct device_queue_manager * dqm,const struct queue * q,u32 * mqd_size,u32 * ctl_stack_size)2313 static void get_queue_checkpoint_info(struct device_queue_manager *dqm,
2314 const struct queue *q,
2315 u32 *mqd_size,
2316 u32 *ctl_stack_size)
2317 {
2318 struct mqd_manager *mqd_mgr;
2319 enum KFD_MQD_TYPE mqd_type =
2320 get_mqd_type_from_queue_type(q->properties.type);
2321
2322 dqm_lock(dqm);
2323 mqd_mgr = dqm->mqd_mgrs[mqd_type];
2324 *mqd_size = mqd_mgr->mqd_size;
2325 *ctl_stack_size = 0;
2326
2327 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE && mqd_mgr->get_checkpoint_info)
2328 mqd_mgr->get_checkpoint_info(mqd_mgr, q->mqd, ctl_stack_size);
2329
2330 dqm_unlock(dqm);
2331 }
2332
checkpoint_mqd(struct device_queue_manager * dqm,const struct queue * q,void * mqd,void * ctl_stack)2333 static int checkpoint_mqd(struct device_queue_manager *dqm,
2334 const struct queue *q,
2335 void *mqd,
2336 void *ctl_stack)
2337 {
2338 struct mqd_manager *mqd_mgr;
2339 int r = 0;
2340 enum KFD_MQD_TYPE mqd_type =
2341 get_mqd_type_from_queue_type(q->properties.type);
2342
2343 dqm_lock(dqm);
2344
2345 if (q->properties.is_active || !q->device->kfd->cwsr_enabled) {
2346 r = -EINVAL;
2347 goto dqm_unlock;
2348 }
2349
2350 mqd_mgr = dqm->mqd_mgrs[mqd_type];
2351 if (!mqd_mgr->checkpoint_mqd) {
2352 r = -EOPNOTSUPP;
2353 goto dqm_unlock;
2354 }
2355
2356 mqd_mgr->checkpoint_mqd(mqd_mgr, q->mqd, mqd, ctl_stack);
2357
2358 dqm_unlock:
2359 dqm_unlock(dqm);
2360 return r;
2361 }
2362
process_termination_cpsch(struct device_queue_manager * dqm,struct qcm_process_device * qpd)2363 static int process_termination_cpsch(struct device_queue_manager *dqm,
2364 struct qcm_process_device *qpd)
2365 {
2366 int retval;
2367 struct queue *q;
2368 struct kernel_queue *kq, *kq_next;
2369 struct mqd_manager *mqd_mgr;
2370 struct device_process_node *cur, *next_dpn;
2371 enum kfd_unmap_queues_filter filter =
2372 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES;
2373 bool found = false;
2374
2375 retval = 0;
2376
2377 dqm_lock(dqm);
2378
2379 /* Clean all kernel queues */
2380 list_for_each_entry_safe(kq, kq_next, &qpd->priv_queue_list, list) {
2381 list_del(&kq->list);
2382 decrement_queue_count(dqm, qpd, kq->queue);
2383 qpd->is_debug = false;
2384 dqm->total_queue_count--;
2385 filter = KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES;
2386 }
2387
2388 /* Clear all user mode queues */
2389 list_for_each_entry(q, &qpd->queues_list, list) {
2390 if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
2391 deallocate_sdma_queue(dqm, q);
2392 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
2393 deallocate_sdma_queue(dqm, q);
2394
2395 if (q->properties.is_active) {
2396 decrement_queue_count(dqm, qpd, q);
2397
2398 if (dqm->dev->kfd->shared_resources.enable_mes) {
2399 retval = remove_queue_mes(dqm, q, qpd);
2400 if (retval)
2401 pr_err("Failed to remove queue %d\n",
2402 q->properties.queue_id);
2403 }
2404 }
2405
2406 dqm->total_queue_count--;
2407 }
2408
2409 /* Unregister process */
2410 list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) {
2411 if (qpd == cur->qpd) {
2412 list_del(&cur->list);
2413 kfree(cur);
2414 dqm->processes_count--;
2415 found = true;
2416 break;
2417 }
2418 }
2419
2420 if (!dqm->dev->kfd->shared_resources.enable_mes)
2421 retval = execute_queues_cpsch(dqm, filter, 0, USE_DEFAULT_GRACE_PERIOD);
2422
2423 if ((!dqm->is_hws_hang) && (retval || qpd->reset_wavefronts)) {
2424 pr_warn("Resetting wave fronts (cpsch) on dev %p\n", dqm->dev);
2425 dbgdev_wave_reset_wavefronts(dqm->dev, qpd->pqm->process);
2426 qpd->reset_wavefronts = false;
2427 }
2428
2429 /* Lastly, free mqd resources.
2430 * Do free_mqd() after dqm_unlock to avoid circular locking.
2431 */
2432 while (!list_empty(&qpd->queues_list)) {
2433 q = list_first_entry(&qpd->queues_list, struct queue, list);
2434 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
2435 q->properties.type)];
2436 list_del(&q->list);
2437 qpd->queue_count--;
2438 dqm_unlock(dqm);
2439 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
2440 dqm_lock(dqm);
2441 }
2442 dqm_unlock(dqm);
2443
2444 /* Outside the DQM lock because under the DQM lock we can't do
2445 * reclaim or take other locks that others hold while reclaiming.
2446 */
2447 if (found)
2448 kfd_dec_compute_active(dqm->dev);
2449
2450 return retval;
2451 }
2452
init_mqd_managers(struct device_queue_manager * dqm)2453 static int init_mqd_managers(struct device_queue_manager *dqm)
2454 {
2455 int i, j;
2456 struct mqd_manager *mqd_mgr;
2457
2458 for (i = 0; i < KFD_MQD_TYPE_MAX; i++) {
2459 mqd_mgr = dqm->asic_ops.mqd_manager_init(i, dqm->dev);
2460 if (!mqd_mgr) {
2461 pr_err("mqd manager [%d] initialization failed\n", i);
2462 goto out_free;
2463 }
2464 dqm->mqd_mgrs[i] = mqd_mgr;
2465 }
2466
2467 return 0;
2468
2469 out_free:
2470 for (j = 0; j < i; j++) {
2471 kfree(dqm->mqd_mgrs[j]);
2472 dqm->mqd_mgrs[j] = NULL;
2473 }
2474
2475 return -ENOMEM;
2476 }
2477
2478 /* Allocate one hiq mqd (HWS) and all SDMA mqd in a continuous trunk*/
allocate_hiq_sdma_mqd(struct device_queue_manager * dqm)2479 static int allocate_hiq_sdma_mqd(struct device_queue_manager *dqm)
2480 {
2481 int retval;
2482 struct kfd_node *dev = dqm->dev;
2483 struct kfd_mem_obj *mem_obj = &dqm->hiq_sdma_mqd;
2484 uint32_t size = dqm->mqd_mgrs[KFD_MQD_TYPE_SDMA]->mqd_size *
2485 get_num_all_sdma_engines(dqm) *
2486 dev->kfd->device_info.num_sdma_queues_per_engine +
2487 (dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]->mqd_size *
2488 NUM_XCC(dqm->dev->xcc_mask));
2489
2490 retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev, size,
2491 &(mem_obj->gtt_mem), &(mem_obj->gpu_addr),
2492 (void *)&(mem_obj->cpu_ptr), false);
2493
2494 return retval;
2495 }
2496
device_queue_manager_init(struct kfd_node * dev)2497 struct device_queue_manager *device_queue_manager_init(struct kfd_node *dev)
2498 {
2499 struct device_queue_manager *dqm;
2500
2501 pr_debug("Loading device queue manager\n");
2502
2503 dqm = kzalloc(sizeof(*dqm), GFP_KERNEL);
2504 if (!dqm)
2505 return NULL;
2506
2507 switch (dev->adev->asic_type) {
2508 /* HWS is not available on Hawaii. */
2509 case CHIP_HAWAII:
2510 /* HWS depends on CWSR for timely dequeue. CWSR is not
2511 * available on Tonga.
2512 *
2513 * FIXME: This argument also applies to Kaveri.
2514 */
2515 case CHIP_TONGA:
2516 dqm->sched_policy = KFD_SCHED_POLICY_NO_HWS;
2517 break;
2518 default:
2519 dqm->sched_policy = sched_policy;
2520 break;
2521 }
2522
2523 dqm->dev = dev;
2524 switch (dqm->sched_policy) {
2525 case KFD_SCHED_POLICY_HWS:
2526 case KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION:
2527 /* initialize dqm for cp scheduling */
2528 dqm->ops.create_queue = create_queue_cpsch;
2529 dqm->ops.initialize = initialize_cpsch;
2530 dqm->ops.start = start_cpsch;
2531 dqm->ops.stop = stop_cpsch;
2532 dqm->ops.pre_reset = pre_reset;
2533 dqm->ops.destroy_queue = destroy_queue_cpsch;
2534 dqm->ops.update_queue = update_queue;
2535 dqm->ops.register_process = register_process;
2536 dqm->ops.unregister_process = unregister_process;
2537 dqm->ops.uninitialize = uninitialize;
2538 dqm->ops.create_kernel_queue = create_kernel_queue_cpsch;
2539 dqm->ops.destroy_kernel_queue = destroy_kernel_queue_cpsch;
2540 dqm->ops.set_cache_memory_policy = set_cache_memory_policy;
2541 dqm->ops.process_termination = process_termination_cpsch;
2542 dqm->ops.evict_process_queues = evict_process_queues_cpsch;
2543 dqm->ops.restore_process_queues = restore_process_queues_cpsch;
2544 dqm->ops.get_wave_state = get_wave_state;
2545 dqm->ops.reset_queues = reset_queues_cpsch;
2546 dqm->ops.get_queue_checkpoint_info = get_queue_checkpoint_info;
2547 dqm->ops.checkpoint_mqd = checkpoint_mqd;
2548 break;
2549 case KFD_SCHED_POLICY_NO_HWS:
2550 /* initialize dqm for no cp scheduling */
2551 dqm->ops.start = start_nocpsch;
2552 dqm->ops.stop = stop_nocpsch;
2553 dqm->ops.pre_reset = pre_reset;
2554 dqm->ops.create_queue = create_queue_nocpsch;
2555 dqm->ops.destroy_queue = destroy_queue_nocpsch;
2556 dqm->ops.update_queue = update_queue;
2557 dqm->ops.register_process = register_process;
2558 dqm->ops.unregister_process = unregister_process;
2559 dqm->ops.initialize = initialize_nocpsch;
2560 dqm->ops.uninitialize = uninitialize;
2561 dqm->ops.set_cache_memory_policy = set_cache_memory_policy;
2562 dqm->ops.process_termination = process_termination_nocpsch;
2563 dqm->ops.evict_process_queues = evict_process_queues_nocpsch;
2564 dqm->ops.restore_process_queues =
2565 restore_process_queues_nocpsch;
2566 dqm->ops.get_wave_state = get_wave_state;
2567 dqm->ops.get_queue_checkpoint_info = get_queue_checkpoint_info;
2568 dqm->ops.checkpoint_mqd = checkpoint_mqd;
2569 break;
2570 default:
2571 pr_err("Invalid scheduling policy %d\n", dqm->sched_policy);
2572 goto out_free;
2573 }
2574
2575 switch (dev->adev->asic_type) {
2576 case CHIP_KAVERI:
2577 case CHIP_HAWAII:
2578 device_queue_manager_init_cik(&dqm->asic_ops);
2579 break;
2580
2581 case CHIP_CARRIZO:
2582 case CHIP_TONGA:
2583 case CHIP_FIJI:
2584 case CHIP_POLARIS10:
2585 case CHIP_POLARIS11:
2586 case CHIP_POLARIS12:
2587 case CHIP_VEGAM:
2588 device_queue_manager_init_vi(&dqm->asic_ops);
2589 break;
2590
2591 default:
2592 if (KFD_GC_VERSION(dev) >= IP_VERSION(11, 0, 0))
2593 device_queue_manager_init_v11(&dqm->asic_ops);
2594 else if (KFD_GC_VERSION(dev) >= IP_VERSION(10, 1, 1))
2595 device_queue_manager_init_v10(&dqm->asic_ops);
2596 else if (KFD_GC_VERSION(dev) >= IP_VERSION(9, 0, 1))
2597 device_queue_manager_init_v9(&dqm->asic_ops);
2598 else {
2599 WARN(1, "Unexpected ASIC family %u",
2600 dev->adev->asic_type);
2601 goto out_free;
2602 }
2603 }
2604
2605 if (init_mqd_managers(dqm))
2606 goto out_free;
2607
2608 if (!dev->kfd->shared_resources.enable_mes && allocate_hiq_sdma_mqd(dqm)) {
2609 pr_err("Failed to allocate hiq sdma mqd trunk buffer\n");
2610 goto out_free;
2611 }
2612
2613 if (!dqm->ops.initialize(dqm)) {
2614 init_waitqueue_head(&dqm->destroy_wait);
2615 return dqm;
2616 }
2617
2618 out_free:
2619 kfree(dqm);
2620 return NULL;
2621 }
2622
deallocate_hiq_sdma_mqd(struct kfd_node * dev,struct kfd_mem_obj * mqd)2623 static void deallocate_hiq_sdma_mqd(struct kfd_node *dev,
2624 struct kfd_mem_obj *mqd)
2625 {
2626 WARN(!mqd, "No hiq sdma mqd trunk to free");
2627
2628 amdgpu_amdkfd_free_gtt_mem(dev->adev, &mqd->gtt_mem);
2629 }
2630
device_queue_manager_uninit(struct device_queue_manager * dqm)2631 void device_queue_manager_uninit(struct device_queue_manager *dqm)
2632 {
2633 dqm->ops.stop(dqm);
2634 dqm->ops.uninitialize(dqm);
2635 if (!dqm->dev->kfd->shared_resources.enable_mes)
2636 deallocate_hiq_sdma_mqd(dqm->dev, &dqm->hiq_sdma_mqd);
2637 kfree(dqm);
2638 }
2639
kfd_dqm_evict_pasid(struct device_queue_manager * dqm,u32 pasid)2640 int kfd_dqm_evict_pasid(struct device_queue_manager *dqm, u32 pasid)
2641 {
2642 struct kfd_process_device *pdd;
2643 struct kfd_process *p = kfd_lookup_process_by_pasid(pasid);
2644 int ret = 0;
2645
2646 if (!p)
2647 return -EINVAL;
2648 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid);
2649 pdd = kfd_get_process_device_data(dqm->dev, p);
2650 if (pdd)
2651 ret = dqm->ops.evict_process_queues(dqm, &pdd->qpd);
2652 kfd_unref_process(p);
2653
2654 return ret;
2655 }
2656
kfd_process_hw_exception(struct work_struct * work)2657 static void kfd_process_hw_exception(struct work_struct *work)
2658 {
2659 struct device_queue_manager *dqm = container_of(work,
2660 struct device_queue_manager, hw_exception_work);
2661 amdgpu_amdkfd_gpu_reset(dqm->dev->adev);
2662 }
2663
reserve_debug_trap_vmid(struct device_queue_manager * dqm,struct qcm_process_device * qpd)2664 int reserve_debug_trap_vmid(struct device_queue_manager *dqm,
2665 struct qcm_process_device *qpd)
2666 {
2667 int r;
2668 int updated_vmid_mask;
2669
2670 if (dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) {
2671 pr_err("Unsupported on sched_policy: %i\n", dqm->sched_policy);
2672 return -EINVAL;
2673 }
2674
2675 dqm_lock(dqm);
2676
2677 if (dqm->trap_debug_vmid != 0) {
2678 pr_err("Trap debug id already reserved\n");
2679 r = -EBUSY;
2680 goto out_unlock;
2681 }
2682
2683 r = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0,
2684 USE_DEFAULT_GRACE_PERIOD, false);
2685 if (r)
2686 goto out_unlock;
2687
2688 updated_vmid_mask = dqm->dev->kfd->shared_resources.compute_vmid_bitmap;
2689 updated_vmid_mask &= ~(1 << dqm->dev->vm_info.last_vmid_kfd);
2690
2691 dqm->dev->kfd->shared_resources.compute_vmid_bitmap = updated_vmid_mask;
2692 dqm->trap_debug_vmid = dqm->dev->vm_info.last_vmid_kfd;
2693 r = set_sched_resources(dqm);
2694 if (r)
2695 goto out_unlock;
2696
2697 r = map_queues_cpsch(dqm);
2698 if (r)
2699 goto out_unlock;
2700
2701 pr_debug("Reserved VMID for trap debug: %i\n", dqm->trap_debug_vmid);
2702
2703 out_unlock:
2704 dqm_unlock(dqm);
2705 return r;
2706 }
2707
2708 /*
2709 * Releases vmid for the trap debugger
2710 */
release_debug_trap_vmid(struct device_queue_manager * dqm,struct qcm_process_device * qpd)2711 int release_debug_trap_vmid(struct device_queue_manager *dqm,
2712 struct qcm_process_device *qpd)
2713 {
2714 int r;
2715 int updated_vmid_mask;
2716 uint32_t trap_debug_vmid;
2717
2718 if (dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) {
2719 pr_err("Unsupported on sched_policy: %i\n", dqm->sched_policy);
2720 return -EINVAL;
2721 }
2722
2723 dqm_lock(dqm);
2724 trap_debug_vmid = dqm->trap_debug_vmid;
2725 if (dqm->trap_debug_vmid == 0) {
2726 pr_err("Trap debug id is not reserved\n");
2727 r = -EINVAL;
2728 goto out_unlock;
2729 }
2730
2731 r = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0,
2732 USE_DEFAULT_GRACE_PERIOD, false);
2733 if (r)
2734 goto out_unlock;
2735
2736 updated_vmid_mask = dqm->dev->kfd->shared_resources.compute_vmid_bitmap;
2737 updated_vmid_mask |= (1 << dqm->dev->vm_info.last_vmid_kfd);
2738
2739 dqm->dev->kfd->shared_resources.compute_vmid_bitmap = updated_vmid_mask;
2740 dqm->trap_debug_vmid = 0;
2741 r = set_sched_resources(dqm);
2742 if (r)
2743 goto out_unlock;
2744
2745 r = map_queues_cpsch(dqm);
2746 if (r)
2747 goto out_unlock;
2748
2749 pr_debug("Released VMID for trap debug: %i\n", trap_debug_vmid);
2750
2751 out_unlock:
2752 dqm_unlock(dqm);
2753 return r;
2754 }
2755
2756 #define QUEUE_NOT_FOUND -1
2757 /* invalidate queue operation in array */
q_array_invalidate(uint32_t num_queues,uint32_t * queue_ids)2758 static void q_array_invalidate(uint32_t num_queues, uint32_t *queue_ids)
2759 {
2760 int i;
2761
2762 for (i = 0; i < num_queues; i++)
2763 queue_ids[i] |= KFD_DBG_QUEUE_INVALID_MASK;
2764 }
2765
2766 /* find queue index in array */
q_array_get_index(unsigned int queue_id,uint32_t num_queues,uint32_t * queue_ids)2767 static int q_array_get_index(unsigned int queue_id,
2768 uint32_t num_queues,
2769 uint32_t *queue_ids)
2770 {
2771 int i;
2772
2773 for (i = 0; i < num_queues; i++)
2774 if (queue_id == (queue_ids[i] & ~KFD_DBG_QUEUE_INVALID_MASK))
2775 return i;
2776
2777 return QUEUE_NOT_FOUND;
2778 }
2779
2780 struct copy_context_work_handler_workarea {
2781 struct work_struct copy_context_work;
2782 struct kfd_process *p;
2783 };
2784
copy_context_work_handler(struct work_struct * work)2785 static void copy_context_work_handler (struct work_struct *work)
2786 {
2787 struct copy_context_work_handler_workarea *workarea;
2788 struct mqd_manager *mqd_mgr;
2789 struct queue *q;
2790 struct mm_struct *mm;
2791 struct kfd_process *p;
2792 uint32_t tmp_ctl_stack_used_size, tmp_save_area_used_size;
2793 int i;
2794
2795 workarea = container_of(work,
2796 struct copy_context_work_handler_workarea,
2797 copy_context_work);
2798
2799 p = workarea->p;
2800 mm = get_task_mm(p->lead_thread);
2801
2802 if (!mm)
2803 return;
2804
2805 kthread_use_mm(mm);
2806 for (i = 0; i < p->n_pdds; i++) {
2807 struct kfd_process_device *pdd = p->pdds[i];
2808 struct device_queue_manager *dqm = pdd->dev->dqm;
2809 struct qcm_process_device *qpd = &pdd->qpd;
2810
2811 list_for_each_entry(q, &qpd->queues_list, list) {
2812 mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_CP];
2813
2814 /* We ignore the return value from get_wave_state
2815 * because
2816 * i) right now, it always returns 0, and
2817 * ii) if we hit an error, we would continue to the
2818 * next queue anyway.
2819 */
2820 mqd_mgr->get_wave_state(mqd_mgr,
2821 q->mqd,
2822 &q->properties,
2823 (void __user *) q->properties.ctx_save_restore_area_address,
2824 &tmp_ctl_stack_used_size,
2825 &tmp_save_area_used_size);
2826 }
2827 }
2828 kthread_unuse_mm(mm);
2829 mmput(mm);
2830 }
2831
get_queue_ids(uint32_t num_queues,uint32_t * usr_queue_id_array)2832 static uint32_t *get_queue_ids(uint32_t num_queues, uint32_t *usr_queue_id_array)
2833 {
2834 size_t array_size = num_queues * sizeof(uint32_t);
2835
2836 if (!usr_queue_id_array)
2837 return NULL;
2838
2839 return memdup_user(usr_queue_id_array, array_size);
2840 }
2841
resume_queues(struct kfd_process * p,uint32_t num_queues,uint32_t * usr_queue_id_array)2842 int resume_queues(struct kfd_process *p,
2843 uint32_t num_queues,
2844 uint32_t *usr_queue_id_array)
2845 {
2846 uint32_t *queue_ids = NULL;
2847 int total_resumed = 0;
2848 int i;
2849
2850 if (usr_queue_id_array) {
2851 queue_ids = get_queue_ids(num_queues, usr_queue_id_array);
2852
2853 if (IS_ERR(queue_ids))
2854 return PTR_ERR(queue_ids);
2855
2856 /* mask all queues as invalid. unmask per successful request */
2857 q_array_invalidate(num_queues, queue_ids);
2858 }
2859
2860 for (i = 0; i < p->n_pdds; i++) {
2861 struct kfd_process_device *pdd = p->pdds[i];
2862 struct device_queue_manager *dqm = pdd->dev->dqm;
2863 struct qcm_process_device *qpd = &pdd->qpd;
2864 struct queue *q;
2865 int r, per_device_resumed = 0;
2866
2867 dqm_lock(dqm);
2868
2869 /* unmask queues that resume or already resumed as valid */
2870 list_for_each_entry(q, &qpd->queues_list, list) {
2871 int q_idx = QUEUE_NOT_FOUND;
2872
2873 if (queue_ids)
2874 q_idx = q_array_get_index(
2875 q->properties.queue_id,
2876 num_queues,
2877 queue_ids);
2878
2879 if (!queue_ids || q_idx != QUEUE_NOT_FOUND) {
2880 int err = resume_single_queue(dqm, &pdd->qpd, q);
2881
2882 if (queue_ids) {
2883 if (!err) {
2884 queue_ids[q_idx] &=
2885 ~KFD_DBG_QUEUE_INVALID_MASK;
2886 } else {
2887 queue_ids[q_idx] |=
2888 KFD_DBG_QUEUE_ERROR_MASK;
2889 break;
2890 }
2891 }
2892
2893 if (dqm->dev->kfd->shared_resources.enable_mes) {
2894 wake_up_all(&dqm->destroy_wait);
2895 if (!err)
2896 total_resumed++;
2897 } else {
2898 per_device_resumed++;
2899 }
2900 }
2901 }
2902
2903 if (!per_device_resumed) {
2904 dqm_unlock(dqm);
2905 continue;
2906 }
2907
2908 r = execute_queues_cpsch(dqm,
2909 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES,
2910 0,
2911 USE_DEFAULT_GRACE_PERIOD);
2912 if (r) {
2913 pr_err("Failed to resume process queues\n");
2914 if (queue_ids) {
2915 list_for_each_entry(q, &qpd->queues_list, list) {
2916 int q_idx = q_array_get_index(
2917 q->properties.queue_id,
2918 num_queues,
2919 queue_ids);
2920
2921 /* mask queue as error on resume fail */
2922 if (q_idx != QUEUE_NOT_FOUND)
2923 queue_ids[q_idx] |=
2924 KFD_DBG_QUEUE_ERROR_MASK;
2925 }
2926 }
2927 } else {
2928 wake_up_all(&dqm->destroy_wait);
2929 total_resumed += per_device_resumed;
2930 }
2931
2932 dqm_unlock(dqm);
2933 }
2934
2935 if (queue_ids) {
2936 if (copy_to_user((void __user *)usr_queue_id_array, queue_ids,
2937 num_queues * sizeof(uint32_t)))
2938 pr_err("copy_to_user failed on queue resume\n");
2939
2940 kfree(queue_ids);
2941 }
2942
2943 return total_resumed;
2944 }
2945
suspend_queues(struct kfd_process * p,uint32_t num_queues,uint32_t grace_period,uint64_t exception_clear_mask,uint32_t * usr_queue_id_array)2946 int suspend_queues(struct kfd_process *p,
2947 uint32_t num_queues,
2948 uint32_t grace_period,
2949 uint64_t exception_clear_mask,
2950 uint32_t *usr_queue_id_array)
2951 {
2952 uint32_t *queue_ids = get_queue_ids(num_queues, usr_queue_id_array);
2953 int total_suspended = 0;
2954 int i;
2955
2956 if (IS_ERR(queue_ids))
2957 return PTR_ERR(queue_ids);
2958
2959 /* mask all queues as invalid. umask on successful request */
2960 q_array_invalidate(num_queues, queue_ids);
2961
2962 for (i = 0; i < p->n_pdds; i++) {
2963 struct kfd_process_device *pdd = p->pdds[i];
2964 struct device_queue_manager *dqm = pdd->dev->dqm;
2965 struct qcm_process_device *qpd = &pdd->qpd;
2966 struct queue *q;
2967 int r, per_device_suspended = 0;
2968
2969 mutex_lock(&p->event_mutex);
2970 dqm_lock(dqm);
2971
2972 /* unmask queues that suspend or already suspended */
2973 list_for_each_entry(q, &qpd->queues_list, list) {
2974 int q_idx = q_array_get_index(q->properties.queue_id,
2975 num_queues,
2976 queue_ids);
2977
2978 if (q_idx != QUEUE_NOT_FOUND) {
2979 int err = suspend_single_queue(dqm, pdd, q);
2980 bool is_mes = dqm->dev->kfd->shared_resources.enable_mes;
2981
2982 if (!err) {
2983 queue_ids[q_idx] &= ~KFD_DBG_QUEUE_INVALID_MASK;
2984 if (exception_clear_mask && is_mes)
2985 q->properties.exception_status &=
2986 ~exception_clear_mask;
2987
2988 if (is_mes)
2989 total_suspended++;
2990 else
2991 per_device_suspended++;
2992 } else if (err != -EBUSY) {
2993 r = err;
2994 queue_ids[q_idx] |= KFD_DBG_QUEUE_ERROR_MASK;
2995 break;
2996 }
2997 }
2998 }
2999
3000 if (!per_device_suspended) {
3001 dqm_unlock(dqm);
3002 mutex_unlock(&p->event_mutex);
3003 if (total_suspended)
3004 amdgpu_amdkfd_debug_mem_fence(dqm->dev->adev);
3005 continue;
3006 }
3007
3008 r = execute_queues_cpsch(dqm,
3009 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0,
3010 grace_period);
3011
3012 if (r)
3013 pr_err("Failed to suspend process queues.\n");
3014 else
3015 total_suspended += per_device_suspended;
3016
3017 list_for_each_entry(q, &qpd->queues_list, list) {
3018 int q_idx = q_array_get_index(q->properties.queue_id,
3019 num_queues, queue_ids);
3020
3021 if (q_idx == QUEUE_NOT_FOUND)
3022 continue;
3023
3024 /* mask queue as error on suspend fail */
3025 if (r)
3026 queue_ids[q_idx] |= KFD_DBG_QUEUE_ERROR_MASK;
3027 else if (exception_clear_mask)
3028 q->properties.exception_status &=
3029 ~exception_clear_mask;
3030 }
3031
3032 dqm_unlock(dqm);
3033 mutex_unlock(&p->event_mutex);
3034 amdgpu_device_flush_hdp(dqm->dev->adev, NULL);
3035 }
3036
3037 if (total_suspended) {
3038 struct copy_context_work_handler_workarea copy_context_worker;
3039
3040 INIT_WORK_ONSTACK(
3041 ©_context_worker.copy_context_work,
3042 copy_context_work_handler);
3043
3044 copy_context_worker.p = p;
3045
3046 schedule_work(©_context_worker.copy_context_work);
3047
3048
3049 flush_work(©_context_worker.copy_context_work);
3050 destroy_work_on_stack(©_context_worker.copy_context_work);
3051 }
3052
3053 if (copy_to_user((void __user *)usr_queue_id_array, queue_ids,
3054 num_queues * sizeof(uint32_t)))
3055 pr_err("copy_to_user failed on queue suspend\n");
3056
3057 kfree(queue_ids);
3058
3059 return total_suspended;
3060 }
3061
set_queue_type_for_user(struct queue_properties * q_props)3062 static uint32_t set_queue_type_for_user(struct queue_properties *q_props)
3063 {
3064 switch (q_props->type) {
3065 case KFD_QUEUE_TYPE_COMPUTE:
3066 return q_props->format == KFD_QUEUE_FORMAT_PM4
3067 ? KFD_IOC_QUEUE_TYPE_COMPUTE
3068 : KFD_IOC_QUEUE_TYPE_COMPUTE_AQL;
3069 case KFD_QUEUE_TYPE_SDMA:
3070 return KFD_IOC_QUEUE_TYPE_SDMA;
3071 case KFD_QUEUE_TYPE_SDMA_XGMI:
3072 return KFD_IOC_QUEUE_TYPE_SDMA_XGMI;
3073 default:
3074 WARN_ONCE(true, "queue type not recognized!");
3075 return 0xffffffff;
3076 };
3077 }
3078
set_queue_snapshot_entry(struct queue * q,uint64_t exception_clear_mask,struct kfd_queue_snapshot_entry * qss_entry)3079 void set_queue_snapshot_entry(struct queue *q,
3080 uint64_t exception_clear_mask,
3081 struct kfd_queue_snapshot_entry *qss_entry)
3082 {
3083 qss_entry->ring_base_address = q->properties.queue_address;
3084 qss_entry->write_pointer_address = (uint64_t)q->properties.write_ptr;
3085 qss_entry->read_pointer_address = (uint64_t)q->properties.read_ptr;
3086 qss_entry->ctx_save_restore_address =
3087 q->properties.ctx_save_restore_area_address;
3088 qss_entry->ctx_save_restore_area_size =
3089 q->properties.ctx_save_restore_area_size;
3090 qss_entry->exception_status = q->properties.exception_status;
3091 qss_entry->queue_id = q->properties.queue_id;
3092 qss_entry->gpu_id = q->device->id;
3093 qss_entry->ring_size = (uint32_t)q->properties.queue_size;
3094 qss_entry->queue_type = set_queue_type_for_user(&q->properties);
3095 q->properties.exception_status &= ~exception_clear_mask;
3096 }
3097
debug_lock_and_unmap(struct device_queue_manager * dqm)3098 int debug_lock_and_unmap(struct device_queue_manager *dqm)
3099 {
3100 int r;
3101
3102 if (dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) {
3103 pr_err("Unsupported on sched_policy: %i\n", dqm->sched_policy);
3104 return -EINVAL;
3105 }
3106
3107 if (!kfd_dbg_is_per_vmid_supported(dqm->dev))
3108 return 0;
3109
3110 dqm_lock(dqm);
3111
3112 r = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, 0, false);
3113 if (r)
3114 dqm_unlock(dqm);
3115
3116 return r;
3117 }
3118
debug_map_and_unlock(struct device_queue_manager * dqm)3119 int debug_map_and_unlock(struct device_queue_manager *dqm)
3120 {
3121 int r;
3122
3123 if (dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) {
3124 pr_err("Unsupported on sched_policy: %i\n", dqm->sched_policy);
3125 return -EINVAL;
3126 }
3127
3128 if (!kfd_dbg_is_per_vmid_supported(dqm->dev))
3129 return 0;
3130
3131 r = map_queues_cpsch(dqm);
3132
3133 dqm_unlock(dqm);
3134
3135 return r;
3136 }
3137
debug_refresh_runlist(struct device_queue_manager * dqm)3138 int debug_refresh_runlist(struct device_queue_manager *dqm)
3139 {
3140 int r = debug_lock_and_unmap(dqm);
3141
3142 if (r)
3143 return r;
3144
3145 return debug_map_and_unlock(dqm);
3146 }
3147
3148 #if defined(CONFIG_DEBUG_FS)
3149
seq_reg_dump(struct seq_file * m,uint32_t (* dump)[2],uint32_t n_regs)3150 static void seq_reg_dump(struct seq_file *m,
3151 uint32_t (*dump)[2], uint32_t n_regs)
3152 {
3153 uint32_t i, count;
3154
3155 for (i = 0, count = 0; i < n_regs; i++) {
3156 if (count == 0 ||
3157 dump[i-1][0] + sizeof(uint32_t) != dump[i][0]) {
3158 seq_printf(m, "%s %08x: %08x",
3159 i ? "\n" : "",
3160 dump[i][0], dump[i][1]);
3161 count = 7;
3162 } else {
3163 seq_printf(m, " %08x", dump[i][1]);
3164 count--;
3165 }
3166 }
3167
3168 seq_puts(m, "\n");
3169 }
3170
dqm_debugfs_hqds(struct seq_file * m,void * data)3171 int dqm_debugfs_hqds(struct seq_file *m, void *data)
3172 {
3173 struct device_queue_manager *dqm = data;
3174 uint32_t xcc_mask = dqm->dev->xcc_mask;
3175 uint32_t (*dump)[2], n_regs;
3176 int pipe, queue;
3177 int r = 0, xcc_id;
3178 uint32_t sdma_engine_start;
3179
3180 if (!dqm->sched_running) {
3181 seq_puts(m, " Device is stopped\n");
3182 return 0;
3183 }
3184
3185 for_each_inst(xcc_id, xcc_mask) {
3186 r = dqm->dev->kfd2kgd->hqd_dump(dqm->dev->adev,
3187 KFD_CIK_HIQ_PIPE,
3188 KFD_CIK_HIQ_QUEUE, &dump,
3189 &n_regs, xcc_id);
3190 if (!r) {
3191 seq_printf(
3192 m,
3193 " Inst %d, HIQ on MEC %d Pipe %d Queue %d\n",
3194 xcc_id,
3195 KFD_CIK_HIQ_PIPE / get_pipes_per_mec(dqm) + 1,
3196 KFD_CIK_HIQ_PIPE % get_pipes_per_mec(dqm),
3197 KFD_CIK_HIQ_QUEUE);
3198 seq_reg_dump(m, dump, n_regs);
3199
3200 kfree(dump);
3201 }
3202
3203 for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) {
3204 int pipe_offset = pipe * get_queues_per_pipe(dqm);
3205
3206 for (queue = 0; queue < get_queues_per_pipe(dqm); queue++) {
3207 if (!test_bit(pipe_offset + queue,
3208 dqm->dev->kfd->shared_resources.cp_queue_bitmap))
3209 continue;
3210
3211 r = dqm->dev->kfd2kgd->hqd_dump(dqm->dev->adev,
3212 pipe, queue,
3213 &dump, &n_regs,
3214 xcc_id);
3215 if (r)
3216 break;
3217
3218 seq_printf(m,
3219 " Inst %d, CP Pipe %d, Queue %d\n",
3220 xcc_id, pipe, queue);
3221 seq_reg_dump(m, dump, n_regs);
3222
3223 kfree(dump);
3224 }
3225 }
3226 }
3227
3228 sdma_engine_start = dqm->dev->node_id * get_num_all_sdma_engines(dqm);
3229 for (pipe = sdma_engine_start;
3230 pipe < (sdma_engine_start + get_num_all_sdma_engines(dqm));
3231 pipe++) {
3232 for (queue = 0;
3233 queue < dqm->dev->kfd->device_info.num_sdma_queues_per_engine;
3234 queue++) {
3235 r = dqm->dev->kfd2kgd->hqd_sdma_dump(
3236 dqm->dev->adev, pipe, queue, &dump, &n_regs);
3237 if (r)
3238 break;
3239
3240 seq_printf(m, " SDMA Engine %d, RLC %d\n",
3241 pipe, queue);
3242 seq_reg_dump(m, dump, n_regs);
3243
3244 kfree(dump);
3245 }
3246 }
3247
3248 return r;
3249 }
3250
dqm_debugfs_hang_hws(struct device_queue_manager * dqm)3251 int dqm_debugfs_hang_hws(struct device_queue_manager *dqm)
3252 {
3253 int r = 0;
3254
3255 dqm_lock(dqm);
3256 r = pm_debugfs_hang_hws(&dqm->packet_mgr);
3257 if (r) {
3258 dqm_unlock(dqm);
3259 return r;
3260 }
3261 dqm->active_runlist = true;
3262 r = execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES,
3263 0, USE_DEFAULT_GRACE_PERIOD);
3264 dqm_unlock(dqm);
3265
3266 return r;
3267 }
3268
3269 #endif
3270