xref: /openbmc/linux/drivers/ufs/host/ufs-exynos.h (revision 216f74e8)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * UFS Host Controller driver for Exynos specific extensions
4  *
5  * Copyright (C) 2014-2015 Samsung Electronics Co., Ltd.
6  *
7  */
8 
9 #ifndef _UFS_EXYNOS_H_
10 #define _UFS_EXYNOS_H_
11 
12 /*
13  * UNIPRO registers
14  */
15 #define UNIPRO_DBG_FORCE_DME_CTRL_STATE		0x150
16 
17 /*
18  * MIBs for PA debug registers
19  */
20 #define PA_DBG_CLK_PERIOD	0x9514
21 #define PA_DBG_TXPHY_CFGUPDT	0x9518
22 #define PA_DBG_RXPHY_CFGUPDT	0x9519
23 #define PA_DBG_MODE		0x9529
24 #define PA_DBG_SKIP_RESET_PHY	0x9539
25 #define PA_DBG_AUTOMODE_THLD	0x9536
26 #define PA_DBG_OV_TM		0x9540
27 #define PA_DBG_SKIP_LINE_RESET	0x9541
28 #define PA_DBG_LINE_RESET_REQ	0x9543
29 #define PA_DBG_OPTION_SUITE	0x9564
30 #define PA_DBG_OPTION_SUITE_DYN	0x9565
31 
32 /*
33  * MIBs for Transport Layer debug registers
34  */
35 #define T_DBG_SKIP_INIT_HIBERN8_EXIT	0xc001
36 
37 /*
38  * Exynos MPHY attributes
39  */
40 #define TX_LINERESET_N_VAL	0x0277
41 #define TX_LINERESET_N(v)	(((v) >> 10) & 0xFF)
42 #define TX_LINERESET_P_VAL	0x027D
43 #define TX_LINERESET_P(v)	(((v) >> 12) & 0xFF)
44 #define TX_OV_SLEEP_CNT_TIMER	0x028E
45 #define TX_OV_H8_ENTER_EN	(1 << 7)
46 #define TX_OV_SLEEP_CNT(v)	(((v) >> 5) & 0x7F)
47 #define TX_HIGH_Z_CNT_11_08	0x028C
48 #define TX_HIGH_Z_CNT_H(v)	(((v) >> 8) & 0xF)
49 #define TX_HIGH_Z_CNT_07_00	0x028D
50 #define TX_HIGH_Z_CNT_L(v)	((v) & 0xFF)
51 #define TX_BASE_NVAL_07_00	0x0293
52 #define TX_BASE_NVAL_L(v)	((v) & 0xFF)
53 #define TX_BASE_NVAL_15_08	0x0294
54 #define TX_BASE_NVAL_H(v)	(((v) >> 8) & 0xFF)
55 #define TX_GRAN_NVAL_07_00	0x0295
56 #define TX_GRAN_NVAL_L(v)	((v) & 0xFF)
57 #define TX_GRAN_NVAL_10_08	0x0296
58 #define TX_GRAN_NVAL_H(v)	(((v) >> 8) & 0x3)
59 
60 #define VND_TX_CLK_PRD		0xAA
61 #define VND_TX_CLK_PRD_EN	0xA9
62 #define VND_TX_LINERESET_PVALUE0	0xAD
63 #define VND_TX_LINERESET_PVALUE1	0xAC
64 #define VND_TX_LINERESET_PVALUE2	0xAB
65 
66 #define TX_LINE_RESET_TIME	3200
67 
68 #define VND_RX_CLK_PRD		0x12
69 #define VND_RX_CLK_PRD_EN	0x11
70 #define VND_RX_LINERESET_VALUE0	0x1D
71 #define VND_RX_LINERESET_VALUE1	0x1C
72 #define VND_RX_LINERESET_VALUE2	0x1B
73 
74 #define RX_LINE_RESET_TIME	1000
75 
76 #define RX_FILLER_ENABLE	0x0316
77 #define RX_FILLER_EN		(1 << 1)
78 #define RX_LINERESET_VAL	0x0317
79 #define RX_LINERESET(v)	(((v) >> 12) & 0xFF)
80 #define RX_LCC_IGNORE		0x0318
81 #define RX_SYNC_MASK_LENGTH	0x0321
82 #define RX_HIBERN8_WAIT_VAL_BIT_20_16	0x0331
83 #define RX_HIBERN8_WAIT_VAL_BIT_15_08	0x0332
84 #define RX_HIBERN8_WAIT_VAL_BIT_07_00	0x0333
85 #define RX_OV_SLEEP_CNT_TIMER	0x0340
86 #define RX_OV_SLEEP_CNT(v)	(((v) >> 6) & 0x1F)
87 #define RX_OV_STALL_CNT_TIMER	0x0341
88 #define RX_OV_STALL_CNT(v)	(((v) >> 4) & 0xFF)
89 #define RX_BASE_NVAL_07_00	0x0355
90 #define RX_BASE_NVAL_L(v)	((v) & 0xFF)
91 #define RX_BASE_NVAL_15_08	0x0354
92 #define RX_BASE_NVAL_H(v)	(((v) >> 8) & 0xFF)
93 #define RX_GRAN_NVAL_07_00	0x0353
94 #define RX_GRAN_NVAL_L(v)	((v) & 0xFF)
95 #define RX_GRAN_NVAL_10_08	0x0352
96 #define RX_GRAN_NVAL_H(v)	(((v) >> 8) & 0x3)
97 
98 #define CMN_PWM_CLK_CTRL	0x0402
99 #define PWM_CLK_CTRL_MASK	0x3
100 
101 #define IATOVAL_NSEC		20000	/* unit: ns */
102 #define UNIPRO_PCLK_PERIOD(ufs) (NSEC_PER_SEC / ufs->pclk_rate)
103 
104 struct exynos_ufs;
105 
106 /* vendor specific pre-defined parameters */
107 #define SLOW 1
108 #define FAST 2
109 
110 #define RX_ADV_FINE_GRAN_SUP_EN	0x1
111 #define RX_ADV_FINE_GRAN_STEP_VAL	0x3
112 #define RX_ADV_MIN_ACTV_TIME_CAP	0x9
113 
114 #define PA_GRANULARITY_VAL	0x6
115 #define PA_TACTIVATE_VAL	0x3
116 #define PA_HIBERN8TIME_VAL	0x20
117 
118 #define PCLK_AVAIL_MIN	70000000
119 #define PCLK_AVAIL_MAX	167000000
120 
121 struct exynos_ufs_uic_attr {
122 	/* TX Attributes */
123 	unsigned int tx_trailingclks;
124 	unsigned int tx_dif_p_nsec;
125 	unsigned int tx_dif_n_nsec;
126 	unsigned int tx_high_z_cnt_nsec;
127 	unsigned int tx_base_unit_nsec;
128 	unsigned int tx_gran_unit_nsec;
129 	unsigned int tx_sleep_cnt;
130 	unsigned int tx_min_activatetime;
131 	/* RX Attributes */
132 	unsigned int rx_filler_enable;
133 	unsigned int rx_dif_p_nsec;
134 	unsigned int rx_hibern8_wait_nsec;
135 	unsigned int rx_base_unit_nsec;
136 	unsigned int rx_gran_unit_nsec;
137 	unsigned int rx_sleep_cnt;
138 	unsigned int rx_stall_cnt;
139 	unsigned int rx_hs_g1_sync_len_cap;
140 	unsigned int rx_hs_g2_sync_len_cap;
141 	unsigned int rx_hs_g3_sync_len_cap;
142 	unsigned int rx_hs_g1_prep_sync_len_cap;
143 	unsigned int rx_hs_g2_prep_sync_len_cap;
144 	unsigned int rx_hs_g3_prep_sync_len_cap;
145 	/* Common Attributes */
146 	unsigned int cmn_pwm_clk_ctrl;
147 	/* Internal Attributes */
148 	unsigned int pa_dbg_option_suite;
149 	/* Changeable Attributes */
150 	unsigned int rx_adv_fine_gran_sup_en;
151 	unsigned int rx_adv_fine_gran_step;
152 	unsigned int rx_min_actv_time_cap;
153 	unsigned int rx_hibern8_time_cap;
154 	unsigned int rx_adv_min_actv_time_cap;
155 	unsigned int rx_adv_hibern8_time_cap;
156 	unsigned int pa_granularity;
157 	unsigned int pa_tactivate;
158 	unsigned int pa_hibern8time;
159 };
160 
161 struct exynos_ufs_drv_data {
162 	const struct ufs_hba_variant_ops *vops;
163 	struct exynos_ufs_uic_attr *uic_attr;
164 	unsigned int quirks;
165 	unsigned int opts;
166 	/* SoC's specific operations */
167 	int (*drv_init)(struct device *dev, struct exynos_ufs *ufs);
168 	int (*pre_link)(struct exynos_ufs *ufs);
169 	int (*post_link)(struct exynos_ufs *ufs);
170 	int (*pre_pwr_change)(struct exynos_ufs *ufs,
171 				struct ufs_pa_layer_attr *pwr);
172 	int (*post_pwr_change)(struct exynos_ufs *ufs,
173 				struct ufs_pa_layer_attr *pwr);
174 	int (*pre_hce_enable)(struct exynos_ufs *ufs);
175 	int (*post_hce_enable)(struct exynos_ufs *ufs);
176 };
177 
178 struct ufs_phy_time_cfg {
179 	u32 tx_linereset_p;
180 	u32 tx_linereset_n;
181 	u32 tx_high_z_cnt;
182 	u32 tx_base_n_val;
183 	u32 tx_gran_n_val;
184 	u32 tx_sleep_cnt;
185 	u32 rx_linereset;
186 	u32 rx_hibern8_wait;
187 	u32 rx_base_n_val;
188 	u32 rx_gran_n_val;
189 	u32 rx_sleep_cnt;
190 	u32 rx_stall_cnt;
191 };
192 
193 struct exynos_ufs {
194 	struct ufs_hba *hba;
195 	struct phy *phy;
196 	void __iomem *reg_hci;
197 	void __iomem *reg_unipro;
198 	void __iomem *reg_ufsp;
199 	struct clk *clk_hci_core;
200 	struct clk *clk_unipro_main;
201 	struct clk *clk_apb;
202 	u32 pclk_rate;
203 	u32 pclk_div;
204 	u32 pclk_avail_min;
205 	u32 pclk_avail_max;
206 	unsigned long mclk_rate;
207 	int avail_ln_rx;
208 	int avail_ln_tx;
209 	int rx_sel_idx;
210 	struct ufs_pa_layer_attr dev_req_params;
211 	struct ufs_phy_time_cfg t_cfg;
212 	ktime_t entry_hibern8_t;
213 	const struct exynos_ufs_drv_data *drv_data;
214 	struct regmap *sysreg;
215 	u32 shareability_reg_offset;
216 
217 	u32 opts;
218 #define EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL		BIT(0)
219 #define EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB	BIT(1)
220 #define EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL	BIT(2)
221 #define EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX	BIT(3)
222 #define EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER	BIT(4)
223 #define EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR	BIT(5)
224 };
225 
226 #define for_each_ufs_rx_lane(ufs, i) \
227 	for (i = (ufs)->rx_sel_idx; \
228 		i < (ufs)->rx_sel_idx + (ufs)->avail_ln_rx; i++)
229 #define for_each_ufs_tx_lane(ufs, i) \
230 	for (i = 0; i < (ufs)->avail_ln_tx; i++)
231 
232 #define EXYNOS_UFS_MMIO_FUNC(name)					  \
233 static inline void name##_writel(struct exynos_ufs *ufs, u32 val, u32 reg)\
234 {									  \
235 	writel(val, ufs->reg_##name + reg);				  \
236 }									  \
237 									  \
238 static inline u32 name##_readl(struct exynos_ufs *ufs, u32 reg)		  \
239 {									  \
240 	return readl(ufs->reg_##name + reg);				  \
241 }
242 
243 EXYNOS_UFS_MMIO_FUNC(hci);
244 EXYNOS_UFS_MMIO_FUNC(unipro);
245 EXYNOS_UFS_MMIO_FUNC(ufsp);
246 #undef EXYNOS_UFS_MMIO_FUNC
247 
248 long exynos_ufs_calc_time_cntr(struct exynos_ufs *, long);
249 
exynos_ufs_enable_ov_tm(struct ufs_hba * hba)250 static inline void exynos_ufs_enable_ov_tm(struct ufs_hba *hba)
251 {
252 	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OV_TM), true);
253 }
254 
exynos_ufs_disable_ov_tm(struct ufs_hba * hba)255 static inline void exynos_ufs_disable_ov_tm(struct ufs_hba *hba)
256 {
257 	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OV_TM), false);
258 }
259 
exynos_ufs_enable_dbg_mode(struct ufs_hba * hba)260 static inline void exynos_ufs_enable_dbg_mode(struct ufs_hba *hba)
261 {
262 	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_MODE), true);
263 }
264 
exynos_ufs_disable_dbg_mode(struct ufs_hba * hba)265 static inline void exynos_ufs_disable_dbg_mode(struct ufs_hba *hba)
266 {
267 	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_MODE), false);
268 }
269 
270 #endif /* _UFS_EXYNOS_H_ */
271