1 2 /* 3 * PowerPC CPU initialization for qemu. 4 * 5 * Copyright (c) 2003-2007 Jocelyn Mayer 6 * Copyright 2011 Freescale Semiconductor, Inc. 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2.1 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "disas/dis-asm.h" 24 #include "gdbstub/helpers.h" 25 #include "system/cpus.h" 26 #include "system/hw_accel.h" 27 #include "system/tcg.h" 28 #include "cpu-models.h" 29 #include "mmu-hash32.h" 30 #include "mmu-hash64.h" 31 #include "qemu/error-report.h" 32 #include "qemu/module.h" 33 #include "qemu/qemu-print.h" 34 #include "qapi/error.h" 35 #include "qobject/qnull.h" 36 #include "qapi/visitor.h" 37 #include "hw/qdev-properties.h" 38 #include "hw/ppc/ppc.h" 39 #include "mmu-book3s-v3.h" 40 #include "qemu/cutils.h" 41 #include "disas/capstone.h" 42 #include "fpu/softfloat.h" 43 #include "exec/watchpoint.h" 44 #include "helper_regs.h" 45 #include "internal.h" 46 #include "spr_common.h" 47 #include "power8-pmu.h" 48 #ifndef CONFIG_USER_ONLY 49 #include "hw/boards.h" 50 #include "hw/intc/intc.h" 51 #include "kvm_ppc.h" 52 #endif 53 54 #include "cpu_init.h" 55 /* #define PPC_DEBUG_SPR */ 56 /* #define USE_APPLE_GDB */ 57 58 static inline void vscr_init(CPUPPCState *env, uint32_t val) 59 { 60 /* Altivec always uses round-to-nearest */ 61 set_float_rounding_mode(float_round_nearest_even, &env->vec_status); 62 ppc_store_vscr(env, val); 63 } 64 65 static void register_745_sprs(CPUPPCState *env) 66 { 67 /* SGPRs */ 68 spr_register(env, SPR_SPRG4, "SPRG4", 69 SPR_NOACCESS, SPR_NOACCESS, 70 &spr_read_generic, &spr_write_generic, 71 0x00000000); 72 spr_register(env, SPR_SPRG5, "SPRG5", 73 SPR_NOACCESS, SPR_NOACCESS, 74 &spr_read_generic, &spr_write_generic, 75 0x00000000); 76 spr_register(env, SPR_SPRG6, "SPRG6", 77 SPR_NOACCESS, SPR_NOACCESS, 78 &spr_read_generic, &spr_write_generic, 79 0x00000000); 80 spr_register(env, SPR_SPRG7, "SPRG7", 81 SPR_NOACCESS, SPR_NOACCESS, 82 &spr_read_generic, &spr_write_generic, 83 0x00000000); 84 85 /* Hardware implementation registers */ 86 spr_register(env, SPR_HID0, "HID0", 87 SPR_NOACCESS, SPR_NOACCESS, 88 &spr_read_generic, &spr_write_generic, 89 0x00000000); 90 91 spr_register(env, SPR_HID1, "HID1", 92 SPR_NOACCESS, SPR_NOACCESS, 93 &spr_read_generic, &spr_write_generic, 94 0x00000000); 95 96 spr_register(env, SPR_HID2, "HID2", 97 SPR_NOACCESS, SPR_NOACCESS, 98 &spr_read_generic, &spr_write_generic, 99 0x00000000); 100 } 101 102 static void register_755_sprs(CPUPPCState *env) 103 { 104 /* L2 cache control */ 105 spr_register(env, SPR_L2CR, "L2CR", 106 SPR_NOACCESS, SPR_NOACCESS, 107 &spr_read_generic, spr_access_nop, 108 0x00000000); 109 110 spr_register(env, SPR_L2PMCR, "L2PMCR", 111 SPR_NOACCESS, SPR_NOACCESS, 112 &spr_read_generic, &spr_write_generic, 113 0x00000000); 114 } 115 116 /* SPR common to all 7xx PowerPC implementations */ 117 static void register_7xx_sprs(CPUPPCState *env) 118 { 119 /* Breakpoints */ 120 spr_register_kvm(env, SPR_DABR, "DABR", 121 SPR_NOACCESS, SPR_NOACCESS, 122 &spr_read_generic, &spr_write_generic, 123 KVM_REG_PPC_DABR, 0x00000000); 124 125 spr_register(env, SPR_IABR, "IABR", 126 SPR_NOACCESS, SPR_NOACCESS, 127 &spr_read_generic, &spr_write_generic, 128 0x00000000); 129 /* Cache management */ 130 spr_register(env, SPR_ICTC, "ICTC", 131 SPR_NOACCESS, SPR_NOACCESS, 132 &spr_read_generic, &spr_write_generic, 133 0x00000000); 134 /* Performance monitors */ 135 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 136 SPR_NOACCESS, SPR_NOACCESS, 137 &spr_read_generic, &spr_write_generic, 138 0x00000000); 139 140 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 141 SPR_NOACCESS, SPR_NOACCESS, 142 &spr_read_generic, &spr_write_generic, 143 0x00000000); 144 145 spr_register(env, SPR_7XX_PMC1, "PMC1", 146 SPR_NOACCESS, SPR_NOACCESS, 147 &spr_read_generic, &spr_write_generic, 148 0x00000000); 149 150 spr_register(env, SPR_7XX_PMC2, "PMC2", 151 SPR_NOACCESS, SPR_NOACCESS, 152 &spr_read_generic, &spr_write_generic, 153 0x00000000); 154 155 spr_register(env, SPR_7XX_PMC3, "PMC3", 156 SPR_NOACCESS, SPR_NOACCESS, 157 &spr_read_generic, &spr_write_generic, 158 0x00000000); 159 160 spr_register(env, SPR_7XX_PMC4, "PMC4", 161 SPR_NOACCESS, SPR_NOACCESS, 162 &spr_read_generic, &spr_write_generic, 163 0x00000000); 164 165 spr_register(env, SPR_7XX_SIAR, "SIAR", 166 SPR_NOACCESS, SPR_NOACCESS, 167 &spr_read_generic, SPR_NOACCESS, 168 0x00000000); 169 170 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0", 171 &spr_read_ureg, SPR_NOACCESS, 172 &spr_read_ureg, SPR_NOACCESS, 173 0x00000000); 174 175 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1", 176 &spr_read_ureg, SPR_NOACCESS, 177 &spr_read_ureg, SPR_NOACCESS, 178 0x00000000); 179 180 spr_register(env, SPR_7XX_UPMC1, "UPMC1", 181 &spr_read_ureg, SPR_NOACCESS, 182 &spr_read_ureg, SPR_NOACCESS, 183 0x00000000); 184 185 spr_register(env, SPR_7XX_UPMC2, "UPMC2", 186 &spr_read_ureg, SPR_NOACCESS, 187 &spr_read_ureg, SPR_NOACCESS, 188 0x00000000); 189 190 spr_register(env, SPR_7XX_UPMC3, "UPMC3", 191 &spr_read_ureg, SPR_NOACCESS, 192 &spr_read_ureg, SPR_NOACCESS, 193 0x00000000); 194 195 spr_register(env, SPR_7XX_UPMC4, "UPMC4", 196 &spr_read_ureg, SPR_NOACCESS, 197 &spr_read_ureg, SPR_NOACCESS, 198 0x00000000); 199 200 spr_register(env, SPR_7XX_USIAR, "USIAR", 201 &spr_read_ureg, SPR_NOACCESS, 202 &spr_read_ureg, SPR_NOACCESS, 203 0x00000000); 204 /* External access control */ 205 spr_register(env, SPR_EAR, "EAR", 206 SPR_NOACCESS, SPR_NOACCESS, 207 &spr_read_generic, &spr_write_generic, 208 0x00000000); 209 210 /* Hardware implementation registers */ 211 spr_register(env, SPR_HID0, "HID0", 212 SPR_NOACCESS, SPR_NOACCESS, 213 &spr_read_generic, &spr_write_generic, 214 0x00000000); 215 216 spr_register(env, SPR_HID1, "HID1", 217 SPR_NOACCESS, SPR_NOACCESS, 218 &spr_read_generic, &spr_write_generic, 219 0x00000000); 220 } 221 222 #ifdef TARGET_PPC64 223 static void register_amr_sprs(CPUPPCState *env) 224 { 225 #ifndef CONFIG_USER_ONLY 226 /* 227 * Virtual Page Class Key protection 228 * 229 * The AMR is accessible either via SPR 13 or SPR 29. 13 is 230 * userspace accessible, 29 is privileged. So we only need to set 231 * the kvm ONE_REG id on one of them, we use 29 232 */ 233 spr_register(env, SPR_UAMR, "UAMR", 234 &spr_read_generic, &spr_write_amr, 235 &spr_read_generic, &spr_write_amr, 236 0); 237 spr_register_kvm_hv(env, SPR_AMR, "AMR", 238 SPR_NOACCESS, SPR_NOACCESS, 239 &spr_read_generic, &spr_write_amr, 240 &spr_read_generic, &spr_write_generic, 241 KVM_REG_PPC_AMR, 0); 242 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR", 243 SPR_NOACCESS, SPR_NOACCESS, 244 &spr_read_generic, &spr_write_uamor, 245 &spr_read_generic, &spr_write_generic, 246 KVM_REG_PPC_UAMOR, 0); 247 spr_register_hv(env, SPR_AMOR, "AMOR", 248 SPR_NOACCESS, SPR_NOACCESS, 249 SPR_NOACCESS, SPR_NOACCESS, 250 &spr_read_generic, &spr_core_lpar_write_generic, 251 0); 252 #endif /* !CONFIG_USER_ONLY */ 253 } 254 255 static void register_iamr_sprs(CPUPPCState *env) 256 { 257 #ifndef CONFIG_USER_ONLY 258 spr_register_kvm_hv(env, SPR_IAMR, "IAMR", 259 SPR_NOACCESS, SPR_NOACCESS, 260 &spr_read_generic, &spr_write_iamr, 261 &spr_read_generic, &spr_write_generic, 262 KVM_REG_PPC_IAMR, 0); 263 #endif /* !CONFIG_USER_ONLY */ 264 } 265 #endif /* TARGET_PPC64 */ 266 267 /* SPR specific to PowerPC 604 implementation */ 268 static void register_604_sprs(CPUPPCState *env) 269 { 270 /* Processor identification */ 271 spr_register(env, SPR_PIR, "PIR", 272 SPR_NOACCESS, SPR_NOACCESS, 273 &spr_read_generic, &spr_write_pir, 274 0x00000000); 275 /* Breakpoints */ 276 spr_register(env, SPR_IABR, "IABR", 277 SPR_NOACCESS, SPR_NOACCESS, 278 &spr_read_generic, &spr_write_generic, 279 0x00000000); 280 281 spr_register_kvm(env, SPR_DABR, "DABR", 282 SPR_NOACCESS, SPR_NOACCESS, 283 &spr_read_generic, &spr_write_generic, 284 KVM_REG_PPC_DABR, 0x00000000); 285 /* Performance counters */ 286 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 287 SPR_NOACCESS, SPR_NOACCESS, 288 &spr_read_generic, &spr_write_generic, 289 0x00000000); 290 291 spr_register(env, SPR_7XX_PMC1, "PMC1", 292 SPR_NOACCESS, SPR_NOACCESS, 293 &spr_read_generic, &spr_write_generic, 294 0x00000000); 295 296 spr_register(env, SPR_7XX_PMC2, "PMC2", 297 SPR_NOACCESS, SPR_NOACCESS, 298 &spr_read_generic, &spr_write_generic, 299 0x00000000); 300 301 spr_register(env, SPR_7XX_SIAR, "SIAR", 302 SPR_NOACCESS, SPR_NOACCESS, 303 &spr_read_generic, SPR_NOACCESS, 304 0x00000000); 305 306 spr_register(env, SPR_SDA, "SDA", 307 SPR_NOACCESS, SPR_NOACCESS, 308 &spr_read_generic, SPR_NOACCESS, 309 0x00000000); 310 /* External access control */ 311 spr_register(env, SPR_EAR, "EAR", 312 SPR_NOACCESS, SPR_NOACCESS, 313 &spr_read_generic, &spr_write_generic, 314 0x00000000); 315 316 /* Hardware implementation registers */ 317 spr_register(env, SPR_HID0, "HID0", 318 SPR_NOACCESS, SPR_NOACCESS, 319 &spr_read_generic, &spr_write_generic, 320 0x00000000); 321 } 322 323 static void register_604e_sprs(CPUPPCState *env) 324 { 325 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 326 SPR_NOACCESS, SPR_NOACCESS, 327 &spr_read_generic, &spr_write_generic, 328 0x00000000); 329 330 spr_register(env, SPR_7XX_PMC3, "PMC3", 331 SPR_NOACCESS, SPR_NOACCESS, 332 &spr_read_generic, &spr_write_generic, 333 0x00000000); 334 335 spr_register(env, SPR_7XX_PMC4, "PMC4", 336 SPR_NOACCESS, SPR_NOACCESS, 337 &spr_read_generic, &spr_write_generic, 338 0x00000000); 339 /* Hardware implementation registers */ 340 spr_register(env, SPR_HID1, "HID1", 341 SPR_NOACCESS, SPR_NOACCESS, 342 &spr_read_generic, &spr_write_generic, 343 0x00000000); 344 } 345 346 /* SPR specific to PowerPC 603 implementation */ 347 static void register_603_sprs(CPUPPCState *env) 348 { 349 /* External access control */ 350 spr_register(env, SPR_EAR, "EAR", 351 SPR_NOACCESS, SPR_NOACCESS, 352 &spr_read_generic, &spr_write_generic, 353 0x00000000); 354 /* Breakpoints */ 355 spr_register(env, SPR_IABR, "IABR", 356 SPR_NOACCESS, SPR_NOACCESS, 357 &spr_read_generic, &spr_write_generic, 358 0x00000000); 359 360 spr_register(env, SPR_HID0, "HID0", 361 SPR_NOACCESS, SPR_NOACCESS, 362 &spr_read_generic, &spr_write_generic, 363 0x00000000); 364 365 spr_register(env, SPR_HID1, "HID1", 366 SPR_NOACCESS, SPR_NOACCESS, 367 &spr_read_generic, &spr_write_generic, 368 0x00000000); 369 } 370 371 static void register_e300_sprs(CPUPPCState *env) 372 { 373 /* hardware implementation registers */ 374 spr_register(env, SPR_HID2, "HID2", 375 SPR_NOACCESS, SPR_NOACCESS, 376 &spr_read_generic, &spr_write_generic, 377 0x00000000); 378 /* Breakpoints */ 379 spr_register(env, SPR_DABR, "DABR", 380 SPR_NOACCESS, SPR_NOACCESS, 381 &spr_read_generic, &spr_write_generic, 382 0x00000000); 383 384 spr_register(env, SPR_DABR2, "DABR2", 385 SPR_NOACCESS, SPR_NOACCESS, 386 &spr_read_generic, &spr_write_generic, 387 0x00000000); 388 389 spr_register(env, SPR_IABR2, "IABR2", 390 SPR_NOACCESS, SPR_NOACCESS, 391 &spr_read_generic, &spr_write_generic, 392 0x00000000); 393 394 spr_register(env, SPR_IBCR, "IBCR", 395 SPR_NOACCESS, SPR_NOACCESS, 396 &spr_read_generic, &spr_write_generic, 397 0x00000000); 398 399 spr_register(env, SPR_DBCR, "DBCR", 400 SPR_NOACCESS, SPR_NOACCESS, 401 &spr_read_generic, &spr_write_generic, 402 0x00000000); 403 } 404 405 /* SPR specific to PowerPC G2 implementation */ 406 static void register_G2_sprs(CPUPPCState *env) 407 { 408 /* Memory base address */ 409 /* MBAR */ 410 spr_register(env, SPR_MBAR, "MBAR", 411 SPR_NOACCESS, SPR_NOACCESS, 412 &spr_read_generic, &spr_write_generic, 413 0x00000000); 414 /* Exception processing */ 415 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 416 SPR_NOACCESS, SPR_NOACCESS, 417 &spr_read_generic, &spr_write_generic, 418 0x00000000); 419 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 420 SPR_NOACCESS, SPR_NOACCESS, 421 &spr_read_generic, &spr_write_generic, 422 0x00000000); 423 /* Breakpoints */ 424 spr_register(env, SPR_DABR, "DABR", 425 SPR_NOACCESS, SPR_NOACCESS, 426 &spr_read_generic, &spr_write_generic, 427 0x00000000); 428 429 spr_register(env, SPR_DABR2, "DABR2", 430 SPR_NOACCESS, SPR_NOACCESS, 431 &spr_read_generic, &spr_write_generic, 432 0x00000000); 433 434 spr_register(env, SPR_IABR, "IABR", 435 SPR_NOACCESS, SPR_NOACCESS, 436 &spr_read_generic, &spr_write_generic, 437 0x00000000); 438 439 spr_register(env, SPR_IABR2, "IABR2", 440 SPR_NOACCESS, SPR_NOACCESS, 441 &spr_read_generic, &spr_write_generic, 442 0x00000000); 443 444 spr_register(env, SPR_IBCR, "IBCR", 445 SPR_NOACCESS, SPR_NOACCESS, 446 &spr_read_generic, &spr_write_generic, 447 0x00000000); 448 449 spr_register(env, SPR_DBCR, "DBCR", 450 SPR_NOACCESS, SPR_NOACCESS, 451 &spr_read_generic, &spr_write_generic, 452 0x00000000); 453 454 /* External access control */ 455 spr_register(env, SPR_EAR, "EAR", 456 SPR_NOACCESS, SPR_NOACCESS, 457 &spr_read_generic, &spr_write_generic, 458 0x00000000); 459 /* Hardware implementation register */ 460 spr_register(env, SPR_HID0, "HID0", 461 SPR_NOACCESS, SPR_NOACCESS, 462 &spr_read_generic, &spr_write_generic, 463 0x00000000); 464 465 spr_register(env, SPR_HID1, "HID1", 466 SPR_NOACCESS, SPR_NOACCESS, 467 &spr_read_generic, &spr_write_generic, 468 0x00000000); 469 470 spr_register(env, SPR_HID2, "HID2", 471 SPR_NOACCESS, SPR_NOACCESS, 472 &spr_read_generic, &spr_write_generic, 473 0x00000000); 474 475 /* SGPRs */ 476 spr_register(env, SPR_SPRG4, "SPRG4", 477 SPR_NOACCESS, SPR_NOACCESS, 478 &spr_read_generic, &spr_write_generic, 479 0x00000000); 480 spr_register(env, SPR_SPRG5, "SPRG5", 481 SPR_NOACCESS, SPR_NOACCESS, 482 &spr_read_generic, &spr_write_generic, 483 0x00000000); 484 spr_register(env, SPR_SPRG6, "SPRG6", 485 SPR_NOACCESS, SPR_NOACCESS, 486 &spr_read_generic, &spr_write_generic, 487 0x00000000); 488 spr_register(env, SPR_SPRG7, "SPRG7", 489 SPR_NOACCESS, SPR_NOACCESS, 490 &spr_read_generic, &spr_write_generic, 491 0x00000000); 492 } 493 494 static void register_74xx_sprs(CPUPPCState *env) 495 { 496 /* Breakpoints */ 497 spr_register_kvm(env, SPR_DABR, "DABR", 498 SPR_NOACCESS, SPR_NOACCESS, 499 &spr_read_generic, &spr_write_generic, 500 KVM_REG_PPC_DABR, 0x00000000); 501 502 spr_register(env, SPR_IABR, "IABR", 503 SPR_NOACCESS, SPR_NOACCESS, 504 &spr_read_generic, &spr_write_generic, 505 0x00000000); 506 /* Cache management */ 507 spr_register(env, SPR_ICTC, "ICTC", 508 SPR_NOACCESS, SPR_NOACCESS, 509 &spr_read_generic, &spr_write_generic, 510 0x00000000); 511 /* Performance monitors */ 512 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 513 SPR_NOACCESS, SPR_NOACCESS, 514 &spr_read_generic, &spr_write_generic, 515 0x00000000); 516 517 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 518 SPR_NOACCESS, SPR_NOACCESS, 519 &spr_read_generic, &spr_write_generic, 520 0x00000000); 521 522 spr_register(env, SPR_7XX_PMC1, "PMC1", 523 SPR_NOACCESS, SPR_NOACCESS, 524 &spr_read_generic, &spr_write_generic, 525 0x00000000); 526 527 spr_register(env, SPR_7XX_PMC2, "PMC2", 528 SPR_NOACCESS, SPR_NOACCESS, 529 &spr_read_generic, &spr_write_generic, 530 0x00000000); 531 532 spr_register(env, SPR_7XX_PMC3, "PMC3", 533 SPR_NOACCESS, SPR_NOACCESS, 534 &spr_read_generic, &spr_write_generic, 535 0x00000000); 536 537 spr_register(env, SPR_7XX_PMC4, "PMC4", 538 SPR_NOACCESS, SPR_NOACCESS, 539 &spr_read_generic, &spr_write_generic, 540 0x00000000); 541 542 spr_register(env, SPR_7XX_SIAR, "SIAR", 543 SPR_NOACCESS, SPR_NOACCESS, 544 &spr_read_generic, SPR_NOACCESS, 545 0x00000000); 546 547 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0", 548 &spr_read_ureg, SPR_NOACCESS, 549 &spr_read_ureg, SPR_NOACCESS, 550 0x00000000); 551 552 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1", 553 &spr_read_ureg, SPR_NOACCESS, 554 &spr_read_ureg, SPR_NOACCESS, 555 0x00000000); 556 557 spr_register(env, SPR_7XX_UPMC1, "UPMC1", 558 &spr_read_ureg, SPR_NOACCESS, 559 &spr_read_ureg, SPR_NOACCESS, 560 0x00000000); 561 562 spr_register(env, SPR_7XX_UPMC2, "UPMC2", 563 &spr_read_ureg, SPR_NOACCESS, 564 &spr_read_ureg, SPR_NOACCESS, 565 0x00000000); 566 567 spr_register(env, SPR_7XX_UPMC3, "UPMC3", 568 &spr_read_ureg, SPR_NOACCESS, 569 &spr_read_ureg, SPR_NOACCESS, 570 0x00000000); 571 572 spr_register(env, SPR_7XX_UPMC4, "UPMC4", 573 &spr_read_ureg, SPR_NOACCESS, 574 &spr_read_ureg, SPR_NOACCESS, 575 0x00000000); 576 577 spr_register(env, SPR_7XX_USIAR, "USIAR", 578 &spr_read_ureg, SPR_NOACCESS, 579 &spr_read_ureg, SPR_NOACCESS, 580 0x00000000); 581 /* External access control */ 582 spr_register(env, SPR_EAR, "EAR", 583 SPR_NOACCESS, SPR_NOACCESS, 584 &spr_read_generic, &spr_write_generic, 585 0x00000000); 586 587 /* Processor identification */ 588 spr_register(env, SPR_PIR, "PIR", 589 SPR_NOACCESS, SPR_NOACCESS, 590 &spr_read_generic, &spr_write_pir, 591 0x00000000); 592 593 spr_register(env, SPR_74XX_MMCR2, "MMCR2", 594 SPR_NOACCESS, SPR_NOACCESS, 595 &spr_read_generic, &spr_write_generic, 596 0x00000000); 597 598 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2", 599 &spr_read_ureg, SPR_NOACCESS, 600 &spr_read_ureg, SPR_NOACCESS, 601 0x00000000); 602 603 spr_register(env, SPR_BAMR, "BAMR", 604 SPR_NOACCESS, SPR_NOACCESS, 605 &spr_read_generic, &spr_write_generic, 606 0x00000000); 607 608 spr_register(env, SPR_MSSCR0, "MSSCR0", 609 SPR_NOACCESS, SPR_NOACCESS, 610 &spr_read_generic, &spr_write_generic, 611 0x00000000); 612 /* Hardware implementation registers */ 613 spr_register(env, SPR_HID0, "HID0", 614 SPR_NOACCESS, SPR_NOACCESS, 615 &spr_read_generic, &spr_write_generic, 616 0x00000000); 617 618 spr_register(env, SPR_HID1, "HID1", 619 SPR_NOACCESS, SPR_NOACCESS, 620 &spr_read_generic, &spr_write_generic, 621 0x00000000); 622 /* Altivec */ 623 spr_register(env, SPR_VRSAVE, "VRSAVE", 624 &spr_read_generic, &spr_write_generic, 625 &spr_read_generic, &spr_write_generic, 626 0x00000000); 627 628 spr_register(env, SPR_L2CR, "L2CR", 629 SPR_NOACCESS, SPR_NOACCESS, 630 &spr_read_generic, spr_access_nop, 631 0x00000000); 632 } 633 634 static void register_l3_ctrl(CPUPPCState *env) 635 { 636 /* L3CR */ 637 spr_register(env, SPR_L3CR, "L3CR", 638 SPR_NOACCESS, SPR_NOACCESS, 639 &spr_read_generic, &spr_write_generic, 640 0x00000000); 641 /* L3ITCR0 */ 642 spr_register(env, SPR_L3ITCR0, "L3ITCR0", 643 SPR_NOACCESS, SPR_NOACCESS, 644 &spr_read_generic, &spr_write_generic, 645 0x00000000); 646 /* L3PM */ 647 spr_register(env, SPR_L3PM, "L3PM", 648 SPR_NOACCESS, SPR_NOACCESS, 649 &spr_read_generic, &spr_write_generic, 650 0x00000000); 651 } 652 653 /* PowerPC BookE SPR */ 654 static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask) 655 { 656 const char *ivor_names[64] = { 657 "IVOR0", "IVOR1", "IVOR2", "IVOR3", 658 "IVOR4", "IVOR5", "IVOR6", "IVOR7", 659 "IVOR8", "IVOR9", "IVOR10", "IVOR11", 660 "IVOR12", "IVOR13", "IVOR14", "IVOR15", 661 "IVOR16", "IVOR17", "IVOR18", "IVOR19", 662 "IVOR20", "IVOR21", "IVOR22", "IVOR23", 663 "IVOR24", "IVOR25", "IVOR26", "IVOR27", 664 "IVOR28", "IVOR29", "IVOR30", "IVOR31", 665 "IVOR32", "IVOR33", "IVOR34", "IVOR35", 666 "IVOR36", "IVOR37", "IVOR38", "IVOR39", 667 "IVOR40", "IVOR41", "IVOR42", "IVOR43", 668 "IVOR44", "IVOR45", "IVOR46", "IVOR47", 669 "IVOR48", "IVOR49", "IVOR50", "IVOR51", 670 "IVOR52", "IVOR53", "IVOR54", "IVOR55", 671 "IVOR56", "IVOR57", "IVOR58", "IVOR59", 672 "IVOR60", "IVOR61", "IVOR62", "IVOR63", 673 }; 674 #define SPR_BOOKE_IVORxx (-1) 675 int ivor_sprn[64] = { 676 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3, 677 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7, 678 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11, 679 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15, 680 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 681 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 682 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 683 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 684 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35, 685 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39, 686 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx, 687 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 688 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 689 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 690 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 691 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 692 }; 693 int i; 694 695 /* Interrupt processing */ 696 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 697 SPR_NOACCESS, SPR_NOACCESS, 698 &spr_read_generic, &spr_write_generic, 699 0x00000000); 700 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 701 SPR_NOACCESS, SPR_NOACCESS, 702 &spr_read_generic, &spr_write_generic, 703 0x00000000); 704 /* Debug */ 705 spr_register(env, SPR_BOOKE_IAC1, "IAC1", 706 SPR_NOACCESS, SPR_NOACCESS, 707 &spr_read_generic, &spr_write_generic, 708 0x00000000); 709 710 spr_register(env, SPR_BOOKE_IAC2, "IAC2", 711 SPR_NOACCESS, SPR_NOACCESS, 712 &spr_read_generic, &spr_write_generic, 713 0x00000000); 714 715 spr_register(env, SPR_BOOKE_DAC1, "DAC1", 716 SPR_NOACCESS, SPR_NOACCESS, 717 &spr_read_generic, &spr_write_generic, 718 0x00000000); 719 720 spr_register(env, SPR_BOOKE_DAC2, "DAC2", 721 SPR_NOACCESS, SPR_NOACCESS, 722 &spr_read_generic, &spr_write_generic, 723 0x00000000); 724 725 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0", 726 SPR_NOACCESS, SPR_NOACCESS, 727 &spr_read_generic, &spr_write_40x_dbcr0, 728 0x00000000); 729 730 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1", 731 SPR_NOACCESS, SPR_NOACCESS, 732 &spr_read_generic, &spr_write_generic, 733 0x00000000); 734 735 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2", 736 SPR_NOACCESS, SPR_NOACCESS, 737 &spr_read_generic, &spr_write_generic, 738 0x00000000); 739 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 740 SPR_NOACCESS, SPR_NOACCESS, 741 &spr_read_generic, &spr_write_generic, 742 0x00000000); 743 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 744 SPR_NOACCESS, SPR_NOACCESS, 745 &spr_read_generic, &spr_write_generic, 746 0x00000000); 747 748 spr_register(env, SPR_BOOKE_DBSR, "DBSR", 749 SPR_NOACCESS, SPR_NOACCESS, 750 &spr_read_generic, &spr_write_clear, 751 0x00000000); 752 spr_register(env, SPR_BOOKE_DEAR, "DEAR", 753 SPR_NOACCESS, SPR_NOACCESS, 754 &spr_read_generic, &spr_write_generic, 755 0x00000000); 756 spr_register(env, SPR_BOOKE_ESR, "ESR", 757 SPR_NOACCESS, SPR_NOACCESS, 758 &spr_read_generic, &spr_write_generic, 759 0x00000000); 760 spr_register(env, SPR_BOOKE_IVPR, "IVPR", 761 SPR_NOACCESS, SPR_NOACCESS, 762 &spr_read_generic, &spr_write_excp_prefix, 763 0x00000000); 764 /* Exception vectors */ 765 for (i = 0; i < 64; i++) { 766 if (ivor_mask & (1ULL << i)) { 767 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) { 768 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i); 769 exit(1); 770 } 771 spr_register(env, ivor_sprn[i], ivor_names[i], 772 SPR_NOACCESS, SPR_NOACCESS, 773 &spr_read_generic, &spr_write_excp_vector, 774 0x00000000); 775 } 776 } 777 spr_register(env, SPR_BOOKE_PID, "PID", 778 SPR_NOACCESS, SPR_NOACCESS, 779 &spr_read_generic, &spr_write_booke_pid, 780 0x00000000); 781 spr_register(env, SPR_BOOKE_TCR, "TCR", 782 SPR_NOACCESS, SPR_NOACCESS, 783 &spr_read_generic, &spr_write_booke_tcr, 784 0x00000000); 785 spr_register(env, SPR_BOOKE_TSR, "TSR", 786 SPR_NOACCESS, SPR_NOACCESS, 787 &spr_read_generic, &spr_write_booke_tsr, 788 0x00000000); 789 /* Timer */ 790 spr_register(env, SPR_DECR, "DECR", 791 SPR_NOACCESS, SPR_NOACCESS, 792 &spr_read_decr, &spr_write_decr, 793 0x00000000); 794 spr_register(env, SPR_BOOKE_DECAR, "DECAR", 795 SPR_NOACCESS, SPR_NOACCESS, 796 SPR_NOACCESS, &spr_write_generic32, 797 0x00000000); 798 /* SPRGs */ 799 spr_register(env, SPR_USPRG0, "USPRG0", 800 &spr_read_generic, &spr_write_generic, 801 &spr_read_generic, &spr_write_generic, 802 0x00000000); 803 spr_register(env, SPR_SPRG4, "SPRG4", 804 SPR_NOACCESS, SPR_NOACCESS, 805 &spr_read_generic, &spr_write_generic, 806 0x00000000); 807 spr_register(env, SPR_SPRG5, "SPRG5", 808 SPR_NOACCESS, SPR_NOACCESS, 809 &spr_read_generic, &spr_write_generic, 810 0x00000000); 811 spr_register(env, SPR_SPRG6, "SPRG6", 812 SPR_NOACCESS, SPR_NOACCESS, 813 &spr_read_generic, &spr_write_generic, 814 0x00000000); 815 spr_register(env, SPR_SPRG7, "SPRG7", 816 SPR_NOACCESS, SPR_NOACCESS, 817 &spr_read_generic, &spr_write_generic, 818 0x00000000); 819 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8", 820 SPR_NOACCESS, SPR_NOACCESS, 821 &spr_read_generic, &spr_write_generic, 822 0x00000000); 823 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9", 824 SPR_NOACCESS, SPR_NOACCESS, 825 &spr_read_generic, &spr_write_generic, 826 0x00000000); 827 } 828 829 #if !defined(CONFIG_USER_ONLY) 830 static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize, 831 uint32_t maxsize, uint32_t flags, 832 uint32_t nentries) 833 { 834 return (assoc << TLBnCFG_ASSOC_SHIFT) | 835 (minsize << TLBnCFG_MINSIZE_SHIFT) | 836 (maxsize << TLBnCFG_MAXSIZE_SHIFT) | 837 flags | nentries; 838 } 839 #endif /* !CONFIG_USER_ONLY */ 840 841 /* BookE 2.06 storage control registers */ 842 static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask, 843 uint32_t *tlbncfg, uint32_t mmucfg) 844 { 845 #if !defined(CONFIG_USER_ONLY) 846 const char *mas_names[8] = { 847 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7", 848 }; 849 int mas_sprn[8] = { 850 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3, 851 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7, 852 }; 853 const char *tlbcfg_names[4] = { 854 "TLB0CFG", "TLB1CFG", "TLB2CFG", "TLB3CFG", 855 }; 856 const int tlbcfg_sprn[4] = { 857 SPR_BOOKE_TLB0CFG, SPR_BOOKE_TLB1CFG, 858 SPR_BOOKE_TLB2CFG, SPR_BOOKE_TLB3CFG, 859 }; 860 int i; 861 862 /* TLB assist registers */ 863 for (i = 0; i < 8; i++) { 864 if (mas_mask & (1 << i)) { 865 spr_register(env, mas_sprn[i], mas_names[i], 866 SPR_NOACCESS, SPR_NOACCESS, 867 &spr_read_generic, 868 (i == 2 && (env->insns_flags & PPC_64B)) 869 ? &spr_write_generic : &spr_write_generic32, 870 0x00000000); 871 } 872 } 873 if (env->nb_pids > 1) { 874 spr_register(env, SPR_BOOKE_PID1, "PID1", 875 SPR_NOACCESS, SPR_NOACCESS, 876 &spr_read_generic, &spr_write_booke_pid, 877 0x00000000); 878 } 879 if (env->nb_pids > 2) { 880 spr_register(env, SPR_BOOKE_PID2, "PID2", 881 SPR_NOACCESS, SPR_NOACCESS, 882 &spr_read_generic, &spr_write_booke_pid, 883 0x00000000); 884 } 885 886 spr_register(env, SPR_BOOKE_EPLC, "EPLC", 887 SPR_NOACCESS, SPR_NOACCESS, 888 &spr_read_generic, &spr_write_eplc, 889 0x00000000); 890 spr_register(env, SPR_BOOKE_EPSC, "EPSC", 891 SPR_NOACCESS, SPR_NOACCESS, 892 &spr_read_generic, &spr_write_epsc, 893 0x00000000); 894 895 spr_register(env, SPR_MMUCFG, "MMUCFG", 896 SPR_NOACCESS, SPR_NOACCESS, 897 &spr_read_generic, SPR_NOACCESS, 898 mmucfg); 899 900 assert(env->nb_ways <= ARRAY_SIZE(tlbcfg_names)); 901 for (i = 0; i < env->nb_ways; i++) { 902 spr_register(env, tlbcfg_sprn[i], tlbcfg_names[i], 903 SPR_NOACCESS, SPR_NOACCESS, 904 &spr_read_generic, SPR_NOACCESS, 905 tlbncfg[i]); 906 } 907 #endif 908 } 909 910 static void register_atb_sprs(CPUPPCState *env) 911 { 912 spr_register(env, SPR_ATBL, "ATBL", 913 &spr_read_atbl, SPR_NOACCESS, 914 &spr_read_atbl, SPR_NOACCESS, 915 0x00000000); 916 spr_register(env, SPR_ATBU, "ATBU", 917 &spr_read_atbu, SPR_NOACCESS, 918 &spr_read_atbu, SPR_NOACCESS, 919 0x00000000); 920 } 921 922 /* SPR specific to PowerPC 440 implementation */ 923 static void register_440_sprs(CPUPPCState *env) 924 { 925 /* Cache control */ 926 spr_register(env, SPR_440_DNV0, "DNV0", 927 SPR_NOACCESS, SPR_NOACCESS, 928 &spr_read_generic, &spr_write_generic, 929 0x00000000); 930 931 spr_register(env, SPR_440_DNV1, "DNV1", 932 SPR_NOACCESS, SPR_NOACCESS, 933 &spr_read_generic, &spr_write_generic, 934 0x00000000); 935 936 spr_register(env, SPR_440_DNV2, "DNV2", 937 SPR_NOACCESS, SPR_NOACCESS, 938 &spr_read_generic, &spr_write_generic, 939 0x00000000); 940 941 spr_register(env, SPR_440_DNV3, "DNV3", 942 SPR_NOACCESS, SPR_NOACCESS, 943 &spr_read_generic, &spr_write_generic, 944 0x00000000); 945 946 spr_register(env, SPR_440_DTV0, "DTV0", 947 SPR_NOACCESS, SPR_NOACCESS, 948 &spr_read_generic, &spr_write_generic, 949 0x00000000); 950 951 spr_register(env, SPR_440_DTV1, "DTV1", 952 SPR_NOACCESS, SPR_NOACCESS, 953 &spr_read_generic, &spr_write_generic, 954 0x00000000); 955 956 spr_register(env, SPR_440_DTV2, "DTV2", 957 SPR_NOACCESS, SPR_NOACCESS, 958 &spr_read_generic, &spr_write_generic, 959 0x00000000); 960 961 spr_register(env, SPR_440_DTV3, "DTV3", 962 SPR_NOACCESS, SPR_NOACCESS, 963 &spr_read_generic, &spr_write_generic, 964 0x00000000); 965 966 spr_register(env, SPR_440_DVLIM, "DVLIM", 967 SPR_NOACCESS, SPR_NOACCESS, 968 &spr_read_generic, &spr_write_generic, 969 0x00000000); 970 971 spr_register(env, SPR_440_INV0, "INV0", 972 SPR_NOACCESS, SPR_NOACCESS, 973 &spr_read_generic, &spr_write_generic, 974 0x00000000); 975 976 spr_register(env, SPR_440_INV1, "INV1", 977 SPR_NOACCESS, SPR_NOACCESS, 978 &spr_read_generic, &spr_write_generic, 979 0x00000000); 980 981 spr_register(env, SPR_440_INV2, "INV2", 982 SPR_NOACCESS, SPR_NOACCESS, 983 &spr_read_generic, &spr_write_generic, 984 0x00000000); 985 986 spr_register(env, SPR_440_INV3, "INV3", 987 SPR_NOACCESS, SPR_NOACCESS, 988 &spr_read_generic, &spr_write_generic, 989 0x00000000); 990 991 spr_register(env, SPR_440_ITV0, "ITV0", 992 SPR_NOACCESS, SPR_NOACCESS, 993 &spr_read_generic, &spr_write_generic, 994 0x00000000); 995 996 spr_register(env, SPR_440_ITV1, "ITV1", 997 SPR_NOACCESS, SPR_NOACCESS, 998 &spr_read_generic, &spr_write_generic, 999 0x00000000); 1000 1001 spr_register(env, SPR_440_ITV2, "ITV2", 1002 SPR_NOACCESS, SPR_NOACCESS, 1003 &spr_read_generic, &spr_write_generic, 1004 0x00000000); 1005 1006 spr_register(env, SPR_440_ITV3, "ITV3", 1007 SPR_NOACCESS, SPR_NOACCESS, 1008 &spr_read_generic, &spr_write_generic, 1009 0x00000000); 1010 1011 spr_register(env, SPR_440_IVLIM, "IVLIM", 1012 SPR_NOACCESS, SPR_NOACCESS, 1013 &spr_read_generic, &spr_write_generic, 1014 0x00000000); 1015 /* Cache debug */ 1016 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH", 1017 SPR_NOACCESS, SPR_NOACCESS, 1018 &spr_read_generic, SPR_NOACCESS, 1019 0x00000000); 1020 1021 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL", 1022 SPR_NOACCESS, SPR_NOACCESS, 1023 &spr_read_generic, SPR_NOACCESS, 1024 0x00000000); 1025 1026 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1027 SPR_NOACCESS, SPR_NOACCESS, 1028 &spr_read_generic, SPR_NOACCESS, 1029 0x00000000); 1030 1031 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH", 1032 SPR_NOACCESS, SPR_NOACCESS, 1033 &spr_read_generic, SPR_NOACCESS, 1034 0x00000000); 1035 1036 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL", 1037 SPR_NOACCESS, SPR_NOACCESS, 1038 &spr_read_generic, SPR_NOACCESS, 1039 0x00000000); 1040 1041 spr_register(env, SPR_440_DBDR, "DBDR", 1042 SPR_NOACCESS, SPR_NOACCESS, 1043 &spr_read_generic, &spr_write_generic, 1044 0x00000000); 1045 /* Processor control */ 1046 spr_register(env, SPR_4xx_CCR0, "CCR0", 1047 SPR_NOACCESS, SPR_NOACCESS, 1048 &spr_read_generic, &spr_write_generic, 1049 0x00000000); 1050 spr_register(env, SPR_440_RSTCFG, "RSTCFG", 1051 SPR_NOACCESS, SPR_NOACCESS, 1052 &spr_read_generic, SPR_NOACCESS, 1053 0x00000000); 1054 /* Storage control */ 1055 spr_register(env, SPR_440_MMUCR, "MMUCR", 1056 SPR_NOACCESS, SPR_NOACCESS, 1057 &spr_read_generic, &spr_write_generic, 1058 0x00000000); 1059 1060 /* Processor identification */ 1061 spr_register(env, SPR_BOOKE_PIR, "PIR", 1062 SPR_NOACCESS, SPR_NOACCESS, 1063 &spr_read_generic, &spr_write_pir, 1064 0x00000000); 1065 1066 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 1067 SPR_NOACCESS, SPR_NOACCESS, 1068 &spr_read_generic, &spr_write_generic, 1069 0x00000000); 1070 1071 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 1072 SPR_NOACCESS, SPR_NOACCESS, 1073 &spr_read_generic, &spr_write_generic, 1074 0x00000000); 1075 1076 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 1077 SPR_NOACCESS, SPR_NOACCESS, 1078 &spr_read_generic, &spr_write_generic, 1079 0x00000000); 1080 1081 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 1082 SPR_NOACCESS, SPR_NOACCESS, 1083 &spr_read_generic, &spr_write_generic, 1084 0x00000000); 1085 } 1086 1087 /* SPR shared between PowerPC 40x implementations */ 1088 static void register_40x_sprs(CPUPPCState *env) 1089 { 1090 /* Cache */ 1091 /* not emulated, as QEMU do not emulate caches */ 1092 spr_register(env, SPR_40x_DCCR, "DCCR", 1093 SPR_NOACCESS, SPR_NOACCESS, 1094 &spr_read_generic, &spr_write_generic, 1095 0x00000000); 1096 /* not emulated, as QEMU do not emulate caches */ 1097 spr_register(env, SPR_40x_ICCR, "ICCR", 1098 SPR_NOACCESS, SPR_NOACCESS, 1099 &spr_read_generic, &spr_write_generic, 1100 0x00000000); 1101 /* not emulated, as QEMU do not emulate caches */ 1102 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1103 SPR_NOACCESS, SPR_NOACCESS, 1104 &spr_read_generic, SPR_NOACCESS, 1105 0x00000000); 1106 /* Exception */ 1107 spr_register(env, SPR_40x_DEAR, "DEAR", 1108 SPR_NOACCESS, SPR_NOACCESS, 1109 &spr_read_generic, &spr_write_generic, 1110 0x00000000); 1111 spr_register(env, SPR_40x_ESR, "ESR", 1112 SPR_NOACCESS, SPR_NOACCESS, 1113 &spr_read_generic, &spr_write_generic, 1114 0x00000000); 1115 spr_register(env, SPR_40x_EVPR, "EVPR", 1116 SPR_NOACCESS, SPR_NOACCESS, 1117 &spr_read_generic, &spr_write_excp_prefix, 1118 0x00000000); 1119 spr_register(env, SPR_40x_SRR2, "SRR2", 1120 &spr_read_generic, &spr_write_generic, 1121 &spr_read_generic, &spr_write_generic, 1122 0x00000000); 1123 spr_register(env, SPR_40x_SRR3, "SRR3", 1124 &spr_read_generic, &spr_write_generic, 1125 &spr_read_generic, &spr_write_generic, 1126 0x00000000); 1127 /* Timers */ 1128 spr_register(env, SPR_40x_PIT, "PIT", 1129 SPR_NOACCESS, SPR_NOACCESS, 1130 &spr_read_40x_pit, &spr_write_40x_pit, 1131 0x00000000); 1132 spr_register(env, SPR_40x_TCR, "TCR", 1133 SPR_NOACCESS, SPR_NOACCESS, 1134 &spr_read_generic, &spr_write_40x_tcr, 1135 0x00000000); 1136 spr_register(env, SPR_40x_TSR, "TSR", 1137 SPR_NOACCESS, SPR_NOACCESS, 1138 &spr_read_generic, &spr_write_40x_tsr, 1139 0x00000000); 1140 } 1141 1142 /* SPR specific to PowerPC 405 implementation */ 1143 static void register_405_sprs(CPUPPCState *env) 1144 { 1145 /* MMU */ 1146 spr_register(env, SPR_40x_PID, "PID", 1147 SPR_NOACCESS, SPR_NOACCESS, 1148 &spr_read_generic, &spr_write_40x_pid, 1149 0x00000000); 1150 spr_register(env, SPR_4xx_CCR0, "CCR0", 1151 SPR_NOACCESS, SPR_NOACCESS, 1152 &spr_read_generic, &spr_write_generic, 1153 0x00700000); 1154 /* Debug interface */ 1155 spr_register(env, SPR_40x_DBCR0, "DBCR0", 1156 SPR_NOACCESS, SPR_NOACCESS, 1157 &spr_read_generic, &spr_write_40x_dbcr0, 1158 0x00000000); 1159 1160 spr_register(env, SPR_405_DBCR1, "DBCR1", 1161 SPR_NOACCESS, SPR_NOACCESS, 1162 &spr_read_generic, &spr_write_generic, 1163 0x00000000); 1164 1165 spr_register(env, SPR_40x_DBSR, "DBSR", 1166 SPR_NOACCESS, SPR_NOACCESS, 1167 &spr_read_generic, &spr_write_clear, 1168 /* Last reset was system reset */ 1169 0x00000300); 1170 1171 spr_register(env, SPR_40x_DAC1, "DAC1", 1172 SPR_NOACCESS, SPR_NOACCESS, 1173 &spr_read_generic, &spr_write_generic, 1174 0x00000000); 1175 spr_register(env, SPR_40x_DAC2, "DAC2", 1176 SPR_NOACCESS, SPR_NOACCESS, 1177 &spr_read_generic, &spr_write_generic, 1178 0x00000000); 1179 1180 spr_register(env, SPR_405_DVC1, "DVC1", 1181 SPR_NOACCESS, SPR_NOACCESS, 1182 &spr_read_generic, &spr_write_generic, 1183 0x00000000); 1184 1185 spr_register(env, SPR_405_DVC2, "DVC2", 1186 SPR_NOACCESS, SPR_NOACCESS, 1187 &spr_read_generic, &spr_write_generic, 1188 0x00000000); 1189 1190 spr_register(env, SPR_40x_IAC1, "IAC1", 1191 SPR_NOACCESS, SPR_NOACCESS, 1192 &spr_read_generic, &spr_write_generic, 1193 0x00000000); 1194 spr_register(env, SPR_40x_IAC2, "IAC2", 1195 SPR_NOACCESS, SPR_NOACCESS, 1196 &spr_read_generic, &spr_write_generic, 1197 0x00000000); 1198 1199 spr_register(env, SPR_405_IAC3, "IAC3", 1200 SPR_NOACCESS, SPR_NOACCESS, 1201 &spr_read_generic, &spr_write_generic, 1202 0x00000000); 1203 1204 spr_register(env, SPR_405_IAC4, "IAC4", 1205 SPR_NOACCESS, SPR_NOACCESS, 1206 &spr_read_generic, &spr_write_generic, 1207 0x00000000); 1208 /* Storage control */ 1209 spr_register(env, SPR_405_SLER, "SLER", 1210 SPR_NOACCESS, SPR_NOACCESS, 1211 &spr_read_generic, &spr_write_40x_sler, 1212 0x00000000); 1213 spr_register(env, SPR_40x_ZPR, "ZPR", 1214 SPR_NOACCESS, SPR_NOACCESS, 1215 &spr_read_generic, &spr_write_generic, 1216 0x00000000); 1217 1218 spr_register(env, SPR_405_SU0R, "SU0R", 1219 SPR_NOACCESS, SPR_NOACCESS, 1220 &spr_read_generic, &spr_write_generic, 1221 0x00000000); 1222 /* SPRG */ 1223 spr_register(env, SPR_USPRG0, "USPRG0", 1224 &spr_read_ureg, SPR_NOACCESS, 1225 &spr_read_ureg, SPR_NOACCESS, 1226 0x00000000); 1227 spr_register(env, SPR_SPRG4, "SPRG4", 1228 SPR_NOACCESS, SPR_NOACCESS, 1229 &spr_read_generic, &spr_write_generic, 1230 0x00000000); 1231 spr_register(env, SPR_SPRG5, "SPRG5", 1232 SPR_NOACCESS, SPR_NOACCESS, 1233 spr_read_generic, &spr_write_generic, 1234 0x00000000); 1235 spr_register(env, SPR_SPRG6, "SPRG6", 1236 SPR_NOACCESS, SPR_NOACCESS, 1237 spr_read_generic, &spr_write_generic, 1238 0x00000000); 1239 spr_register(env, SPR_SPRG7, "SPRG7", 1240 SPR_NOACCESS, SPR_NOACCESS, 1241 spr_read_generic, &spr_write_generic, 1242 0x00000000); 1243 1244 /* Bus access control */ 1245 /* not emulated, as QEMU never does speculative access */ 1246 spr_register(env, SPR_40x_SGR, "SGR", 1247 SPR_NOACCESS, SPR_NOACCESS, 1248 &spr_read_generic, &spr_write_generic, 1249 0xFFFFFFFF); 1250 /* not emulated, as QEMU do not emulate caches */ 1251 spr_register(env, SPR_40x_DCWR, "DCWR", 1252 SPR_NOACCESS, SPR_NOACCESS, 1253 &spr_read_generic, &spr_write_generic, 1254 0x00000000); 1255 } 1256 1257 1258 static void register_5xx_8xx_sprs(CPUPPCState *env) 1259 { 1260 /* Exception processing */ 1261 spr_register_kvm(env, SPR_DSISR, "DSISR", 1262 SPR_NOACCESS, SPR_NOACCESS, 1263 &spr_read_generic, &spr_write_generic, 1264 KVM_REG_PPC_DSISR, 0x00000000); 1265 spr_register_kvm(env, SPR_DAR, "DAR", 1266 SPR_NOACCESS, SPR_NOACCESS, 1267 &spr_read_generic, &spr_write_generic, 1268 KVM_REG_PPC_DAR, 0x00000000); 1269 /* Timer */ 1270 spr_register(env, SPR_DECR, "DECR", 1271 SPR_NOACCESS, SPR_NOACCESS, 1272 &spr_read_decr, &spr_write_decr, 1273 0x00000000); 1274 1275 spr_register(env, SPR_MPC_EIE, "EIE", 1276 SPR_NOACCESS, SPR_NOACCESS, 1277 &spr_read_generic, &spr_write_generic, 1278 0x00000000); 1279 1280 spr_register(env, SPR_MPC_EID, "EID", 1281 SPR_NOACCESS, SPR_NOACCESS, 1282 &spr_read_generic, &spr_write_generic, 1283 0x00000000); 1284 1285 spr_register(env, SPR_MPC_NRI, "NRI", 1286 SPR_NOACCESS, SPR_NOACCESS, 1287 &spr_read_generic, &spr_write_generic, 1288 0x00000000); 1289 1290 spr_register(env, SPR_MPC_CMPA, "CMPA", 1291 SPR_NOACCESS, SPR_NOACCESS, 1292 &spr_read_generic, &spr_write_generic, 1293 0x00000000); 1294 1295 spr_register(env, SPR_MPC_CMPB, "CMPB", 1296 SPR_NOACCESS, SPR_NOACCESS, 1297 &spr_read_generic, &spr_write_generic, 1298 0x00000000); 1299 1300 spr_register(env, SPR_MPC_CMPC, "CMPC", 1301 SPR_NOACCESS, SPR_NOACCESS, 1302 &spr_read_generic, &spr_write_generic, 1303 0x00000000); 1304 1305 spr_register(env, SPR_MPC_CMPD, "CMPD", 1306 SPR_NOACCESS, SPR_NOACCESS, 1307 &spr_read_generic, &spr_write_generic, 1308 0x00000000); 1309 1310 spr_register(env, SPR_MPC_ECR, "ECR", 1311 SPR_NOACCESS, SPR_NOACCESS, 1312 &spr_read_generic, &spr_write_generic, 1313 0x00000000); 1314 1315 spr_register(env, SPR_MPC_DER, "DER", 1316 SPR_NOACCESS, SPR_NOACCESS, 1317 &spr_read_generic, &spr_write_generic, 1318 0x00000000); 1319 1320 spr_register(env, SPR_MPC_COUNTA, "COUNTA", 1321 SPR_NOACCESS, SPR_NOACCESS, 1322 &spr_read_generic, &spr_write_generic, 1323 0x00000000); 1324 1325 spr_register(env, SPR_MPC_COUNTB, "COUNTB", 1326 SPR_NOACCESS, SPR_NOACCESS, 1327 &spr_read_generic, &spr_write_generic, 1328 0x00000000); 1329 1330 spr_register(env, SPR_MPC_CMPE, "CMPE", 1331 SPR_NOACCESS, SPR_NOACCESS, 1332 &spr_read_generic, &spr_write_generic, 1333 0x00000000); 1334 1335 spr_register(env, SPR_MPC_CMPF, "CMPF", 1336 SPR_NOACCESS, SPR_NOACCESS, 1337 &spr_read_generic, &spr_write_generic, 1338 0x00000000); 1339 1340 spr_register(env, SPR_MPC_CMPG, "CMPG", 1341 SPR_NOACCESS, SPR_NOACCESS, 1342 &spr_read_generic, &spr_write_generic, 1343 0x00000000); 1344 1345 spr_register(env, SPR_MPC_CMPH, "CMPH", 1346 SPR_NOACCESS, SPR_NOACCESS, 1347 &spr_read_generic, &spr_write_generic, 1348 0x00000000); 1349 1350 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1", 1351 SPR_NOACCESS, SPR_NOACCESS, 1352 &spr_read_generic, &spr_write_generic, 1353 0x00000000); 1354 1355 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2", 1356 SPR_NOACCESS, SPR_NOACCESS, 1357 &spr_read_generic, &spr_write_generic, 1358 0x00000000); 1359 1360 spr_register(env, SPR_MPC_BAR, "BAR", 1361 SPR_NOACCESS, SPR_NOACCESS, 1362 &spr_read_generic, &spr_write_generic, 1363 0x00000000); 1364 1365 spr_register(env, SPR_MPC_DPDR, "DPDR", 1366 SPR_NOACCESS, SPR_NOACCESS, 1367 &spr_read_generic, &spr_write_generic, 1368 0x00000000); 1369 1370 spr_register(env, SPR_MPC_IMMR, "IMMR", 1371 SPR_NOACCESS, SPR_NOACCESS, 1372 &spr_read_generic, &spr_write_generic, 1373 0x00000000); 1374 } 1375 1376 static void register_5xx_sprs(CPUPPCState *env) 1377 { 1378 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA", 1379 SPR_NOACCESS, SPR_NOACCESS, 1380 &spr_read_generic, &spr_write_generic, 1381 0x00000000); 1382 1383 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA", 1384 SPR_NOACCESS, SPR_NOACCESS, 1385 &spr_read_generic, &spr_write_generic, 1386 0x00000000); 1387 1388 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR", 1389 SPR_NOACCESS, SPR_NOACCESS, 1390 &spr_read_generic, &spr_write_generic, 1391 0x00000000); 1392 1393 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR", 1394 SPR_NOACCESS, SPR_NOACCESS, 1395 &spr_read_generic, &spr_write_generic, 1396 0x00000000); 1397 1398 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0", 1399 SPR_NOACCESS, SPR_NOACCESS, 1400 &spr_read_generic, &spr_write_generic, 1401 0x00000000); 1402 1403 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1", 1404 SPR_NOACCESS, SPR_NOACCESS, 1405 &spr_read_generic, &spr_write_generic, 1406 0x00000000); 1407 1408 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2", 1409 SPR_NOACCESS, SPR_NOACCESS, 1410 &spr_read_generic, &spr_write_generic, 1411 0x00000000); 1412 1413 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3", 1414 SPR_NOACCESS, SPR_NOACCESS, 1415 &spr_read_generic, &spr_write_generic, 1416 0x00000000); 1417 1418 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0", 1419 SPR_NOACCESS, SPR_NOACCESS, 1420 &spr_read_generic, &spr_write_generic, 1421 0x00000000); 1422 1423 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1", 1424 SPR_NOACCESS, SPR_NOACCESS, 1425 &spr_read_generic, &spr_write_generic, 1426 0x00000000); 1427 1428 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2", 1429 SPR_NOACCESS, SPR_NOACCESS, 1430 &spr_read_generic, &spr_write_generic, 1431 0x00000000); 1432 1433 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3", 1434 SPR_NOACCESS, SPR_NOACCESS, 1435 &spr_read_generic, &spr_write_generic, 1436 0x00000000); 1437 1438 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0", 1439 SPR_NOACCESS, SPR_NOACCESS, 1440 &spr_read_generic, &spr_write_generic, 1441 0x00000000); 1442 1443 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1", 1444 SPR_NOACCESS, SPR_NOACCESS, 1445 &spr_read_generic, &spr_write_generic, 1446 0x00000000); 1447 1448 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2", 1449 SPR_NOACCESS, SPR_NOACCESS, 1450 &spr_read_generic, &spr_write_generic, 1451 0x00000000); 1452 1453 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3", 1454 SPR_NOACCESS, SPR_NOACCESS, 1455 &spr_read_generic, &spr_write_generic, 1456 0x00000000); 1457 1458 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0", 1459 SPR_NOACCESS, SPR_NOACCESS, 1460 &spr_read_generic, &spr_write_generic, 1461 0x00000000); 1462 1463 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1", 1464 SPR_NOACCESS, SPR_NOACCESS, 1465 &spr_read_generic, &spr_write_generic, 1466 0x00000000); 1467 1468 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2", 1469 SPR_NOACCESS, SPR_NOACCESS, 1470 &spr_read_generic, &spr_write_generic, 1471 0x00000000); 1472 1473 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3", 1474 SPR_NOACCESS, SPR_NOACCESS, 1475 &spr_read_generic, &spr_write_generic, 1476 0x00000000); 1477 1478 spr_register(env, SPR_RCPU_FPECR, "FPECR", 1479 SPR_NOACCESS, SPR_NOACCESS, 1480 &spr_read_generic, &spr_write_generic, 1481 0x00000000); 1482 } 1483 1484 static void register_8xx_sprs(CPUPPCState *env) 1485 { 1486 1487 spr_register(env, SPR_MPC_IC_CST, "IC_CST", 1488 SPR_NOACCESS, SPR_NOACCESS, 1489 &spr_read_generic, &spr_write_generic, 1490 0x00000000); 1491 1492 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR", 1493 SPR_NOACCESS, SPR_NOACCESS, 1494 &spr_read_generic, &spr_write_generic, 1495 0x00000000); 1496 1497 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT", 1498 SPR_NOACCESS, SPR_NOACCESS, 1499 &spr_read_generic, &spr_write_generic, 1500 0x00000000); 1501 1502 spr_register(env, SPR_MPC_DC_CST, "DC_CST", 1503 SPR_NOACCESS, SPR_NOACCESS, 1504 &spr_read_generic, &spr_write_generic, 1505 0x00000000); 1506 1507 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR", 1508 SPR_NOACCESS, SPR_NOACCESS, 1509 &spr_read_generic, &spr_write_generic, 1510 0x00000000); 1511 1512 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT", 1513 SPR_NOACCESS, SPR_NOACCESS, 1514 &spr_read_generic, &spr_write_generic, 1515 0x00000000); 1516 1517 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR", 1518 SPR_NOACCESS, SPR_NOACCESS, 1519 &spr_read_generic, &spr_write_generic, 1520 0x00000000); 1521 1522 spr_register(env, SPR_MPC_MI_AP, "MI_AP", 1523 SPR_NOACCESS, SPR_NOACCESS, 1524 &spr_read_generic, &spr_write_generic, 1525 0x00000000); 1526 1527 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN", 1528 SPR_NOACCESS, SPR_NOACCESS, 1529 &spr_read_generic, &spr_write_generic, 1530 0x00000000); 1531 1532 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC", 1533 SPR_NOACCESS, SPR_NOACCESS, 1534 &spr_read_generic, &spr_write_generic, 1535 0x00000000); 1536 1537 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN", 1538 SPR_NOACCESS, SPR_NOACCESS, 1539 &spr_read_generic, &spr_write_generic, 1540 0x00000000); 1541 1542 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM", 1543 SPR_NOACCESS, SPR_NOACCESS, 1544 &spr_read_generic, &spr_write_generic, 1545 0x00000000); 1546 1547 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0", 1548 SPR_NOACCESS, SPR_NOACCESS, 1549 &spr_read_generic, &spr_write_generic, 1550 0x00000000); 1551 1552 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1", 1553 SPR_NOACCESS, SPR_NOACCESS, 1554 &spr_read_generic, &spr_write_generic, 1555 0x00000000); 1556 1557 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR", 1558 SPR_NOACCESS, SPR_NOACCESS, 1559 &spr_read_generic, &spr_write_generic, 1560 0x00000000); 1561 1562 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID", 1563 SPR_NOACCESS, SPR_NOACCESS, 1564 &spr_read_generic, &spr_write_generic, 1565 0x00000000); 1566 1567 spr_register(env, SPR_MPC_MD_AP, "MD_AP", 1568 SPR_NOACCESS, SPR_NOACCESS, 1569 &spr_read_generic, &spr_write_generic, 1570 0x00000000); 1571 1572 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN", 1573 SPR_NOACCESS, SPR_NOACCESS, 1574 &spr_read_generic, &spr_write_generic, 1575 0x00000000); 1576 1577 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB", 1578 SPR_NOACCESS, SPR_NOACCESS, 1579 &spr_read_generic, &spr_write_generic, 1580 0x00000000); 1581 1582 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC", 1583 SPR_NOACCESS, SPR_NOACCESS, 1584 &spr_read_generic, &spr_write_generic, 1585 0x00000000); 1586 1587 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN", 1588 SPR_NOACCESS, SPR_NOACCESS, 1589 &spr_read_generic, &spr_write_generic, 1590 0x00000000); 1591 1592 spr_register(env, SPR_MPC_MD_TW, "MD_TW", 1593 SPR_NOACCESS, SPR_NOACCESS, 1594 &spr_read_generic, &spr_write_generic, 1595 0x00000000); 1596 1597 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM", 1598 SPR_NOACCESS, SPR_NOACCESS, 1599 &spr_read_generic, &spr_write_generic, 1600 0x00000000); 1601 1602 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0", 1603 SPR_NOACCESS, SPR_NOACCESS, 1604 &spr_read_generic, &spr_write_generic, 1605 0x00000000); 1606 1607 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1", 1608 SPR_NOACCESS, SPR_NOACCESS, 1609 &spr_read_generic, &spr_write_generic, 1610 0x00000000); 1611 } 1612 1613 /* 1614 * AMR => SPR 29 (Power 2.04) 1615 * CTRL => SPR 136 (Power 2.04) 1616 * CTRL => SPR 152 (Power 2.04) 1617 * SCOMC => SPR 276 (64 bits ?) 1618 * SCOMD => SPR 277 (64 bits ?) 1619 * TBU40 => SPR 286 (Power 2.04 hypv) 1620 * HSPRG0 => SPR 304 (Power 2.04 hypv) 1621 * HSPRG1 => SPR 305 (Power 2.04 hypv) 1622 * HDSISR => SPR 306 (Power 2.04 hypv) 1623 * HDAR => SPR 307 (Power 2.04 hypv) 1624 * PURR => SPR 309 (Power 2.04 hypv) 1625 * HDEC => SPR 310 (Power 2.04 hypv) 1626 * HIOR => SPR 311 (hypv) 1627 * RMOR => SPR 312 (970) 1628 * HRMOR => SPR 313 (Power 2.04 hypv) 1629 * HSRR0 => SPR 314 (Power 2.04 hypv) 1630 * HSRR1 => SPR 315 (Power 2.04 hypv) 1631 * LPIDR => SPR 317 (970) 1632 * HEIR => SPR 339 (Power 2.05 hypv) (64-bit reg from 3.1) 1633 * EPR => SPR 702 (Power 2.04 emb) 1634 * perf => 768-783 (Power 2.04) 1635 * perf => 784-799 (Power 2.04) 1636 * PPR => SPR 896 (Power 2.04) 1637 * DABRX => 1015 (Power 2.04 hypv) 1638 * FPECR => SPR 1022 (?) 1639 * ... and more (thermal management, performance counters, ...) 1640 */ 1641 1642 static void register_ppe42_sprs(CPUPPCState *env) 1643 { 1644 spr_register(env, SPR_PPE42_EDR, "EDR", 1645 SPR_NOACCESS, SPR_NOACCESS, 1646 &spr_read_generic, &spr_write_generic, 1647 0x00000000); 1648 spr_register(env, SPR_PPE42_ISR, "ISR", 1649 SPR_NOACCESS, SPR_NOACCESS, 1650 &spr_read_generic, &spr_write_generic, 1651 0x00000000); 1652 spr_register(env, SPR_PPE42_IVPR, "IVPR", 1653 SPR_NOACCESS, SPR_NOACCESS, 1654 &spr_read_generic, SPR_NOACCESS, 1655 0xfff80000); 1656 spr_register(env, SPR_PPE42_PIR, "PIR", 1657 SPR_NOACCESS, SPR_NOACCESS, 1658 &spr_read_generic, &spr_write_pir, 1659 0x00000000); 1660 spr_register(env, SPR_PPE42_DBCR, "DBCR", 1661 SPR_NOACCESS, SPR_NOACCESS, 1662 &spr_read_generic, &spr_write_40x_dbcr0, 1663 0x00000000); 1664 spr_register(env, SPR_PPE42_DACR, "DACR", 1665 SPR_NOACCESS, SPR_NOACCESS, 1666 &spr_read_generic, &spr_write_generic, 1667 0x00000000); 1668 /* Timer */ 1669 spr_register(env, SPR_DECR, "DECR", 1670 SPR_NOACCESS, SPR_NOACCESS, 1671 &spr_read_decr, &spr_write_decr, 1672 0x00000000); 1673 spr_register(env, SPR_PPE42_TSR, "TSR", 1674 SPR_NOACCESS, SPR_NOACCESS, 1675 &spr_read_generic, &spr_write_booke_tsr, 1676 0x00000000); 1677 spr_register(env, SPR_BOOKE_TCR, "TCR", 1678 SPR_NOACCESS, SPR_NOACCESS, 1679 &spr_read_generic, &spr_write_booke_tcr, 1680 0x00000000); 1681 } 1682 1683 /*****************************************************************************/ 1684 /* Exception vectors models */ 1685 static void init_excp_4xx(CPUPPCState *env) 1686 { 1687 #if !defined(CONFIG_USER_ONLY) 1688 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; 1689 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1690 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1691 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1692 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1693 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1694 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1695 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1696 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; 1697 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; 1698 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; 1699 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100; 1700 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200; 1701 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; 1702 env->ivor_mask = 0x0000FFF0UL; 1703 env->ivpr_mask = 0xFFFF0000UL; 1704 /* Hardware reset vector */ 1705 env->hreset_vector = 0xFFFFFFFCUL; 1706 #endif 1707 } 1708 1709 static void init_excp_ppe42(CPUPPCState *env) 1710 { 1711 #if !defined(CONFIG_USER_ONLY) 1712 /* Machine Check vector changed after version 0 */ 1713 if (((env->spr[SPR_PVR] & 0xf00000ul) >> 20) == 0) { 1714 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 1715 } else { 1716 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000020; 1717 } 1718 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000040; 1719 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000060; 1720 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000080; 1721 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x000000A0; 1722 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x000000C0; 1723 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x000000E0; 1724 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000100; 1725 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000120; 1726 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000140; 1727 env->ivpr_mask = 0xFFFFFE00UL; 1728 /* Hardware reset vector */ 1729 env->hreset_vector = 0x00000040UL; 1730 #endif 1731 } 1732 1733 static void init_excp_MPC5xx(CPUPPCState *env) 1734 { 1735 #if !defined(CONFIG_USER_ONLY) 1736 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1737 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1738 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1739 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1740 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1741 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1742 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1743 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1744 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1745 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 1746 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 1747 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 1748 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 1749 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 1750 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 1751 env->ivor_mask = 0x0000FFF0UL; 1752 env->ivpr_mask = 0xFFFF0000UL; 1753 /* Hardware reset vector */ 1754 env->hreset_vector = 0x00000100UL; 1755 #endif 1756 } 1757 1758 static void init_excp_MPC8xx(CPUPPCState *env) 1759 { 1760 #if !defined(CONFIG_USER_ONLY) 1761 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1762 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1763 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1764 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1765 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1766 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1767 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1768 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1769 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1770 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1771 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1772 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 1773 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 1774 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100; 1775 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200; 1776 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300; 1777 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400; 1778 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 1779 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 1780 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 1781 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 1782 env->ivor_mask = 0x0000FFF0UL; 1783 env->ivpr_mask = 0xFFFF0000UL; 1784 /* Hardware reset vector */ 1785 env->hreset_vector = 0x00000100UL; 1786 #endif 1787 } 1788 1789 static void init_excp_G2(CPUPPCState *env) 1790 { 1791 #if !defined(CONFIG_USER_ONLY) 1792 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1793 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1794 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1795 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1796 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1797 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1798 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1799 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1800 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1801 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00; 1802 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1803 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1804 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 1805 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 1806 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 1807 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1808 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1809 /* Hardware reset vector */ 1810 env->hreset_vector = 0x00000100UL; 1811 #endif 1812 } 1813 1814 static void init_excp_e500(CPUPPCState *env, target_ulong ivpr_mask) 1815 { 1816 #if !defined(CONFIG_USER_ONLY) 1817 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC; 1818 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 1819 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 1820 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 1821 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 1822 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 1823 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 1824 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 1825 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 1826 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 1827 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 1828 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 1829 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 1830 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 1831 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 1832 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 1833 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 1834 /* 1835 * These two are the same IVOR as POWERPC_EXCP_VPU and 1836 * POWERPC_EXCP_VPUA. We deal with that when dispatching at 1837 * powerpc_excp(). 1838 */ 1839 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000; 1840 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000; 1841 1842 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000; 1843 env->ivor_mask = 0x0000FFF7UL; 1844 env->ivpr_mask = ivpr_mask; 1845 /* Hardware reset vector */ 1846 env->hreset_vector = 0xFFFFFFFCUL; 1847 #endif 1848 } 1849 1850 static void init_excp_BookE(CPUPPCState *env) 1851 { 1852 #if !defined(CONFIG_USER_ONLY) 1853 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 1854 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 1855 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 1856 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 1857 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 1858 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 1859 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 1860 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 1861 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 1862 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 1863 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 1864 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 1865 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 1866 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 1867 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 1868 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 1869 env->ivor_mask = 0x0000FFF0UL; 1870 env->ivpr_mask = 0xFFFF0000UL; 1871 /* Hardware reset vector */ 1872 env->hreset_vector = 0xFFFFFFFCUL; 1873 #endif 1874 } 1875 1876 static void init_excp_603(CPUPPCState *env) 1877 { 1878 #if !defined(CONFIG_USER_ONLY) 1879 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1880 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1881 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1882 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1883 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1884 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1885 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1886 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1887 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1888 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1889 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1890 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 1891 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 1892 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 1893 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1894 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1895 /* Hardware reset vector */ 1896 env->hreset_vector = 0x00000100UL; 1897 #endif 1898 } 1899 1900 static void init_excp_604(CPUPPCState *env) 1901 { 1902 #if !defined(CONFIG_USER_ONLY) 1903 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1904 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1905 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1906 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1907 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1908 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1909 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1910 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1911 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1912 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1913 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1914 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1915 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1916 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1917 /* Hardware reset vector */ 1918 env->hreset_vector = 0x00000100UL; 1919 #endif 1920 } 1921 1922 static void init_excp_7x0(CPUPPCState *env) 1923 { 1924 #if !defined(CONFIG_USER_ONLY) 1925 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1926 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1927 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1928 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1929 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1930 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1931 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1932 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1933 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1934 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1935 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1936 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1937 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1938 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1939 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 1940 /* Hardware reset vector */ 1941 env->hreset_vector = 0x00000100UL; 1942 #endif 1943 } 1944 1945 static void init_excp_750cl(CPUPPCState *env) 1946 { 1947 #if !defined(CONFIG_USER_ONLY) 1948 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1949 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1950 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1951 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1952 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1953 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1954 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1955 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1956 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1957 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1958 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1959 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1960 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1961 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1962 /* Hardware reset vector */ 1963 env->hreset_vector = 0x00000100UL; 1964 #endif 1965 } 1966 1967 static void init_excp_750cx(CPUPPCState *env) 1968 { 1969 #if !defined(CONFIG_USER_ONLY) 1970 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1971 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1972 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1973 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1974 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1975 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1976 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1977 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1978 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1979 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1980 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1981 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1982 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1983 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 1984 /* Hardware reset vector */ 1985 env->hreset_vector = 0x00000100UL; 1986 #endif 1987 } 1988 1989 /* XXX: Check if this is correct */ 1990 static void init_excp_7x5(CPUPPCState *env) 1991 { 1992 #if !defined(CONFIG_USER_ONLY) 1993 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1994 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1995 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1996 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1997 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1998 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1999 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2000 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2001 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2002 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2003 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2004 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2005 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2006 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2007 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2008 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2009 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2010 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2011 /* Hardware reset vector */ 2012 env->hreset_vector = 0x00000100UL; 2013 #endif 2014 } 2015 2016 static void init_excp_7400(CPUPPCState *env) 2017 { 2018 #if !defined(CONFIG_USER_ONLY) 2019 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2020 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2021 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2022 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2023 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2024 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2025 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2026 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2027 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2028 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2029 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2030 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2031 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2032 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2033 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2034 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 2035 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2036 /* Hardware reset vector */ 2037 env->hreset_vector = 0x00000100UL; 2038 #endif 2039 } 2040 2041 static void init_excp_7450(CPUPPCState *env) 2042 { 2043 #if !defined(CONFIG_USER_ONLY) 2044 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2045 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2046 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2047 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2048 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2049 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2050 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2051 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2052 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2053 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2054 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2055 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2056 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2057 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2058 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2059 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 2060 /* Hardware reset vector */ 2061 env->hreset_vector = 0x00000100UL; 2062 #endif 2063 } 2064 2065 #if defined(TARGET_PPC64) 2066 static void init_excp_970(CPUPPCState *env) 2067 { 2068 #if !defined(CONFIG_USER_ONLY) 2069 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2070 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2071 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2072 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2073 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2074 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2075 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2076 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2077 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2078 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2079 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2080 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2081 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2082 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2083 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2084 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2085 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2086 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600; 2087 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700; 2088 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800; 2089 /* Hardware reset vector */ 2090 env->hreset_vector = 0x0000000000000100ULL; 2091 #endif 2092 } 2093 2094 static void init_excp_POWER7(CPUPPCState *env) 2095 { 2096 #if !defined(CONFIG_USER_ONLY) 2097 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2098 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2099 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2100 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2101 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2102 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2103 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2104 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2105 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2106 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2107 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2108 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2109 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2110 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2111 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00; 2112 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20; 2113 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40; 2114 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60; 2115 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2116 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2117 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40; 2118 /* Hardware reset vector */ 2119 env->hreset_vector = 0x0000000000000100ULL; 2120 #endif 2121 } 2122 2123 static void init_excp_POWER8(CPUPPCState *env) 2124 { 2125 init_excp_POWER7(env); 2126 2127 #if !defined(CONFIG_USER_ONLY) 2128 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00; 2129 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60; 2130 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80; 2131 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80; 2132 2133 /* Userland exceptions without vector value in PowerISA v3.1 */ 2134 env->excp_vectors[POWERPC_EXCP_PERFM_EBB] = 0x0; 2135 env->excp_vectors[POWERPC_EXCP_EXTERNAL_EBB] = 0x0; 2136 #endif 2137 } 2138 2139 static void init_excp_POWER9(CPUPPCState *env) 2140 { 2141 init_excp_POWER8(env); 2142 2143 #if !defined(CONFIG_USER_ONLY) 2144 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0; 2145 env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000; 2146 #endif 2147 } 2148 2149 static void init_excp_POWER10(CPUPPCState *env) 2150 { 2151 init_excp_POWER9(env); 2152 } 2153 2154 #endif 2155 2156 static int check_pow_hid0(CPUPPCState *env) 2157 { 2158 if (env->spr[SPR_HID0] & 0x00E00000) { 2159 return 1; 2160 } 2161 2162 return 0; 2163 } 2164 2165 static int check_pow_hid0_74xx(CPUPPCState *env) 2166 { 2167 if (env->spr[SPR_HID0] & 0x00600000) { 2168 return 1; 2169 } 2170 2171 return 0; 2172 } 2173 2174 #if defined(TARGET_PPC64) 2175 static int check_attn_hid0(CPUPPCState *env) 2176 { 2177 if (env->spr[SPR_HID0] & HID0_ENABLE_ATTN) { 2178 return 1; 2179 } 2180 2181 return 0; 2182 } 2183 2184 static int check_attn_hid0_power9(CPUPPCState *env) 2185 { 2186 if (env->spr[SPR_HID0] & HID0_POWER9_ENABLE_ATTN) { 2187 return 1; 2188 } 2189 2190 return 0; 2191 } 2192 #endif 2193 2194 static void init_tlbs_emb(CPUPPCState *env) 2195 { 2196 #ifndef CONFIG_USER_ONLY 2197 env->nb_tlb = 64; 2198 env->nb_ways = 1; 2199 env->tlb_type = TLB_EMB; 2200 #endif 2201 } 2202 2203 static void init_proc_405(CPUPPCState *env) 2204 { 2205 register_40x_sprs(env); 2206 register_405_sprs(env); 2207 register_usprgh_sprs(env); 2208 2209 init_tlbs_emb(env); 2210 init_excp_4xx(env); 2211 env->dcache_line_size = 32; 2212 env->icache_line_size = 32; 2213 /* Allocate hardware IRQ controller */ 2214 ppc40x_irq_init(env_archcpu(env)); 2215 2216 SET_FIT_PERIOD(8, 12, 16, 20); 2217 SET_WDT_PERIOD(16, 20, 24, 28); 2218 } 2219 2220 POWERPC_FAMILY(405)(ObjectClass *oc, const void *data) 2221 { 2222 DeviceClass *dc = DEVICE_CLASS(oc); 2223 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2224 2225 dc->desc = "PowerPC 405"; 2226 pcc->init_proc = init_proc_405; 2227 pcc->check_pow = check_pow_nocheck; 2228 pcc->check_attn = check_attn_none; 2229 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2230 PPC_DCR | PPC_WRTEE | 2231 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 2232 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2233 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2234 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 2235 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP; 2236 pcc->msr_mask = (1ull << MSR_WE) | 2237 (1ull << MSR_CE) | 2238 (1ull << MSR_EE) | 2239 (1ull << MSR_PR) | 2240 (1ull << MSR_FP) | 2241 (1ull << MSR_ME) | 2242 (1ull << MSR_DWE) | 2243 (1ull << MSR_DE) | 2244 (1ull << MSR_IR) | 2245 (1ull << MSR_DR); 2246 pcc->mmu_model = POWERPC_MMU_SOFT_4xx; 2247 pcc->excp_model = POWERPC_EXCP_40x; 2248 pcc->bus_model = PPC_FLAGS_INPUT_405; 2249 pcc->bfd_mach = bfd_mach_ppc_403; 2250 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2251 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2252 } 2253 2254 static void init_proc_ppe42(CPUPPCState *env) 2255 { 2256 register_ppe42_sprs(env); 2257 2258 init_excp_ppe42(env); 2259 env->dcache_line_size = 32; 2260 env->icache_line_size = 32; 2261 /* Allocate hardware IRQ controller */ 2262 ppc40x_irq_init(env_archcpu(env)); 2263 2264 SET_FIT_PERIOD(8, 12, 16, 20); 2265 SET_WDT_PERIOD(16, 20, 24, 28); 2266 } 2267 2268 static void ppe42_class_common_init(PowerPCCPUClass *pcc) 2269 { 2270 pcc->init_proc = init_proc_ppe42; 2271 pcc->check_pow = check_pow_nocheck; 2272 pcc->check_attn = check_attn_none; 2273 pcc->insns_flags = PPC_INSNS_BASE | 2274 PPC_WRTEE | 2275 PPC_CACHE | 2276 PPC_CACHE_DCBZ | 2277 PPC_MEM_SYNC; 2278 pcc->msr_mask = R_MSR_SEM_MASK | 2279 (1ull << MSR_IS0) | 2280 R_MSR_SIBRC_MASK | 2281 (1ull << MSR_LP) | 2282 (1ull << MSR_WE) | 2283 (1ull << MSR_IS1) | 2284 (1ull << MSR_UIE) | 2285 (1ull << MSR_EE) | 2286 (1ull << MSR_ME) | 2287 (1ull << MSR_IS2) | 2288 (1ull << MSR_IS3) | 2289 (1ull << MSR_IPE) | 2290 R_MSR_SIBRCA_MASK; 2291 pcc->mmu_model = POWERPC_MMU_REAL; 2292 pcc->excp_model = POWERPC_EXCP_PPE42; 2293 pcc->bus_model = PPC_FLAGS_INPUT_PPE42; 2294 pcc->bfd_mach = bfd_mach_ppc_403; 2295 pcc->flags = POWERPC_FLAG_PPE42 | POWERPC_FLAG_BUS_CLK; 2296 } 2297 2298 POWERPC_FAMILY(ppe42)(ObjectClass *oc, const void *data) 2299 { 2300 DeviceClass *dc = DEVICE_CLASS(oc); 2301 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2302 2303 dc->desc = "PPE 42"; 2304 pcc->insns_flags2 = PPC2_PPE42; 2305 ppe42_class_common_init(pcc); 2306 } 2307 2308 POWERPC_FAMILY(ppe42x)(ObjectClass *oc, const void *data) 2309 { 2310 DeviceClass *dc = DEVICE_CLASS(oc); 2311 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2312 2313 dc->desc = "PPE 42X"; 2314 pcc->insns_flags2 = PPC2_PPE42 | PPC2_PPE42X; 2315 ppe42_class_common_init(pcc); 2316 } 2317 2318 POWERPC_FAMILY(ppe42xm)(ObjectClass *oc, const void *data) 2319 { 2320 DeviceClass *dc = DEVICE_CLASS(oc); 2321 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2322 2323 dc->desc = "PPE 42XM"; 2324 pcc->insns_flags2 = PPC2_PPE42 | PPC2_PPE42X | PPC2_PPE42XM; 2325 ppe42_class_common_init(pcc); 2326 } 2327 2328 static void init_proc_440EP(CPUPPCState *env) 2329 { 2330 register_BookE_sprs(env, 0x000000000000FFFFULL); 2331 register_440_sprs(env); 2332 register_usprgh_sprs(env); 2333 2334 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2335 SPR_NOACCESS, SPR_NOACCESS, 2336 &spr_read_generic, &spr_write_generic, 2337 0x00000000); 2338 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2339 SPR_NOACCESS, SPR_NOACCESS, 2340 &spr_read_generic, &spr_write_generic, 2341 0x00000000); 2342 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2343 SPR_NOACCESS, SPR_NOACCESS, 2344 &spr_read_generic, &spr_write_generic, 2345 0x00000000); 2346 2347 spr_register(env, SPR_440_CCR1, "CCR1", 2348 SPR_NOACCESS, SPR_NOACCESS, 2349 &spr_read_generic, &spr_write_generic, 2350 0x00000000); 2351 2352 init_tlbs_emb(env); 2353 init_excp_BookE(env); 2354 env->dcache_line_size = 32; 2355 env->icache_line_size = 32; 2356 ppc40x_irq_init(env_archcpu(env)); 2357 2358 SET_FIT_PERIOD(12, 16, 20, 24); 2359 SET_WDT_PERIOD(20, 24, 28, 32); 2360 } 2361 2362 POWERPC_FAMILY(440EP)(ObjectClass *oc, const void *data) 2363 { 2364 DeviceClass *dc = DEVICE_CLASS(oc); 2365 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2366 2367 dc->desc = "PowerPC 440 EP"; 2368 pcc->init_proc = init_proc_440EP; 2369 pcc->check_pow = check_pow_nocheck; 2370 pcc->check_attn = check_attn_none; 2371 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2372 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 2373 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 2374 PPC_FLOAT_STFIWX | 2375 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2376 PPC_CACHE | PPC_CACHE_ICBI | 2377 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2378 PPC_MEM_TLBSYNC | PPC_MFTB | 2379 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2380 PPC_440_SPEC; 2381 pcc->msr_mask = (1ull << MSR_POW) | 2382 (1ull << MSR_CE) | 2383 (1ull << MSR_EE) | 2384 (1ull << MSR_PR) | 2385 (1ull << MSR_FP) | 2386 (1ull << MSR_ME) | 2387 (1ull << MSR_FE0) | 2388 (1ull << MSR_DWE) | 2389 (1ull << MSR_DE) | 2390 (1ull << MSR_FE1) | 2391 (1ull << MSR_IR) | 2392 (1ull << MSR_DR); 2393 pcc->mmu_model = POWERPC_MMU_BOOKE; 2394 pcc->excp_model = POWERPC_EXCP_BOOKE; 2395 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2396 pcc->bfd_mach = bfd_mach_ppc_403; 2397 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2398 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2399 } 2400 2401 POWERPC_FAMILY(460EX)(ObjectClass *oc, const void *data) 2402 { 2403 DeviceClass *dc = DEVICE_CLASS(oc); 2404 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2405 2406 dc->desc = "PowerPC 460 EX"; 2407 pcc->init_proc = init_proc_440EP; 2408 pcc->check_pow = check_pow_nocheck; 2409 pcc->check_attn = check_attn_none; 2410 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2411 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 2412 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 2413 PPC_FLOAT_STFIWX | 2414 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI | 2415 PPC_CACHE | PPC_CACHE_ICBI | 2416 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2417 PPC_MEM_TLBSYNC | PPC_MFTB | 2418 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2419 PPC_440_SPEC; 2420 pcc->msr_mask = (1ull << MSR_POW) | 2421 (1ull << MSR_CE) | 2422 (1ull << MSR_EE) | 2423 (1ull << MSR_PR) | 2424 (1ull << MSR_FP) | 2425 (1ull << MSR_ME) | 2426 (1ull << MSR_FE0) | 2427 (1ull << MSR_DWE) | 2428 (1ull << MSR_DE) | 2429 (1ull << MSR_FE1) | 2430 (1ull << MSR_IR) | 2431 (1ull << MSR_DR); 2432 pcc->mmu_model = POWERPC_MMU_BOOKE; 2433 pcc->excp_model = POWERPC_EXCP_BOOKE; 2434 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2435 pcc->bfd_mach = bfd_mach_ppc_403; 2436 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2437 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2438 } 2439 2440 static void init_proc_440GP(CPUPPCState *env) 2441 { 2442 register_BookE_sprs(env, 0x000000000000FFFFULL); 2443 register_440_sprs(env); 2444 register_usprgh_sprs(env); 2445 2446 init_tlbs_emb(env); 2447 init_excp_BookE(env); 2448 env->dcache_line_size = 32; 2449 env->icache_line_size = 32; 2450 /* XXX: TODO: allocate internal IRQ controller */ 2451 2452 SET_FIT_PERIOD(12, 16, 20, 24); 2453 SET_WDT_PERIOD(20, 24, 28, 32); 2454 } 2455 2456 POWERPC_FAMILY(440GP)(ObjectClass *oc, const void *data) 2457 { 2458 DeviceClass *dc = DEVICE_CLASS(oc); 2459 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2460 2461 dc->desc = "PowerPC 440 GP"; 2462 pcc->init_proc = init_proc_440GP; 2463 pcc->check_pow = check_pow_nocheck; 2464 pcc->check_attn = check_attn_none; 2465 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2466 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | 2467 PPC_CACHE | PPC_CACHE_ICBI | 2468 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2469 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | 2470 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2471 PPC_440_SPEC; 2472 pcc->msr_mask = (1ull << MSR_POW) | 2473 (1ull << MSR_CE) | 2474 (1ull << MSR_EE) | 2475 (1ull << MSR_PR) | 2476 (1ull << MSR_FP) | 2477 (1ull << MSR_ME) | 2478 (1ull << MSR_FE0) | 2479 (1ull << MSR_DWE) | 2480 (1ull << MSR_DE) | 2481 (1ull << MSR_FE1) | 2482 (1ull << MSR_IR) | 2483 (1ull << MSR_DR); 2484 pcc->mmu_model = POWERPC_MMU_BOOKE; 2485 pcc->excp_model = POWERPC_EXCP_BOOKE; 2486 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2487 pcc->bfd_mach = bfd_mach_ppc_403; 2488 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2489 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2490 } 2491 2492 static void init_proc_440x5(CPUPPCState *env) 2493 { 2494 register_BookE_sprs(env, 0x000000000000FFFFULL); 2495 register_440_sprs(env); 2496 register_usprgh_sprs(env); 2497 2498 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2499 SPR_NOACCESS, SPR_NOACCESS, 2500 &spr_read_generic, &spr_write_generic, 2501 0x00000000); 2502 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2503 SPR_NOACCESS, SPR_NOACCESS, 2504 &spr_read_generic, &spr_write_generic, 2505 0x00000000); 2506 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2507 SPR_NOACCESS, SPR_NOACCESS, 2508 &spr_read_generic, &spr_write_generic, 2509 0x00000000); 2510 2511 spr_register(env, SPR_440_CCR1, "CCR1", 2512 SPR_NOACCESS, SPR_NOACCESS, 2513 &spr_read_generic, &spr_write_generic, 2514 0x00000000); 2515 2516 init_tlbs_emb(env); 2517 init_excp_BookE(env); 2518 env->dcache_line_size = 32; 2519 env->icache_line_size = 32; 2520 ppc40x_irq_init(env_archcpu(env)); 2521 2522 SET_FIT_PERIOD(12, 16, 20, 24); 2523 SET_WDT_PERIOD(20, 24, 28, 32); 2524 } 2525 2526 POWERPC_FAMILY(440x5)(ObjectClass *oc, const void *data) 2527 { 2528 DeviceClass *dc = DEVICE_CLASS(oc); 2529 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2530 2531 dc->desc = "PowerPC 440x5"; 2532 pcc->init_proc = init_proc_440x5; 2533 pcc->check_pow = check_pow_nocheck; 2534 pcc->check_attn = check_attn_none; 2535 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2536 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2537 PPC_CACHE | PPC_CACHE_ICBI | 2538 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2539 PPC_MEM_TLBSYNC | PPC_MFTB | 2540 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2541 PPC_440_SPEC; 2542 pcc->msr_mask = (1ull << MSR_POW) | 2543 (1ull << MSR_CE) | 2544 (1ull << MSR_EE) | 2545 (1ull << MSR_PR) | 2546 (1ull << MSR_FP) | 2547 (1ull << MSR_ME) | 2548 (1ull << MSR_FE0) | 2549 (1ull << MSR_DWE) | 2550 (1ull << MSR_DE) | 2551 (1ull << MSR_FE1) | 2552 (1ull << MSR_IR) | 2553 (1ull << MSR_DR); 2554 pcc->mmu_model = POWERPC_MMU_BOOKE; 2555 pcc->excp_model = POWERPC_EXCP_BOOKE; 2556 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2557 pcc->bfd_mach = bfd_mach_ppc_403; 2558 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2559 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2560 } 2561 2562 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, const void *data) 2563 { 2564 DeviceClass *dc = DEVICE_CLASS(oc); 2565 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2566 2567 dc->desc = "PowerPC 440x5 with double precision FPU"; 2568 pcc->init_proc = init_proc_440x5; 2569 pcc->check_pow = check_pow_nocheck; 2570 pcc->check_attn = check_attn_none; 2571 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2572 PPC_FLOAT | PPC_FLOAT_FSQRT | 2573 PPC_FLOAT_STFIWX | 2574 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2575 PPC_CACHE | PPC_CACHE_ICBI | 2576 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2577 PPC_MEM_TLBSYNC | PPC_MFTB | 2578 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2579 PPC_440_SPEC; 2580 pcc->insns_flags2 = PPC2_FP_CVT_S64; 2581 pcc->msr_mask = (1ull << MSR_POW) | 2582 (1ull << MSR_CE) | 2583 (1ull << MSR_EE) | 2584 (1ull << MSR_PR) | 2585 (1ull << MSR_FP) | 2586 (1ull << MSR_ME) | 2587 (1ull << MSR_FE0) | 2588 (1ull << MSR_DWE) | 2589 (1ull << MSR_DE) | 2590 (1ull << MSR_FE1) | 2591 (1ull << MSR_IR) | 2592 (1ull << MSR_DR); 2593 pcc->mmu_model = POWERPC_MMU_BOOKE; 2594 pcc->excp_model = POWERPC_EXCP_BOOKE; 2595 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2596 pcc->bfd_mach = bfd_mach_ppc_403; 2597 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2598 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2599 } 2600 2601 static void init_proc_MPC5xx(CPUPPCState *env) 2602 { 2603 register_5xx_8xx_sprs(env); 2604 register_5xx_sprs(env); 2605 init_excp_MPC5xx(env); 2606 env->dcache_line_size = 32; 2607 env->icache_line_size = 32; 2608 /* XXX: TODO: allocate internal IRQ controller */ 2609 } 2610 2611 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, const void *data) 2612 { 2613 DeviceClass *dc = DEVICE_CLASS(oc); 2614 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2615 2616 dc->desc = "Freescale 5xx cores (aka RCPU)"; 2617 pcc->init_proc = init_proc_MPC5xx; 2618 pcc->check_pow = check_pow_none; 2619 pcc->check_attn = check_attn_none; 2620 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2621 PPC_MEM_EIEIO | PPC_MEM_SYNC | 2622 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | 2623 PPC_MFTB; 2624 pcc->msr_mask = (1ull << MSR_ILE) | 2625 (1ull << MSR_EE) | 2626 (1ull << MSR_PR) | 2627 (1ull << MSR_FP) | 2628 (1ull << MSR_ME) | 2629 (1ull << MSR_FE0) | 2630 (1ull << MSR_SE) | 2631 (1ull << MSR_DE) | 2632 (1ull << MSR_FE1) | 2633 (1ull << MSR_EP) | 2634 (1ull << MSR_RI) | 2635 (1ull << MSR_LE); 2636 pcc->mmu_model = POWERPC_MMU_REAL; 2637 pcc->excp_model = POWERPC_EXCP_6xx; 2638 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 2639 pcc->bfd_mach = bfd_mach_ppc_505; 2640 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 2641 POWERPC_FLAG_BUS_CLK; 2642 } 2643 2644 static void init_proc_MPC8xx(CPUPPCState *env) 2645 { 2646 register_5xx_8xx_sprs(env); 2647 register_8xx_sprs(env); 2648 init_excp_MPC8xx(env); 2649 env->dcache_line_size = 32; 2650 env->icache_line_size = 32; 2651 /* XXX: TODO: allocate internal IRQ controller */ 2652 } 2653 2654 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, const void *data) 2655 { 2656 DeviceClass *dc = DEVICE_CLASS(oc); 2657 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2658 2659 dc->desc = "Freescale 8xx cores (aka PowerQUICC)"; 2660 pcc->init_proc = init_proc_MPC8xx; 2661 pcc->check_pow = check_pow_none; 2662 pcc->check_attn = check_attn_none; 2663 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2664 PPC_MEM_EIEIO | PPC_MEM_SYNC | 2665 PPC_CACHE_ICBI | PPC_MFTB; 2666 pcc->msr_mask = (1ull << MSR_ILE) | 2667 (1ull << MSR_EE) | 2668 (1ull << MSR_PR) | 2669 (1ull << MSR_FP) | 2670 (1ull << MSR_ME) | 2671 (1ull << MSR_SE) | 2672 (1ull << MSR_DE) | 2673 (1ull << MSR_EP) | 2674 (1ull << MSR_IR) | 2675 (1ull << MSR_DR) | 2676 (1ull << MSR_RI) | 2677 (1ull << MSR_LE); 2678 pcc->mmu_model = POWERPC_MMU_MPC8xx; 2679 pcc->excp_model = POWERPC_EXCP_6xx; 2680 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 2681 pcc->bfd_mach = bfd_mach_ppc_860; 2682 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 2683 POWERPC_FLAG_BUS_CLK; 2684 } 2685 2686 /* Freescale 82xx cores (aka PowerQUICC-II) */ 2687 2688 static void init_proc_G2(CPUPPCState *env) 2689 { 2690 register_non_embedded_sprs(env); 2691 register_sdr1_sprs(env); 2692 register_G2_sprs(env); 2693 2694 /* Memory management */ 2695 register_low_BATs(env); 2696 register_high_BATs(env); 2697 register_6xx_7xx_soft_tlb(env, 64, 2); 2698 init_excp_G2(env); 2699 env->dcache_line_size = 32; 2700 env->icache_line_size = 32; 2701 /* Allocate hardware IRQ controller */ 2702 ppc6xx_irq_init(env_archcpu(env)); 2703 } 2704 2705 POWERPC_FAMILY(G2)(ObjectClass *oc, const void *data) 2706 { 2707 DeviceClass *dc = DEVICE_CLASS(oc); 2708 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2709 2710 dc->desc = "PowerPC G2"; 2711 pcc->init_proc = init_proc_G2; 2712 pcc->check_pow = check_pow_hid0; 2713 pcc->check_attn = check_attn_none; 2714 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2715 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 2716 PPC_FLOAT_STFIWX | 2717 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 2718 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2719 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 2720 PPC_SEGMENT | PPC_EXTERN; 2721 pcc->msr_mask = (1ull << MSR_POW) | 2722 (1ull << MSR_TGPR) | 2723 (1ull << MSR_EE) | 2724 (1ull << MSR_PR) | 2725 (1ull << MSR_FP) | 2726 (1ull << MSR_ME) | 2727 (1ull << MSR_FE0) | 2728 (1ull << MSR_SE) | 2729 (1ull << MSR_DE) | 2730 (1ull << MSR_FE1) | 2731 (1ull << MSR_AL) | 2732 (1ull << MSR_EP) | 2733 (1ull << MSR_IR) | 2734 (1ull << MSR_DR) | 2735 (1ull << MSR_RI); 2736 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 2737 pcc->excp_model = POWERPC_EXCP_6xx; 2738 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 2739 pcc->bfd_mach = bfd_mach_ppc_ec603e; 2740 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 2741 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 2742 } 2743 2744 POWERPC_FAMILY(G2LE)(ObjectClass *oc, const void *data) 2745 { 2746 DeviceClass *dc = DEVICE_CLASS(oc); 2747 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2748 2749 dc->desc = "PowerPC G2LE"; 2750 pcc->init_proc = init_proc_G2; 2751 pcc->check_pow = check_pow_hid0; 2752 pcc->check_attn = check_attn_none; 2753 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2754 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 2755 PPC_FLOAT_STFIWX | 2756 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 2757 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2758 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 2759 PPC_SEGMENT | PPC_EXTERN; 2760 pcc->msr_mask = (1ull << MSR_POW) | 2761 (1ull << MSR_TGPR) | 2762 (1ull << MSR_ILE) | 2763 (1ull << MSR_EE) | 2764 (1ull << MSR_PR) | 2765 (1ull << MSR_FP) | 2766 (1ull << MSR_ME) | 2767 (1ull << MSR_FE0) | 2768 (1ull << MSR_SE) | 2769 (1ull << MSR_DE) | 2770 (1ull << MSR_FE1) | 2771 (1ull << MSR_AL) | 2772 (1ull << MSR_EP) | 2773 (1ull << MSR_IR) | 2774 (1ull << MSR_DR) | 2775 (1ull << MSR_RI) | 2776 (1ull << MSR_LE); 2777 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 2778 pcc->excp_model = POWERPC_EXCP_6xx; 2779 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 2780 pcc->bfd_mach = bfd_mach_ppc_ec603e; 2781 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 2782 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 2783 } 2784 2785 enum fsl_e500_version { 2786 fsl_e500v1, 2787 fsl_e500v2, 2788 fsl_e500mc, 2789 fsl_e5500, 2790 fsl_e6500, 2791 }; 2792 2793 static void init_proc_e500(CPUPPCState *env, int version) 2794 { 2795 uint32_t tlbncfg[2]; 2796 uint64_t ivor_mask; 2797 uint64_t ivpr_mask = 0xFFFF0000ULL; 2798 uint32_t l1cfg0 = 0x3800 /* 8 ways */ 2799 | 0x0020; /* 32 kb */ 2800 uint32_t l1cfg1 = 0x3800 /* 8 ways */ 2801 | 0x0020; /* 32 kb */ 2802 uint32_t mmucfg = 0; 2803 #if !defined(CONFIG_USER_ONLY) 2804 int i; 2805 #endif 2806 2807 /* 2808 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't 2809 * complain when accessing them. 2810 * register_BookE_sprs(env, 0x0000000F0000FD7FULL); 2811 */ 2812 switch (version) { 2813 case fsl_e500v1: 2814 case fsl_e500v2: 2815 default: 2816 ivor_mask = 0x0000000F0000FFFFULL; 2817 break; 2818 case fsl_e500mc: 2819 case fsl_e5500: 2820 ivor_mask = 0x000003FE0000FFFFULL; 2821 break; 2822 case fsl_e6500: 2823 ivor_mask = 0x000003FF0000FFFFULL; 2824 break; 2825 } 2826 register_BookE_sprs(env, ivor_mask); 2827 2828 spr_register(env, SPR_USPRG3, "USPRG3", 2829 &spr_read_ureg, SPR_NOACCESS, 2830 &spr_read_ureg, SPR_NOACCESS, 2831 0x00000000); 2832 2833 /* Processor identification */ 2834 spr_register(env, SPR_BOOKE_PIR, "PIR", 2835 SPR_NOACCESS, SPR_NOACCESS, 2836 &spr_read_generic, &spr_write_pir, 2837 0x00000000); 2838 2839 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 2840 &spr_read_spefscr, &spr_write_spefscr, 2841 &spr_read_spefscr, &spr_write_spefscr, 2842 0x00000000); 2843 #if !defined(CONFIG_USER_ONLY) 2844 /* Memory management */ 2845 env->nb_pids = 3; 2846 env->nb_ways = 2; 2847 switch (version) { 2848 case fsl_e500v1: 2849 tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256); 2850 tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 2851 break; 2852 case fsl_e500v2: 2853 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 2854 tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 2855 break; 2856 case fsl_e500mc: 2857 case fsl_e5500: 2858 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 2859 tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64); 2860 break; 2861 case fsl_e6500: 2862 mmucfg = 0x6510B45; 2863 env->nb_pids = 1; 2864 tlbncfg[0] = 0x08052400; 2865 tlbncfg[1] = 0x40028040; 2866 break; 2867 default: 2868 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 2869 env->spr[SPR_PVR]); 2870 } 2871 #endif 2872 /* Cache sizes */ 2873 switch (version) { 2874 case fsl_e500v1: 2875 case fsl_e500v2: 2876 env->dcache_line_size = 32; 2877 env->icache_line_size = 32; 2878 break; 2879 case fsl_e500mc: 2880 case fsl_e5500: 2881 env->dcache_line_size = 64; 2882 env->icache_line_size = 64; 2883 l1cfg0 |= 0x1000000; /* 64 byte cache block size */ 2884 l1cfg1 |= 0x1000000; /* 64 byte cache block size */ 2885 break; 2886 case fsl_e6500: 2887 env->dcache_line_size = 32; 2888 env->icache_line_size = 32; 2889 l1cfg0 |= 0x0F83820; 2890 l1cfg1 |= 0x0B83820; 2891 break; 2892 default: 2893 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 2894 env->spr[SPR_PVR]); 2895 } 2896 register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg); 2897 register_usprgh_sprs(env); 2898 2899 if (version != fsl_e500v1) { 2900 /* e500v1 has no support for alternate timebase */ 2901 register_atb_sprs(env); 2902 } 2903 2904 spr_register(env, SPR_HID0, "HID0", 2905 SPR_NOACCESS, SPR_NOACCESS, 2906 &spr_read_generic, &spr_write_generic, 2907 0x00000000); 2908 2909 spr_register(env, SPR_HID1, "HID1", 2910 SPR_NOACCESS, SPR_NOACCESS, 2911 &spr_read_generic, &spr_write_generic, 2912 0x00000000); 2913 2914 spr_register(env, SPR_Exxx_BBEAR, "BBEAR", 2915 SPR_NOACCESS, SPR_NOACCESS, 2916 &spr_read_generic, &spr_write_generic, 2917 0x00000000); 2918 2919 spr_register(env, SPR_Exxx_BBTAR, "BBTAR", 2920 SPR_NOACCESS, SPR_NOACCESS, 2921 &spr_read_generic, &spr_write_generic, 2922 0x00000000); 2923 2924 spr_register(env, SPR_Exxx_MCAR, "MCAR", 2925 SPR_NOACCESS, SPR_NOACCESS, 2926 &spr_read_generic, &spr_write_generic, 2927 0x00000000); 2928 2929 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2930 SPR_NOACCESS, SPR_NOACCESS, 2931 &spr_read_generic, &spr_write_generic, 2932 0x00000000); 2933 2934 spr_register(env, SPR_Exxx_NPIDR, "NPIDR", 2935 SPR_NOACCESS, SPR_NOACCESS, 2936 &spr_read_generic, &spr_write_generic, 2937 0x00000000); 2938 2939 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 2940 SPR_NOACCESS, SPR_NOACCESS, 2941 &spr_read_generic, &spr_write_generic, 2942 0x00000000); 2943 2944 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 2945 &spr_read_generic, SPR_NOACCESS, 2946 &spr_read_generic, SPR_NOACCESS, 2947 l1cfg0); 2948 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1", 2949 &spr_read_generic, SPR_NOACCESS, 2950 &spr_read_generic, SPR_NOACCESS, 2951 l1cfg1); 2952 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 2953 SPR_NOACCESS, SPR_NOACCESS, 2954 &spr_read_generic, &spr_write_e500_l1csr0, 2955 0x00000000); 2956 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1", 2957 SPR_NOACCESS, SPR_NOACCESS, 2958 &spr_read_generic, &spr_write_e500_l1csr1, 2959 0x00000000); 2960 if (version != fsl_e500v1 && version != fsl_e500v2) { 2961 spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0", 2962 SPR_NOACCESS, SPR_NOACCESS, 2963 &spr_read_generic, &spr_write_e500_l2csr0, 2964 0x00000000); 2965 } 2966 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2967 SPR_NOACCESS, SPR_NOACCESS, 2968 &spr_read_generic, &spr_write_generic, 2969 0x00000000); 2970 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2971 SPR_NOACCESS, SPR_NOACCESS, 2972 &spr_read_generic, &spr_write_generic, 2973 0x00000000); 2974 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 2975 SPR_NOACCESS, SPR_NOACCESS, 2976 &spr_read_generic, &spr_write_booke206_mmucsr0, 2977 0x00000000); 2978 spr_register(env, SPR_BOOKE_EPR, "EPR", 2979 SPR_NOACCESS, SPR_NOACCESS, 2980 &spr_read_generic, SPR_NOACCESS, 2981 0x00000000); 2982 /* XXX better abstract into Emb.xxx features */ 2983 if ((version == fsl_e5500) || (version == fsl_e6500)) { 2984 spr_register(env, SPR_BOOKE_EPCR, "EPCR", 2985 SPR_NOACCESS, SPR_NOACCESS, 2986 &spr_read_generic, &spr_write_generic, 2987 0x00000000); 2988 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3", 2989 SPR_NOACCESS, SPR_NOACCESS, 2990 &spr_read_mas73, &spr_write_mas73, 2991 0x00000000); 2992 ivpr_mask = (target_ulong)~0xFFFFULL; 2993 } 2994 2995 if (version == fsl_e6500) { 2996 /* Thread identification */ 2997 spr_register(env, SPR_TIR, "TIR", 2998 SPR_NOACCESS, SPR_NOACCESS, 2999 &spr_read_generic, SPR_NOACCESS, 3000 0x00000000); 3001 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS", 3002 SPR_NOACCESS, SPR_NOACCESS, 3003 &spr_read_generic, SPR_NOACCESS, 3004 0x00000004); 3005 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS", 3006 SPR_NOACCESS, SPR_NOACCESS, 3007 &spr_read_generic, SPR_NOACCESS, 3008 0x7FFFFFFC); 3009 } 3010 3011 #if !defined(CONFIG_USER_ONLY) 3012 env->nb_tlb = 0; 3013 env->tlb_type = TLB_MAS; 3014 for (i = 0; i < BOOKE206_MAX_TLBN; i++) { 3015 env->nb_tlb += booke206_tlb_size(env, i); 3016 } 3017 #endif 3018 3019 init_excp_e500(env, ivpr_mask); 3020 /* Allocate hardware IRQ controller */ 3021 ppce500_irq_init(env_archcpu(env)); 3022 } 3023 3024 static void init_proc_e500v1(CPUPPCState *env) 3025 { 3026 init_proc_e500(env, fsl_e500v1); 3027 } 3028 3029 POWERPC_FAMILY(e500v1)(ObjectClass *oc, const void *data) 3030 { 3031 DeviceClass *dc = DEVICE_CLASS(oc); 3032 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3033 3034 dc->desc = "e500v1 core"; 3035 pcc->init_proc = init_proc_e500v1; 3036 pcc->check_pow = check_pow_hid0; 3037 pcc->check_attn = check_attn_none; 3038 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3039 PPC_SPE | PPC_SPE_SINGLE | 3040 PPC_WRTEE | PPC_RFDI | 3041 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3042 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3043 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3044 pcc->insns_flags2 = PPC2_BOOKE206; 3045 pcc->msr_mask = (1ull << MSR_UCLE) | 3046 (1ull << MSR_SPE) | 3047 (1ull << MSR_POW) | 3048 (1ull << MSR_CE) | 3049 (1ull << MSR_EE) | 3050 (1ull << MSR_PR) | 3051 (1ull << MSR_FP) | 3052 (1ull << MSR_ME) | 3053 (1ull << MSR_FE0) | 3054 (1ull << MSR_DWE) | 3055 (1ull << MSR_DE) | 3056 (1ull << MSR_FE1) | 3057 (1ull << MSR_IR) | 3058 (1ull << MSR_DR); 3059 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3060 pcc->excp_model = POWERPC_EXCP_BOOKE; 3061 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3062 pcc->bfd_mach = bfd_mach_ppc_860; 3063 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3064 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3065 POWERPC_FLAG_BUS_CLK; 3066 } 3067 3068 static void init_proc_e500v2(CPUPPCState *env) 3069 { 3070 init_proc_e500(env, fsl_e500v2); 3071 } 3072 3073 POWERPC_FAMILY(e500v2)(ObjectClass *oc, const void *data) 3074 { 3075 DeviceClass *dc = DEVICE_CLASS(oc); 3076 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3077 3078 dc->desc = "e500v2 core"; 3079 pcc->init_proc = init_proc_e500v2; 3080 pcc->check_pow = check_pow_hid0; 3081 pcc->check_attn = check_attn_none; 3082 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3083 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | 3084 PPC_WRTEE | PPC_RFDI | 3085 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3086 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3087 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3088 pcc->insns_flags2 = PPC2_BOOKE206; 3089 pcc->msr_mask = (1ull << MSR_UCLE) | 3090 (1ull << MSR_SPE) | 3091 (1ull << MSR_POW) | 3092 (1ull << MSR_CE) | 3093 (1ull << MSR_EE) | 3094 (1ull << MSR_PR) | 3095 (1ull << MSR_FP) | 3096 (1ull << MSR_ME) | 3097 (1ull << MSR_FE0) | 3098 (1ull << MSR_DWE) | 3099 (1ull << MSR_DE) | 3100 (1ull << MSR_FE1) | 3101 (1ull << MSR_IR) | 3102 (1ull << MSR_DR); 3103 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3104 pcc->excp_model = POWERPC_EXCP_BOOKE; 3105 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3106 pcc->bfd_mach = bfd_mach_ppc_860; 3107 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3108 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3109 POWERPC_FLAG_BUS_CLK; 3110 } 3111 3112 static void init_proc_e500mc(CPUPPCState *env) 3113 { 3114 init_proc_e500(env, fsl_e500mc); 3115 } 3116 3117 POWERPC_FAMILY(e500mc)(ObjectClass *oc, const void *data) 3118 { 3119 DeviceClass *dc = DEVICE_CLASS(oc); 3120 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3121 3122 dc->desc = "e500mc core"; 3123 pcc->init_proc = init_proc_e500mc; 3124 pcc->check_pow = check_pow_none; 3125 pcc->check_attn = check_attn_none; 3126 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3127 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3128 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3129 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3130 PPC_FLOAT | PPC_FLOAT_FRES | 3131 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3132 PPC_FLOAT_STFIWX | PPC_WAIT | 3133 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3134 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL; 3135 pcc->msr_mask = (1ull << MSR_GS) | 3136 (1ull << MSR_UCLE) | 3137 (1ull << MSR_CE) | 3138 (1ull << MSR_EE) | 3139 (1ull << MSR_PR) | 3140 (1ull << MSR_FP) | 3141 (1ull << MSR_ME) | 3142 (1ull << MSR_FE0) | 3143 (1ull << MSR_DE) | 3144 (1ull << MSR_FE1) | 3145 (1ull << MSR_IR) | 3146 (1ull << MSR_DR) | 3147 (1ull << MSR_PX) | 3148 (1ull << MSR_RI); 3149 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3150 pcc->excp_model = POWERPC_EXCP_BOOKE; 3151 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3152 /* FIXME: figure out the correct flag for e500mc */ 3153 pcc->bfd_mach = bfd_mach_ppc_e500; 3154 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3155 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3156 } 3157 3158 #ifdef TARGET_PPC64 3159 static void init_proc_e5500(CPUPPCState *env) 3160 { 3161 init_proc_e500(env, fsl_e5500); 3162 } 3163 3164 POWERPC_FAMILY(e5500)(ObjectClass *oc, const void *data) 3165 { 3166 DeviceClass *dc = DEVICE_CLASS(oc); 3167 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3168 3169 dc->desc = "e5500 core"; 3170 pcc->init_proc = init_proc_e5500; 3171 pcc->check_pow = check_pow_none; 3172 pcc->check_attn = check_attn_none; 3173 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3174 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3175 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3176 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3177 PPC_FLOAT | PPC_FLOAT_FRES | 3178 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3179 PPC_FLOAT_STFIWX | PPC_WAIT | 3180 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 3181 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD; 3182 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 3183 PPC2_FP_CVT_S64; 3184 pcc->msr_mask = (1ull << MSR_CM) | 3185 (1ull << MSR_GS) | 3186 (1ull << MSR_UCLE) | 3187 (1ull << MSR_CE) | 3188 (1ull << MSR_EE) | 3189 (1ull << MSR_PR) | 3190 (1ull << MSR_FP) | 3191 (1ull << MSR_ME) | 3192 (1ull << MSR_FE0) | 3193 (1ull << MSR_DE) | 3194 (1ull << MSR_FE1) | 3195 (1ull << MSR_IR) | 3196 (1ull << MSR_DR) | 3197 (1ull << MSR_PX) | 3198 (1ull << MSR_RI); 3199 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3200 pcc->excp_model = POWERPC_EXCP_BOOKE; 3201 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3202 /* FIXME: figure out the correct flag for e5500 */ 3203 pcc->bfd_mach = bfd_mach_ppc_e500; 3204 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3205 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3206 } 3207 3208 static void init_proc_e6500(CPUPPCState *env) 3209 { 3210 init_proc_e500(env, fsl_e6500); 3211 } 3212 3213 POWERPC_FAMILY(e6500)(ObjectClass *oc, const void *data) 3214 { 3215 DeviceClass *dc = DEVICE_CLASS(oc); 3216 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3217 3218 dc->desc = "e6500 core"; 3219 pcc->init_proc = init_proc_e6500; 3220 pcc->check_pow = check_pow_none; 3221 pcc->check_attn = check_attn_none; 3222 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3223 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3224 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3225 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3226 PPC_FLOAT | PPC_FLOAT_FRES | 3227 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3228 PPC_FLOAT_STFIWX | PPC_WAIT | 3229 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 3230 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC; 3231 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 3232 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206; 3233 pcc->msr_mask = (1ull << MSR_CM) | 3234 (1ull << MSR_GS) | 3235 (1ull << MSR_UCLE) | 3236 (1ull << MSR_CE) | 3237 (1ull << MSR_EE) | 3238 (1ull << MSR_PR) | 3239 (1ull << MSR_FP) | 3240 (1ull << MSR_ME) | 3241 (1ull << MSR_FE0) | 3242 (1ull << MSR_DE) | 3243 (1ull << MSR_FE1) | 3244 (1ull << MSR_IS) | 3245 (1ull << MSR_DS) | 3246 (1ull << MSR_PX) | 3247 (1ull << MSR_RI) | 3248 (1ull << MSR_VR); 3249 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3250 pcc->excp_model = POWERPC_EXCP_BOOKE; 3251 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3252 pcc->bfd_mach = bfd_mach_ppc_e500; 3253 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3254 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE; 3255 } 3256 3257 #endif 3258 3259 /* Non-embedded PowerPC */ 3260 static void init_proc_603(CPUPPCState *env) 3261 { 3262 register_non_embedded_sprs(env); 3263 register_sdr1_sprs(env); 3264 register_603_sprs(env); 3265 3266 /* Memory management */ 3267 register_low_BATs(env); 3268 register_6xx_7xx_soft_tlb(env, 64, 2); 3269 init_excp_603(env); 3270 env->dcache_line_size = 32; 3271 env->icache_line_size = 32; 3272 /* Allocate hardware IRQ controller */ 3273 ppc6xx_irq_init(env_archcpu(env)); 3274 } 3275 3276 POWERPC_FAMILY(603)(ObjectClass *oc, const void *data) 3277 { 3278 DeviceClass *dc = DEVICE_CLASS(oc); 3279 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3280 3281 dc->desc = "PowerPC 603"; 3282 pcc->init_proc = init_proc_603; 3283 pcc->check_pow = check_pow_hid0; 3284 pcc->check_attn = check_attn_none; 3285 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3286 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3287 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3288 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3289 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3290 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3291 PPC_SEGMENT | PPC_EXTERN; 3292 pcc->msr_mask = (1ull << MSR_POW) | 3293 (1ull << MSR_TGPR) | 3294 (1ull << MSR_ILE) | 3295 (1ull << MSR_EE) | 3296 (1ull << MSR_PR) | 3297 (1ull << MSR_FP) | 3298 (1ull << MSR_ME) | 3299 (1ull << MSR_FE0) | 3300 (1ull << MSR_SE) | 3301 (1ull << MSR_DE) | 3302 (1ull << MSR_FE1) | 3303 (1ull << MSR_EP) | 3304 (1ull << MSR_IR) | 3305 (1ull << MSR_DR) | 3306 (1ull << MSR_RI) | 3307 (1ull << MSR_LE); 3308 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3309 pcc->excp_model = POWERPC_EXCP_6xx; 3310 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3311 pcc->bfd_mach = bfd_mach_ppc_603; 3312 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3313 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3314 } 3315 3316 POWERPC_FAMILY(603E)(ObjectClass *oc, const void *data) 3317 { 3318 DeviceClass *dc = DEVICE_CLASS(oc); 3319 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3320 3321 dc->desc = "PowerPC 603e"; 3322 pcc->init_proc = init_proc_603; 3323 pcc->check_pow = check_pow_hid0; 3324 pcc->check_attn = check_attn_none; 3325 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3326 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3327 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3328 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3329 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3330 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3331 PPC_SEGMENT | PPC_EXTERN; 3332 pcc->msr_mask = (1ull << MSR_POW) | 3333 (1ull << MSR_TGPR) | 3334 (1ull << MSR_ILE) | 3335 (1ull << MSR_EE) | 3336 (1ull << MSR_PR) | 3337 (1ull << MSR_FP) | 3338 (1ull << MSR_ME) | 3339 (1ull << MSR_FE0) | 3340 (1ull << MSR_SE) | 3341 (1ull << MSR_DE) | 3342 (1ull << MSR_FE1) | 3343 (1ull << MSR_EP) | 3344 (1ull << MSR_IR) | 3345 (1ull << MSR_DR) | 3346 (1ull << MSR_RI) | 3347 (1ull << MSR_LE); 3348 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3349 pcc->excp_model = POWERPC_EXCP_6xx; 3350 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3351 pcc->bfd_mach = bfd_mach_ppc_ec603e; 3352 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3353 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3354 } 3355 3356 static void init_proc_e300(CPUPPCState *env) 3357 { 3358 init_proc_603(env); 3359 register_e300_sprs(env); 3360 } 3361 3362 POWERPC_FAMILY(e300)(ObjectClass *oc, const void *data) 3363 { 3364 DeviceClass *dc = DEVICE_CLASS(oc); 3365 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3366 3367 dc->desc = "e300 core"; 3368 pcc->init_proc = init_proc_e300; 3369 pcc->check_pow = check_pow_hid0; 3370 pcc->check_attn = check_attn_none; 3371 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3372 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3373 PPC_FLOAT_STFIWX | 3374 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3375 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3376 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3377 PPC_SEGMENT | PPC_EXTERN; 3378 pcc->msr_mask = (1ull << MSR_POW) | 3379 (1ull << MSR_TGPR) | 3380 (1ull << MSR_ILE) | 3381 (1ull << MSR_EE) | 3382 (1ull << MSR_PR) | 3383 (1ull << MSR_FP) | 3384 (1ull << MSR_ME) | 3385 (1ull << MSR_FE0) | 3386 (1ull << MSR_SE) | 3387 (1ull << MSR_DE) | 3388 (1ull << MSR_FE1) | 3389 (1ull << MSR_AL) | 3390 (1ull << MSR_EP) | 3391 (1ull << MSR_IR) | 3392 (1ull << MSR_DR) | 3393 (1ull << MSR_RI) | 3394 (1ull << MSR_LE); 3395 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3396 pcc->excp_model = POWERPC_EXCP_6xx; 3397 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3398 pcc->bfd_mach = bfd_mach_ppc_603; 3399 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3400 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3401 } 3402 3403 static void init_proc_604(CPUPPCState *env) 3404 { 3405 register_non_embedded_sprs(env); 3406 register_sdr1_sprs(env); 3407 register_604_sprs(env); 3408 3409 /* Memory management */ 3410 register_low_BATs(env); 3411 init_excp_604(env); 3412 env->dcache_line_size = 32; 3413 env->icache_line_size = 32; 3414 /* Allocate hardware IRQ controller */ 3415 ppc6xx_irq_init(env_archcpu(env)); 3416 } 3417 3418 POWERPC_FAMILY(604)(ObjectClass *oc, const void *data) 3419 { 3420 DeviceClass *dc = DEVICE_CLASS(oc); 3421 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3422 3423 dc->desc = "PowerPC 604"; 3424 pcc->init_proc = init_proc_604; 3425 pcc->check_pow = check_pow_nocheck; 3426 pcc->check_attn = check_attn_none; 3427 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3428 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3429 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3430 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3431 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3432 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3433 PPC_SEGMENT | PPC_EXTERN; 3434 pcc->msr_mask = (1ull << MSR_POW) | 3435 (1ull << MSR_ILE) | 3436 (1ull << MSR_EE) | 3437 (1ull << MSR_PR) | 3438 (1ull << MSR_FP) | 3439 (1ull << MSR_ME) | 3440 (1ull << MSR_FE0) | 3441 (1ull << MSR_SE) | 3442 (1ull << MSR_DE) | 3443 (1ull << MSR_FE1) | 3444 (1ull << MSR_EP) | 3445 (1ull << MSR_IR) | 3446 (1ull << MSR_DR) | 3447 (1ull << MSR_PMM) | 3448 (1ull << MSR_RI) | 3449 (1ull << MSR_LE); 3450 pcc->mmu_model = POWERPC_MMU_32B; 3451 pcc->excp_model = POWERPC_EXCP_6xx; 3452 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3453 pcc->bfd_mach = bfd_mach_ppc_604; 3454 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3455 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3456 } 3457 3458 static void init_proc_604E(CPUPPCState *env) 3459 { 3460 init_proc_604(env); 3461 register_604e_sprs(env); 3462 } 3463 3464 POWERPC_FAMILY(604E)(ObjectClass *oc, const void *data) 3465 { 3466 DeviceClass *dc = DEVICE_CLASS(oc); 3467 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3468 3469 dc->desc = "PowerPC 604E"; 3470 pcc->init_proc = init_proc_604E; 3471 pcc->check_pow = check_pow_nocheck; 3472 pcc->check_attn = check_attn_none; 3473 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3474 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3475 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3476 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3477 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3478 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3479 PPC_SEGMENT | PPC_EXTERN; 3480 pcc->msr_mask = (1ull << MSR_POW) | 3481 (1ull << MSR_ILE) | 3482 (1ull << MSR_EE) | 3483 (1ull << MSR_PR) | 3484 (1ull << MSR_FP) | 3485 (1ull << MSR_ME) | 3486 (1ull << MSR_FE0) | 3487 (1ull << MSR_SE) | 3488 (1ull << MSR_DE) | 3489 (1ull << MSR_FE1) | 3490 (1ull << MSR_EP) | 3491 (1ull << MSR_IR) | 3492 (1ull << MSR_DR) | 3493 (1ull << MSR_PMM) | 3494 (1ull << MSR_RI) | 3495 (1ull << MSR_LE); 3496 pcc->mmu_model = POWERPC_MMU_32B; 3497 pcc->excp_model = POWERPC_EXCP_6xx; 3498 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3499 pcc->bfd_mach = bfd_mach_ppc_604; 3500 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3501 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3502 } 3503 3504 static void init_proc_740(CPUPPCState *env) 3505 { 3506 register_non_embedded_sprs(env); 3507 register_sdr1_sprs(env); 3508 register_7xx_sprs(env); 3509 /* Thermal management */ 3510 register_thrm_sprs(env); 3511 3512 /* Memory management */ 3513 register_low_BATs(env); 3514 init_excp_7x0(env); 3515 env->dcache_line_size = 32; 3516 env->icache_line_size = 32; 3517 /* Allocate hardware IRQ controller */ 3518 ppc6xx_irq_init(env_archcpu(env)); 3519 } 3520 3521 POWERPC_FAMILY(740)(ObjectClass *oc, const void *data) 3522 { 3523 DeviceClass *dc = DEVICE_CLASS(oc); 3524 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3525 3526 dc->desc = "PowerPC 740"; 3527 pcc->init_proc = init_proc_740; 3528 pcc->check_pow = check_pow_hid0; 3529 pcc->check_attn = check_attn_none; 3530 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3531 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3532 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3533 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3534 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3535 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3536 PPC_SEGMENT | PPC_EXTERN; 3537 pcc->msr_mask = (1ull << MSR_POW) | 3538 (1ull << MSR_ILE) | 3539 (1ull << MSR_EE) | 3540 (1ull << MSR_PR) | 3541 (1ull << MSR_FP) | 3542 (1ull << MSR_ME) | 3543 (1ull << MSR_FE0) | 3544 (1ull << MSR_SE) | 3545 (1ull << MSR_DE) | 3546 (1ull << MSR_FE1) | 3547 (1ull << MSR_EP) | 3548 (1ull << MSR_IR) | 3549 (1ull << MSR_DR) | 3550 (1ull << MSR_PMM) | 3551 (1ull << MSR_RI) | 3552 (1ull << MSR_LE); 3553 pcc->mmu_model = POWERPC_MMU_32B; 3554 pcc->excp_model = POWERPC_EXCP_7xx; 3555 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3556 pcc->bfd_mach = bfd_mach_ppc_750; 3557 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3558 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3559 } 3560 3561 static void init_proc_750(CPUPPCState *env) 3562 { 3563 register_non_embedded_sprs(env); 3564 register_sdr1_sprs(env); 3565 register_7xx_sprs(env); 3566 3567 spr_register(env, SPR_L2CR, "L2CR", 3568 SPR_NOACCESS, SPR_NOACCESS, 3569 &spr_read_generic, spr_access_nop, 3570 0x00000000); 3571 /* Thermal management */ 3572 register_thrm_sprs(env); 3573 3574 /* Memory management */ 3575 register_low_BATs(env); 3576 /* 3577 * XXX: high BATs are also present but are known to be bugged on 3578 * die version 1.x 3579 */ 3580 init_excp_7x0(env); 3581 env->dcache_line_size = 32; 3582 env->icache_line_size = 32; 3583 /* Allocate hardware IRQ controller */ 3584 ppc6xx_irq_init(env_archcpu(env)); 3585 } 3586 3587 POWERPC_FAMILY(750)(ObjectClass *oc, const void *data) 3588 { 3589 DeviceClass *dc = DEVICE_CLASS(oc); 3590 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3591 3592 dc->desc = "PowerPC 750"; 3593 pcc->init_proc = init_proc_750; 3594 pcc->check_pow = check_pow_hid0; 3595 pcc->check_attn = check_attn_none; 3596 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3597 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3598 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3599 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3600 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3601 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3602 PPC_SEGMENT | PPC_EXTERN; 3603 pcc->msr_mask = (1ull << MSR_POW) | 3604 (1ull << MSR_ILE) | 3605 (1ull << MSR_EE) | 3606 (1ull << MSR_PR) | 3607 (1ull << MSR_FP) | 3608 (1ull << MSR_ME) | 3609 (1ull << MSR_FE0) | 3610 (1ull << MSR_SE) | 3611 (1ull << MSR_DE) | 3612 (1ull << MSR_FE1) | 3613 (1ull << MSR_EP) | 3614 (1ull << MSR_IR) | 3615 (1ull << MSR_DR) | 3616 (1ull << MSR_PMM) | 3617 (1ull << MSR_RI) | 3618 (1ull << MSR_LE); 3619 pcc->mmu_model = POWERPC_MMU_32B; 3620 pcc->excp_model = POWERPC_EXCP_7xx; 3621 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3622 pcc->bfd_mach = bfd_mach_ppc_750; 3623 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3624 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3625 } 3626 3627 static void init_proc_750cl(CPUPPCState *env) 3628 { 3629 register_non_embedded_sprs(env); 3630 register_sdr1_sprs(env); 3631 register_7xx_sprs(env); 3632 3633 spr_register(env, SPR_L2CR, "L2CR", 3634 SPR_NOACCESS, SPR_NOACCESS, 3635 &spr_read_generic, spr_access_nop, 3636 0x00000000); 3637 /* Thermal management */ 3638 /* Those registers are fake on 750CL */ 3639 spr_register(env, SPR_THRM1, "THRM1", 3640 SPR_NOACCESS, SPR_NOACCESS, 3641 &spr_read_generic, &spr_write_generic, 3642 0x00000000); 3643 spr_register(env, SPR_THRM2, "THRM2", 3644 SPR_NOACCESS, SPR_NOACCESS, 3645 &spr_read_generic, &spr_write_generic, 3646 0x00000000); 3647 spr_register(env, SPR_THRM3, "THRM3", 3648 SPR_NOACCESS, SPR_NOACCESS, 3649 &spr_read_generic, &spr_write_generic, 3650 0x00000000); 3651 3652 spr_register(env, SPR_750_TDCL, "TDCL", 3653 SPR_NOACCESS, SPR_NOACCESS, 3654 &spr_read_generic, &spr_write_generic, 3655 0x00000000); 3656 spr_register(env, SPR_750_TDCH, "TDCH", 3657 SPR_NOACCESS, SPR_NOACCESS, 3658 &spr_read_generic, &spr_write_generic, 3659 0x00000000); 3660 /* DMA */ 3661 spr_register(env, SPR_750_WPAR, "WPAR", 3662 SPR_NOACCESS, SPR_NOACCESS, 3663 &spr_read_generic, &spr_write_generic, 3664 0x00000000); 3665 spr_register(env, SPR_750_DMAL, "DMAL", 3666 SPR_NOACCESS, SPR_NOACCESS, 3667 &spr_read_generic, &spr_write_generic, 3668 0x00000000); 3669 spr_register(env, SPR_750_DMAU, "DMAU", 3670 SPR_NOACCESS, SPR_NOACCESS, 3671 &spr_read_generic, &spr_write_generic, 3672 0x00000000); 3673 /* Hardware implementation registers */ 3674 spr_register(env, SPR_750CL_HID2, "HID2", 3675 SPR_NOACCESS, SPR_NOACCESS, 3676 &spr_read_generic, &spr_write_generic, 3677 0x00000000); 3678 3679 spr_register(env, SPR_750CL_HID4, "HID4", 3680 SPR_NOACCESS, SPR_NOACCESS, 3681 &spr_read_generic, &spr_write_generic, 3682 0x00000000); 3683 /* Quantization registers */ 3684 spr_register(env, SPR_750_GQR0, "GQR0", 3685 SPR_NOACCESS, SPR_NOACCESS, 3686 &spr_read_generic, &spr_write_generic, 3687 0x00000000); 3688 3689 spr_register(env, SPR_750_GQR1, "GQR1", 3690 SPR_NOACCESS, SPR_NOACCESS, 3691 &spr_read_generic, &spr_write_generic, 3692 0x00000000); 3693 3694 spr_register(env, SPR_750_GQR2, "GQR2", 3695 SPR_NOACCESS, SPR_NOACCESS, 3696 &spr_read_generic, &spr_write_generic, 3697 0x00000000); 3698 3699 spr_register(env, SPR_750_GQR3, "GQR3", 3700 SPR_NOACCESS, SPR_NOACCESS, 3701 &spr_read_generic, &spr_write_generic, 3702 0x00000000); 3703 3704 spr_register(env, SPR_750_GQR4, "GQR4", 3705 SPR_NOACCESS, SPR_NOACCESS, 3706 &spr_read_generic, &spr_write_generic, 3707 0x00000000); 3708 3709 spr_register(env, SPR_750_GQR5, "GQR5", 3710 SPR_NOACCESS, SPR_NOACCESS, 3711 &spr_read_generic, &spr_write_generic, 3712 0x00000000); 3713 3714 spr_register(env, SPR_750_GQR6, "GQR6", 3715 SPR_NOACCESS, SPR_NOACCESS, 3716 &spr_read_generic, &spr_write_generic, 3717 0x00000000); 3718 3719 spr_register(env, SPR_750_GQR7, "GQR7", 3720 SPR_NOACCESS, SPR_NOACCESS, 3721 &spr_read_generic, &spr_write_generic, 3722 0x00000000); 3723 /* Memory management */ 3724 register_low_BATs(env); 3725 /* PowerPC 750cl has 8 DBATs and 8 IBATs */ 3726 register_high_BATs(env); 3727 init_excp_750cl(env); 3728 env->dcache_line_size = 32; 3729 env->icache_line_size = 32; 3730 /* Allocate hardware IRQ controller */ 3731 ppc6xx_irq_init(env_archcpu(env)); 3732 } 3733 3734 POWERPC_FAMILY(750cl)(ObjectClass *oc, const void *data) 3735 { 3736 DeviceClass *dc = DEVICE_CLASS(oc); 3737 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3738 3739 dc->desc = "PowerPC 750 CL"; 3740 pcc->init_proc = init_proc_750cl; 3741 pcc->check_pow = check_pow_hid0; 3742 pcc->check_attn = check_attn_none; 3743 /* 3744 * XXX: not implemented: 3745 * cache lock instructions: 3746 * dcbz_l 3747 * floating point paired instructions 3748 * psq_lux 3749 * psq_lx 3750 * psq_stux 3751 * psq_stx 3752 * ps_abs 3753 * ps_add 3754 * ps_cmpo0 3755 * ps_cmpo1 3756 * ps_cmpu0 3757 * ps_cmpu1 3758 * ps_div 3759 * ps_madd 3760 * ps_madds0 3761 * ps_madds1 3762 * ps_merge00 3763 * ps_merge01 3764 * ps_merge10 3765 * ps_merge11 3766 * ps_mr 3767 * ps_msub 3768 * ps_mul 3769 * ps_muls0 3770 * ps_muls1 3771 * ps_nabs 3772 * ps_neg 3773 * ps_nmadd 3774 * ps_nmsub 3775 * ps_res 3776 * ps_rsqrte 3777 * ps_sel 3778 * ps_sub 3779 * ps_sum0 3780 * ps_sum1 3781 */ 3782 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3783 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3784 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3785 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3786 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3787 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3788 PPC_SEGMENT | PPC_EXTERN; 3789 pcc->msr_mask = (1ull << MSR_POW) | 3790 (1ull << MSR_ILE) | 3791 (1ull << MSR_EE) | 3792 (1ull << MSR_PR) | 3793 (1ull << MSR_FP) | 3794 (1ull << MSR_ME) | 3795 (1ull << MSR_FE0) | 3796 (1ull << MSR_SE) | 3797 (1ull << MSR_DE) | 3798 (1ull << MSR_FE1) | 3799 (1ull << MSR_EP) | 3800 (1ull << MSR_IR) | 3801 (1ull << MSR_DR) | 3802 (1ull << MSR_PMM) | 3803 (1ull << MSR_RI) | 3804 (1ull << MSR_LE); 3805 pcc->mmu_model = POWERPC_MMU_32B; 3806 pcc->excp_model = POWERPC_EXCP_7xx; 3807 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3808 pcc->bfd_mach = bfd_mach_ppc_750; 3809 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3810 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3811 } 3812 3813 static void init_proc_750cx(CPUPPCState *env) 3814 { 3815 register_non_embedded_sprs(env); 3816 register_sdr1_sprs(env); 3817 register_7xx_sprs(env); 3818 3819 spr_register(env, SPR_L2CR, "L2CR", 3820 SPR_NOACCESS, SPR_NOACCESS, 3821 &spr_read_generic, spr_access_nop, 3822 0x00000000); 3823 /* Thermal management */ 3824 register_thrm_sprs(env); 3825 3826 spr_register(env, SPR_SDA, "SDA", 3827 SPR_NOACCESS, SPR_NOACCESS, 3828 &spr_read_generic, &spr_write_generic, 3829 0x00000000); 3830 3831 /* Memory management */ 3832 register_low_BATs(env); 3833 /* PowerPC 750cx has 8 DBATs and 8 IBATs */ 3834 register_high_BATs(env); 3835 init_excp_750cx(env); 3836 env->dcache_line_size = 32; 3837 env->icache_line_size = 32; 3838 /* Allocate hardware IRQ controller */ 3839 ppc6xx_irq_init(env_archcpu(env)); 3840 } 3841 3842 POWERPC_FAMILY(750cx)(ObjectClass *oc, const void *data) 3843 { 3844 DeviceClass *dc = DEVICE_CLASS(oc); 3845 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3846 3847 dc->desc = "PowerPC 750CX"; 3848 pcc->init_proc = init_proc_750cx; 3849 pcc->check_pow = check_pow_hid0; 3850 pcc->check_attn = check_attn_none; 3851 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3852 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3853 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3854 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3855 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3856 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3857 PPC_SEGMENT | PPC_EXTERN; 3858 pcc->msr_mask = (1ull << MSR_POW) | 3859 (1ull << MSR_ILE) | 3860 (1ull << MSR_EE) | 3861 (1ull << MSR_PR) | 3862 (1ull << MSR_FP) | 3863 (1ull << MSR_ME) | 3864 (1ull << MSR_FE0) | 3865 (1ull << MSR_SE) | 3866 (1ull << MSR_DE) | 3867 (1ull << MSR_FE1) | 3868 (1ull << MSR_EP) | 3869 (1ull << MSR_IR) | 3870 (1ull << MSR_DR) | 3871 (1ull << MSR_PMM) | 3872 (1ull << MSR_RI) | 3873 (1ull << MSR_LE); 3874 pcc->mmu_model = POWERPC_MMU_32B; 3875 pcc->excp_model = POWERPC_EXCP_7xx; 3876 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3877 pcc->bfd_mach = bfd_mach_ppc_750; 3878 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3879 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3880 } 3881 3882 static void init_proc_750fx(CPUPPCState *env) 3883 { 3884 register_non_embedded_sprs(env); 3885 register_sdr1_sprs(env); 3886 register_7xx_sprs(env); 3887 3888 spr_register(env, SPR_L2CR, "L2CR", 3889 SPR_NOACCESS, SPR_NOACCESS, 3890 &spr_read_generic, spr_access_nop, 3891 0x00000000); 3892 /* Thermal management */ 3893 register_thrm_sprs(env); 3894 3895 spr_register(env, SPR_750_THRM4, "THRM4", 3896 SPR_NOACCESS, SPR_NOACCESS, 3897 &spr_read_generic, &spr_write_generic, 3898 0x00000000); 3899 /* Hardware implementation registers */ 3900 spr_register(env, SPR_750FX_HID2, "HID2", 3901 SPR_NOACCESS, SPR_NOACCESS, 3902 &spr_read_generic, &spr_write_generic, 3903 0x00000000); 3904 /* Memory management */ 3905 register_low_BATs(env); 3906 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 3907 register_high_BATs(env); 3908 init_excp_7x0(env); 3909 env->dcache_line_size = 32; 3910 env->icache_line_size = 32; 3911 /* Allocate hardware IRQ controller */ 3912 ppc6xx_irq_init(env_archcpu(env)); 3913 } 3914 3915 POWERPC_FAMILY(750fx)(ObjectClass *oc, const void *data) 3916 { 3917 DeviceClass *dc = DEVICE_CLASS(oc); 3918 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3919 3920 dc->desc = "PowerPC 750FX"; 3921 pcc->init_proc = init_proc_750fx; 3922 pcc->check_pow = check_pow_hid0; 3923 pcc->check_attn = check_attn_none; 3924 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3925 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3926 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3927 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3928 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3929 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3930 PPC_SEGMENT | PPC_EXTERN; 3931 pcc->msr_mask = (1ull << MSR_POW) | 3932 (1ull << MSR_ILE) | 3933 (1ull << MSR_EE) | 3934 (1ull << MSR_PR) | 3935 (1ull << MSR_FP) | 3936 (1ull << MSR_ME) | 3937 (1ull << MSR_FE0) | 3938 (1ull << MSR_SE) | 3939 (1ull << MSR_DE) | 3940 (1ull << MSR_FE1) | 3941 (1ull << MSR_EP) | 3942 (1ull << MSR_IR) | 3943 (1ull << MSR_DR) | 3944 (1ull << MSR_PMM) | 3945 (1ull << MSR_RI) | 3946 (1ull << MSR_LE); 3947 pcc->mmu_model = POWERPC_MMU_32B; 3948 pcc->excp_model = POWERPC_EXCP_7xx; 3949 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3950 pcc->bfd_mach = bfd_mach_ppc_750; 3951 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3952 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3953 } 3954 3955 static void init_proc_750gx(CPUPPCState *env) 3956 { 3957 register_non_embedded_sprs(env); 3958 register_sdr1_sprs(env); 3959 register_7xx_sprs(env); 3960 3961 spr_register(env, SPR_L2CR, "L2CR", 3962 SPR_NOACCESS, SPR_NOACCESS, 3963 &spr_read_generic, spr_access_nop, 3964 0x00000000); 3965 /* Thermal management */ 3966 register_thrm_sprs(env); 3967 3968 spr_register(env, SPR_750_THRM4, "THRM4", 3969 SPR_NOACCESS, SPR_NOACCESS, 3970 &spr_read_generic, &spr_write_generic, 3971 0x00000000); 3972 /* Hardware implementation registers */ 3973 spr_register(env, SPR_750FX_HID2, "HID2", 3974 SPR_NOACCESS, SPR_NOACCESS, 3975 &spr_read_generic, &spr_write_generic, 3976 0x00000000); 3977 /* Memory management */ 3978 register_low_BATs(env); 3979 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 3980 register_high_BATs(env); 3981 init_excp_7x0(env); 3982 env->dcache_line_size = 32; 3983 env->icache_line_size = 32; 3984 /* Allocate hardware IRQ controller */ 3985 ppc6xx_irq_init(env_archcpu(env)); 3986 } 3987 3988 POWERPC_FAMILY(750gx)(ObjectClass *oc, const void *data) 3989 { 3990 DeviceClass *dc = DEVICE_CLASS(oc); 3991 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3992 3993 dc->desc = "PowerPC 750GX"; 3994 pcc->init_proc = init_proc_750gx; 3995 pcc->check_pow = check_pow_hid0; 3996 pcc->check_attn = check_attn_none; 3997 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3998 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3999 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4000 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4001 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4002 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4003 PPC_SEGMENT | PPC_EXTERN; 4004 pcc->msr_mask = (1ull << MSR_POW) | 4005 (1ull << MSR_ILE) | 4006 (1ull << MSR_EE) | 4007 (1ull << MSR_PR) | 4008 (1ull << MSR_FP) | 4009 (1ull << MSR_ME) | 4010 (1ull << MSR_FE0) | 4011 (1ull << MSR_SE) | 4012 (1ull << MSR_DE) | 4013 (1ull << MSR_FE1) | 4014 (1ull << MSR_EP) | 4015 (1ull << MSR_IR) | 4016 (1ull << MSR_DR) | 4017 (1ull << MSR_PMM) | 4018 (1ull << MSR_RI) | 4019 (1ull << MSR_LE); 4020 pcc->mmu_model = POWERPC_MMU_32B; 4021 pcc->excp_model = POWERPC_EXCP_7xx; 4022 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4023 pcc->bfd_mach = bfd_mach_ppc_750; 4024 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4025 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4026 } 4027 4028 static void init_proc_745(CPUPPCState *env) 4029 { 4030 register_non_embedded_sprs(env); 4031 register_sdr1_sprs(env); 4032 register_7xx_sprs(env); 4033 register_745_sprs(env); 4034 /* Thermal management */ 4035 register_thrm_sprs(env); 4036 4037 /* Memory management */ 4038 register_low_BATs(env); 4039 register_high_BATs(env); 4040 register_6xx_7xx_soft_tlb(env, 64, 2); 4041 init_excp_7x5(env); 4042 env->dcache_line_size = 32; 4043 env->icache_line_size = 32; 4044 /* Allocate hardware IRQ controller */ 4045 ppc6xx_irq_init(env_archcpu(env)); 4046 } 4047 4048 POWERPC_FAMILY(745)(ObjectClass *oc, const void *data) 4049 { 4050 DeviceClass *dc = DEVICE_CLASS(oc); 4051 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4052 4053 dc->desc = "PowerPC 745"; 4054 pcc->init_proc = init_proc_745; 4055 pcc->check_pow = check_pow_hid0; 4056 pcc->check_attn = check_attn_none; 4057 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4058 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4059 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4060 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4061 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4062 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4063 PPC_SEGMENT | PPC_EXTERN; 4064 pcc->msr_mask = (1ull << MSR_POW) | 4065 (1ull << MSR_ILE) | 4066 (1ull << MSR_EE) | 4067 (1ull << MSR_PR) | 4068 (1ull << MSR_FP) | 4069 (1ull << MSR_ME) | 4070 (1ull << MSR_FE0) | 4071 (1ull << MSR_SE) | 4072 (1ull << MSR_DE) | 4073 (1ull << MSR_FE1) | 4074 (1ull << MSR_EP) | 4075 (1ull << MSR_IR) | 4076 (1ull << MSR_DR) | 4077 (1ull << MSR_PMM) | 4078 (1ull << MSR_RI) | 4079 (1ull << MSR_LE); 4080 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4081 pcc->excp_model = POWERPC_EXCP_7xx; 4082 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4083 pcc->bfd_mach = bfd_mach_ppc_750; 4084 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4085 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4086 } 4087 4088 static void init_proc_755(CPUPPCState *env) 4089 { 4090 init_proc_745(env); 4091 register_755_sprs(env); 4092 } 4093 4094 POWERPC_FAMILY(755)(ObjectClass *oc, const void *data) 4095 { 4096 DeviceClass *dc = DEVICE_CLASS(oc); 4097 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4098 4099 dc->desc = "PowerPC 755"; 4100 pcc->init_proc = init_proc_755; 4101 pcc->check_pow = check_pow_hid0; 4102 pcc->check_attn = check_attn_none; 4103 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4104 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4105 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4106 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4107 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4108 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4109 PPC_SEGMENT | PPC_EXTERN; 4110 pcc->msr_mask = (1ull << MSR_POW) | 4111 (1ull << MSR_ILE) | 4112 (1ull << MSR_EE) | 4113 (1ull << MSR_PR) | 4114 (1ull << MSR_FP) | 4115 (1ull << MSR_ME) | 4116 (1ull << MSR_FE0) | 4117 (1ull << MSR_SE) | 4118 (1ull << MSR_DE) | 4119 (1ull << MSR_FE1) | 4120 (1ull << MSR_EP) | 4121 (1ull << MSR_IR) | 4122 (1ull << MSR_DR) | 4123 (1ull << MSR_PMM) | 4124 (1ull << MSR_RI) | 4125 (1ull << MSR_LE); 4126 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4127 pcc->excp_model = POWERPC_EXCP_7xx; 4128 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4129 pcc->bfd_mach = bfd_mach_ppc_750; 4130 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4131 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4132 } 4133 4134 static void init_proc_7400(CPUPPCState *env) 4135 { 4136 register_non_embedded_sprs(env); 4137 register_sdr1_sprs(env); 4138 register_74xx_sprs(env); 4139 vscr_init(env, 0x00010000); 4140 4141 spr_register(env, SPR_UBAMR, "UBAMR", 4142 &spr_read_ureg, SPR_NOACCESS, 4143 &spr_read_ureg, SPR_NOACCESS, 4144 0x00000000); 4145 4146 spr_register(env, SPR_MSSCR1, "MSSCR1", 4147 SPR_NOACCESS, SPR_NOACCESS, 4148 &spr_read_generic, &spr_write_generic, 4149 0x00000000); 4150 /* Thermal management */ 4151 register_thrm_sprs(env); 4152 /* Memory management */ 4153 register_low_BATs(env); 4154 init_excp_7400(env); 4155 env->dcache_line_size = 32; 4156 env->icache_line_size = 32; 4157 /* Allocate hardware IRQ controller */ 4158 ppc6xx_irq_init(env_archcpu(env)); 4159 } 4160 4161 POWERPC_FAMILY(7400)(ObjectClass *oc, const void *data) 4162 { 4163 DeviceClass *dc = DEVICE_CLASS(oc); 4164 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4165 4166 dc->desc = "PowerPC 7400 (aka G4)"; 4167 pcc->init_proc = init_proc_7400; 4168 pcc->check_pow = check_pow_hid0; 4169 pcc->check_attn = check_attn_none; 4170 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4171 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4172 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4173 PPC_FLOAT_STFIWX | 4174 PPC_CACHE | PPC_CACHE_ICBI | 4175 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4176 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4177 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4178 PPC_MEM_TLBIA | 4179 PPC_SEGMENT | PPC_EXTERN | 4180 PPC_ALTIVEC; 4181 pcc->msr_mask = (1ull << MSR_VR) | 4182 (1ull << MSR_POW) | 4183 (1ull << MSR_ILE) | 4184 (1ull << MSR_EE) | 4185 (1ull << MSR_PR) | 4186 (1ull << MSR_FP) | 4187 (1ull << MSR_ME) | 4188 (1ull << MSR_FE0) | 4189 (1ull << MSR_SE) | 4190 (1ull << MSR_DE) | 4191 (1ull << MSR_FE1) | 4192 (1ull << MSR_EP) | 4193 (1ull << MSR_IR) | 4194 (1ull << MSR_DR) | 4195 (1ull << MSR_PMM) | 4196 (1ull << MSR_RI) | 4197 (1ull << MSR_LE); 4198 pcc->mmu_model = POWERPC_MMU_32B; 4199 pcc->excp_model = POWERPC_EXCP_74xx; 4200 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4201 pcc->bfd_mach = bfd_mach_ppc_7400; 4202 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4203 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4204 POWERPC_FLAG_BUS_CLK; 4205 } 4206 4207 static void init_proc_7410(CPUPPCState *env) 4208 { 4209 register_non_embedded_sprs(env); 4210 register_sdr1_sprs(env); 4211 register_74xx_sprs(env); 4212 vscr_init(env, 0x00010000); 4213 4214 spr_register(env, SPR_UBAMR, "UBAMR", 4215 &spr_read_ureg, SPR_NOACCESS, 4216 &spr_read_ureg, SPR_NOACCESS, 4217 0x00000000); 4218 /* Thermal management */ 4219 register_thrm_sprs(env); 4220 /* L2PMCR */ 4221 4222 spr_register(env, SPR_L2PMCR, "L2PMCR", 4223 SPR_NOACCESS, SPR_NOACCESS, 4224 &spr_read_generic, &spr_write_generic, 4225 0x00000000); 4226 /* LDSTDB */ 4227 4228 spr_register(env, SPR_LDSTDB, "LDSTDB", 4229 SPR_NOACCESS, SPR_NOACCESS, 4230 &spr_read_generic, &spr_write_generic, 4231 0x00000000); 4232 /* Memory management */ 4233 register_low_BATs(env); 4234 init_excp_7400(env); 4235 env->dcache_line_size = 32; 4236 env->icache_line_size = 32; 4237 /* Allocate hardware IRQ controller */ 4238 ppc6xx_irq_init(env_archcpu(env)); 4239 } 4240 4241 POWERPC_FAMILY(7410)(ObjectClass *oc, const void *data) 4242 { 4243 DeviceClass *dc = DEVICE_CLASS(oc); 4244 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4245 4246 dc->desc = "PowerPC 7410 (aka G4)"; 4247 pcc->init_proc = init_proc_7410; 4248 pcc->check_pow = check_pow_hid0; 4249 pcc->check_attn = check_attn_none; 4250 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4251 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4252 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4253 PPC_FLOAT_STFIWX | 4254 PPC_CACHE | PPC_CACHE_ICBI | 4255 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4256 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4257 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4258 PPC_MEM_TLBIA | 4259 PPC_SEGMENT | PPC_EXTERN | 4260 PPC_ALTIVEC; 4261 pcc->msr_mask = (1ull << MSR_VR) | 4262 (1ull << MSR_POW) | 4263 (1ull << MSR_ILE) | 4264 (1ull << MSR_EE) | 4265 (1ull << MSR_PR) | 4266 (1ull << MSR_FP) | 4267 (1ull << MSR_ME) | 4268 (1ull << MSR_FE0) | 4269 (1ull << MSR_SE) | 4270 (1ull << MSR_DE) | 4271 (1ull << MSR_FE1) | 4272 (1ull << MSR_EP) | 4273 (1ull << MSR_IR) | 4274 (1ull << MSR_DR) | 4275 (1ull << MSR_PMM) | 4276 (1ull << MSR_RI) | 4277 (1ull << MSR_LE); 4278 pcc->mmu_model = POWERPC_MMU_32B; 4279 pcc->excp_model = POWERPC_EXCP_74xx; 4280 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4281 pcc->bfd_mach = bfd_mach_ppc_7400; 4282 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4283 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4284 POWERPC_FLAG_BUS_CLK; 4285 } 4286 4287 static void init_proc_7440(CPUPPCState *env) 4288 { 4289 register_non_embedded_sprs(env); 4290 register_sdr1_sprs(env); 4291 register_74xx_sprs(env); 4292 vscr_init(env, 0x00010000); 4293 4294 spr_register(env, SPR_UBAMR, "UBAMR", 4295 &spr_read_ureg, SPR_NOACCESS, 4296 &spr_read_ureg, SPR_NOACCESS, 4297 0x00000000); 4298 /* LDSTCR */ 4299 spr_register(env, SPR_LDSTCR, "LDSTCR", 4300 SPR_NOACCESS, SPR_NOACCESS, 4301 &spr_read_generic, &spr_write_generic, 4302 0x00000000); 4303 /* ICTRL */ 4304 spr_register(env, SPR_ICTRL, "ICTRL", 4305 SPR_NOACCESS, SPR_NOACCESS, 4306 &spr_read_generic, &spr_write_generic, 4307 0x00000000); 4308 /* MSSSR0 */ 4309 spr_register(env, SPR_MSSSR0, "MSSSR0", 4310 SPR_NOACCESS, SPR_NOACCESS, 4311 &spr_read_generic, &spr_write_generic, 4312 0x00000000); 4313 /* PMC */ 4314 spr_register(env, SPR_7XX_PMC5, "PMC5", 4315 SPR_NOACCESS, SPR_NOACCESS, 4316 &spr_read_generic, &spr_write_generic, 4317 0x00000000); 4318 4319 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4320 &spr_read_ureg, SPR_NOACCESS, 4321 &spr_read_ureg, SPR_NOACCESS, 4322 0x00000000); 4323 4324 spr_register(env, SPR_7XX_PMC6, "PMC6", 4325 SPR_NOACCESS, SPR_NOACCESS, 4326 &spr_read_generic, &spr_write_generic, 4327 0x00000000); 4328 4329 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4330 &spr_read_ureg, SPR_NOACCESS, 4331 &spr_read_ureg, SPR_NOACCESS, 4332 0x00000000); 4333 /* Memory management */ 4334 register_low_BATs(env); 4335 init_excp_7450(env); 4336 env->dcache_line_size = 32; 4337 env->icache_line_size = 32; 4338 /* Allocate hardware IRQ controller */ 4339 ppc6xx_irq_init(env_archcpu(env)); 4340 } 4341 4342 POWERPC_FAMILY(7440)(ObjectClass *oc, const void *data) 4343 { 4344 DeviceClass *dc = DEVICE_CLASS(oc); 4345 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4346 4347 dc->desc = "PowerPC 7440 (aka G4)"; 4348 pcc->init_proc = init_proc_7440; 4349 pcc->check_pow = check_pow_hid0_74xx; 4350 pcc->check_attn = check_attn_none; 4351 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4352 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4353 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4354 PPC_FLOAT_STFIWX | 4355 PPC_CACHE | PPC_CACHE_ICBI | 4356 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4357 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4358 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4359 PPC_MEM_TLBIA | 4360 PPC_SEGMENT | PPC_EXTERN | 4361 PPC_ALTIVEC; 4362 pcc->msr_mask = (1ull << MSR_VR) | 4363 (1ull << MSR_POW) | 4364 (1ull << MSR_ILE) | 4365 (1ull << MSR_EE) | 4366 (1ull << MSR_PR) | 4367 (1ull << MSR_FP) | 4368 (1ull << MSR_ME) | 4369 (1ull << MSR_FE0) | 4370 (1ull << MSR_SE) | 4371 (1ull << MSR_DE) | 4372 (1ull << MSR_FE1) | 4373 (1ull << MSR_EP) | 4374 (1ull << MSR_IR) | 4375 (1ull << MSR_DR) | 4376 (1ull << MSR_PMM) | 4377 (1ull << MSR_RI) | 4378 (1ull << MSR_LE); 4379 pcc->mmu_model = POWERPC_MMU_32B; 4380 pcc->excp_model = POWERPC_EXCP_74xx; 4381 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4382 pcc->bfd_mach = bfd_mach_ppc_7400; 4383 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4384 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4385 POWERPC_FLAG_BUS_CLK; 4386 } 4387 4388 static void init_proc_7450(CPUPPCState *env) 4389 { 4390 register_non_embedded_sprs(env); 4391 register_sdr1_sprs(env); 4392 register_74xx_sprs(env); 4393 vscr_init(env, 0x00010000); 4394 /* Level 3 cache control */ 4395 register_l3_ctrl(env); 4396 /* L3ITCR1 */ 4397 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 4398 SPR_NOACCESS, SPR_NOACCESS, 4399 &spr_read_generic, &spr_write_generic, 4400 0x00000000); 4401 /* L3ITCR2 */ 4402 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 4403 SPR_NOACCESS, SPR_NOACCESS, 4404 &spr_read_generic, &spr_write_generic, 4405 0x00000000); 4406 /* L3ITCR3 */ 4407 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 4408 SPR_NOACCESS, SPR_NOACCESS, 4409 &spr_read_generic, &spr_write_generic, 4410 0x00000000); 4411 /* L3OHCR */ 4412 spr_register(env, SPR_L3OHCR, "L3OHCR", 4413 SPR_NOACCESS, SPR_NOACCESS, 4414 &spr_read_generic, &spr_write_generic, 4415 0x00000000); 4416 4417 spr_register(env, SPR_UBAMR, "UBAMR", 4418 &spr_read_ureg, SPR_NOACCESS, 4419 &spr_read_ureg, SPR_NOACCESS, 4420 0x00000000); 4421 /* LDSTCR */ 4422 spr_register(env, SPR_LDSTCR, "LDSTCR", 4423 SPR_NOACCESS, SPR_NOACCESS, 4424 &spr_read_generic, &spr_write_generic, 4425 0x00000000); 4426 /* ICTRL */ 4427 spr_register(env, SPR_ICTRL, "ICTRL", 4428 SPR_NOACCESS, SPR_NOACCESS, 4429 &spr_read_generic, &spr_write_generic, 4430 0x00000000); 4431 /* MSSSR0 */ 4432 spr_register(env, SPR_MSSSR0, "MSSSR0", 4433 SPR_NOACCESS, SPR_NOACCESS, 4434 &spr_read_generic, &spr_write_generic, 4435 0x00000000); 4436 /* PMC */ 4437 spr_register(env, SPR_7XX_PMC5, "PMC5", 4438 SPR_NOACCESS, SPR_NOACCESS, 4439 &spr_read_generic, &spr_write_generic, 4440 0x00000000); 4441 4442 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4443 &spr_read_ureg, SPR_NOACCESS, 4444 &spr_read_ureg, SPR_NOACCESS, 4445 0x00000000); 4446 4447 spr_register(env, SPR_7XX_PMC6, "PMC6", 4448 SPR_NOACCESS, SPR_NOACCESS, 4449 &spr_read_generic, &spr_write_generic, 4450 0x00000000); 4451 4452 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4453 &spr_read_ureg, SPR_NOACCESS, 4454 &spr_read_ureg, SPR_NOACCESS, 4455 0x00000000); 4456 /* Memory management */ 4457 register_low_BATs(env); 4458 init_excp_7450(env); 4459 env->dcache_line_size = 32; 4460 env->icache_line_size = 32; 4461 /* Allocate hardware IRQ controller */ 4462 ppc6xx_irq_init(env_archcpu(env)); 4463 } 4464 4465 POWERPC_FAMILY(7450)(ObjectClass *oc, const void *data) 4466 { 4467 DeviceClass *dc = DEVICE_CLASS(oc); 4468 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4469 4470 dc->desc = "PowerPC 7450 (aka G4)"; 4471 pcc->init_proc = init_proc_7450; 4472 pcc->check_pow = check_pow_hid0_74xx; 4473 pcc->check_attn = check_attn_none; 4474 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4475 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4476 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4477 PPC_FLOAT_STFIWX | 4478 PPC_CACHE | PPC_CACHE_ICBI | 4479 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4480 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4481 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4482 PPC_MEM_TLBIA | 4483 PPC_SEGMENT | PPC_EXTERN | 4484 PPC_ALTIVEC; 4485 pcc->msr_mask = (1ull << MSR_VR) | 4486 (1ull << MSR_POW) | 4487 (1ull << MSR_ILE) | 4488 (1ull << MSR_EE) | 4489 (1ull << MSR_PR) | 4490 (1ull << MSR_FP) | 4491 (1ull << MSR_ME) | 4492 (1ull << MSR_FE0) | 4493 (1ull << MSR_SE) | 4494 (1ull << MSR_DE) | 4495 (1ull << MSR_FE1) | 4496 (1ull << MSR_EP) | 4497 (1ull << MSR_IR) | 4498 (1ull << MSR_DR) | 4499 (1ull << MSR_PMM) | 4500 (1ull << MSR_RI) | 4501 (1ull << MSR_LE); 4502 pcc->mmu_model = POWERPC_MMU_32B; 4503 pcc->excp_model = POWERPC_EXCP_74xx; 4504 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4505 pcc->bfd_mach = bfd_mach_ppc_7400; 4506 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4507 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4508 POWERPC_FLAG_BUS_CLK; 4509 } 4510 4511 static void init_proc_7445(CPUPPCState *env) 4512 { 4513 register_non_embedded_sprs(env); 4514 register_sdr1_sprs(env); 4515 register_74xx_sprs(env); 4516 vscr_init(env, 0x00010000); 4517 /* LDSTCR */ 4518 spr_register(env, SPR_LDSTCR, "LDSTCR", 4519 SPR_NOACCESS, SPR_NOACCESS, 4520 &spr_read_generic, &spr_write_generic, 4521 0x00000000); 4522 /* ICTRL */ 4523 spr_register(env, SPR_ICTRL, "ICTRL", 4524 SPR_NOACCESS, SPR_NOACCESS, 4525 &spr_read_generic, &spr_write_generic, 4526 0x00000000); 4527 /* MSSSR0 */ 4528 spr_register(env, SPR_MSSSR0, "MSSSR0", 4529 SPR_NOACCESS, SPR_NOACCESS, 4530 &spr_read_generic, &spr_write_generic, 4531 0x00000000); 4532 /* PMC */ 4533 spr_register(env, SPR_7XX_PMC5, "PMC5", 4534 SPR_NOACCESS, SPR_NOACCESS, 4535 &spr_read_generic, &spr_write_generic, 4536 0x00000000); 4537 4538 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4539 &spr_read_ureg, SPR_NOACCESS, 4540 &spr_read_ureg, SPR_NOACCESS, 4541 0x00000000); 4542 4543 spr_register(env, SPR_7XX_PMC6, "PMC6", 4544 SPR_NOACCESS, SPR_NOACCESS, 4545 &spr_read_generic, &spr_write_generic, 4546 0x00000000); 4547 4548 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4549 &spr_read_ureg, SPR_NOACCESS, 4550 &spr_read_ureg, SPR_NOACCESS, 4551 0x00000000); 4552 /* SPRGs */ 4553 spr_register(env, SPR_SPRG4, "SPRG4", 4554 SPR_NOACCESS, SPR_NOACCESS, 4555 &spr_read_generic, &spr_write_generic, 4556 0x00000000); 4557 spr_register(env, SPR_USPRG4, "USPRG4", 4558 &spr_read_ureg, SPR_NOACCESS, 4559 &spr_read_ureg, SPR_NOACCESS, 4560 0x00000000); 4561 spr_register(env, SPR_SPRG5, "SPRG5", 4562 SPR_NOACCESS, SPR_NOACCESS, 4563 &spr_read_generic, &spr_write_generic, 4564 0x00000000); 4565 spr_register(env, SPR_USPRG5, "USPRG5", 4566 &spr_read_ureg, SPR_NOACCESS, 4567 &spr_read_ureg, SPR_NOACCESS, 4568 0x00000000); 4569 spr_register(env, SPR_SPRG6, "SPRG6", 4570 SPR_NOACCESS, SPR_NOACCESS, 4571 &spr_read_generic, &spr_write_generic, 4572 0x00000000); 4573 spr_register(env, SPR_USPRG6, "USPRG6", 4574 &spr_read_ureg, SPR_NOACCESS, 4575 &spr_read_ureg, SPR_NOACCESS, 4576 0x00000000); 4577 spr_register(env, SPR_SPRG7, "SPRG7", 4578 SPR_NOACCESS, SPR_NOACCESS, 4579 &spr_read_generic, &spr_write_generic, 4580 0x00000000); 4581 spr_register(env, SPR_USPRG7, "USPRG7", 4582 &spr_read_ureg, SPR_NOACCESS, 4583 &spr_read_ureg, SPR_NOACCESS, 4584 0x00000000); 4585 /* Memory management */ 4586 register_low_BATs(env); 4587 register_high_BATs(env); 4588 init_excp_7450(env); 4589 env->dcache_line_size = 32; 4590 env->icache_line_size = 32; 4591 /* Allocate hardware IRQ controller */ 4592 ppc6xx_irq_init(env_archcpu(env)); 4593 } 4594 4595 POWERPC_FAMILY(7445)(ObjectClass *oc, const void *data) 4596 { 4597 DeviceClass *dc = DEVICE_CLASS(oc); 4598 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4599 4600 dc->desc = "PowerPC 7445 (aka G4)"; 4601 pcc->init_proc = init_proc_7445; 4602 pcc->check_pow = check_pow_hid0_74xx; 4603 pcc->check_attn = check_attn_none; 4604 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4605 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4606 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4607 PPC_FLOAT_STFIWX | 4608 PPC_CACHE | PPC_CACHE_ICBI | 4609 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4610 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4611 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4612 PPC_MEM_TLBIA | 4613 PPC_SEGMENT | PPC_EXTERN | 4614 PPC_ALTIVEC; 4615 pcc->msr_mask = (1ull << MSR_VR) | 4616 (1ull << MSR_POW) | 4617 (1ull << MSR_ILE) | 4618 (1ull << MSR_EE) | 4619 (1ull << MSR_PR) | 4620 (1ull << MSR_FP) | 4621 (1ull << MSR_ME) | 4622 (1ull << MSR_FE0) | 4623 (1ull << MSR_SE) | 4624 (1ull << MSR_DE) | 4625 (1ull << MSR_FE1) | 4626 (1ull << MSR_EP) | 4627 (1ull << MSR_IR) | 4628 (1ull << MSR_DR) | 4629 (1ull << MSR_PMM) | 4630 (1ull << MSR_RI) | 4631 (1ull << MSR_LE); 4632 pcc->mmu_model = POWERPC_MMU_32B; 4633 pcc->excp_model = POWERPC_EXCP_74xx; 4634 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4635 pcc->bfd_mach = bfd_mach_ppc_7400; 4636 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4637 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4638 POWERPC_FLAG_BUS_CLK; 4639 } 4640 4641 static void init_proc_7455(CPUPPCState *env) 4642 { 4643 register_non_embedded_sprs(env); 4644 register_sdr1_sprs(env); 4645 register_74xx_sprs(env); 4646 vscr_init(env, 0x00010000); 4647 /* Level 3 cache control */ 4648 register_l3_ctrl(env); 4649 /* LDSTCR */ 4650 spr_register(env, SPR_LDSTCR, "LDSTCR", 4651 SPR_NOACCESS, SPR_NOACCESS, 4652 &spr_read_generic, &spr_write_generic, 4653 0x00000000); 4654 /* ICTRL */ 4655 spr_register(env, SPR_ICTRL, "ICTRL", 4656 SPR_NOACCESS, SPR_NOACCESS, 4657 &spr_read_generic, &spr_write_generic, 4658 0x00000000); 4659 /* MSSSR0 */ 4660 spr_register(env, SPR_MSSSR0, "MSSSR0", 4661 SPR_NOACCESS, SPR_NOACCESS, 4662 &spr_read_generic, &spr_write_generic, 4663 0x00000000); 4664 /* PMC */ 4665 spr_register(env, SPR_7XX_PMC5, "PMC5", 4666 SPR_NOACCESS, SPR_NOACCESS, 4667 &spr_read_generic, &spr_write_generic, 4668 0x00000000); 4669 4670 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4671 &spr_read_ureg, SPR_NOACCESS, 4672 &spr_read_ureg, SPR_NOACCESS, 4673 0x00000000); 4674 4675 spr_register(env, SPR_7XX_PMC6, "PMC6", 4676 SPR_NOACCESS, SPR_NOACCESS, 4677 &spr_read_generic, &spr_write_generic, 4678 0x00000000); 4679 4680 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4681 &spr_read_ureg, SPR_NOACCESS, 4682 &spr_read_ureg, SPR_NOACCESS, 4683 0x00000000); 4684 /* SPRGs */ 4685 spr_register(env, SPR_SPRG4, "SPRG4", 4686 SPR_NOACCESS, SPR_NOACCESS, 4687 &spr_read_generic, &spr_write_generic, 4688 0x00000000); 4689 spr_register(env, SPR_USPRG4, "USPRG4", 4690 &spr_read_ureg, SPR_NOACCESS, 4691 &spr_read_ureg, SPR_NOACCESS, 4692 0x00000000); 4693 spr_register(env, SPR_SPRG5, "SPRG5", 4694 SPR_NOACCESS, SPR_NOACCESS, 4695 &spr_read_generic, &spr_write_generic, 4696 0x00000000); 4697 spr_register(env, SPR_USPRG5, "USPRG5", 4698 &spr_read_ureg, SPR_NOACCESS, 4699 &spr_read_ureg, SPR_NOACCESS, 4700 0x00000000); 4701 spr_register(env, SPR_SPRG6, "SPRG6", 4702 SPR_NOACCESS, SPR_NOACCESS, 4703 &spr_read_generic, &spr_write_generic, 4704 0x00000000); 4705 spr_register(env, SPR_USPRG6, "USPRG6", 4706 &spr_read_ureg, SPR_NOACCESS, 4707 &spr_read_ureg, SPR_NOACCESS, 4708 0x00000000); 4709 spr_register(env, SPR_SPRG7, "SPRG7", 4710 SPR_NOACCESS, SPR_NOACCESS, 4711 &spr_read_generic, &spr_write_generic, 4712 0x00000000); 4713 spr_register(env, SPR_USPRG7, "USPRG7", 4714 &spr_read_ureg, SPR_NOACCESS, 4715 &spr_read_ureg, SPR_NOACCESS, 4716 0x00000000); 4717 /* Memory management */ 4718 register_low_BATs(env); 4719 register_high_BATs(env); 4720 init_excp_7450(env); 4721 env->dcache_line_size = 32; 4722 env->icache_line_size = 32; 4723 /* Allocate hardware IRQ controller */ 4724 ppc6xx_irq_init(env_archcpu(env)); 4725 } 4726 4727 POWERPC_FAMILY(7455)(ObjectClass *oc, const void *data) 4728 { 4729 DeviceClass *dc = DEVICE_CLASS(oc); 4730 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4731 4732 dc->desc = "PowerPC 7455 (aka G4)"; 4733 pcc->init_proc = init_proc_7455; 4734 pcc->check_pow = check_pow_hid0_74xx; 4735 pcc->check_attn = check_attn_none; 4736 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4737 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4738 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4739 PPC_FLOAT_STFIWX | 4740 PPC_CACHE | PPC_CACHE_ICBI | 4741 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4742 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4743 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4744 PPC_MEM_TLBIA | 4745 PPC_SEGMENT | PPC_EXTERN | 4746 PPC_ALTIVEC; 4747 pcc->msr_mask = (1ull << MSR_VR) | 4748 (1ull << MSR_POW) | 4749 (1ull << MSR_ILE) | 4750 (1ull << MSR_EE) | 4751 (1ull << MSR_PR) | 4752 (1ull << MSR_FP) | 4753 (1ull << MSR_ME) | 4754 (1ull << MSR_FE0) | 4755 (1ull << MSR_SE) | 4756 (1ull << MSR_DE) | 4757 (1ull << MSR_FE1) | 4758 (1ull << MSR_EP) | 4759 (1ull << MSR_IR) | 4760 (1ull << MSR_DR) | 4761 (1ull << MSR_PMM) | 4762 (1ull << MSR_RI) | 4763 (1ull << MSR_LE); 4764 pcc->mmu_model = POWERPC_MMU_32B; 4765 pcc->excp_model = POWERPC_EXCP_74xx; 4766 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4767 pcc->bfd_mach = bfd_mach_ppc_7400; 4768 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4769 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4770 POWERPC_FLAG_BUS_CLK; 4771 } 4772 4773 static void init_proc_7457(CPUPPCState *env) 4774 { 4775 register_non_embedded_sprs(env); 4776 register_sdr1_sprs(env); 4777 register_74xx_sprs(env); 4778 vscr_init(env, 0x00010000); 4779 /* Level 3 cache control */ 4780 register_l3_ctrl(env); 4781 /* L3ITCR1 */ 4782 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 4783 SPR_NOACCESS, SPR_NOACCESS, 4784 &spr_read_generic, &spr_write_generic, 4785 0x00000000); 4786 /* L3ITCR2 */ 4787 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 4788 SPR_NOACCESS, SPR_NOACCESS, 4789 &spr_read_generic, &spr_write_generic, 4790 0x00000000); 4791 /* L3ITCR3 */ 4792 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 4793 SPR_NOACCESS, SPR_NOACCESS, 4794 &spr_read_generic, &spr_write_generic, 4795 0x00000000); 4796 /* L3OHCR */ 4797 spr_register(env, SPR_L3OHCR, "L3OHCR", 4798 SPR_NOACCESS, SPR_NOACCESS, 4799 &spr_read_generic, &spr_write_generic, 4800 0x00000000); 4801 /* LDSTCR */ 4802 spr_register(env, SPR_LDSTCR, "LDSTCR", 4803 SPR_NOACCESS, SPR_NOACCESS, 4804 &spr_read_generic, &spr_write_generic, 4805 0x00000000); 4806 /* ICTRL */ 4807 spr_register(env, SPR_ICTRL, "ICTRL", 4808 SPR_NOACCESS, SPR_NOACCESS, 4809 &spr_read_generic, &spr_write_generic, 4810 0x00000000); 4811 /* MSSSR0 */ 4812 spr_register(env, SPR_MSSSR0, "MSSSR0", 4813 SPR_NOACCESS, SPR_NOACCESS, 4814 &spr_read_generic, &spr_write_generic, 4815 0x00000000); 4816 /* PMC */ 4817 spr_register(env, SPR_7XX_PMC5, "PMC5", 4818 SPR_NOACCESS, SPR_NOACCESS, 4819 &spr_read_generic, &spr_write_generic, 4820 0x00000000); 4821 4822 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4823 &spr_read_ureg, SPR_NOACCESS, 4824 &spr_read_ureg, SPR_NOACCESS, 4825 0x00000000); 4826 4827 spr_register(env, SPR_7XX_PMC6, "PMC6", 4828 SPR_NOACCESS, SPR_NOACCESS, 4829 &spr_read_generic, &spr_write_generic, 4830 0x00000000); 4831 4832 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4833 &spr_read_ureg, SPR_NOACCESS, 4834 &spr_read_ureg, SPR_NOACCESS, 4835 0x00000000); 4836 /* SPRGs */ 4837 spr_register(env, SPR_SPRG4, "SPRG4", 4838 SPR_NOACCESS, SPR_NOACCESS, 4839 &spr_read_generic, &spr_write_generic, 4840 0x00000000); 4841 spr_register(env, SPR_USPRG4, "USPRG4", 4842 &spr_read_ureg, SPR_NOACCESS, 4843 &spr_read_ureg, SPR_NOACCESS, 4844 0x00000000); 4845 spr_register(env, SPR_SPRG5, "SPRG5", 4846 SPR_NOACCESS, SPR_NOACCESS, 4847 &spr_read_generic, &spr_write_generic, 4848 0x00000000); 4849 spr_register(env, SPR_USPRG5, "USPRG5", 4850 &spr_read_ureg, SPR_NOACCESS, 4851 &spr_read_ureg, SPR_NOACCESS, 4852 0x00000000); 4853 spr_register(env, SPR_SPRG6, "SPRG6", 4854 SPR_NOACCESS, SPR_NOACCESS, 4855 &spr_read_generic, &spr_write_generic, 4856 0x00000000); 4857 spr_register(env, SPR_USPRG6, "USPRG6", 4858 &spr_read_ureg, SPR_NOACCESS, 4859 &spr_read_ureg, SPR_NOACCESS, 4860 0x00000000); 4861 spr_register(env, SPR_SPRG7, "SPRG7", 4862 SPR_NOACCESS, SPR_NOACCESS, 4863 &spr_read_generic, &spr_write_generic, 4864 0x00000000); 4865 spr_register(env, SPR_USPRG7, "USPRG7", 4866 &spr_read_ureg, SPR_NOACCESS, 4867 &spr_read_ureg, SPR_NOACCESS, 4868 0x00000000); 4869 /* Memory management */ 4870 register_low_BATs(env); 4871 register_high_BATs(env); 4872 init_excp_7450(env); 4873 env->dcache_line_size = 32; 4874 env->icache_line_size = 32; 4875 /* Allocate hardware IRQ controller */ 4876 ppc6xx_irq_init(env_archcpu(env)); 4877 } 4878 4879 POWERPC_FAMILY(7457)(ObjectClass *oc, const void *data) 4880 { 4881 DeviceClass *dc = DEVICE_CLASS(oc); 4882 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4883 4884 dc->desc = "PowerPC 7457 (aka G4)"; 4885 pcc->init_proc = init_proc_7457; 4886 pcc->check_pow = check_pow_hid0_74xx; 4887 pcc->check_attn = check_attn_none; 4888 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4889 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4890 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4891 PPC_FLOAT_STFIWX | 4892 PPC_CACHE | PPC_CACHE_ICBI | 4893 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4894 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4895 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4896 PPC_MEM_TLBIA | 4897 PPC_SEGMENT | PPC_EXTERN | 4898 PPC_ALTIVEC; 4899 pcc->msr_mask = (1ull << MSR_VR) | 4900 (1ull << MSR_POW) | 4901 (1ull << MSR_ILE) | 4902 (1ull << MSR_EE) | 4903 (1ull << MSR_PR) | 4904 (1ull << MSR_FP) | 4905 (1ull << MSR_ME) | 4906 (1ull << MSR_FE0) | 4907 (1ull << MSR_SE) | 4908 (1ull << MSR_DE) | 4909 (1ull << MSR_FE1) | 4910 (1ull << MSR_EP) | 4911 (1ull << MSR_IR) | 4912 (1ull << MSR_DR) | 4913 (1ull << MSR_PMM) | 4914 (1ull << MSR_RI) | 4915 (1ull << MSR_LE); 4916 pcc->mmu_model = POWERPC_MMU_32B; 4917 pcc->excp_model = POWERPC_EXCP_74xx; 4918 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4919 pcc->bfd_mach = bfd_mach_ppc_7400; 4920 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4921 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4922 POWERPC_FLAG_BUS_CLK; 4923 } 4924 4925 static void init_proc_e600(CPUPPCState *env) 4926 { 4927 register_non_embedded_sprs(env); 4928 register_sdr1_sprs(env); 4929 register_74xx_sprs(env); 4930 vscr_init(env, 0x00010000); 4931 4932 spr_register(env, SPR_UBAMR, "UBAMR", 4933 &spr_read_ureg, SPR_NOACCESS, 4934 &spr_read_ureg, SPR_NOACCESS, 4935 0x00000000); 4936 4937 spr_register(env, SPR_LDSTCR, "LDSTCR", 4938 SPR_NOACCESS, SPR_NOACCESS, 4939 &spr_read_generic, &spr_write_generic, 4940 0x00000000); 4941 4942 spr_register(env, SPR_ICTRL, "ICTRL", 4943 SPR_NOACCESS, SPR_NOACCESS, 4944 &spr_read_generic, &spr_write_generic, 4945 0x00000000); 4946 4947 spr_register(env, SPR_MSSSR0, "MSSSR0", 4948 SPR_NOACCESS, SPR_NOACCESS, 4949 &spr_read_generic, &spr_write_generic, 4950 0x00000000); 4951 4952 spr_register(env, SPR_7XX_PMC5, "PMC5", 4953 SPR_NOACCESS, SPR_NOACCESS, 4954 &spr_read_generic, &spr_write_generic, 4955 0x00000000); 4956 4957 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4958 &spr_read_ureg, SPR_NOACCESS, 4959 &spr_read_ureg, SPR_NOACCESS, 4960 0x00000000); 4961 4962 spr_register(env, SPR_7XX_PMC6, "PMC6", 4963 SPR_NOACCESS, SPR_NOACCESS, 4964 &spr_read_generic, &spr_write_generic, 4965 0x00000000); 4966 4967 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4968 &spr_read_ureg, SPR_NOACCESS, 4969 &spr_read_ureg, SPR_NOACCESS, 4970 0x00000000); 4971 /* SPRGs */ 4972 spr_register(env, SPR_SPRG4, "SPRG4", 4973 SPR_NOACCESS, SPR_NOACCESS, 4974 &spr_read_generic, &spr_write_generic, 4975 0x00000000); 4976 spr_register(env, SPR_USPRG4, "USPRG4", 4977 &spr_read_ureg, SPR_NOACCESS, 4978 &spr_read_ureg, SPR_NOACCESS, 4979 0x00000000); 4980 spr_register(env, SPR_SPRG5, "SPRG5", 4981 SPR_NOACCESS, SPR_NOACCESS, 4982 &spr_read_generic, &spr_write_generic, 4983 0x00000000); 4984 spr_register(env, SPR_USPRG5, "USPRG5", 4985 &spr_read_ureg, SPR_NOACCESS, 4986 &spr_read_ureg, SPR_NOACCESS, 4987 0x00000000); 4988 spr_register(env, SPR_SPRG6, "SPRG6", 4989 SPR_NOACCESS, SPR_NOACCESS, 4990 &spr_read_generic, &spr_write_generic, 4991 0x00000000); 4992 spr_register(env, SPR_USPRG6, "USPRG6", 4993 &spr_read_ureg, SPR_NOACCESS, 4994 &spr_read_ureg, SPR_NOACCESS, 4995 0x00000000); 4996 spr_register(env, SPR_SPRG7, "SPRG7", 4997 SPR_NOACCESS, SPR_NOACCESS, 4998 &spr_read_generic, &spr_write_generic, 4999 0x00000000); 5000 spr_register(env, SPR_USPRG7, "USPRG7", 5001 &spr_read_ureg, SPR_NOACCESS, 5002 &spr_read_ureg, SPR_NOACCESS, 5003 0x00000000); 5004 /* Memory management */ 5005 register_low_BATs(env); 5006 register_high_BATs(env); 5007 init_excp_7450(env); 5008 env->dcache_line_size = 32; 5009 env->icache_line_size = 32; 5010 /* Allocate hardware IRQ controller */ 5011 ppc6xx_irq_init(env_archcpu(env)); 5012 } 5013 5014 POWERPC_FAMILY(e600)(ObjectClass *oc, const void *data) 5015 { 5016 DeviceClass *dc = DEVICE_CLASS(oc); 5017 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5018 5019 dc->desc = "PowerPC e600"; 5020 pcc->init_proc = init_proc_e600; 5021 pcc->check_pow = check_pow_hid0_74xx; 5022 pcc->check_attn = check_attn_none; 5023 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5024 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5025 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5026 PPC_FLOAT_STFIWX | 5027 PPC_CACHE | PPC_CACHE_ICBI | 5028 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5029 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5030 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5031 PPC_MEM_TLBIA | 5032 PPC_SEGMENT | PPC_EXTERN | 5033 PPC_ALTIVEC; 5034 pcc->insns_flags2 = PPC_NONE; 5035 pcc->msr_mask = (1ull << MSR_VR) | 5036 (1ull << MSR_POW) | 5037 (1ull << MSR_ILE) | 5038 (1ull << MSR_EE) | 5039 (1ull << MSR_PR) | 5040 (1ull << MSR_FP) | 5041 (1ull << MSR_ME) | 5042 (1ull << MSR_FE0) | 5043 (1ull << MSR_SE) | 5044 (1ull << MSR_DE) | 5045 (1ull << MSR_FE1) | 5046 (1ull << MSR_EP) | 5047 (1ull << MSR_IR) | 5048 (1ull << MSR_DR) | 5049 (1ull << MSR_PMM) | 5050 (1ull << MSR_RI) | 5051 (1ull << MSR_LE); 5052 pcc->mmu_model = POWERPC_MMU_32B; 5053 pcc->excp_model = POWERPC_EXCP_74xx; 5054 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5055 pcc->bfd_mach = bfd_mach_ppc_7400; 5056 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5057 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5058 POWERPC_FLAG_BUS_CLK; 5059 } 5060 5061 #if defined(TARGET_PPC64) 5062 #if defined(CONFIG_USER_ONLY) 5063 #define POWERPC970_HID5_INIT 0x00000080 5064 #else 5065 #define POWERPC970_HID5_INIT 0x00000000 5066 #endif 5067 5068 static int check_pow_970(CPUPPCState *env) 5069 { 5070 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) { 5071 return 1; 5072 } 5073 5074 return 0; 5075 } 5076 5077 static void register_970_hid_sprs(CPUPPCState *env) 5078 { 5079 /* Hardware implementation registers */ 5080 spr_register(env, SPR_HID0, "HID0", 5081 SPR_NOACCESS, SPR_NOACCESS, 5082 &spr_read_generic, &spr_write_clear, 5083 0x60000000); 5084 spr_register(env, SPR_HID1, "HID1", 5085 SPR_NOACCESS, SPR_NOACCESS, 5086 &spr_read_generic, &spr_write_generic, 5087 0x00000000); 5088 spr_register(env, SPR_970_HID5, "HID5", 5089 SPR_NOACCESS, SPR_NOACCESS, 5090 &spr_read_generic, &spr_write_generic, 5091 POWERPC970_HID5_INIT); 5092 } 5093 5094 static void register_970_hior_sprs(CPUPPCState *env) 5095 { 5096 spr_register(env, SPR_HIOR, "HIOR", 5097 SPR_NOACCESS, SPR_NOACCESS, 5098 &spr_read_hior, &spr_write_hior, 5099 0x00000000); 5100 } 5101 5102 static void register_book3s_ctrl_sprs(CPUPPCState *env) 5103 { 5104 spr_register(env, SPR_CTRL, "CTRL", 5105 SPR_NOACCESS, SPR_NOACCESS, 5106 SPR_NOACCESS, &spr_write_CTRL, 5107 0x00000000); 5108 spr_register(env, SPR_UCTRL, "UCTRL", 5109 &spr_read_ureg, SPR_NOACCESS, 5110 &spr_read_ureg, SPR_NOACCESS, 5111 0x00000000); 5112 } 5113 5114 static void register_book3s_altivec_sprs(CPUPPCState *env) 5115 { 5116 if (!(env->insns_flags & PPC_ALTIVEC)) { 5117 return; 5118 } 5119 5120 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE", 5121 &spr_read_generic, &spr_write_generic32, 5122 &spr_read_generic, &spr_write_generic32, 5123 KVM_REG_PPC_VRSAVE, 0x00000000); 5124 5125 } 5126 5127 static void register_book3s_dbg_sprs(CPUPPCState *env) 5128 { 5129 /* 5130 * TODO: different specs define different scopes for these, 5131 * will have to address this: 5132 * 970: super/write and super/read 5133 * powerisa 2.03..2.04: hypv/write and super/read. 5134 * powerisa 2.05 and newer: hypv/write and hypv/read. 5135 */ 5136 spr_register_kvm(env, SPR_DABR, "DABR", 5137 SPR_NOACCESS, SPR_NOACCESS, 5138 &spr_read_generic, &spr_write_generic, 5139 KVM_REG_PPC_DABR, 0x00000000); 5140 spr_register_kvm(env, SPR_DABRX, "DABRX", 5141 SPR_NOACCESS, SPR_NOACCESS, 5142 &spr_read_generic, &spr_write_generic, 5143 KVM_REG_PPC_DABRX, 0x00000000); 5144 } 5145 5146 static void register_book3s_207_dbg_sprs(CPUPPCState *env) 5147 { 5148 spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0", 5149 SPR_NOACCESS, SPR_NOACCESS, 5150 SPR_NOACCESS, SPR_NOACCESS, 5151 &spr_read_generic, &spr_write_dawr0, 5152 KVM_REG_PPC_DAWR, 0x00000000); 5153 spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0", 5154 SPR_NOACCESS, SPR_NOACCESS, 5155 SPR_NOACCESS, SPR_NOACCESS, 5156 &spr_read_generic, &spr_write_dawrx0, 5157 KVM_REG_PPC_DAWRX, 0x00000000); 5158 spr_register_kvm_hv(env, SPR_CIABR, "CIABR", 5159 SPR_NOACCESS, SPR_NOACCESS, 5160 SPR_NOACCESS, SPR_NOACCESS, 5161 &spr_read_generic, &spr_write_ciabr, 5162 KVM_REG_PPC_CIABR, 0x00000000); 5163 } 5164 5165 static void register_book3s_310_dbg_sprs(CPUPPCState *env) 5166 { 5167 spr_register_kvm_hv(env, SPR_DAWR1, "DAWR1", 5168 SPR_NOACCESS, SPR_NOACCESS, 5169 SPR_NOACCESS, SPR_NOACCESS, 5170 &spr_read_generic, &spr_write_dawr1, 5171 KVM_REG_PPC_DAWR1, 0x00000000); 5172 spr_register_kvm_hv(env, SPR_DAWRX1, "DAWRX1", 5173 SPR_NOACCESS, SPR_NOACCESS, 5174 SPR_NOACCESS, SPR_NOACCESS, 5175 &spr_read_generic, &spr_write_dawrx1, 5176 KVM_REG_PPC_DAWRX1, 0x00000000); 5177 } 5178 5179 static void register_970_dbg_sprs(CPUPPCState *env) 5180 { 5181 /* Breakpoints */ 5182 spr_register(env, SPR_IABR, "IABR", 5183 SPR_NOACCESS, SPR_NOACCESS, 5184 &spr_read_generic, &spr_write_generic, 5185 0x00000000); 5186 } 5187 5188 static void register_book3s_pmu_sup_sprs(CPUPPCState *env) 5189 { 5190 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0", 5191 SPR_NOACCESS, SPR_NOACCESS, 5192 &spr_read_generic, &spr_write_MMCR0, 5193 KVM_REG_PPC_MMCR0, 0x80000000); 5194 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1", 5195 SPR_NOACCESS, SPR_NOACCESS, 5196 &spr_read_generic, &spr_write_MMCR1, 5197 KVM_REG_PPC_MMCR1, 0x00000000); 5198 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA", 5199 SPR_NOACCESS, SPR_NOACCESS, 5200 &spr_read_generic, &spr_write_MMCRA, 5201 KVM_REG_PPC_MMCRA, 0x00000000); 5202 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1", 5203 SPR_NOACCESS, SPR_NOACCESS, 5204 &spr_read_PMC, &spr_write_PMC, 5205 KVM_REG_PPC_PMC1, 0x00000000); 5206 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2", 5207 SPR_NOACCESS, SPR_NOACCESS, 5208 &spr_read_PMC, &spr_write_PMC, 5209 KVM_REG_PPC_PMC2, 0x00000000); 5210 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3", 5211 SPR_NOACCESS, SPR_NOACCESS, 5212 &spr_read_PMC, &spr_write_PMC, 5213 KVM_REG_PPC_PMC3, 0x00000000); 5214 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4", 5215 SPR_NOACCESS, SPR_NOACCESS, 5216 &spr_read_PMC, &spr_write_PMC, 5217 KVM_REG_PPC_PMC4, 0x00000000); 5218 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5", 5219 SPR_NOACCESS, SPR_NOACCESS, 5220 &spr_read_PMC, &spr_write_PMC, 5221 KVM_REG_PPC_PMC5, 0x00000000); 5222 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6", 5223 SPR_NOACCESS, SPR_NOACCESS, 5224 &spr_read_PMC, &spr_write_PMC, 5225 KVM_REG_PPC_PMC6, 0x00000000); 5226 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR", 5227 SPR_NOACCESS, SPR_NOACCESS, 5228 &spr_read_generic, &spr_write_generic, 5229 KVM_REG_PPC_SIAR, 0x00000000); 5230 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR", 5231 SPR_NOACCESS, SPR_NOACCESS, 5232 &spr_read_generic, &spr_write_generic, 5233 KVM_REG_PPC_SDAR, 0x00000000); 5234 } 5235 5236 static void register_book3s_pmu_user_sprs(CPUPPCState *env) 5237 { 5238 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0", 5239 &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg, 5240 &spr_read_ureg, &spr_write_ureg, 5241 0x80000000); 5242 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1", 5243 &spr_read_ureg, SPR_NOACCESS, 5244 &spr_read_ureg, &spr_write_ureg, 5245 0x00000000); 5246 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA", 5247 &spr_read_ureg, SPR_NOACCESS, 5248 &spr_read_ureg, &spr_write_ureg, 5249 0x00000000); 5250 spr_register(env, SPR_POWER_UPMC1, "UPMC1", 5251 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5252 &spr_read_ureg, &spr_write_ureg, 5253 0x00000000); 5254 spr_register(env, SPR_POWER_UPMC2, "UPMC2", 5255 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5256 &spr_read_ureg, &spr_write_ureg, 5257 0x00000000); 5258 spr_register(env, SPR_POWER_UPMC3, "UPMC3", 5259 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5260 &spr_read_ureg, &spr_write_ureg, 5261 0x00000000); 5262 spr_register(env, SPR_POWER_UPMC4, "UPMC4", 5263 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5264 &spr_read_ureg, &spr_write_ureg, 5265 0x00000000); 5266 spr_register(env, SPR_POWER_UPMC5, "UPMC5", 5267 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg, 5268 &spr_read_ureg, &spr_write_ureg, 5269 0x00000000); 5270 spr_register(env, SPR_POWER_UPMC6, "UPMC6", 5271 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg, 5272 &spr_read_ureg, &spr_write_ureg, 5273 0x00000000); 5274 spr_register(env, SPR_POWER_USIAR, "USIAR", 5275 &spr_read_ureg, SPR_NOACCESS, 5276 &spr_read_ureg, &spr_write_ureg, 5277 0x00000000); 5278 spr_register(env, SPR_POWER_USDAR, "USDAR", 5279 &spr_read_ureg, SPR_NOACCESS, 5280 &spr_read_ureg, &spr_write_ureg, 5281 0x00000000); 5282 } 5283 5284 static void register_970_pmu_sup_sprs(CPUPPCState *env) 5285 { 5286 spr_register_kvm(env, SPR_970_PMC7, "PMC7", 5287 SPR_NOACCESS, SPR_NOACCESS, 5288 &spr_read_generic, &spr_write_generic, 5289 KVM_REG_PPC_PMC7, 0x00000000); 5290 spr_register_kvm(env, SPR_970_PMC8, "PMC8", 5291 SPR_NOACCESS, SPR_NOACCESS, 5292 &spr_read_generic, &spr_write_generic, 5293 KVM_REG_PPC_PMC8, 0x00000000); 5294 } 5295 5296 static void register_970_pmu_user_sprs(CPUPPCState *env) 5297 { 5298 spr_register(env, SPR_970_UPMC7, "UPMC7", 5299 &spr_read_ureg, SPR_NOACCESS, 5300 &spr_read_ureg, &spr_write_ureg, 5301 0x00000000); 5302 spr_register(env, SPR_970_UPMC8, "UPMC8", 5303 &spr_read_ureg, SPR_NOACCESS, 5304 &spr_read_ureg, &spr_write_ureg, 5305 0x00000000); 5306 } 5307 5308 static void register_power8_pmu_sup_sprs(CPUPPCState *env) 5309 { 5310 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2", 5311 SPR_NOACCESS, SPR_NOACCESS, 5312 &spr_read_generic, &spr_write_generic, 5313 KVM_REG_PPC_MMCR2, 0x00000000); 5314 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS", 5315 SPR_NOACCESS, SPR_NOACCESS, 5316 &spr_read_generic, &spr_write_generic, 5317 KVM_REG_PPC_MMCRS, 0x00000000); 5318 spr_register_kvm(env, SPR_POWER_SIER, "SIER", 5319 SPR_NOACCESS, SPR_NOACCESS, 5320 &spr_read_generic, &spr_write_generic, 5321 KVM_REG_PPC_SIER, 0x00000000); 5322 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1", 5323 SPR_NOACCESS, SPR_NOACCESS, 5324 &spr_read_generic, &spr_write_generic, 5325 KVM_REG_PPC_SPMC1, 0x00000000); 5326 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2", 5327 SPR_NOACCESS, SPR_NOACCESS, 5328 &spr_read_generic, &spr_write_generic, 5329 KVM_REG_PPC_SPMC2, 0x00000000); 5330 spr_register_kvm(env, SPR_TACR, "TACR", 5331 SPR_NOACCESS, SPR_NOACCESS, 5332 &spr_read_generic, &spr_write_generic, 5333 KVM_REG_PPC_TACR, 0x00000000); 5334 spr_register_kvm(env, SPR_TCSCR, "TCSCR", 5335 SPR_NOACCESS, SPR_NOACCESS, 5336 &spr_read_generic, &spr_write_generic, 5337 KVM_REG_PPC_TCSCR, 0x00000000); 5338 spr_register_kvm(env, SPR_CSIGR, "CSIGR", 5339 SPR_NOACCESS, SPR_NOACCESS, 5340 &spr_read_generic, &spr_write_generic, 5341 KVM_REG_PPC_CSIGR, 0x00000000); 5342 } 5343 5344 static void register_power8_pmu_user_sprs(CPUPPCState *env) 5345 { 5346 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2", 5347 &spr_read_MMCR2_ureg, &spr_write_MMCR2_ureg, 5348 &spr_read_ureg, &spr_write_ureg, 5349 0x00000000); 5350 spr_register(env, SPR_POWER_USIER, "USIER", 5351 &spr_read_generic, SPR_NOACCESS, 5352 &spr_read_generic, &spr_write_generic, 5353 0x00000000); 5354 } 5355 5356 static void register_power10_pmu_sup_sprs(CPUPPCState *env) 5357 { 5358 spr_register_kvm(env, SPR_POWER_MMCR3, "MMCR3", 5359 SPR_NOACCESS, SPR_NOACCESS, 5360 &spr_read_generic, &spr_write_generic, 5361 KVM_REG_PPC_MMCR3, 0x00000000); 5362 spr_register_kvm(env, SPR_POWER_SIER2, "SIER2", 5363 SPR_NOACCESS, SPR_NOACCESS, 5364 &spr_read_generic, &spr_write_generic, 5365 KVM_REG_PPC_SIER2, 0x00000000); 5366 spr_register_kvm(env, SPR_POWER_SIER3, "SIER3", 5367 SPR_NOACCESS, SPR_NOACCESS, 5368 &spr_read_generic, &spr_write_generic, 5369 KVM_REG_PPC_SIER3, 0x00000000); 5370 } 5371 5372 static void register_power10_pmu_user_sprs(CPUPPCState *env) 5373 { 5374 spr_register(env, SPR_POWER_UMMCR3, "UMMCR3", 5375 &spr_read_generic, &spr_write_generic, 5376 &spr_read_generic, &spr_write_generic, 5377 0x00000000); 5378 spr_register(env, SPR_POWER_USIER2, "USIER2", 5379 &spr_read_generic, SPR_NOACCESS, 5380 &spr_read_generic, &spr_write_generic, 5381 0x00000000); 5382 spr_register(env, SPR_POWER_USIER3, "USIER3", 5383 &spr_read_generic, SPR_NOACCESS, 5384 &spr_read_generic, &spr_write_generic, 5385 0x00000000); 5386 } 5387 5388 static void register_power5p_ear_sprs(CPUPPCState *env) 5389 { 5390 /* External access control */ 5391 spr_register(env, SPR_EAR, "EAR", 5392 SPR_NOACCESS, SPR_NOACCESS, 5393 &spr_read_generic, &spr_write_generic, 5394 0x00000000); 5395 } 5396 5397 static void register_power5p_tb_sprs(CPUPPCState *env) 5398 { 5399 /* TBU40 (High 40 bits of the Timebase register */ 5400 spr_register_hv(env, SPR_TBU40, "TBU40", 5401 SPR_NOACCESS, SPR_NOACCESS, 5402 SPR_NOACCESS, SPR_NOACCESS, 5403 SPR_NOACCESS, &spr_write_tbu40, 5404 0x00000000); 5405 } 5406 5407 static void register_970_lpar_sprs(CPUPPCState *env) 5408 { 5409 #if !defined(CONFIG_USER_ONLY) 5410 /* 5411 * PPC970: HID4 covers things later controlled by the LPCR and 5412 * RMOR in later CPUs, but with a different encoding. We only 5413 * support the 970 in "Apple mode" which has all hypervisor 5414 * facilities disabled by strapping, so we can basically just 5415 * ignore it 5416 */ 5417 spr_register(env, SPR_970_HID4, "HID4", 5418 SPR_NOACCESS, SPR_NOACCESS, 5419 &spr_read_generic, &spr_write_generic, 5420 0x00000000); 5421 #endif 5422 } 5423 5424 static void register_power5p_lpar_sprs(CPUPPCState *env) 5425 { 5426 #if !defined(CONFIG_USER_ONLY) 5427 /* Logical partitioning */ 5428 spr_register_kvm_hv(env, SPR_LPCR, "LPCR", 5429 SPR_NOACCESS, SPR_NOACCESS, 5430 SPR_NOACCESS, SPR_NOACCESS, 5431 &spr_read_generic, &spr_write_lpcr, 5432 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1); 5433 spr_register_hv(env, SPR_HDEC, "HDEC", 5434 SPR_NOACCESS, SPR_NOACCESS, 5435 SPR_NOACCESS, SPR_NOACCESS, 5436 &spr_read_hdecr, &spr_write_hdecr, 0); 5437 #endif 5438 } 5439 5440 static void register_book3s_ids_sprs(CPUPPCState *env) 5441 { 5442 /* FIXME: Will need to deal with thread vs core only SPRs */ 5443 5444 /* Processor identification */ 5445 spr_register_hv(env, SPR_PIR, "PIR", 5446 SPR_NOACCESS, SPR_NOACCESS, 5447 &spr_read_generic, SPR_NOACCESS, 5448 &spr_read_generic, NULL, 5449 0x00000000); 5450 spr_register_hv(env, SPR_LPIDR, "LPIDR", 5451 SPR_NOACCESS, SPR_NOACCESS, 5452 SPR_NOACCESS, SPR_NOACCESS, 5453 &spr_read_generic, &spr_write_lpidr, 5454 0x00000000); 5455 spr_register_hv(env, SPR_HFSCR, "HFSCR", 5456 SPR_NOACCESS, SPR_NOACCESS, 5457 SPR_NOACCESS, SPR_NOACCESS, 5458 &spr_read_generic, &spr_write_generic, 5459 0x00000000); 5460 spr_register_hv(env, SPR_MMCRC, "MMCRC", 5461 SPR_NOACCESS, SPR_NOACCESS, 5462 SPR_NOACCESS, SPR_NOACCESS, 5463 &spr_read_generic, &spr_core_write_generic32, 5464 0x00000000); 5465 spr_register_hv(env, SPR_MMCRH, "MMCRH", 5466 SPR_NOACCESS, SPR_NOACCESS, 5467 SPR_NOACCESS, SPR_NOACCESS, 5468 &spr_read_generic, &spr_write_generic, 5469 0x00000000); 5470 spr_register_hv(env, SPR_HSPRG0, "HSPRG0", 5471 SPR_NOACCESS, SPR_NOACCESS, 5472 SPR_NOACCESS, SPR_NOACCESS, 5473 &spr_read_generic, &spr_write_generic, 5474 0x00000000); 5475 spr_register_hv(env, SPR_HSPRG1, "HSPRG1", 5476 SPR_NOACCESS, SPR_NOACCESS, 5477 SPR_NOACCESS, SPR_NOACCESS, 5478 &spr_read_generic, &spr_write_generic, 5479 0x00000000); 5480 spr_register_hv(env, SPR_HSRR0, "HSRR0", 5481 SPR_NOACCESS, SPR_NOACCESS, 5482 SPR_NOACCESS, SPR_NOACCESS, 5483 &spr_read_generic, &spr_write_generic, 5484 0x00000000); 5485 spr_register_hv(env, SPR_HSRR1, "HSRR1", 5486 SPR_NOACCESS, SPR_NOACCESS, 5487 SPR_NOACCESS, SPR_NOACCESS, 5488 &spr_read_generic, &spr_write_generic, 5489 0x00000000); 5490 spr_register_hv(env, SPR_HDAR, "HDAR", 5491 SPR_NOACCESS, SPR_NOACCESS, 5492 SPR_NOACCESS, SPR_NOACCESS, 5493 &spr_read_generic, &spr_write_generic, 5494 0x00000000); 5495 spr_register_hv(env, SPR_HDSISR, "HDSISR", 5496 SPR_NOACCESS, SPR_NOACCESS, 5497 SPR_NOACCESS, SPR_NOACCESS, 5498 &spr_read_generic, &spr_write_generic32, 5499 0x00000000); 5500 spr_register_hv(env, SPR_HRMOR, "HRMOR", 5501 SPR_NOACCESS, SPR_NOACCESS, 5502 SPR_NOACCESS, SPR_NOACCESS, 5503 &spr_read_generic, &spr_core_write_generic, 5504 0x00000000); 5505 } 5506 5507 static void register_rmor_sprs(CPUPPCState *env) 5508 { 5509 spr_register_hv(env, SPR_RMOR, "RMOR", 5510 SPR_NOACCESS, SPR_NOACCESS, 5511 SPR_NOACCESS, SPR_NOACCESS, 5512 &spr_read_generic, &spr_write_generic, 5513 0x00000000); 5514 } 5515 5516 static void register_power8_ids_sprs(CPUPPCState *env) 5517 { 5518 /* Thread identification */ 5519 spr_register(env, SPR_TIR, "TIR", 5520 SPR_NOACCESS, SPR_NOACCESS, 5521 &spr_read_generic, SPR_NOACCESS, 5522 0x00000000); 5523 } 5524 5525 static void register_book3s_purr_sprs(CPUPPCState *env) 5526 { 5527 #if !defined(CONFIG_USER_ONLY) 5528 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */ 5529 spr_register_kvm_hv(env, SPR_PURR, "PURR", 5530 &spr_read_purr, SPR_NOACCESS, 5531 &spr_read_purr, SPR_NOACCESS, 5532 &spr_read_purr, &spr_write_purr, 5533 KVM_REG_PPC_PURR, 0x00000000); 5534 spr_register_kvm_hv(env, SPR_SPURR, "SPURR", 5535 &spr_read_purr, SPR_NOACCESS, 5536 &spr_read_purr, SPR_NOACCESS, 5537 &spr_read_purr, &spr_write_purr, 5538 KVM_REG_PPC_SPURR, 0x00000000); 5539 #endif 5540 } 5541 5542 static void register_power6_dbg_sprs(CPUPPCState *env) 5543 { 5544 #if !defined(CONFIG_USER_ONLY) 5545 spr_register(env, SPR_CFAR, "CFAR", 5546 SPR_NOACCESS, SPR_NOACCESS, 5547 &spr_read_cfar, &spr_write_cfar, 5548 0x00000000); 5549 #endif 5550 } 5551 5552 static void register_power5p_common_sprs(CPUPPCState *env) 5553 { 5554 spr_register_kvm(env, SPR_PPR, "PPR", 5555 &spr_read_generic, &spr_write_generic, 5556 &spr_read_generic, &spr_write_generic, 5557 KVM_REG_PPC_PPR, 0x00000000); 5558 } 5559 5560 static void register_power6_common_sprs(CPUPPCState *env) 5561 { 5562 #if !defined(CONFIG_USER_ONLY) 5563 spr_register_kvm(env, SPR_DSCR, "DSCR", 5564 SPR_NOACCESS, SPR_NOACCESS, 5565 &spr_read_generic, &spr_write_generic, 5566 KVM_REG_PPC_DSCR, 0x00000000); 5567 #endif 5568 /* 5569 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of 5570 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access. 5571 */ 5572 spr_register_hv(env, SPR_PCR, "PCR", 5573 SPR_NOACCESS, SPR_NOACCESS, 5574 SPR_NOACCESS, SPR_NOACCESS, 5575 &spr_read_generic, &spr_write_pcr, 5576 0x00000000); 5577 } 5578 5579 static void register_HEIR32_spr(CPUPPCState *env) 5580 { 5581 spr_register_hv(env, SPR_HEIR, "HEIR", 5582 SPR_NOACCESS, SPR_NOACCESS, 5583 SPR_NOACCESS, SPR_NOACCESS, 5584 &spr_read_generic, &spr_write_generic32, 5585 0x00000000); 5586 } 5587 5588 static void register_HEIR64_spr(CPUPPCState *env) 5589 { 5590 spr_register_hv(env, SPR_HEIR, "HEIR", 5591 SPR_NOACCESS, SPR_NOACCESS, 5592 SPR_NOACCESS, SPR_NOACCESS, 5593 &spr_read_generic, &spr_write_generic, 5594 0x00000000); 5595 } 5596 5597 static void register_power7_common_sprs(CPUPPCState *env) 5598 { 5599 spr_register(env, SPR_PPR32, "PPR32", 5600 &spr_read_ppr32, &spr_write_ppr32, 5601 &spr_read_ppr32, &spr_write_ppr32, 5602 0x00000000); 5603 } 5604 5605 static void register_power8_tce_address_control_sprs(CPUPPCState *env) 5606 { 5607 spr_register_kvm(env, SPR_TAR, "TAR", 5608 &spr_read_tar, &spr_write_tar, 5609 &spr_read_generic, &spr_write_generic, 5610 KVM_REG_PPC_TAR, 0x00000000); 5611 } 5612 5613 static void register_power8_tm_sprs(CPUPPCState *env) 5614 { 5615 spr_register_kvm(env, SPR_TFHAR, "TFHAR", 5616 &spr_read_tm, &spr_write_tm, 5617 &spr_read_tm, &spr_write_tm, 5618 KVM_REG_PPC_TFHAR, 0x00000000); 5619 spr_register_kvm(env, SPR_TFIAR, "TFIAR", 5620 &spr_read_tm, &spr_write_tm, 5621 &spr_read_tm, &spr_write_tm, 5622 KVM_REG_PPC_TFIAR, 0x00000000); 5623 spr_register_kvm(env, SPR_TEXASR, "TEXASR", 5624 &spr_read_tm, &spr_write_tm, 5625 &spr_read_tm, &spr_write_tm, 5626 KVM_REG_PPC_TEXASR, 0x00000000); 5627 spr_register(env, SPR_TEXASRU, "TEXASRU", 5628 &spr_read_tm_upper32, &spr_write_tm_upper32, 5629 &spr_read_tm_upper32, &spr_write_tm_upper32, 5630 0x00000000); 5631 } 5632 5633 static void register_power8_ebb_sprs(CPUPPCState *env) 5634 { 5635 spr_register(env, SPR_BESCRS, "BESCRS", 5636 &spr_read_ebb, &spr_write_ebb, 5637 &spr_read_generic, &spr_write_generic, 5638 0x00000000); 5639 spr_register(env, SPR_BESCRSU, "BESCRSU", 5640 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 5641 &spr_read_prev_upper32, &spr_write_prev_upper32, 5642 0x00000000); 5643 spr_register(env, SPR_BESCRR, "BESCRR", 5644 &spr_read_ebb, &spr_write_ebb, 5645 &spr_read_generic, &spr_write_generic, 5646 0x00000000); 5647 spr_register(env, SPR_BESCRRU, "BESCRRU", 5648 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 5649 &spr_read_prev_upper32, &spr_write_prev_upper32, 5650 0x00000000); 5651 spr_register_kvm(env, SPR_EBBHR, "EBBHR", 5652 &spr_read_ebb, &spr_write_ebb, 5653 &spr_read_generic, &spr_write_generic, 5654 KVM_REG_PPC_EBBHR, 0x00000000); 5655 spr_register_kvm(env, SPR_EBBRR, "EBBRR", 5656 &spr_read_ebb, &spr_write_ebb, 5657 &spr_read_generic, &spr_write_generic, 5658 KVM_REG_PPC_EBBRR, 0x00000000); 5659 spr_register_kvm(env, SPR_BESCR, "BESCR", 5660 &spr_read_ebb, &spr_write_ebb, 5661 &spr_read_generic, &spr_write_generic, 5662 KVM_REG_PPC_BESCR, 0x00000000); 5663 } 5664 5665 /* Virtual Time Base */ 5666 static void register_vtb_sprs(CPUPPCState *env) 5667 { 5668 spr_register_kvm_hv(env, SPR_VTB, "VTB", 5669 SPR_NOACCESS, SPR_NOACCESS, 5670 &spr_read_vtb, SPR_NOACCESS, 5671 &spr_read_vtb, &spr_write_vtb, 5672 KVM_REG_PPC_VTB, 0x00000000); 5673 } 5674 5675 static void register_power8_fscr_sprs(CPUPPCState *env) 5676 { 5677 #if defined(CONFIG_USER_ONLY) 5678 target_ulong initval = 1ULL << FSCR_TAR; 5679 #else 5680 target_ulong initval = 0; 5681 #endif 5682 spr_register_kvm(env, SPR_FSCR, "FSCR", 5683 SPR_NOACCESS, SPR_NOACCESS, 5684 &spr_read_generic, &spr_write_generic, 5685 KVM_REG_PPC_FSCR, initval); 5686 } 5687 5688 static void register_power8_pspb_sprs(CPUPPCState *env) 5689 { 5690 spr_register_kvm(env, SPR_PSPB, "PSPB", 5691 SPR_NOACCESS, SPR_NOACCESS, 5692 &spr_read_generic, &spr_write_generic32, 5693 KVM_REG_PPC_PSPB, 0); 5694 } 5695 5696 static void register_power8_dpdes_sprs(CPUPPCState *env) 5697 { 5698 #if !defined(CONFIG_USER_ONLY) 5699 /* Directed Privileged Door-bell Exception State, used for IPI */ 5700 spr_register_kvm_hv(env, SPR_DPDES, "DPDES", 5701 SPR_NOACCESS, SPR_NOACCESS, 5702 &spr_read_dpdes, SPR_NOACCESS, 5703 &spr_read_dpdes, &spr_write_dpdes, 5704 KVM_REG_PPC_DPDES, 0x00000000); 5705 #endif 5706 } 5707 5708 static void register_power8_ic_sprs(CPUPPCState *env) 5709 { 5710 #if !defined(CONFIG_USER_ONLY) 5711 spr_register_hv(env, SPR_IC, "IC", 5712 SPR_NOACCESS, SPR_NOACCESS, 5713 &spr_read_generic, SPR_NOACCESS, 5714 &spr_read_generic, &spr_write_generic, 5715 0); 5716 #endif 5717 } 5718 5719 /* SPRs specific to IBM POWER CPUs */ 5720 static void register_power_common_book4_sprs(CPUPPCState *env) 5721 { 5722 #if !defined(CONFIG_USER_ONLY) 5723 spr_register_hv(env, SPR_HID0, "HID0", 5724 SPR_NOACCESS, SPR_NOACCESS, 5725 SPR_NOACCESS, SPR_NOACCESS, 5726 &spr_read_generic, &spr_core_write_generic, 5727 0x00000000); 5728 spr_register_hv(env, SPR_TSCR, "TSCR", 5729 SPR_NOACCESS, SPR_NOACCESS, 5730 SPR_NOACCESS, SPR_NOACCESS, 5731 &spr_read_generic, &spr_core_write_generic32, 5732 0x00000000); 5733 spr_register_hv(env, SPR_HMER, "HMER", 5734 SPR_NOACCESS, SPR_NOACCESS, 5735 SPR_NOACCESS, SPR_NOACCESS, 5736 &spr_read_generic, &spr_write_hmer, 5737 0x00000000); 5738 spr_register_hv(env, SPR_HMEER, "HMEER", 5739 SPR_NOACCESS, SPR_NOACCESS, 5740 SPR_NOACCESS, SPR_NOACCESS, 5741 &spr_read_generic, &spr_core_write_generic, 5742 0x00000000); 5743 spr_register_hv(env, SPR_TFMR, "TFMR", 5744 SPR_NOACCESS, SPR_NOACCESS, 5745 SPR_NOACCESS, SPR_NOACCESS, 5746 &spr_read_tfmr, &spr_write_tfmr, 5747 0x00000000); 5748 spr_register_hv(env, SPR_TRIG1, "TRIG1", 5749 SPR_NOACCESS, SPR_NOACCESS, 5750 &spr_access_nop, &spr_write_generic, 5751 &spr_access_nop, &spr_write_generic, 5752 0x00000000); 5753 spr_register_hv(env, SPR_TRIG2, "TRIG2", 5754 SPR_NOACCESS, SPR_NOACCESS, 5755 &spr_access_nop, &spr_write_generic, 5756 &spr_access_nop, &spr_write_generic, 5757 0x00000000); 5758 spr_register_hv(env, SPR_LDBAR, "LDBAR", 5759 SPR_NOACCESS, SPR_NOACCESS, 5760 SPR_NOACCESS, SPR_NOACCESS, 5761 &spr_read_generic, &spr_core_lpar_write_generic, 5762 0x00000000); 5763 spr_register_hv(env, SPR_POWER_TTR, "TTR", 5764 SPR_NOACCESS, SPR_NOACCESS, 5765 SPR_NOACCESS, SPR_NOACCESS, 5766 &spr_read_generic, &spr_core_write_generic, 5767 0x00000000); 5768 #endif 5769 } 5770 5771 static void register_power9_book4_sprs(CPUPPCState *env) 5772 { 5773 /* Add a number of P9 book4 registers */ 5774 register_power_common_book4_sprs(env); 5775 #if !defined(CONFIG_USER_ONLY) 5776 spr_register_kvm(env, SPR_WORT, "WORT", 5777 SPR_NOACCESS, SPR_NOACCESS, 5778 &spr_read_generic, &spr_write_generic, 5779 KVM_REG_PPC_WORT, 0); 5780 spr_register_hv(env, SPR_RWMR, "RWMR", 5781 SPR_NOACCESS, SPR_NOACCESS, 5782 &spr_read_generic, &spr_write_generic, 5783 &spr_read_generic, &spr_write_generic, 5784 0x00000000); 5785 5786 /* SPRC/SPRD exist in earlier CPUs but only tested on POWER9/10 */ 5787 spr_register_hv(env, SPR_POWER_SPRC, "SPRC", 5788 SPR_NOACCESS, SPR_NOACCESS, 5789 SPR_NOACCESS, SPR_NOACCESS, 5790 &spr_read_generic, &spr_write_sprc, 5791 0x00000000); 5792 spr_register_hv(env, SPR_POWER_SPRD, "SPRD", 5793 SPR_NOACCESS, SPR_NOACCESS, 5794 SPR_NOACCESS, SPR_NOACCESS, 5795 &spr_read_sprd, &spr_write_sprd, 5796 0x00000000); 5797 #endif 5798 } 5799 5800 static void register_power8_book4_sprs(CPUPPCState *env) 5801 { 5802 /* Add a number of P8 book4 registers */ 5803 register_power_common_book4_sprs(env); 5804 #if !defined(CONFIG_USER_ONLY) 5805 spr_register_kvm(env, SPR_ACOP, "ACOP", 5806 SPR_NOACCESS, SPR_NOACCESS, 5807 &spr_read_generic, &spr_write_generic, 5808 KVM_REG_PPC_ACOP, 0); 5809 /* PID is only in BookE in ISA v2.07 */ 5810 spr_register_kvm(env, SPR_BOOKS_PID, "PIDR", 5811 SPR_NOACCESS, SPR_NOACCESS, 5812 &spr_read_generic, &spr_write_pidr, 5813 KVM_REG_PPC_PID, 0); 5814 spr_register_kvm(env, SPR_WORT, "WORT", 5815 SPR_NOACCESS, SPR_NOACCESS, 5816 &spr_read_generic, &spr_write_generic, 5817 KVM_REG_PPC_WORT, 0); 5818 #endif 5819 } 5820 5821 static void register_power7_book4_sprs(CPUPPCState *env) 5822 { 5823 /* Add a number of P7 book4 registers */ 5824 #if !defined(CONFIG_USER_ONLY) 5825 register_power_common_book4_sprs(env); 5826 spr_register_kvm(env, SPR_ACOP, "ACOP", 5827 SPR_NOACCESS, SPR_NOACCESS, 5828 &spr_read_generic, &spr_write_generic, 5829 KVM_REG_PPC_ACOP, 0); 5830 /* PID is only in BookE in ISA v2.06 */ 5831 spr_register_kvm(env, SPR_BOOKS_PID, "PIDR", 5832 SPR_NOACCESS, SPR_NOACCESS, 5833 &spr_read_generic, &spr_write_generic32, 5834 KVM_REG_PPC_PID, 0); 5835 #endif 5836 } 5837 5838 static void register_power8_rpr_sprs(CPUPPCState *env) 5839 { 5840 #if !defined(CONFIG_USER_ONLY) 5841 spr_register_hv(env, SPR_RPR, "RPR", 5842 SPR_NOACCESS, SPR_NOACCESS, 5843 SPR_NOACCESS, SPR_NOACCESS, 5844 &spr_read_generic, &spr_core_write_generic, 5845 0x00000103070F1F3F); 5846 #endif 5847 } 5848 5849 static void register_power9_mmu_sprs(CPUPPCState *env) 5850 { 5851 #if !defined(CONFIG_USER_ONLY) 5852 /* Partition Table Control */ 5853 spr_register_kvm_hv(env, SPR_PTCR, "PTCR", 5854 SPR_NOACCESS, SPR_NOACCESS, 5855 SPR_NOACCESS, SPR_NOACCESS, 5856 &spr_read_generic, &spr_write_ptcr, 5857 KVM_REG_PPC_PTCR, 0x00000000); 5858 /* Address Segment Descriptor Register */ 5859 spr_register_hv(env, SPR_ASDR, "ASDR", 5860 SPR_NOACCESS, SPR_NOACCESS, 5861 SPR_NOACCESS, SPR_NOACCESS, 5862 &spr_read_generic, &spr_write_generic, 5863 0x0000000000000000); 5864 /* PID is part of the BookS ISA from v3.0 */ 5865 spr_register_kvm(env, SPR_BOOKS_PID, "PIDR", 5866 SPR_NOACCESS, SPR_NOACCESS, 5867 &spr_read_generic, &spr_write_pidr, 5868 KVM_REG_PPC_PID, 0); 5869 #endif 5870 } 5871 5872 static void register_power10_hash_sprs(CPUPPCState *env) 5873 { 5874 /* 5875 * it's the OS responsibility to generate a random value for the registers 5876 * in each process' context. So, initialize it with 0 here. 5877 */ 5878 uint64_t hashkeyr_initial_value = 0, hashpkeyr_initial_value = 0; 5879 #if defined(CONFIG_USER_ONLY) 5880 /* in linux-user, setup the hash register with a random value */ 5881 GRand *rand = g_rand_new(); 5882 hashkeyr_initial_value = 5883 ((uint64_t)g_rand_int(rand) << 32) | (uint64_t)g_rand_int(rand); 5884 hashpkeyr_initial_value = 5885 ((uint64_t)g_rand_int(rand) << 32) | (uint64_t)g_rand_int(rand); 5886 g_rand_free(rand); 5887 #endif 5888 spr_register_kvm(env, SPR_HASHKEYR, "HASHKEYR", 5889 SPR_NOACCESS, SPR_NOACCESS, 5890 &spr_read_generic, &spr_write_generic, 5891 KVM_REG_PPC_HASHKEYR, hashkeyr_initial_value); 5892 spr_register_kvm_hv(env, SPR_HASHPKEYR, "HASHPKEYR", 5893 SPR_NOACCESS, SPR_NOACCESS, 5894 SPR_NOACCESS, SPR_NOACCESS, 5895 &spr_read_generic, &spr_write_generic, 5896 KVM_REG_PPC_HASHPKEYR, hashpkeyr_initial_value); 5897 } 5898 5899 static void register_power10_dexcr_sprs(CPUPPCState *env) 5900 { 5901 spr_register_kvm(env, SPR_DEXCR, "DEXCR", 5902 SPR_NOACCESS, SPR_NOACCESS, 5903 &spr_read_generic, &spr_write_generic, KVM_REG_PPC_DEXCR, 5904 0); 5905 5906 spr_register(env, SPR_UDEXCR, "UDEXCR", 5907 &spr_read_dexcr_ureg, SPR_NOACCESS, 5908 &spr_read_dexcr_ureg, SPR_NOACCESS, 5909 0); 5910 5911 spr_register_hv(env, SPR_HDEXCR, "HDEXCR", 5912 SPR_NOACCESS, SPR_NOACCESS, 5913 SPR_NOACCESS, SPR_NOACCESS, 5914 &spr_read_generic, &spr_write_generic, 5915 0); 5916 5917 spr_register(env, SPR_UHDEXCR, "UHDEXCR", 5918 &spr_read_dexcr_ureg, SPR_NOACCESS, 5919 &spr_read_dexcr_ureg, SPR_NOACCESS, 5920 0); 5921 } 5922 5923 /* 5924 * Initialize PMU counter overflow timers for Power8 and 5925 * newer Power chips when using TCG. 5926 */ 5927 static void init_tcg_pmu_power8(CPUPPCState *env) 5928 { 5929 /* Init PMU overflow timers */ 5930 if (tcg_enabled()) { 5931 cpu_ppc_pmu_init(env); 5932 } 5933 } 5934 5935 static void init_proc_book3s_common(CPUPPCState *env) 5936 { 5937 register_non_embedded_sprs(env); 5938 register_book3s_altivec_sprs(env); 5939 register_book3s_pmu_sup_sprs(env); 5940 register_book3s_pmu_user_sprs(env); 5941 register_book3s_ctrl_sprs(env); 5942 /* 5943 * Can't find information on what this should be on reset. This 5944 * value is the one used by 74xx processors. 5945 */ 5946 vscr_init(env, 0x00010000); 5947 5948 spr_register(env, SPR_USPRG3, "USPRG3", 5949 &spr_read_ureg, SPR_NOACCESS, 5950 &spr_read_ureg, SPR_NOACCESS, 5951 0x00000000); 5952 } 5953 5954 static void init_proc_970(CPUPPCState *env) 5955 { 5956 /* Common Registers */ 5957 init_proc_book3s_common(env); 5958 register_sdr1_sprs(env); 5959 register_book3s_dbg_sprs(env); 5960 5961 /* 970 Specific Registers */ 5962 register_970_hid_sprs(env); 5963 register_970_hior_sprs(env); 5964 register_low_BATs(env); 5965 register_970_pmu_sup_sprs(env); 5966 register_970_pmu_user_sprs(env); 5967 register_970_lpar_sprs(env); 5968 register_970_dbg_sprs(env); 5969 5970 /* env variables */ 5971 env->dcache_line_size = 128; 5972 env->icache_line_size = 128; 5973 5974 /* Allocate hardware IRQ controller */ 5975 init_excp_970(env); 5976 ppc970_irq_init(env_archcpu(env)); 5977 } 5978 5979 POWERPC_FAMILY(970)(ObjectClass *oc, const void *data) 5980 { 5981 DeviceClass *dc = DEVICE_CLASS(oc); 5982 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5983 5984 dc->desc = "PowerPC 970"; 5985 pcc->init_proc = init_proc_970; 5986 pcc->check_pow = check_pow_970; 5987 pcc->check_attn = check_attn_hid0; 5988 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5989 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5990 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5991 PPC_FLOAT_STFIWX | 5992 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5993 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5994 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5995 PPC_64B | PPC_ALTIVEC | 5996 PPC_SEGMENT_64B | PPC_SLBI; 5997 pcc->insns_flags2 = PPC2_FP_CVT_S64 | PPC2_MEM_LWSYNC; 5998 pcc->msr_mask = (1ull << MSR_SF) | 5999 (1ull << MSR_VR) | 6000 (1ull << MSR_POW) | 6001 (1ull << MSR_EE) | 6002 (1ull << MSR_PR) | 6003 (1ull << MSR_FP) | 6004 (1ull << MSR_ME) | 6005 (1ull << MSR_FE0) | 6006 (1ull << MSR_SE) | 6007 (1ull << MSR_DE) | 6008 (1ull << MSR_FE1) | 6009 (1ull << MSR_IR) | 6010 (1ull << MSR_DR) | 6011 (1ull << MSR_PMM) | 6012 (1ull << MSR_RI); 6013 pcc->mmu_model = POWERPC_MMU_64B; 6014 #if !defined(CONFIG_USER_ONLY) 6015 pcc->hash64_opts = &ppc_hash64_opts_basic; 6016 #endif 6017 pcc->excp_model = POWERPC_EXCP_970; 6018 pcc->bus_model = PPC_FLAGS_INPUT_970; 6019 pcc->bfd_mach = bfd_mach_ppc64; 6020 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6021 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6022 POWERPC_FLAG_BUS_CLK; 6023 pcc->l1_dcache_size = 0x8000; 6024 pcc->l1_icache_size = 0x10000; 6025 } 6026 6027 static void init_proc_power5plus(CPUPPCState *env) 6028 { 6029 /* Common Registers */ 6030 init_proc_book3s_common(env); 6031 register_sdr1_sprs(env); 6032 register_book3s_dbg_sprs(env); 6033 6034 /* POWER5+ Specific Registers */ 6035 register_970_hid_sprs(env); 6036 register_970_hior_sprs(env); 6037 register_low_BATs(env); 6038 register_970_pmu_sup_sprs(env); 6039 register_970_pmu_user_sprs(env); 6040 register_power5p_common_sprs(env); 6041 register_power5p_lpar_sprs(env); 6042 register_power5p_ear_sprs(env); 6043 register_power5p_tb_sprs(env); 6044 6045 /* env variables */ 6046 env->dcache_line_size = 128; 6047 env->icache_line_size = 128; 6048 6049 /* Allocate hardware IRQ controller */ 6050 init_excp_970(env); 6051 ppc970_irq_init(env_archcpu(env)); 6052 } 6053 6054 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, const void *data) 6055 { 6056 DeviceClass *dc = DEVICE_CLASS(oc); 6057 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6058 6059 dc->fw_name = "PowerPC,POWER5"; 6060 dc->desc = "POWER5+"; 6061 pcc->init_proc = init_proc_power5plus; 6062 pcc->check_pow = check_pow_970; 6063 pcc->check_attn = check_attn_hid0; 6064 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6065 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6066 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6067 PPC_FLOAT_STFIWX | 6068 PPC_FLOAT_EXT | 6069 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6070 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6071 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6072 PPC_64B | 6073 PPC_POPCNTB | 6074 PPC_SEGMENT_64B | PPC_SLBI; 6075 pcc->insns_flags2 = PPC2_FP_CVT_S64 | PPC2_MEM_LWSYNC; 6076 pcc->msr_mask = (1ull << MSR_SF) | 6077 (1ull << MSR_VR) | 6078 (1ull << MSR_POW) | 6079 (1ull << MSR_EE) | 6080 (1ull << MSR_PR) | 6081 (1ull << MSR_FP) | 6082 (1ull << MSR_ME) | 6083 (1ull << MSR_FE0) | 6084 (1ull << MSR_SE) | 6085 (1ull << MSR_DE) | 6086 (1ull << MSR_FE1) | 6087 (1ull << MSR_IR) | 6088 (1ull << MSR_DR) | 6089 (1ull << MSR_PMM) | 6090 (1ull << MSR_RI); 6091 pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 | 6092 LPCR_RMI | LPCR_HDICE; 6093 pcc->mmu_model = POWERPC_MMU_2_03; 6094 #if !defined(CONFIG_USER_ONLY) 6095 pcc->hash64_opts = &ppc_hash64_opts_basic; 6096 pcc->lrg_decr_bits = 32; 6097 #endif 6098 pcc->excp_model = POWERPC_EXCP_970; 6099 pcc->bus_model = PPC_FLAGS_INPUT_970; 6100 pcc->bfd_mach = bfd_mach_ppc64; 6101 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6102 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6103 POWERPC_FLAG_BUS_CLK; 6104 pcc->l1_dcache_size = 0x8000; 6105 pcc->l1_icache_size = 0x10000; 6106 } 6107 6108 static void init_proc_POWER7(CPUPPCState *env) 6109 { 6110 /* Common Registers */ 6111 init_proc_book3s_common(env); 6112 register_sdr1_sprs(env); 6113 register_book3s_dbg_sprs(env); 6114 6115 /* POWER7 Specific Registers */ 6116 register_book3s_ids_sprs(env); 6117 register_rmor_sprs(env); 6118 register_amr_sprs(env); 6119 register_book3s_purr_sprs(env); 6120 register_power5p_common_sprs(env); 6121 register_power5p_lpar_sprs(env); 6122 register_power5p_ear_sprs(env); 6123 register_power5p_tb_sprs(env); 6124 register_power6_common_sprs(env); 6125 register_HEIR32_spr(env); 6126 register_power6_dbg_sprs(env); 6127 register_power7_common_sprs(env); 6128 register_power7_book4_sprs(env); 6129 6130 /* env variables */ 6131 env->dcache_line_size = 128; 6132 env->icache_line_size = 128; 6133 6134 /* Allocate hardware IRQ controller */ 6135 init_excp_POWER7(env); 6136 ppcPOWER7_irq_init(env_archcpu(env)); 6137 } 6138 6139 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr, bool best) 6140 { 6141 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK; 6142 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK; 6143 6144 if (!best) { 6145 if (base == CPU_POWERPC_POWER7_BASE) { 6146 return true; 6147 } 6148 if (base == CPU_POWERPC_POWER7P_BASE) { 6149 return true; 6150 } 6151 } 6152 6153 if (base != pcc_base) { 6154 return false; 6155 } 6156 6157 return true; 6158 } 6159 6160 POWERPC_FAMILY(POWER7)(ObjectClass *oc, const void *data) 6161 { 6162 DeviceClass *dc = DEVICE_CLASS(oc); 6163 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6164 6165 dc->fw_name = "PowerPC,POWER7"; 6166 dc->desc = "POWER7"; 6167 pcc->spapr_logical_pvr = CPU_POWERPC_LOGICAL_2_06_PLUS; 6168 pcc->pvr_match = ppc_pvr_match_power7; 6169 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05; 6170 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6171 pcc->init_proc = init_proc_POWER7; 6172 pcc->check_pow = check_pow_nocheck; 6173 pcc->check_attn = check_attn_hid0; 6174 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6175 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6176 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6177 PPC_FLOAT_FRSQRTES | 6178 PPC_FLOAT_STFIWX | 6179 PPC_FLOAT_EXT | 6180 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6181 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6182 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6183 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6184 PPC_SEGMENT_64B | PPC_SLBI | 6185 PPC_POPCNTB | PPC_POPCNTWD | 6186 PPC_CILDST; 6187 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 | 6188 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6189 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6190 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 | 6191 PPC2_PM_ISA206 | PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206; 6192 pcc->msr_mask = (1ull << MSR_SF) | 6193 (1ull << MSR_VR) | 6194 (1ull << MSR_VSX) | 6195 (1ull << MSR_EE) | 6196 (1ull << MSR_PR) | 6197 (1ull << MSR_FP) | 6198 (1ull << MSR_ME) | 6199 (1ull << MSR_FE0) | 6200 (1ull << MSR_SE) | 6201 (1ull << MSR_DE) | 6202 (1ull << MSR_FE1) | 6203 (1ull << MSR_IR) | 6204 (1ull << MSR_DR) | 6205 (1ull << MSR_PMM) | 6206 (1ull << MSR_RI) | 6207 (1ull << MSR_LE); 6208 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | 6209 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 6210 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 | 6211 LPCR_MER | LPCR_TC | 6212 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE; 6213 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2; 6214 pcc->mmu_model = POWERPC_MMU_2_06; 6215 #if !defined(CONFIG_USER_ONLY) 6216 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6217 pcc->lrg_decr_bits = 32; 6218 #endif 6219 pcc->excp_model = POWERPC_EXCP_POWER7; 6220 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 6221 pcc->bfd_mach = bfd_mach_ppc64; 6222 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6223 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6224 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6225 POWERPC_FLAG_VSX; 6226 pcc->l1_dcache_size = 0x8000; 6227 pcc->l1_icache_size = 0x8000; 6228 } 6229 6230 static void bhrb_init_state(CPUPPCState *env, target_long num_entries_log2) 6231 { 6232 if (env->flags & POWERPC_FLAG_BHRB) { 6233 if (num_entries_log2 > BHRB_MAX_NUM_ENTRIES_LOG2) { 6234 num_entries_log2 = BHRB_MAX_NUM_ENTRIES_LOG2; 6235 } 6236 env->bhrb_num_entries = 1 << num_entries_log2; 6237 env->bhrb_base = (intptr_t)&env->bhrb[0]; 6238 env->bhrb_offset_mask = (env->bhrb_num_entries * sizeof(uint64_t)) - 1; 6239 } 6240 } 6241 6242 static void bhrb_reset_state(CPUPPCState *env) 6243 { 6244 if (env->flags & POWERPC_FLAG_BHRB) { 6245 env->bhrb_offset = 0; 6246 env->bhrb_filter = 0; 6247 memset(env->bhrb, 0, sizeof(env->bhrb)); 6248 } 6249 } 6250 6251 #define POWER8_BHRB_ENTRIES_LOG2 5 6252 static void init_proc_POWER8(CPUPPCState *env) 6253 { 6254 /* Common Registers */ 6255 init_proc_book3s_common(env); 6256 register_sdr1_sprs(env); 6257 register_book3s_207_dbg_sprs(env); 6258 6259 /* Common TCG PMU */ 6260 init_tcg_pmu_power8(env); 6261 6262 /* POWER8 Specific Registers */ 6263 register_book3s_ids_sprs(env); 6264 register_rmor_sprs(env); 6265 register_amr_sprs(env); 6266 register_iamr_sprs(env); 6267 register_book3s_purr_sprs(env); 6268 register_power5p_common_sprs(env); 6269 register_power5p_lpar_sprs(env); 6270 register_power5p_ear_sprs(env); 6271 register_power5p_tb_sprs(env); 6272 register_power6_common_sprs(env); 6273 register_HEIR32_spr(env); 6274 register_power6_dbg_sprs(env); 6275 register_power7_common_sprs(env); 6276 register_power8_tce_address_control_sprs(env); 6277 register_power8_ids_sprs(env); 6278 register_power8_ebb_sprs(env); 6279 register_power8_fscr_sprs(env); 6280 register_power8_pmu_sup_sprs(env); 6281 register_power8_pmu_user_sprs(env); 6282 register_power8_tm_sprs(env); 6283 register_power8_pspb_sprs(env); 6284 register_power8_dpdes_sprs(env); 6285 register_vtb_sprs(env); 6286 register_power8_ic_sprs(env); 6287 register_power8_book4_sprs(env); 6288 register_power8_rpr_sprs(env); 6289 6290 /* env variables */ 6291 env->dcache_line_size = 128; 6292 env->icache_line_size = 128; 6293 6294 bhrb_init_state(env, POWER8_BHRB_ENTRIES_LOG2); 6295 6296 /* Allocate hardware IRQ controller */ 6297 init_excp_POWER8(env); 6298 ppcPOWER7_irq_init(env_archcpu(env)); 6299 } 6300 6301 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr, bool best) 6302 { 6303 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK; 6304 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK; 6305 6306 if (!best) { 6307 if (base == CPU_POWERPC_POWER8_BASE) { 6308 return true; 6309 } 6310 if (base == CPU_POWERPC_POWER8E_BASE) { 6311 return true; 6312 } 6313 if (base == CPU_POWERPC_POWER8NVL_BASE) { 6314 return true; 6315 } 6316 } 6317 if (base != pcc_base) { 6318 return false; 6319 } 6320 6321 return true; 6322 } 6323 6324 POWERPC_FAMILY(POWER8)(ObjectClass *oc, const void *data) 6325 { 6326 DeviceClass *dc = DEVICE_CLASS(oc); 6327 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6328 6329 dc->fw_name = "PowerPC,POWER8"; 6330 dc->desc = "POWER8"; 6331 pcc->spapr_logical_pvr = CPU_POWERPC_LOGICAL_2_07; 6332 pcc->pvr_match = ppc_pvr_match_power8; 6333 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6334 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6335 pcc->init_proc = init_proc_POWER8; 6336 pcc->check_pow = check_pow_nocheck; 6337 pcc->check_attn = check_attn_hid0; 6338 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6339 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6340 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6341 PPC_FLOAT_FRSQRTES | 6342 PPC_FLOAT_STFIWX | 6343 PPC_FLOAT_EXT | 6344 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6345 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6346 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6347 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6348 PPC_SEGMENT_64B | PPC_SLBI | 6349 PPC_POPCNTB | PPC_POPCNTWD | 6350 PPC_CILDST; 6351 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 6352 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6353 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6354 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 6355 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 6356 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 6357 PPC2_TM | PPC2_PM_ISA206 | PPC2_MEM_LWSYNC | 6358 PPC2_BCDA_ISA206; 6359 pcc->msr_mask = (1ull << MSR_SF) | 6360 (1ull << MSR_HV) | 6361 (1ull << MSR_TM) | 6362 (1ull << MSR_VR) | 6363 (1ull << MSR_VSX) | 6364 (1ull << MSR_EE) | 6365 (1ull << MSR_PR) | 6366 (1ull << MSR_FP) | 6367 (1ull << MSR_ME) | 6368 (1ull << MSR_FE0) | 6369 (1ull << MSR_SE) | 6370 (1ull << MSR_DE) | 6371 (1ull << MSR_FE1) | 6372 (1ull << MSR_IR) | 6373 (1ull << MSR_DR) | 6374 (1ull << MSR_PMM) | 6375 (1ull << MSR_RI) | 6376 (1ull << MSR_TS0) | 6377 (1ull << MSR_TS1) | 6378 (1ull << MSR_LE); 6379 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | 6380 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 6381 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 | 6382 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | 6383 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE; 6384 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 | 6385 LPCR_P8_PECE3 | LPCR_P8_PECE4; 6386 pcc->mmu_model = POWERPC_MMU_2_07; 6387 #if !defined(CONFIG_USER_ONLY) 6388 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6389 pcc->lrg_decr_bits = 32; 6390 pcc->n_host_threads = 8; 6391 #endif 6392 pcc->excp_model = POWERPC_EXCP_POWER8; 6393 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 6394 pcc->bfd_mach = bfd_mach_ppc64; 6395 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6396 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6397 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6398 POWERPC_FLAG_VSX | POWERPC_FLAG_TM; 6399 pcc->l1_dcache_size = 0x8000; 6400 pcc->l1_icache_size = 0x8000; 6401 } 6402 6403 #ifndef CONFIG_USER_ONLY 6404 /* 6405 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 6406 * Encoded as array of int_32s in the form: 6407 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 6408 * x -> AP encoding 6409 * y -> radix mode supported page size (encoded as a shift) 6410 */ 6411 static struct ppc_radix_page_info POWER9_radix_page_info = { 6412 .count = 4, 6413 .entries = { 6414 0x0000000c, /* 4K - enc: 0x0 */ 6415 0xa0000010, /* 64K - enc: 0x5 */ 6416 0x20000015, /* 2M - enc: 0x1 */ 6417 0x4000001e /* 1G - enc: 0x2 */ 6418 } 6419 }; 6420 #endif /* CONFIG_USER_ONLY */ 6421 6422 #define POWER9_BHRB_ENTRIES_LOG2 5 6423 static void register_power9_common_sprs(CPUPPCState *env) 6424 { 6425 /* Common Registers */ 6426 init_proc_book3s_common(env); 6427 register_book3s_207_dbg_sprs(env); 6428 6429 /* Common TCG PMU */ 6430 init_tcg_pmu_power8(env); 6431 6432 /* POWER8 Specific Registers */ 6433 register_book3s_ids_sprs(env); 6434 register_amr_sprs(env); 6435 register_iamr_sprs(env); 6436 register_book3s_purr_sprs(env); 6437 register_power5p_common_sprs(env); 6438 register_power5p_lpar_sprs(env); 6439 register_power5p_ear_sprs(env); 6440 register_power5p_tb_sprs(env); 6441 register_power6_common_sprs(env); 6442 register_power6_dbg_sprs(env); 6443 register_power7_common_sprs(env); 6444 register_power8_tce_address_control_sprs(env); 6445 register_power8_ids_sprs(env); 6446 register_power8_ebb_sprs(env); 6447 register_power8_fscr_sprs(env); 6448 register_power8_pmu_sup_sprs(env); 6449 register_power8_pmu_user_sprs(env); 6450 register_power8_tm_sprs(env); 6451 register_power8_pspb_sprs(env); 6452 register_power8_dpdes_sprs(env); 6453 register_vtb_sprs(env); 6454 register_power8_ic_sprs(env); 6455 register_power9_book4_sprs(env); 6456 register_power8_rpr_sprs(env); 6457 register_power9_mmu_sprs(env); 6458 6459 /* FIXME: Filter fields properly based on privilege level */ 6460 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 6461 spr_read_generic, spr_write_generic, 6462 KVM_REG_PPC_PSSCR, 0); 6463 6464 spr_register_hv(env, SPR_PMSR, "PMSR", 6465 SPR_NOACCESS, SPR_NOACCESS, 6466 SPR_NOACCESS, SPR_NOACCESS, 6467 &spr_read_pmsr, SPR_NOACCESS, 6468 0); 6469 spr_register_hv(env, SPR_PMCR, "PMCR", 6470 SPR_NOACCESS, SPR_NOACCESS, 6471 SPR_NOACCESS, SPR_NOACCESS, 6472 &spr_read_generic, &spr_write_pmcr, 6473 PPC_BIT(63)); /* Version 1 (POWER9/10) */ 6474 6475 } 6476 6477 static void init_proc_POWER9(CPUPPCState *env) 6478 { 6479 register_power9_common_sprs(env); 6480 register_HEIR32_spr(env); 6481 /* POWER9 Specific registers */ 6482 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL, 6483 spr_read_generic, spr_write_generic, 6484 KVM_REG_PPC_TIDR, 0); 6485 /* env variables */ 6486 env->dcache_line_size = 128; 6487 env->icache_line_size = 128; 6488 6489 bhrb_init_state(env, POWER9_BHRB_ENTRIES_LOG2); 6490 6491 /* Allocate hardware IRQ controller */ 6492 init_excp_POWER9(env); 6493 ppcPOWER9_irq_init(env_archcpu(env)); 6494 } 6495 6496 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr, bool best) 6497 { 6498 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK; 6499 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK; 6500 6501 if (!best) { 6502 if (base == CPU_POWERPC_POWER9_BASE) { 6503 return true; 6504 } 6505 } 6506 6507 if (base != pcc_base) { 6508 return false; 6509 } 6510 6511 if ((pvr & 0x0f00) != (pcc->pvr & 0x0f00)) { 6512 /* Major DD version does not match */ 6513 return false; 6514 } 6515 6516 if ((pvr & 0x0f00) == 0x200) { 6517 if ((pvr & 0xf) < 2) { 6518 /* DD2.0, DD2.1 match power9_v2.0 */ 6519 if ((pcc->pvr & 0xf) == 0) { 6520 return true; 6521 } 6522 } else { 6523 /* DD2.2, DD2.3 match power9_v2.2 */ 6524 if ((pcc->pvr & 0xf) == 2) { 6525 return true; 6526 } 6527 } 6528 } 6529 6530 return false; 6531 } 6532 6533 POWERPC_FAMILY(POWER9)(ObjectClass *oc, const void *data) 6534 { 6535 DeviceClass *dc = DEVICE_CLASS(oc); 6536 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6537 6538 dc->fw_name = "PowerPC,POWER9"; 6539 dc->desc = "POWER9"; 6540 pcc->spapr_logical_pvr = CPU_POWERPC_LOGICAL_3_00; 6541 pcc->pvr_match = ppc_pvr_match_power9; 6542 pcc->pcr_mask = PPC_PCR_MASK_POWER9; 6543 pcc->pcr_supported = PPC_PCR_SUPPORTED_POWER9; 6544 pcc->init_proc = init_proc_POWER9; 6545 pcc->check_pow = check_pow_nocheck; 6546 pcc->check_attn = check_attn_hid0_power9; 6547 pcc->insns_flags = PPC_INSNS_FLAGS_POWER9; 6548 pcc->insns_flags2 = PPC_INSNS_FLAGS2_POWER9; 6549 pcc->msr_mask = PPC_MSR_MASK_POWER9; 6550 pcc->lpcr_mask = PPC_LPCR_MASK_POWER9; 6551 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 6552 pcc->mmu_model = POWERPC_MMU_3_00; 6553 #if !defined(CONFIG_USER_ONLY) 6554 /* segment page size remain the same */ 6555 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6556 pcc->radix_page_info = &POWER9_radix_page_info; 6557 pcc->lrg_decr_bits = 56; 6558 pcc->n_host_threads = 4; 6559 #endif 6560 pcc->excp_model = POWERPC_EXCP_POWER9; 6561 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 6562 pcc->bfd_mach = bfd_mach_ppc64; 6563 pcc->flags = POWERPC_FLAGS_POWER9; 6564 pcc->l1_dcache_size = 0x8000; 6565 pcc->l1_icache_size = 0x8000; 6566 } 6567 6568 #ifndef CONFIG_USER_ONLY 6569 /* 6570 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 6571 * Encoded as array of int_32s in the form: 6572 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 6573 * x -> AP encoding 6574 * y -> radix mode supported page size (encoded as a shift) 6575 */ 6576 static struct ppc_radix_page_info POWER10_radix_page_info = { 6577 .count = 4, 6578 .entries = { 6579 0x0000000c, /* 4K - enc: 0x0 */ 6580 0xa0000010, /* 64K - enc: 0x5 */ 6581 0x20000015, /* 2M - enc: 0x1 */ 6582 0x4000001e /* 1G - enc: 0x2 */ 6583 } 6584 }; 6585 #endif /* !CONFIG_USER_ONLY */ 6586 6587 #define POWER10_BHRB_ENTRIES_LOG2 5 6588 static void init_proc_POWER10(CPUPPCState *env) 6589 { 6590 register_power9_common_sprs(env); 6591 register_HEIR64_spr(env); 6592 register_book3s_310_dbg_sprs(env); 6593 register_power10_hash_sprs(env); 6594 register_power10_dexcr_sprs(env); 6595 register_power10_pmu_sup_sprs(env); 6596 register_power10_pmu_user_sprs(env); 6597 /* env variables */ 6598 env->dcache_line_size = 128; 6599 env->icache_line_size = 128; 6600 6601 bhrb_init_state(env, POWER10_BHRB_ENTRIES_LOG2); 6602 6603 /* Allocate hardware IRQ controller */ 6604 init_excp_POWER10(env); 6605 ppcPOWER9_irq_init(env_archcpu(env)); 6606 } 6607 6608 static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr, bool best) 6609 { 6610 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK; 6611 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK; 6612 6613 if (!best) { 6614 if (base == CPU_POWERPC_POWER10_BASE) { 6615 return true; 6616 } 6617 } 6618 6619 if (base != pcc_base) { 6620 return false; 6621 } 6622 6623 if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) { 6624 /* Major DD version matches power10_v2.0 */ 6625 return true; 6626 } 6627 6628 return false; 6629 } 6630 6631 POWERPC_FAMILY(POWER10)(ObjectClass *oc, const void *data) 6632 { 6633 DeviceClass *dc = DEVICE_CLASS(oc); 6634 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6635 6636 dc->fw_name = "PowerPC,POWER10"; 6637 dc->desc = "POWER10"; 6638 pcc->spapr_logical_pvr = CPU_POWERPC_LOGICAL_3_10; 6639 pcc->pvr_match = ppc_pvr_match_power10; 6640 pcc->pcr_mask = PPC_PCR_MASK_POWER10; 6641 pcc->pcr_supported = PPC_PCR_SUPPORTED_POWER10; 6642 pcc->init_proc = init_proc_POWER10; 6643 pcc->check_pow = check_pow_nocheck; 6644 pcc->check_attn = check_attn_hid0_power9; 6645 pcc->insns_flags = PPC_INSNS_FLAGS_POWER10; 6646 pcc->insns_flags2 = PPC_INSNS_FLAGS2_POWER10; 6647 pcc->msr_mask = PPC_MSR_MASK_POWER10; 6648 pcc->lpcr_mask = PPC_LPCR_MASK_POWER10; 6649 6650 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 6651 pcc->mmu_model = POWERPC_MMU_3_00; 6652 #if !defined(CONFIG_USER_ONLY) 6653 /* segment page size remain the same */ 6654 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6655 pcc->radix_page_info = &POWER10_radix_page_info; 6656 pcc->lrg_decr_bits = 56; 6657 #endif 6658 pcc->excp_model = POWERPC_EXCP_POWER10; 6659 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 6660 pcc->bfd_mach = bfd_mach_ppc64; 6661 pcc->flags = POWERPC_FLAGS_POWER10; 6662 pcc->l1_dcache_size = 0x8000; 6663 pcc->l1_icache_size = 0x8000; 6664 } 6665 6666 static void init_proc_POWER11(CPUPPCState *env) 6667 { 6668 init_proc_POWER10(env); 6669 } 6670 6671 static bool ppc_pvr_match_power11(PowerPCCPUClass *pcc, uint32_t pvr, bool best) 6672 { 6673 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK; 6674 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK; 6675 6676 if (!best && (base == CPU_POWERPC_POWER11_BASE)) { 6677 return true; 6678 } 6679 6680 if (base != pcc_base) { 6681 return false; 6682 } 6683 6684 if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) { 6685 return true; 6686 } 6687 6688 return false; 6689 } 6690 6691 POWERPC_FAMILY(POWER11)(ObjectClass *oc, const void *data) 6692 { 6693 DeviceClass *dc = DEVICE_CLASS(oc); 6694 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6695 6696 dc->fw_name = "PowerPC,POWER11"; 6697 dc->desc = "POWER11"; 6698 pcc->spapr_logical_pvr = CPU_POWERPC_LOGICAL_3_10_P11; 6699 pcc->pvr_match = ppc_pvr_match_power11; 6700 pcc->pcr_mask = PPC_PCR_MASK_POWER11; 6701 pcc->pcr_supported = PPC_PCR_SUPPORTED_POWER11; 6702 pcc->init_proc = init_proc_POWER11; 6703 pcc->check_pow = check_pow_nocheck; 6704 pcc->check_attn = check_attn_hid0_power9; 6705 pcc->insns_flags = PPC_INSNS_FLAGS_POWER11; 6706 pcc->insns_flags2 = PPC_INSNS_FLAGS2_POWER11; 6707 pcc->msr_mask = PPC_MSR_MASK_POWER11; 6708 pcc->lpcr_mask = PPC_LPCR_MASK_POWER11; 6709 6710 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 6711 pcc->mmu_model = POWERPC_MMU_3_00; 6712 #if !defined(CONFIG_USER_ONLY) 6713 /* segment page size remain the same */ 6714 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6715 pcc->radix_page_info = &POWER10_radix_page_info; 6716 pcc->lrg_decr_bits = 56; 6717 #endif 6718 pcc->excp_model = POWERPC_EXCP_POWER11; 6719 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 6720 pcc->bfd_mach = bfd_mach_ppc64; 6721 pcc->flags = POWERPC_FLAGS_POWER11; 6722 pcc->l1_dcache_size = 0x8000; 6723 pcc->l1_icache_size = 0x8000; 6724 } 6725 6726 #if !defined(CONFIG_USER_ONLY) 6727 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) 6728 { 6729 CPUPPCState *env = &cpu->env; 6730 6731 cpu->vhyp = vhyp; 6732 cpu->vhyp_class = PPC_VIRTUAL_HYPERVISOR_GET_CLASS(vhyp); 6733 6734 /* 6735 * With a virtual hypervisor mode we never allow the CPU to go 6736 * hypervisor mode itself 6737 */ 6738 env->msr_mask &= ~MSR_HVB; 6739 } 6740 6741 void cpu_ppc_set_1lpar(PowerPCCPU *cpu) 6742 { 6743 CPUPPCState *env = &cpu->env; 6744 6745 /* 6746 * pseries SMT means "LPAR per core" mode, e.g., msgsndp is usable 6747 * between threads. powernv be in either mode, and it mostly affects 6748 * supervisor visible registers and instructions. 6749 */ 6750 if (env->flags & POWERPC_FLAG_SMT) { 6751 env->flags |= POWERPC_FLAG_SMT_1LPAR; 6752 } 6753 } 6754 #endif /* !defined(CONFIG_USER_ONLY) */ 6755 6756 #endif /* defined(TARGET_PPC64) */ 6757 6758 /*****************************************************************************/ 6759 /* Generic CPU instantiation routine */ 6760 static void init_ppc_proc(PowerPCCPU *cpu) 6761 { 6762 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 6763 CPUPPCState *env = &cpu->env; 6764 #if !defined(CONFIG_USER_ONLY) 6765 int i; 6766 6767 /* Set all exception vectors to an invalid address */ 6768 for (i = 0; i < POWERPC_EXCP_NB; i++) { 6769 env->excp_vectors[i] = (target_ulong)(-1ULL); 6770 } 6771 env->ivor_mask = 0x00000000; 6772 env->ivpr_mask = 0x00000000; 6773 /* Default MMU definitions */ 6774 env->nb_BATs = 0; 6775 env->nb_tlb = 0; 6776 env->nb_ways = 0; 6777 env->tlb_type = TLB_NONE; 6778 #endif 6779 /* Register SPR common to all PowerPC implementations */ 6780 register_generic_sprs(cpu); 6781 6782 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */ 6783 (*pcc->init_proc)(env); 6784 6785 /* MSR bits & flags consistency checks */ 6786 if (env->msr_mask & (1 << 25)) { 6787 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE | 6788 POWERPC_FLAG_PPE42)) { 6789 case POWERPC_FLAG_SPE: 6790 case POWERPC_FLAG_VRE: 6791 case POWERPC_FLAG_PPE42: 6792 break; 6793 default: 6794 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6795 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n" 6796 "or POWERPC_FLAG_PPE42\n"); 6797 exit(1); 6798 } 6799 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE | 6800 POWERPC_FLAG_PPE42)) { 6801 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6802 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n" 6803 "nor POWERPC_FLAG_PPE42\n"); 6804 exit(1); 6805 } 6806 if (env->msr_mask & (1 << 17)) { 6807 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE | 6808 POWERPC_FLAG_PPE42)) { 6809 case POWERPC_FLAG_TGPR: 6810 case POWERPC_FLAG_CE: 6811 case POWERPC_FLAG_PPE42: 6812 break; 6813 default: 6814 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6815 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n" 6816 "or POWERPC_FLAG_PPE42\n"); 6817 exit(1); 6818 } 6819 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE | 6820 POWERPC_FLAG_PPE42)) { 6821 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6822 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n" 6823 "nor POWERPC_FLAG_PPE42\n"); 6824 exit(1); 6825 } 6826 if (env->msr_mask & (1 << 10)) { 6827 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 6828 POWERPC_FLAG_UBLE | POWERPC_FLAG_PPE42)) { 6829 case POWERPC_FLAG_SE: 6830 case POWERPC_FLAG_DWE: 6831 case POWERPC_FLAG_UBLE: 6832 case POWERPC_FLAG_PPE42: 6833 break; 6834 default: 6835 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6836 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or " 6837 "POWERPC_FLAG_UBLE or POWERPC_FLAG_PPE42\n"); 6838 exit(1); 6839 } 6840 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 6841 POWERPC_FLAG_UBLE | POWERPC_FLAG_PPE42)) { 6842 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6843 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor " 6844 "POWERPC_FLAG_UBLE nor POWERPC_FLAG_PPE42\n"); 6845 exit(1); 6846 } 6847 if (env->msr_mask & (1 << 9)) { 6848 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 6849 case POWERPC_FLAG_BE: 6850 case POWERPC_FLAG_DE: 6851 break; 6852 default: 6853 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6854 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n"); 6855 exit(1); 6856 } 6857 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 6858 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6859 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n"); 6860 exit(1); 6861 } 6862 if (env->msr_mask & (1 << 2)) { 6863 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM | 6864 POWERPC_FLAG_PPE42)) { 6865 case POWERPC_FLAG_PX: 6866 case POWERPC_FLAG_PMM: 6867 case POWERPC_FLAG_PPE42: 6868 break; 6869 default: 6870 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6871 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n" 6872 "or POWERPC_FLAG_PPE42\n"); 6873 exit(1); 6874 } 6875 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM | 6876 POWERPC_FLAG_PPE42)) { 6877 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6878 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n" 6879 "nor POWERPC_FLAG_PPE42\n"); 6880 exit(1); 6881 } 6882 if ((env->flags & POWERPC_FLAG_BUS_CLK) == 0) { 6883 fprintf(stderr, "PowerPC flags inconsistency\n" 6884 "Should define the time-base and decrementer clock source\n"); 6885 exit(1); 6886 } 6887 /* Allocate TLBs buffer when needed */ 6888 #if !defined(CONFIG_USER_ONLY) 6889 if (env->nb_tlb) { 6890 switch (env->tlb_type) { 6891 case TLB_6XX: 6892 /* 6xx has separate TLBs for instructions and data hence times 2 */ 6893 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, 2 * env->nb_tlb); 6894 break; 6895 case TLB_EMB: 6896 env->tlb.tlbe = g_new0(ppcemb_tlb_t, env->nb_tlb); 6897 break; 6898 case TLB_MAS: 6899 env->tlb.tlbm = g_new0(ppcmas_tlb_t, env->nb_tlb); 6900 break; 6901 } 6902 /* Pre-compute some useful values */ 6903 env->tlb_per_way = env->nb_tlb / env->nb_ways; 6904 } 6905 #endif 6906 if (env->check_pow == NULL) { 6907 warn_report("no power management check handler registered." 6908 " Attempt QEMU to crash very soon !"); 6909 } 6910 6911 if (env->check_attn == NULL) { 6912 warn_report("no attn check handler registered." 6913 " Attempt QEMU to crash very soon !"); 6914 } 6915 } 6916 6917 6918 static void ppc_cpu_realize(DeviceState *dev, Error **errp) 6919 { 6920 CPUState *cs = CPU(dev); 6921 PowerPCCPU *cpu = POWERPC_CPU(dev); 6922 CPUPPCState *env = &cpu->env; 6923 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 6924 Error *local_err = NULL; 6925 6926 cpu_exec_realizefn(cs, &local_err); 6927 if (local_err != NULL) { 6928 error_propagate(errp, local_err); 6929 return; 6930 } 6931 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) { 6932 cpu->vcpu_id = cs->cpu_index; 6933 } 6934 6935 if (tcg_enabled()) { 6936 if (ppc_fixup_cpu(cpu) != 0) { 6937 error_setg(errp, "Unable to emulate selected CPU with TCG"); 6938 goto unrealize; 6939 } 6940 } 6941 6942 create_ppc_opcodes(cpu, &local_err); 6943 if (local_err != NULL) { 6944 error_propagate(errp, local_err); 6945 goto unrealize; 6946 } 6947 init_ppc_proc(cpu); 6948 6949 ppc_gdb_init(cs, pcc); 6950 qemu_init_vcpu(cs); 6951 6952 pcc->parent_realize(dev, errp); 6953 6954 if (!ppc_cpu_core_single_threaded(cs)) { 6955 env->flags |= POWERPC_FLAG_SMT; 6956 } 6957 6958 return; 6959 6960 unrealize: 6961 cpu_exec_unrealizefn(cs); 6962 } 6963 6964 static void ppc_cpu_unrealize(DeviceState *dev) 6965 { 6966 PowerPCCPU *cpu = POWERPC_CPU(dev); 6967 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 6968 6969 pcc->parent_unrealize(dev); 6970 6971 cpu_remove_sync(CPU(cpu)); 6972 6973 destroy_ppc_opcodes(cpu); 6974 } 6975 6976 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b) 6977 { 6978 ObjectClass *oc = (ObjectClass *)a; 6979 uint32_t pvr = *(uint32_t *)b; 6980 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 6981 6982 /* -cpu host does a PVR lookup during construction */ 6983 if (unlikely(strcmp(object_class_get_name(oc), 6984 TYPE_HOST_POWERPC_CPU) == 0)) { 6985 return -1; 6986 } 6987 6988 return pcc->pvr == pvr ? 0 : -1; 6989 } 6990 6991 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr) 6992 { 6993 GSList *list, *item; 6994 PowerPCCPUClass *pcc = NULL; 6995 6996 list = object_class_get_list(TYPE_POWERPC_CPU, false); 6997 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr); 6998 if (item != NULL) { 6999 pcc = POWERPC_CPU_CLASS(item->data); 7000 } 7001 g_slist_free(list); 7002 7003 return pcc; 7004 } 7005 7006 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b) 7007 { 7008 ObjectClass *oc = (ObjectClass *)a; 7009 uint32_t pvr = *(uint32_t *)b; 7010 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 7011 7012 /* -cpu host does a PVR lookup during construction */ 7013 if (unlikely(strcmp(object_class_get_name(oc), 7014 TYPE_HOST_POWERPC_CPU) == 0)) { 7015 return -1; 7016 } 7017 7018 if (pcc->pvr_match(pcc, pvr, true)) { 7019 return 0; 7020 } 7021 7022 return -1; 7023 } 7024 7025 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr) 7026 { 7027 GSList *list, *item; 7028 PowerPCCPUClass *pcc = NULL; 7029 7030 list = object_class_get_list(TYPE_POWERPC_CPU, true); 7031 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask); 7032 if (item != NULL) { 7033 pcc = POWERPC_CPU_CLASS(item->data); 7034 } 7035 g_slist_free(list); 7036 7037 return pcc; 7038 } 7039 7040 static const char *ppc_cpu_lookup_alias(const char *alias) 7041 { 7042 int ai; 7043 7044 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) { 7045 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) { 7046 return ppc_cpu_aliases[ai].model; 7047 } 7048 } 7049 7050 return NULL; 7051 } 7052 7053 ObjectClass *ppc_cpu_class_by_name(const char *name) 7054 { 7055 char *cpu_model, *typename; 7056 ObjectClass *oc; 7057 const char *p; 7058 unsigned long pvr; 7059 7060 /* 7061 * Lookup by PVR if cpu_model is valid 8 digit hex number (excl: 7062 * 0x prefix if present) 7063 */ 7064 if (!qemu_strtoul(name, &p, 16, &pvr)) { 7065 int len = p - name; 7066 len = (len == 10) && (name[1] == 'x') ? len - 2 : len; 7067 if ((len == 8) && (*p == '\0')) { 7068 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr)); 7069 } 7070 } 7071 7072 /* 7073 * All ppc CPUs represent hardware that exists in the real world, i.e.: we 7074 * do not have a "max" CPU with all possible emulated features enabled. 7075 * Return the default CPU type for the machine because that has greater 7076 * chance of being useful as the "max" CPU. 7077 */ 7078 #if !defined(CONFIG_USER_ONLY) 7079 if (strcmp(name, "max") == 0) { 7080 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 7081 if (mc) { 7082 return object_class_by_name(machine_class_default_cpu_type(mc)); 7083 } 7084 } 7085 #endif 7086 7087 cpu_model = g_ascii_strdown(name, -1); 7088 p = ppc_cpu_lookup_alias(cpu_model); 7089 if (p) { 7090 g_free(cpu_model); 7091 cpu_model = g_strdup(p); 7092 } 7093 7094 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model); 7095 oc = object_class_by_name(typename); 7096 g_free(typename); 7097 g_free(cpu_model); 7098 7099 return oc; 7100 } 7101 7102 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc) 7103 { 7104 ObjectClass *oc = OBJECT_CLASS(pcc); 7105 7106 while (oc && !object_class_is_abstract(oc)) { 7107 oc = object_class_get_parent(oc); 7108 } 7109 assert(oc); 7110 7111 return POWERPC_CPU_CLASS(oc); 7112 } 7113 7114 /* Sort by PVR, ordering special case "host" last. */ 7115 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b, gpointer d) 7116 { 7117 ObjectClass *oc_a = (ObjectClass *)a; 7118 ObjectClass *oc_b = (ObjectClass *)b; 7119 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a); 7120 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b); 7121 const char *name_a = object_class_get_name(oc_a); 7122 const char *name_b = object_class_get_name(oc_b); 7123 7124 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) { 7125 return 1; 7126 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) { 7127 return -1; 7128 } else { 7129 /* Avoid an integer overflow during subtraction */ 7130 if (pcc_a->pvr < pcc_b->pvr) { 7131 return -1; 7132 } else if (pcc_a->pvr > pcc_b->pvr) { 7133 return 1; 7134 } else { 7135 return 0; 7136 } 7137 } 7138 } 7139 7140 static void ppc_cpu_list_entry(gpointer data, gpointer user_data) 7141 { 7142 ObjectClass *oc = data; 7143 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7144 CPUClass *cc = CPU_CLASS(oc); 7145 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc)); 7146 const char *typename = object_class_get_name(oc); 7147 char *name; 7148 int i; 7149 7150 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) { 7151 return; 7152 } 7153 7154 name = cpu_model_from_type(typename); 7155 if (cc->deprecation_note) { 7156 qemu_printf(" %-16s PVR %08x (deprecated)\n", name, pcc->pvr); 7157 } else { 7158 qemu_printf(" %-16s PVR %08x\n", name, pcc->pvr); 7159 } 7160 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 7161 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 7162 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model); 7163 7164 if (alias_oc != oc) { 7165 continue; 7166 } 7167 /* 7168 * If running with KVM, we might update the family alias later, so 7169 * avoid printing the wrong alias here and use "preferred" instead 7170 */ 7171 if (strcmp(alias->alias, family->desc) == 0) { 7172 qemu_printf(" %-16s (alias for preferred %s CPU)\n", 7173 alias->alias, family->desc); 7174 } else { 7175 qemu_printf(" %-16s (alias for %s)\n", 7176 alias->alias, name); 7177 } 7178 } 7179 g_free(name); 7180 } 7181 7182 static void ppc_cpu_list(void) 7183 { 7184 GSList *list; 7185 7186 qemu_printf("Available CPUs:\n"); 7187 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7188 list = g_slist_sort_with_data(list, ppc_cpu_list_compare, NULL); 7189 g_slist_foreach(list, ppc_cpu_list_entry, NULL); 7190 g_slist_free(list); 7191 7192 #ifdef CONFIG_KVM 7193 qemu_printf("\n"); 7194 qemu_printf(" %s\n", "host"); 7195 #endif 7196 } 7197 7198 static void ppc_cpu_set_pc(CPUState *cs, vaddr value) 7199 { 7200 PowerPCCPU *cpu = POWERPC_CPU(cs); 7201 7202 cpu->env.nip = value; 7203 } 7204 7205 static vaddr ppc_cpu_get_pc(CPUState *cs) 7206 { 7207 PowerPCCPU *cpu = POWERPC_CPU(cs); 7208 7209 return cpu->env.nip; 7210 } 7211 7212 #ifdef CONFIG_TCG 7213 static void ppc_restore_state_to_opc(CPUState *cs, 7214 const TranslationBlock *tb, 7215 const uint64_t *data) 7216 { 7217 PowerPCCPU *cpu = POWERPC_CPU(cs); 7218 7219 cpu->env.nip = data[0]; 7220 } 7221 7222 static int ppc_cpu_mmu_index(CPUState *cs, bool ifetch) 7223 { 7224 return ppc_env_mmu_index(cpu_env(cs), ifetch); 7225 } 7226 #endif /* CONFIG_TCG */ 7227 7228 #ifndef CONFIG_USER_ONLY 7229 static bool ppc_cpu_has_work(CPUState *cs) 7230 { 7231 return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD); 7232 } 7233 #endif /* !CONFIG_USER_ONLY */ 7234 7235 static void ppc_cpu_reset_hold(Object *obj, ResetType type) 7236 { 7237 CPUState *cs = CPU(obj); 7238 PowerPCCPU *cpu = POWERPC_CPU(cs); 7239 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(obj); 7240 CPUPPCState *env = &cpu->env; 7241 target_ulong msr; 7242 int i; 7243 7244 if (pcc->parent_phases.hold) { 7245 pcc->parent_phases.hold(obj, type); 7246 } 7247 7248 msr = (target_ulong)0; 7249 if (!(env->flags & POWERPC_FLAG_PPE42)) { 7250 msr |= (target_ulong)MSR_HVB; 7251 msr |= (target_ulong)1 << MSR_EP; 7252 #if defined(DO_SINGLE_STEP) && 0 7253 /* Single step trace mode */ 7254 msr |= (target_ulong)1 << MSR_SE; 7255 msr |= (target_ulong)1 << MSR_BE; 7256 #endif 7257 #if defined(CONFIG_USER_ONLY) 7258 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ 7259 msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */ 7260 msr |= (target_ulong)1 << MSR_FE1; 7261 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */ 7262 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */ 7263 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */ 7264 msr |= (target_ulong)1 << MSR_PR; 7265 #if defined(TARGET_PPC64) 7266 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */ 7267 #endif 7268 #if !TARGET_BIG_ENDIAN 7269 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */ 7270 if (!((env->msr_mask >> MSR_LE) & 1)) { 7271 fprintf(stderr, "Selected CPU does not support little-endian.\n"); 7272 exit(1); 7273 } 7274 #endif 7275 #endif 7276 7277 #if defined(TARGET_PPC64) 7278 if (mmu_is_64bit(env->mmu_model)) { 7279 msr |= (1ULL << MSR_SF); 7280 } 7281 #endif 7282 } 7283 hreg_store_msr(env, msr, 1); 7284 7285 #if !defined(CONFIG_USER_ONLY) 7286 env->nip = env->hreset_vector | env->excp_prefix; 7287 7288 if (tcg_enabled()) { 7289 cpu_breakpoint_remove_all(cs, BP_CPU); 7290 cpu_watchpoint_remove_all(cs, BP_CPU); 7291 if (env->mmu_model != POWERPC_MMU_REAL) { 7292 ppc_tlb_invalidate_all(env); 7293 } 7294 pmu_mmcr01a_updated(env); 7295 } 7296 7297 /* clean any pending stop state */ 7298 env->resume_as_sreset = 0; 7299 #endif 7300 hreg_compute_hflags(env); 7301 env->reserve_addr = (target_ulong)-1ULL; 7302 /* Be sure no exception or interrupt is pending */ 7303 env->pending_interrupts = 0; 7304 cs->exception_index = POWERPC_EXCP_NONE; 7305 env->error_code = 0; 7306 ppc_irq_reset(cpu); 7307 7308 /* tininess for underflow is detected before rounding */ 7309 set_float_detect_tininess(float_tininess_before_rounding, 7310 &env->fp_status); 7311 /* Similarly for flush-to-zero */ 7312 set_float_ftz_detection(float_ftz_before_rounding, &env->fp_status); 7313 7314 /* 7315 * PowerPC propagation rules: 7316 * 1. A if it sNaN or qNaN 7317 * 2. B if it sNaN or qNaN 7318 * A signaling NaN is always silenced before returning it. 7319 */ 7320 set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status); 7321 set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status); 7322 /* 7323 * NaN propagation for fused multiply-add: 7324 * if fRA is a NaN return it; otherwise if fRB is a NaN return it; 7325 * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB 7326 * whereas QEMU labels the operands as (a * b) + c. 7327 */ 7328 set_float_3nan_prop_rule(float_3nan_prop_acb, &env->fp_status); 7329 set_float_3nan_prop_rule(float_3nan_prop_acb, &env->vec_status); 7330 /* 7331 * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer 7332 * to return an input NaN if we have one (ie c) rather than generating 7333 * a default NaN 7334 */ 7335 set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); 7336 set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status); 7337 7338 /* Default NaN: sign bit clear, set frac msb */ 7339 set_float_default_nan_pattern(0b01000000, &env->fp_status); 7340 set_float_default_nan_pattern(0b01000000, &env->vec_status); 7341 7342 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { 7343 ppc_spr_t *spr = &env->spr_cb[i]; 7344 7345 if (!spr->name) { 7346 continue; 7347 } 7348 env->spr[i] = spr->default_value; 7349 } 7350 7351 #if defined(TARGET_PPC64) 7352 bhrb_reset_state(env); 7353 #endif 7354 } 7355 7356 #ifndef CONFIG_USER_ONLY 7357 7358 static bool ppc_cpu_is_big_endian(CPUState *cs) 7359 { 7360 cpu_synchronize_state(cs); 7361 7362 return !FIELD_EX64(cpu_env(cs)->msr, MSR, LE); 7363 } 7364 7365 static bool ppc_get_irq_stats(InterruptStatsProvider *obj, 7366 uint64_t **irq_counts, unsigned int *nb_irqs) 7367 { 7368 CPUPPCState *env = &POWERPC_CPU(obj)->env; 7369 7370 *irq_counts = env->excp_stats; 7371 *nb_irqs = ARRAY_SIZE(env->excp_stats); 7372 return true; 7373 } 7374 7375 #ifdef CONFIG_TCG 7376 static void ppc_cpu_exec_enter(CPUState *cs) 7377 { 7378 PowerPCCPU *cpu = POWERPC_CPU(cs); 7379 7380 if (cpu->vhyp) { 7381 cpu->vhyp_class->cpu_exec_enter(cpu->vhyp, cpu); 7382 } 7383 } 7384 7385 static void ppc_cpu_exec_exit(CPUState *cs) 7386 { 7387 PowerPCCPU *cpu = POWERPC_CPU(cs); 7388 7389 if (cpu->vhyp) { 7390 cpu->vhyp_class->cpu_exec_exit(cpu->vhyp, cpu); 7391 } 7392 } 7393 7394 static vaddr ppc_pointer_wrap(CPUState *cs, int mmu_idx, 7395 vaddr result, vaddr base) 7396 { 7397 return (cpu_env(cs)->hflags >> HFLAGS_64) & 1 ? result : (uint32_t)result; 7398 } 7399 #endif /* CONFIG_TCG */ 7400 7401 #endif /* !CONFIG_USER_ONLY */ 7402 7403 static void ppc_cpu_instance_init(Object *obj) 7404 { 7405 PowerPCCPU *cpu = POWERPC_CPU(obj); 7406 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7407 CPUPPCState *env = &cpu->env; 7408 7409 cpu->vcpu_id = UNASSIGNED_CPU_INDEX; 7410 7411 env->msr_mask = pcc->msr_mask; 7412 env->mmu_model = pcc->mmu_model; 7413 env->excp_model = pcc->excp_model; 7414 env->bus_model = pcc->bus_model; 7415 env->insns_flags = pcc->insns_flags; 7416 env->insns_flags2 = pcc->insns_flags2; 7417 env->flags = pcc->flags; 7418 env->bfd_mach = pcc->bfd_mach; 7419 env->check_pow = pcc->check_pow; 7420 env->check_attn = pcc->check_attn; 7421 7422 /* 7423 * Mark HV mode as supported if the CPU has an MSR_HV bit in the 7424 * msr_mask. The mask can later be cleared by PAPR mode but the hv 7425 * mode support will remain, thus enforcing that we cannot use 7426 * priv. instructions in guest in PAPR mode. For 970 we currently 7427 * simply don't set HV in msr_mask thus simulating an "Apple mode" 7428 * 970. If we ever want to support 970 HV mode, we'll have to add 7429 * a processor attribute of some sort. 7430 */ 7431 #if !defined(CONFIG_USER_ONLY) 7432 env->has_hv_mode = !!(env->msr_mask & MSR_HVB); 7433 #endif 7434 7435 ppc_hash64_init(cpu); 7436 } 7437 7438 static void ppc_cpu_instance_finalize(Object *obj) 7439 { 7440 PowerPCCPU *cpu = POWERPC_CPU(obj); 7441 7442 ppc_hash64_finalize(cpu); 7443 } 7444 7445 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr, bool best) 7446 { 7447 return pcc->pvr == pvr; 7448 } 7449 7450 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info) 7451 { 7452 CPUPPCState *env = cpu_env(cs); 7453 7454 if ((env->hflags >> MSR_LE) & 1) { 7455 info->endian = BFD_ENDIAN_LITTLE; 7456 } else { 7457 info->endian = BFD_ENDIAN_BIG; 7458 } 7459 info->mach = env->bfd_mach; 7460 if (!env->bfd_mach) { 7461 #ifdef TARGET_PPC64 7462 info->mach = bfd_mach_ppc64; 7463 #else 7464 info->mach = bfd_mach_ppc; 7465 #endif 7466 } 7467 7468 info->cap_arch = CS_ARCH_PPC; 7469 #ifdef TARGET_PPC64 7470 info->cap_mode = CS_MODE_64; 7471 #endif 7472 } 7473 7474 #ifndef CONFIG_USER_ONLY 7475 #include "hw/core/sysemu-cpu-ops.h" 7476 7477 static const struct SysemuCPUOps ppc_sysemu_ops = { 7478 .has_work = ppc_cpu_has_work, 7479 .get_phys_page_debug = ppc_cpu_get_phys_page_debug, 7480 .write_elf32_note = ppc32_cpu_write_elf32_note, 7481 .write_elf64_note = ppc64_cpu_write_elf64_note, 7482 .virtio_is_big_endian = ppc_cpu_is_big_endian, 7483 .legacy_vmsd = &vmstate_ppc_cpu, 7484 }; 7485 #endif 7486 7487 #ifdef CONFIG_TCG 7488 #include "accel/tcg/cpu-ops.h" 7489 7490 static const TCGCPUOps ppc_tcg_ops = { 7491 .mttcg_supported = TARGET_LONG_BITS == 64, 7492 .guest_default_memory_order = 0, 7493 .initialize = ppc_translate_init, 7494 .translate_code = ppc_translate_code, 7495 .get_tb_cpu_state = ppc_get_tb_cpu_state, 7496 .restore_state_to_opc = ppc_restore_state_to_opc, 7497 .mmu_index = ppc_cpu_mmu_index, 7498 7499 #ifdef CONFIG_USER_ONLY 7500 .record_sigsegv = ppc_cpu_record_sigsegv, 7501 #else 7502 .tlb_fill = ppc_cpu_tlb_fill, 7503 .pointer_wrap = ppc_pointer_wrap, 7504 .cpu_exec_interrupt = ppc_cpu_exec_interrupt, 7505 .cpu_exec_halt = ppc_cpu_has_work, 7506 .cpu_exec_reset = cpu_reset, 7507 .do_interrupt = ppc_cpu_do_interrupt, 7508 .cpu_exec_enter = ppc_cpu_exec_enter, 7509 .cpu_exec_exit = ppc_cpu_exec_exit, 7510 .do_unaligned_access = ppc_cpu_do_unaligned_access, 7511 .do_transaction_failed = ppc_cpu_do_transaction_failed, 7512 .debug_excp_handler = ppc_cpu_debug_excp_handler, 7513 .debug_check_breakpoint = ppc_cpu_debug_check_breakpoint, 7514 .debug_check_watchpoint = ppc_cpu_debug_check_watchpoint, 7515 #endif /* !CONFIG_USER_ONLY */ 7516 }; 7517 #endif /* CONFIG_TCG */ 7518 7519 static void ppc_cpu_class_init(ObjectClass *oc, const void *data) 7520 { 7521 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7522 CPUClass *cc = CPU_CLASS(oc); 7523 DeviceClass *dc = DEVICE_CLASS(oc); 7524 ResettableClass *rc = RESETTABLE_CLASS(oc); 7525 7526 device_class_set_parent_realize(dc, ppc_cpu_realize, 7527 &pcc->parent_realize); 7528 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize, 7529 &pcc->parent_unrealize); 7530 pcc->pvr_match = ppc_pvr_match_default; 7531 7532 resettable_class_set_parent_phases(rc, NULL, ppc_cpu_reset_hold, NULL, 7533 &pcc->parent_phases); 7534 7535 cc->class_by_name = ppc_cpu_class_by_name; 7536 cc->list_cpus = ppc_cpu_list; 7537 cc->dump_state = ppc_cpu_dump_state; 7538 cc->set_pc = ppc_cpu_set_pc; 7539 cc->get_pc = ppc_cpu_get_pc; 7540 cc->gdb_read_register = ppc_cpu_gdb_read_register; 7541 cc->gdb_write_register = ppc_cpu_gdb_write_register; 7542 #ifndef CONFIG_USER_ONLY 7543 cc->sysemu_ops = &ppc_sysemu_ops; 7544 INTERRUPT_STATS_PROVIDER_CLASS(oc)->get_statistics = ppc_get_irq_stats; 7545 7546 /* check_prot_access_type relies on MMU access and PAGE bits relations */ 7547 qemu_build_assert(MMU_DATA_LOAD == 0 && MMU_DATA_STORE == 1 && 7548 MMU_INST_FETCH == 2 && PAGE_READ == 1 && 7549 PAGE_WRITE == 2 && PAGE_EXEC == 4); 7550 #endif 7551 7552 cc->gdb_num_core_regs = 71; 7553 #ifdef USE_APPLE_GDB 7554 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple; 7555 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple; 7556 cc->gdb_num_core_regs = 71 + 32; 7557 #endif 7558 7559 cc->gdb_arch_name = ppc_gdb_arch_name; 7560 #if defined(TARGET_PPC64) 7561 cc->gdb_core_xml_file = "power64-core.xml"; 7562 #else 7563 cc->gdb_core_xml_file = "power-core.xml"; 7564 #endif 7565 cc->disas_set_info = ppc_disas_set_info; 7566 7567 dc->fw_name = "PowerPC,UNKNOWN"; 7568 7569 #ifdef CONFIG_TCG 7570 cc->tcg_ops = &ppc_tcg_ops; 7571 #endif /* CONFIG_TCG */ 7572 } 7573 7574 static const TypeInfo ppc_cpu_type_info = { 7575 .name = TYPE_POWERPC_CPU, 7576 .parent = TYPE_CPU, 7577 .instance_size = sizeof(PowerPCCPU), 7578 .instance_align = __alignof__(PowerPCCPU), 7579 .instance_init = ppc_cpu_instance_init, 7580 .instance_finalize = ppc_cpu_instance_finalize, 7581 .abstract = true, 7582 .class_size = sizeof(PowerPCCPUClass), 7583 .class_init = ppc_cpu_class_init, 7584 #ifndef CONFIG_USER_ONLY 7585 .interfaces = (const InterfaceInfo[]) { 7586 { TYPE_INTERRUPT_STATS_PROVIDER }, 7587 { } 7588 }, 7589 #endif 7590 }; 7591 7592 #ifndef CONFIG_USER_ONLY 7593 static const TypeInfo ppc_vhyp_type_info = { 7594 .name = TYPE_PPC_VIRTUAL_HYPERVISOR, 7595 .parent = TYPE_INTERFACE, 7596 .class_size = sizeof(PPCVirtualHypervisorClass), 7597 }; 7598 #endif 7599 7600 static void ppc_cpu_register_types(void) 7601 { 7602 type_register_static(&ppc_cpu_type_info); 7603 #ifndef CONFIG_USER_ONLY 7604 type_register_static(&ppc_vhyp_type_info); 7605 #endif 7606 } 7607 7608 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) 7609 { 7610 #define RGPL 4 7611 #define RFPL 4 7612 7613 CPUPPCState *env = cpu_env(cs); 7614 int i; 7615 7616 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " 7617 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", 7618 env->nip, env->lr, env->ctr, cpu_read_xer(env), 7619 cs->cpu_index); 7620 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " 7621 "%08x iidx %d didx %d\n", 7622 env->msr, env->spr[SPR_HID0], env->hflags, 7623 ppc_env_mmu_index(env, true), ppc_env_mmu_index(env, false)); 7624 #if !defined(CONFIG_USER_ONLY) 7625 if (env->tb_env) { 7626 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 7627 " DECR " TARGET_FMT_lu "\n", cpu_ppc_load_tbu(env), 7628 cpu_ppc_load_tbl(env), cpu_ppc_load_decr(env)); 7629 } 7630 #else 7631 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 "\n", cpu_ppc_load_tbu(env), 7632 cpu_ppc_load_tbl(env)); 7633 #endif 7634 for (i = 0; i < 32; i++) { 7635 if ((i & (RGPL - 1)) == 0) { 7636 qemu_fprintf(f, "GPR%02d", i); 7637 } 7638 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); 7639 if ((i & (RGPL - 1)) == (RGPL - 1)) { 7640 qemu_fprintf(f, "\n"); 7641 } 7642 } 7643 qemu_fprintf(f, "CR "); 7644 for (i = 0; i < 8; i++) 7645 qemu_fprintf(f, "%01x", env->crf[i]); 7646 qemu_fprintf(f, " ["); 7647 for (i = 0; i < 8; i++) { 7648 char a = '-'; 7649 if (env->crf[i] & 0x08) { 7650 a = 'L'; 7651 } else if (env->crf[i] & 0x04) { 7652 a = 'G'; 7653 } else if (env->crf[i] & 0x02) { 7654 a = 'E'; 7655 } 7656 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); 7657 } 7658 qemu_fprintf(f, " ] RES %03x@" TARGET_FMT_lx "\n", 7659 (int)env->reserve_length, env->reserve_addr); 7660 7661 if (flags & CPU_DUMP_FPU) { 7662 for (i = 0; i < 32; i++) { 7663 if ((i & (RFPL - 1)) == 0) { 7664 qemu_fprintf(f, "FPR%02d", i); 7665 } 7666 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i)); 7667 if ((i & (RFPL - 1)) == (RFPL - 1)) { 7668 qemu_fprintf(f, "\n"); 7669 } 7670 } 7671 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); 7672 } 7673 7674 #if !defined(CONFIG_USER_ONLY) 7675 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx 7676 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", 7677 env->spr[SPR_SRR0], env->spr[SPR_SRR1], 7678 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); 7679 7680 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx 7681 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", 7682 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], 7683 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); 7684 7685 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx 7686 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", 7687 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], 7688 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); 7689 7690 switch (env->excp_model) { 7691 #if defined(TARGET_PPC64) 7692 case POWERPC_EXCP_POWER7: 7693 case POWERPC_EXCP_POWER8: 7694 case POWERPC_EXCP_POWER9: 7695 case POWERPC_EXCP_POWER10: 7696 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", 7697 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 7698 break; 7699 #endif 7700 case POWERPC_EXCP_BOOKE: 7701 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx 7702 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", 7703 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], 7704 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 7705 7706 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 7707 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 7708 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], 7709 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); 7710 7711 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx 7712 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", 7713 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], 7714 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); 7715 7716 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx 7717 " EPR " TARGET_FMT_lx "\n", 7718 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], 7719 env->spr[SPR_BOOKE_EPR]); 7720 7721 /* FSL-specific */ 7722 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx 7723 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", 7724 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], 7725 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); 7726 7727 /* 7728 * IVORs are left out as they are large and do not change often -- 7729 * they can be read with "p $ivor0", "p $ivor1", etc. 7730 */ 7731 break; 7732 case POWERPC_EXCP_PPE42: 7733 qemu_fprintf(f, "SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx "\n", 7734 env->spr[SPR_SRR0], env->spr[SPR_SRR1]); 7735 7736 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 7737 " ISR " TARGET_FMT_lx " EDR " TARGET_FMT_lx "\n", 7738 env->spr[SPR_PPE42_TCR], env->spr[SPR_PPE42_TSR], 7739 env->spr[SPR_PPE42_ISR], env->spr[SPR_PPE42_EDR]); 7740 7741 qemu_fprintf(f, " PIR " TARGET_FMT_lx " IVPR " TARGET_FMT_lx "\n", 7742 env->spr[SPR_PPE42_PIR], env->spr[SPR_PPE42_IVPR]); 7743 break; 7744 case POWERPC_EXCP_40x: 7745 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 7746 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 7747 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], 7748 env->spr[SPR_40x_ESR], env->spr[SPR_40x_DEAR]); 7749 7750 qemu_fprintf(f, " EVPR " TARGET_FMT_lx " SRR2 " TARGET_FMT_lx 7751 " SRR3 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 7752 env->spr[SPR_40x_EVPR], env->spr[SPR_40x_SRR2], 7753 env->spr[SPR_40x_SRR3], env->spr[SPR_40x_PID]); 7754 break; 7755 default: 7756 break; 7757 } 7758 7759 #if defined(TARGET_PPC64) 7760 if (env->flags & POWERPC_FLAG_CFAR) { 7761 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); 7762 } 7763 #endif 7764 7765 if (env->spr_cb[SPR_LPCR].name) { 7766 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); 7767 } 7768 7769 switch (env->mmu_model) { 7770 case POWERPC_MMU_32B: 7771 case POWERPC_MMU_SOFT_6xx: 7772 #if defined(TARGET_PPC64) 7773 case POWERPC_MMU_64B: 7774 case POWERPC_MMU_2_03: 7775 case POWERPC_MMU_2_06: 7776 case POWERPC_MMU_2_07: 7777 case POWERPC_MMU_3_00: 7778 #endif 7779 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ 7780 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); 7781 } 7782 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ 7783 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]); 7784 } 7785 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", 7786 env->spr[SPR_DAR], env->spr[SPR_DSISR]); 7787 break; 7788 case POWERPC_MMU_BOOKE206: 7789 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx 7790 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", 7791 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], 7792 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); 7793 7794 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx 7795 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 7796 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], 7797 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); 7798 7799 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx 7800 " TLB1CFG " TARGET_FMT_lx "\n", 7801 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], 7802 env->spr[SPR_BOOKE_TLB1CFG]); 7803 break; 7804 default: 7805 break; 7806 } 7807 #endif 7808 7809 #undef RGPL 7810 #undef RFPL 7811 } 7812 type_init(ppc_cpu_register_types) 7813