1 /*
2 * PowerPC gdb server stub
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 * Copyright (c) 2013 SUSE LINUX Products GmbH
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20 #include "qemu/osdep.h"
21 #include "cpu.h"
22 #include "exec/gdbstub.h"
23 #include "gdbstub/helpers.h"
24 #include "internal.h"
25
ppc_gdb_register_len_apple(int n)26 static int ppc_gdb_register_len_apple(int n)
27 {
28 switch (n) {
29 case 0 ... 31:
30 /* gprs */
31 return 8;
32 case 32 ... 63:
33 /* fprs */
34 return 8;
35 case 64 ... 95:
36 return 16;
37 case 64 + 32: /* nip */
38 case 65 + 32: /* msr */
39 case 67 + 32: /* lr */
40 case 68 + 32: /* ctr */
41 case 70 + 32: /* fpscr */
42 return 8;
43 case 66 + 32: /* cr */
44 case 69 + 32: /* xer */
45 return 4;
46 default:
47 return 0;
48 }
49 }
50
ppc_gdb_register_len(int n)51 static int ppc_gdb_register_len(int n)
52 {
53 switch (n) {
54 case 0 ... 31:
55 /* gprs */
56 return sizeof(target_ulong);
57 case 66:
58 /* cr */
59 case 69:
60 /* xer */
61 return 4;
62 case 64:
63 /* nip */
64 case 65:
65 /* msr */
66 case 67:
67 /* lr */
68 case 68:
69 /* ctr */
70 return sizeof(target_ulong);
71 default:
72 return 0;
73 }
74 }
75
76 /*
77 * We need to present the registers to gdb in the "current" memory
78 * ordering. For user-only mode we get this for free;
79 * TARGET_BIG_ENDIAN is set to the proper ordering for the
80 * binary, and cannot be changed. For system mode,
81 * TARGET_BIG_ENDIAN is always set, and we must check the current
82 * mode of the chip to see if we're running in little-endian.
83 */
ppc_maybe_bswap_register(CPUPPCState * env,uint8_t * mem_buf,int len)84 void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len)
85 {
86 #ifndef CONFIG_USER_ONLY
87 if (!FIELD_EX64(env->msr, MSR, LE)) {
88 /* do nothing */
89 } else if (len == 4) {
90 bswap32s((uint32_t *)mem_buf);
91 } else if (len == 8) {
92 bswap64s((uint64_t *)mem_buf);
93 } else if (len == 16) {
94 bswap128s((Int128 *)mem_buf);
95 } else {
96 g_assert_not_reached();
97 }
98 #endif
99 }
100
101 /*
102 * Old gdb always expects FP registers. Newer (xml-aware) gdb only
103 * expects whatever the target description contains. Due to a
104 * historical mishap the FP registers appear in between core integer
105 * regs and PC, MSR, CR, and so forth. We hack round this by giving
106 * the FP regs zero size when talking to a newer gdb.
107 */
108
ppc_cpu_gdb_read_register(CPUState * cs,GByteArray * buf,int n)109 int ppc_cpu_gdb_read_register(CPUState *cs, GByteArray *buf, int n)
110 {
111 PowerPCCPU *cpu = POWERPC_CPU(cs);
112 CPUPPCState *env = &cpu->env;
113 uint8_t *mem_buf;
114 int r = ppc_gdb_register_len(n);
115
116 if (!r) {
117 return r;
118 }
119
120 if (n < 32) {
121 /* gprs */
122 gdb_get_regl(buf, env->gpr[n]);
123 } else {
124 switch (n) {
125 case 64:
126 gdb_get_regl(buf, env->nip);
127 break;
128 case 65:
129 gdb_get_regl(buf, env->msr);
130 break;
131 case 66:
132 {
133 uint32_t cr = ppc_get_cr(env);
134 gdb_get_reg32(buf, cr);
135 break;
136 }
137 case 67:
138 gdb_get_regl(buf, env->lr);
139 break;
140 case 68:
141 gdb_get_regl(buf, env->ctr);
142 break;
143 case 69:
144 gdb_get_reg32(buf, cpu_read_xer(env));
145 break;
146 }
147 }
148 mem_buf = buf->data + buf->len - r;
149 ppc_maybe_bswap_register(env, mem_buf, r);
150 return r;
151 }
152
ppc_cpu_gdb_read_register_apple(CPUState * cs,GByteArray * buf,int n)153 int ppc_cpu_gdb_read_register_apple(CPUState *cs, GByteArray *buf, int n)
154 {
155 PowerPCCPU *cpu = POWERPC_CPU(cs);
156 CPUPPCState *env = &cpu->env;
157 uint8_t *mem_buf;
158 int r = ppc_gdb_register_len_apple(n);
159
160 if (!r) {
161 return r;
162 }
163
164 if (n < 32) {
165 /* gprs */
166 gdb_get_reg64(buf, env->gpr[n]);
167 } else if (n < 64) {
168 /* fprs */
169 gdb_get_reg64(buf, *cpu_fpr_ptr(env, n - 32));
170 } else if (n < 96) {
171 /* Altivec */
172 gdb_get_reg64(buf, n - 64);
173 gdb_get_reg64(buf, 0);
174 } else {
175 switch (n) {
176 case 64 + 32:
177 gdb_get_reg64(buf, env->nip);
178 break;
179 case 65 + 32:
180 gdb_get_reg64(buf, env->msr);
181 break;
182 case 66 + 32:
183 {
184 uint32_t cr = ppc_get_cr(env);
185 gdb_get_reg32(buf, cr);
186 break;
187 }
188 case 67 + 32:
189 gdb_get_reg64(buf, env->lr);
190 break;
191 case 68 + 32:
192 gdb_get_reg64(buf, env->ctr);
193 break;
194 case 69 + 32:
195 gdb_get_reg32(buf, cpu_read_xer(env));
196 break;
197 case 70 + 32:
198 gdb_get_reg64(buf, env->fpscr);
199 break;
200 }
201 }
202 mem_buf = buf->data + buf->len - r;
203 ppc_maybe_bswap_register(env, mem_buf, r);
204 return r;
205 }
206
ppc_cpu_gdb_write_register(CPUState * cs,uint8_t * mem_buf,int n)207 int ppc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
208 {
209 PowerPCCPU *cpu = POWERPC_CPU(cs);
210 CPUPPCState *env = &cpu->env;
211 int r = ppc_gdb_register_len(n);
212
213 if (!r) {
214 return r;
215 }
216 ppc_maybe_bswap_register(env, mem_buf, r);
217 if (n < 32) {
218 /* gprs */
219 env->gpr[n] = ldtul_p(mem_buf);
220 } else if (n < 64) {
221 /* fprs */
222 *cpu_fpr_ptr(env, n - 32) = ldq_p(mem_buf);
223 } else {
224 switch (n) {
225 case 64:
226 env->nip = ldtul_p(mem_buf);
227 break;
228 case 65:
229 ppc_store_msr(env, ldtul_p(mem_buf));
230 break;
231 case 66:
232 {
233 uint32_t cr = ldl_p(mem_buf);
234 ppc_set_cr(env, cr);
235 break;
236 }
237 case 67:
238 env->lr = ldtul_p(mem_buf);
239 break;
240 case 68:
241 env->ctr = ldtul_p(mem_buf);
242 break;
243 case 69:
244 cpu_write_xer(env, ldl_p(mem_buf));
245 break;
246 case 70:
247 /* fpscr */
248 ppc_store_fpscr(env, ldtul_p(mem_buf));
249 break;
250 }
251 }
252 return r;
253 }
ppc_cpu_gdb_write_register_apple(CPUState * cs,uint8_t * mem_buf,int n)254 int ppc_cpu_gdb_write_register_apple(CPUState *cs, uint8_t *mem_buf, int n)
255 {
256 PowerPCCPU *cpu = POWERPC_CPU(cs);
257 CPUPPCState *env = &cpu->env;
258 int r = ppc_gdb_register_len_apple(n);
259
260 if (!r) {
261 return r;
262 }
263 ppc_maybe_bswap_register(env, mem_buf, r);
264 if (n < 32) {
265 /* gprs */
266 env->gpr[n] = ldq_p(mem_buf);
267 } else if (n < 64) {
268 /* fprs */
269 *cpu_fpr_ptr(env, n - 32) = ldq_p(mem_buf);
270 } else {
271 switch (n) {
272 case 64 + 32:
273 env->nip = ldq_p(mem_buf);
274 break;
275 case 65 + 32:
276 ppc_store_msr(env, ldq_p(mem_buf));
277 break;
278 case 66 + 32:
279 {
280 uint32_t cr = ldl_p(mem_buf);
281 ppc_set_cr(env, cr);
282 break;
283 }
284 case 67 + 32:
285 env->lr = ldq_p(mem_buf);
286 break;
287 case 68 + 32:
288 env->ctr = ldq_p(mem_buf);
289 break;
290 case 69 + 32:
291 cpu_write_xer(env, ldl_p(mem_buf));
292 break;
293 case 70 + 32:
294 /* fpscr */
295 ppc_store_fpscr(env, ldq_p(mem_buf));
296 break;
297 }
298 }
299 return r;
300 }
301
302 #ifndef CONFIG_USER_ONLY
ppc_gdb_gen_spr_xml(PowerPCCPU * cpu)303 void ppc_gdb_gen_spr_xml(PowerPCCPU *cpu)
304 {
305 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
306 CPUPPCState *env = &cpu->env;
307 GString *xml;
308 char *spr_name;
309 unsigned int num_regs = 0;
310 int i;
311
312 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
313 ppc_spr_t *spr = &env->spr_cb[i];
314
315 if (!spr->name) {
316 continue;
317 }
318
319 /*
320 * GDB identifies registers based on the order they are
321 * presented in the XML. These ids will not match QEMU's
322 * representation (which follows the PowerISA).
323 *
324 * Store the position of the current register description so
325 * we can make the correspondence later.
326 */
327 spr->gdb_id = num_regs;
328 num_regs++;
329 }
330
331 if (pcc->gdb_spr_xml) {
332 return;
333 }
334
335 xml = g_string_new("<?xml version=\"1.0\"?>");
336 g_string_append(xml, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
337 g_string_append(xml, "<feature name=\"org.qemu.power.spr\">");
338
339 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
340 ppc_spr_t *spr = &env->spr_cb[i];
341
342 if (!spr->name) {
343 continue;
344 }
345
346 spr_name = g_ascii_strdown(spr->name, -1);
347 g_string_append_printf(xml, "<reg name=\"%s\"", spr_name);
348 g_free(spr_name);
349
350 g_string_append_printf(xml, " bitsize=\"%d\"", TARGET_LONG_BITS);
351 g_string_append(xml, " group=\"spr\"/>");
352 }
353
354 g_string_append(xml, "</feature>");
355
356 pcc->gdb_num_sprs = num_regs;
357 pcc->gdb_spr_xml = g_string_free(xml, false);
358 }
359
ppc_gdb_get_dynamic_xml(CPUState * cs,const char * xml_name)360 const char *ppc_gdb_get_dynamic_xml(CPUState *cs, const char *xml_name)
361 {
362 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
363
364 if (strcmp(xml_name, "power-spr.xml") == 0) {
365 return pcc->gdb_spr_xml;
366 }
367 return NULL;
368 }
369 #endif
370
371 #if !defined(CONFIG_USER_ONLY)
gdb_find_spr_idx(CPUPPCState * env,int n)372 static int gdb_find_spr_idx(CPUPPCState *env, int n)
373 {
374 int i;
375
376 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
377 ppc_spr_t *spr = &env->spr_cb[i];
378
379 if (spr->name && spr->gdb_id == n) {
380 return i;
381 }
382 }
383 return -1;
384 }
385
gdb_get_spr_reg(CPUPPCState * env,GByteArray * buf,int n)386 static int gdb_get_spr_reg(CPUPPCState *env, GByteArray *buf, int n)
387 {
388 int reg;
389 int len;
390
391 reg = gdb_find_spr_idx(env, n);
392 if (reg < 0) {
393 return 0;
394 }
395
396 len = TARGET_LONG_SIZE;
397 gdb_get_regl(buf, env->spr[reg]);
398 ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, len), len);
399 return len;
400 }
401
gdb_set_spr_reg(CPUPPCState * env,uint8_t * mem_buf,int n)402 static int gdb_set_spr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
403 {
404 int reg;
405 int len;
406
407 reg = gdb_find_spr_idx(env, n);
408 if (reg < 0) {
409 return 0;
410 }
411
412 len = TARGET_LONG_SIZE;
413 ppc_maybe_bswap_register(env, mem_buf, len);
414 env->spr[reg] = ldn_p(mem_buf, len);
415
416 return len;
417 }
418 #endif
419
gdb_get_float_reg(CPUPPCState * env,GByteArray * buf,int n)420 static int gdb_get_float_reg(CPUPPCState *env, GByteArray *buf, int n)
421 {
422 uint8_t *mem_buf;
423 if (n < 32) {
424 gdb_get_reg64(buf, *cpu_fpr_ptr(env, n));
425 mem_buf = gdb_get_reg_ptr(buf, 8);
426 ppc_maybe_bswap_register(env, mem_buf, 8);
427 return 8;
428 }
429 if (n == 32) {
430 gdb_get_reg32(buf, env->fpscr);
431 mem_buf = gdb_get_reg_ptr(buf, 4);
432 ppc_maybe_bswap_register(env, mem_buf, 4);
433 return 4;
434 }
435 return 0;
436 }
437
gdb_set_float_reg(CPUPPCState * env,uint8_t * mem_buf,int n)438 static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
439 {
440 if (n < 32) {
441 ppc_maybe_bswap_register(env, mem_buf, 8);
442 *cpu_fpr_ptr(env, n) = ldq_p(mem_buf);
443 return 8;
444 }
445 if (n == 32) {
446 ppc_maybe_bswap_register(env, mem_buf, 4);
447 ppc_store_fpscr(env, ldl_p(mem_buf));
448 return 4;
449 }
450 return 0;
451 }
452
gdb_get_avr_reg(CPUPPCState * env,GByteArray * buf,int n)453 static int gdb_get_avr_reg(CPUPPCState *env, GByteArray *buf, int n)
454 {
455 uint8_t *mem_buf;
456
457 if (n < 32) {
458 ppc_avr_t *avr = cpu_avr_ptr(env, n);
459 gdb_get_reg128(buf, avr->VsrD(0), avr->VsrD(1));
460 mem_buf = gdb_get_reg_ptr(buf, 16);
461 ppc_maybe_bswap_register(env, mem_buf, 16);
462 return 16;
463 }
464 if (n == 32) {
465 gdb_get_reg32(buf, ppc_get_vscr(env));
466 mem_buf = gdb_get_reg_ptr(buf, 4);
467 ppc_maybe_bswap_register(env, mem_buf, 4);
468 return 4;
469 }
470 if (n == 33) {
471 gdb_get_reg32(buf, (uint32_t)env->spr[SPR_VRSAVE]);
472 mem_buf = gdb_get_reg_ptr(buf, 4);
473 ppc_maybe_bswap_register(env, mem_buf, 4);
474 return 4;
475 }
476 return 0;
477 }
478
gdb_set_avr_reg(CPUPPCState * env,uint8_t * mem_buf,int n)479 static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
480 {
481 if (n < 32) {
482 ppc_avr_t *avr = cpu_avr_ptr(env, n);
483 ppc_maybe_bswap_register(env, mem_buf, 16);
484 avr->VsrD(0) = ldq_p(mem_buf);
485 avr->VsrD(1) = ldq_p(mem_buf + 8);
486 return 16;
487 }
488 if (n == 32) {
489 ppc_maybe_bswap_register(env, mem_buf, 4);
490 ppc_store_vscr(env, ldl_p(mem_buf));
491 return 4;
492 }
493 if (n == 33) {
494 ppc_maybe_bswap_register(env, mem_buf, 4);
495 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
496 return 4;
497 }
498 return 0;
499 }
500
gdb_get_spe_reg(CPUPPCState * env,GByteArray * buf,int n)501 static int gdb_get_spe_reg(CPUPPCState *env, GByteArray *buf, int n)
502 {
503 if (n < 32) {
504 #if defined(TARGET_PPC64)
505 gdb_get_reg32(buf, env->gpr[n] >> 32);
506 ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 4), 4);
507 #else
508 gdb_get_reg32(buf, env->gprh[n]);
509 #endif
510 return 4;
511 }
512 if (n == 32) {
513 gdb_get_reg64(buf, env->spe_acc);
514 ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 8), 8);
515 return 8;
516 }
517 if (n == 33) {
518 gdb_get_reg32(buf, env->spe_fscr);
519 ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 4), 4);
520 return 4;
521 }
522 return 0;
523 }
524
gdb_set_spe_reg(CPUPPCState * env,uint8_t * mem_buf,int n)525 static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
526 {
527 if (n < 32) {
528 #if defined(TARGET_PPC64)
529 target_ulong lo = (uint32_t)env->gpr[n];
530 target_ulong hi;
531
532 ppc_maybe_bswap_register(env, mem_buf, 4);
533
534 hi = (target_ulong)ldl_p(mem_buf) << 32;
535 env->gpr[n] = lo | hi;
536 #else
537 env->gprh[n] = ldl_p(mem_buf);
538 #endif
539 return 4;
540 }
541 if (n == 32) {
542 ppc_maybe_bswap_register(env, mem_buf, 8);
543 env->spe_acc = ldq_p(mem_buf);
544 return 8;
545 }
546 if (n == 33) {
547 ppc_maybe_bswap_register(env, mem_buf, 4);
548 env->spe_fscr = ldl_p(mem_buf);
549 return 4;
550 }
551 return 0;
552 }
553
gdb_get_vsx_reg(CPUPPCState * env,GByteArray * buf,int n)554 static int gdb_get_vsx_reg(CPUPPCState *env, GByteArray *buf, int n)
555 {
556 if (n < 32) {
557 gdb_get_reg64(buf, *cpu_vsrl_ptr(env, n));
558 ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 8), 8);
559 return 8;
560 }
561 return 0;
562 }
563
gdb_set_vsx_reg(CPUPPCState * env,uint8_t * mem_buf,int n)564 static int gdb_set_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
565 {
566 if (n < 32) {
567 ppc_maybe_bswap_register(env, mem_buf, 8);
568 *cpu_vsrl_ptr(env, n) = ldq_p(mem_buf);
569 return 8;
570 }
571 return 0;
572 }
573
ppc_gdb_arch_name(CPUState * cs)574 const gchar *ppc_gdb_arch_name(CPUState *cs)
575 {
576 #if defined(TARGET_PPC64)
577 return "powerpc:common64";
578 #else
579 return "powerpc:common";
580 #endif
581 }
582
ppc_gdb_init(CPUState * cs,PowerPCCPUClass * pcc)583 void ppc_gdb_init(CPUState *cs, PowerPCCPUClass *pcc)
584 {
585 if (pcc->insns_flags & PPC_FLOAT) {
586 gdb_register_coprocessor(cs, gdb_get_float_reg, gdb_set_float_reg,
587 33, "power-fpu.xml", 0);
588 }
589 if (pcc->insns_flags & PPC_ALTIVEC) {
590 gdb_register_coprocessor(cs, gdb_get_avr_reg, gdb_set_avr_reg,
591 34, "power-altivec.xml", 0);
592 }
593 if (pcc->insns_flags & PPC_SPE) {
594 gdb_register_coprocessor(cs, gdb_get_spe_reg, gdb_set_spe_reg,
595 34, "power-spe.xml", 0);
596 }
597 if (pcc->insns_flags2 & PPC2_VSX) {
598 gdb_register_coprocessor(cs, gdb_get_vsx_reg, gdb_set_vsx_reg,
599 32, "power-vsx.xml", 0);
600 }
601 #ifndef CONFIG_USER_ONLY
602 gdb_register_coprocessor(cs, gdb_get_spr_reg, gdb_set_spr_reg,
603 pcc->gdb_num_sprs, "power-spr.xml", 0);
604 #endif
605 }
606