1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/datadir.h" 22 #include "qemu/units.h" 23 #include "qemu/cutils.h" 24 #include "qapi/error.h" 25 #include "sysemu/qtest.h" 26 #include "sysemu/sysemu.h" 27 #include "sysemu/numa.h" 28 #include "sysemu/reset.h" 29 #include "sysemu/runstate.h" 30 #include "sysemu/cpus.h" 31 #include "sysemu/device_tree.h" 32 #include "sysemu/hw_accel.h" 33 #include "target/ppc/cpu.h" 34 #include "hw/ppc/fdt.h" 35 #include "hw/ppc/ppc.h" 36 #include "hw/ppc/pnv.h" 37 #include "hw/ppc/pnv_core.h" 38 #include "hw/loader.h" 39 #include "hw/nmi.h" 40 #include "qapi/visitor.h" 41 #include "hw/intc/intc.h" 42 #include "hw/ipmi/ipmi.h" 43 #include "target/ppc/mmu-hash64.h" 44 #include "hw/pci/msi.h" 45 #include "hw/pci-host/pnv_phb.h" 46 #include "hw/pci-host/pnv_phb3.h" 47 #include "hw/pci-host/pnv_phb4.h" 48 49 #include "hw/ppc/xics.h" 50 #include "hw/qdev-properties.h" 51 #include "hw/ppc/pnv_chip.h" 52 #include "hw/ppc/pnv_xscom.h" 53 #include "hw/ppc/pnv_pnor.h" 54 55 #include "hw/isa/isa.h" 56 #include "hw/char/serial-isa.h" 57 #include "hw/rtc/mc146818rtc.h" 58 59 #include <libfdt.h> 60 61 #define FDT_MAX_SIZE (1 * MiB) 62 63 #define FW_FILE_NAME "skiboot.lid" 64 #define FW_LOAD_ADDR 0x0 65 #define FW_MAX_SIZE (16 * MiB) 66 67 #define KERNEL_LOAD_ADDR 0x20000000 68 #define KERNEL_MAX_SIZE (128 * MiB) 69 #define INITRD_LOAD_ADDR 0x28000000 70 #define INITRD_MAX_SIZE (128 * MiB) 71 pnv_chip_core_typename(const PnvChip * o)72 static const char *pnv_chip_core_typename(const PnvChip *o) 73 { 74 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 75 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 76 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 77 const char *core_type = object_class_get_name(object_class_by_name(s)); 78 g_free(s); 79 return core_type; 80 } 81 82 /* 83 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 84 * 4 * 4 sockets * 12 cores * 8 threads = 1536 85 * Let's make it 2^11 86 */ 87 #define MAX_CPUS 2048 88 89 /* 90 * Memory nodes are created by hostboot, one for each range of memory 91 * that has a different "affinity". In practice, it means one range 92 * per chip. 93 */ pnv_dt_memory(void * fdt,int chip_id,hwaddr start,hwaddr size)94 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 95 { 96 char *mem_name; 97 uint64_t mem_reg_property[2]; 98 int off; 99 100 mem_reg_property[0] = cpu_to_be64(start); 101 mem_reg_property[1] = cpu_to_be64(size); 102 103 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 104 off = fdt_add_subnode(fdt, 0, mem_name); 105 g_free(mem_name); 106 107 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 108 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 109 sizeof(mem_reg_property)))); 110 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 111 } 112 get_cpus_node(void * fdt)113 static int get_cpus_node(void *fdt) 114 { 115 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 116 117 if (cpus_offset < 0) { 118 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 119 if (cpus_offset) { 120 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 121 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 122 } 123 } 124 _FDT(cpus_offset); 125 return cpus_offset; 126 } 127 128 /* 129 * The PowerNV cores (and threads) need to use real HW ids and not an 130 * incremental index like it has been done on other platforms. This HW 131 * id is stored in the CPU PIR, it is used to create cpu nodes in the 132 * device tree, used in XSCOM to address cores and in interrupt 133 * servers. 134 */ pnv_dt_core(PnvChip * chip,PnvCore * pc,void * fdt)135 static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 136 { 137 PowerPCCPU *cpu = pc->threads[0]; 138 CPUState *cs = CPU(cpu); 139 DeviceClass *dc = DEVICE_GET_CLASS(cs); 140 int smt_threads = CPU_CORE(pc)->nr_threads; 141 CPUPPCState *env = &cpu->env; 142 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 143 PnvChipClass *pnv_cc = PNV_CHIP_GET_CLASS(chip); 144 uint32_t *servers_prop; 145 int i; 146 uint32_t pir, tir; 147 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 148 0xffffffff, 0xffffffff}; 149 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 150 uint32_t cpufreq = 1000000000; 151 uint32_t page_sizes_prop[64]; 152 size_t page_sizes_prop_size; 153 int offset; 154 char *nodename; 155 int cpus_offset = get_cpus_node(fdt); 156 157 pnv_cc->get_pir_tir(chip, pc->hwid, 0, &pir, &tir); 158 159 /* Only one DT node per (big) core */ 160 g_assert(tir == 0); 161 162 nodename = g_strdup_printf("%s@%x", dc->fw_name, pir); 163 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 164 _FDT(offset); 165 g_free(nodename); 166 167 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 168 169 _FDT((fdt_setprop_cell(fdt, offset, "reg", pir))); 170 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pir))); 171 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 172 173 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 174 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 175 env->dcache_line_size))); 176 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 177 env->dcache_line_size))); 178 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 179 env->icache_line_size))); 180 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 181 env->icache_line_size))); 182 183 if (pcc->l1_dcache_size) { 184 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 185 pcc->l1_dcache_size))); 186 } else { 187 warn_report("Unknown L1 dcache size for cpu"); 188 } 189 if (pcc->l1_icache_size) { 190 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 191 pcc->l1_icache_size))); 192 } else { 193 warn_report("Unknown L1 icache size for cpu"); 194 } 195 196 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 197 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 198 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 199 cpu->hash64_opts->slb_size))); 200 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 201 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 202 203 if (ppc_has_spr(cpu, SPR_PURR)) { 204 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 205 } 206 207 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 208 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 209 segs, sizeof(segs)))); 210 } 211 212 /* 213 * Advertise VMX/VSX (vector extensions) if available 214 * 0 / no property == no vector extensions 215 * 1 == VMX / Altivec available 216 * 2 == VSX available 217 */ 218 if (env->insns_flags & PPC_ALTIVEC) { 219 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 220 221 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 222 } 223 224 /* 225 * Advertise DFP (Decimal Floating Point) if available 226 * 0 / no property == no DFP 227 * 1 == DFP available 228 */ 229 if (env->insns_flags2 & PPC2_DFP) { 230 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 231 } 232 233 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 234 sizeof(page_sizes_prop)); 235 if (page_sizes_prop_size) { 236 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 237 page_sizes_prop, page_sizes_prop_size))); 238 } 239 240 /* Build interrupt servers properties */ 241 if (pc->big_core) { 242 servers_prop = g_new(uint32_t, smt_threads * 2); 243 for (i = 0; i < smt_threads; i++) { 244 pnv_cc->get_pir_tir(chip, pc->hwid, i, &pir, NULL); 245 servers_prop[i * 2] = cpu_to_be32(pir); 246 247 pnv_cc->get_pir_tir(chip, pc->hwid + 1, i, &pir, NULL); 248 servers_prop[i * 2 + 1] = cpu_to_be32(pir); 249 } 250 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 251 servers_prop, sizeof(*servers_prop) * smt_threads 252 * 2))); 253 } else { 254 servers_prop = g_new(uint32_t, smt_threads); 255 for (i = 0; i < smt_threads; i++) { 256 pnv_cc->get_pir_tir(chip, pc->hwid, i, &pir, NULL); 257 servers_prop[i] = cpu_to_be32(pir); 258 } 259 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 260 servers_prop, sizeof(*servers_prop) * smt_threads))); 261 } 262 g_free(servers_prop); 263 264 return offset; 265 } 266 pnv_dt_icp(PnvChip * chip,void * fdt,uint32_t hwid,uint32_t nr_threads)267 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t hwid, 268 uint32_t nr_threads) 269 { 270 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 271 uint32_t pir; 272 uint64_t addr; 273 char *name; 274 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 275 uint32_t irange[2], i, rsize; 276 uint64_t *reg; 277 int offset; 278 279 pcc->get_pir_tir(chip, hwid, 0, &pir, NULL); 280 addr = PNV_ICP_BASE(chip) | (pir << 12); 281 282 irange[0] = cpu_to_be32(pir); 283 irange[1] = cpu_to_be32(nr_threads); 284 285 rsize = sizeof(uint64_t) * 2 * nr_threads; 286 reg = g_malloc(rsize); 287 for (i = 0; i < nr_threads; i++) { 288 /* We know P8 PIR is linear with thread id */ 289 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 290 reg[i * 2 + 1] = cpu_to_be64(0x1000); 291 } 292 293 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 294 offset = fdt_add_subnode(fdt, 0, name); 295 _FDT(offset); 296 g_free(name); 297 298 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 299 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 300 _FDT((fdt_setprop_string(fdt, offset, "device_type", 301 "PowerPC-External-Interrupt-Presentation"))); 302 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 303 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 304 irange, sizeof(irange)))); 305 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 306 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 307 g_free(reg); 308 } 309 310 /* 311 * Adds a PnvPHB to the chip on P8. 312 * Implemented here, like for defaults PHBs 313 */ pnv_chip_add_phb(PnvChip * chip,PnvPHB * phb)314 PnvChip *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb) 315 { 316 Pnv8Chip *chip8 = PNV8_CHIP(chip); 317 318 phb->chip = chip; 319 320 chip8->phbs[chip8->num_phbs] = phb; 321 chip8->num_phbs++; 322 return chip; 323 } 324 325 /* 326 * Same as spapr pa_features_207 except pnv always enables CI largepages bit. 327 * HTM is always enabled because TCG does implement HTM, it's just a 328 * degenerate implementation. 329 */ 330 static const uint8_t pa_features_207[] = { 24, 0, 331 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, 332 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 333 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 334 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 335 pnv_chip_power8_dt_populate(PnvChip * chip,void * fdt)336 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 337 { 338 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 339 int i; 340 341 pnv_dt_xscom(chip, fdt, 0, 342 cpu_to_be64(PNV_XSCOM_BASE(chip)), 343 cpu_to_be64(PNV_XSCOM_SIZE), 344 compat, sizeof(compat)); 345 346 for (i = 0; i < chip->nr_cores; i++) { 347 PnvCore *pnv_core = chip->cores[i]; 348 int offset; 349 350 offset = pnv_dt_core(chip, pnv_core, fdt); 351 352 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 353 pa_features_207, sizeof(pa_features_207)))); 354 355 /* Interrupt Control Presenters (ICP). One per core. */ 356 pnv_dt_icp(chip, fdt, pnv_core->hwid, CPU_CORE(pnv_core)->nr_threads); 357 } 358 359 if (chip->ram_size) { 360 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 361 } 362 } 363 364 /* 365 * Same as spapr pa_features_300 except pnv always enables CI largepages bit. 366 */ 367 static const uint8_t pa_features_300[] = { 66, 0, 368 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 369 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 370 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 371 /* 6: DS207 */ 372 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 373 /* 16: Vector */ 374 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 375 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 376 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 18 - 23 */ 377 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 378 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 379 /* 32: LE atomic, 34: EBB + ext EBB */ 380 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 381 /* 40: Radix MMU */ 382 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 383 /* 42: PM, 44: PC RA, 46: SC vec'd */ 384 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 385 /* 48: SIMD, 50: QP BFP, 52: String */ 386 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 387 /* 54: DecFP, 56: DecI, 58: SHA */ 388 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 389 /* 60: NM atomic, 62: RNG */ 390 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 391 }; 392 pnv_chip_power9_dt_populate(PnvChip * chip,void * fdt)393 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 394 { 395 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 396 int i; 397 398 pnv_dt_xscom(chip, fdt, 0, 399 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 400 cpu_to_be64(PNV9_XSCOM_SIZE), 401 compat, sizeof(compat)); 402 403 for (i = 0; i < chip->nr_cores; i++) { 404 PnvCore *pnv_core = chip->cores[i]; 405 int offset; 406 407 offset = pnv_dt_core(chip, pnv_core, fdt); 408 409 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 410 pa_features_300, sizeof(pa_features_300)))); 411 412 if (pnv_core->big_core) { 413 i++; /* Big-core groups two QEMU cores */ 414 } 415 } 416 417 if (chip->ram_size) { 418 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 419 } 420 421 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 422 } 423 424 /* 425 * Same as spapr pa_features_31 except pnv always enables CI largepages bit, 426 * always disables copy/paste. 427 */ 428 static const uint8_t pa_features_31[] = { 74, 0, 429 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 430 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 431 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 432 /* 6: DS207 */ 433 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 434 /* 16: Vector */ 435 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 436 /* 18: Vec. Scalar, 20: Vec. XOR */ 437 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 438 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 439 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 440 /* 32: LE atomic, 34: EBB + ext EBB */ 441 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 442 /* 40: Radix MMU */ 443 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 444 /* 42: PM, 44: PC RA, 46: SC vec'd */ 445 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 446 /* 48: SIMD, 50: QP BFP, 52: String */ 447 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 448 /* 54: DecFP, 56: DecI, 58: SHA */ 449 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 450 /* 60: NM atomic, 62: RNG */ 451 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 452 /* 68: DEXCR[SBHE|IBRTPDUS|SRAPD|NPHIE|PHIE] */ 453 0x00, 0x00, 0xce, 0x00, 0x00, 0x00, /* 66 - 71 */ 454 /* 72: [P]HASHST/[P]HASHCHK */ 455 0x80, 0x00, /* 72 - 73 */ 456 }; 457 pnv_chip_power10_dt_populate(PnvChip * chip,void * fdt)458 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 459 { 460 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 461 int i; 462 463 pnv_dt_xscom(chip, fdt, 0, 464 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 465 cpu_to_be64(PNV10_XSCOM_SIZE), 466 compat, sizeof(compat)); 467 468 for (i = 0; i < chip->nr_cores; i++) { 469 PnvCore *pnv_core = chip->cores[i]; 470 int offset; 471 472 offset = pnv_dt_core(chip, pnv_core, fdt); 473 474 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 475 pa_features_31, sizeof(pa_features_31)))); 476 477 if (pnv_core->big_core) { 478 i++; /* Big-core groups two QEMU cores */ 479 } 480 } 481 482 if (chip->ram_size) { 483 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 484 } 485 486 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 487 } 488 pnv_dt_rtc(ISADevice * d,void * fdt,int lpc_off)489 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 490 { 491 uint32_t io_base = d->ioport_id; 492 uint32_t io_regs[] = { 493 cpu_to_be32(1), 494 cpu_to_be32(io_base), 495 cpu_to_be32(2) 496 }; 497 char *name; 498 int node; 499 500 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 501 node = fdt_add_subnode(fdt, lpc_off, name); 502 _FDT(node); 503 g_free(name); 504 505 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 506 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 507 } 508 pnv_dt_serial(ISADevice * d,void * fdt,int lpc_off)509 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 510 { 511 const char compatible[] = "ns16550\0pnpPNP,501"; 512 uint32_t io_base = d->ioport_id; 513 uint32_t io_regs[] = { 514 cpu_to_be32(1), 515 cpu_to_be32(io_base), 516 cpu_to_be32(8) 517 }; 518 uint32_t irq; 519 char *name; 520 int node; 521 522 irq = object_property_get_uint(OBJECT(d), "irq", &error_fatal); 523 524 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 525 node = fdt_add_subnode(fdt, lpc_off, name); 526 _FDT(node); 527 g_free(name); 528 529 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 530 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 531 sizeof(compatible)))); 532 533 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 534 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 535 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 536 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 537 fdt_get_phandle(fdt, lpc_off)))); 538 539 /* This is needed by Linux */ 540 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 541 } 542 pnv_dt_ipmi_bt(ISADevice * d,void * fdt,int lpc_off)543 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 544 { 545 const char compatible[] = "bt\0ipmi-bt"; 546 uint32_t io_base; 547 uint32_t io_regs[] = { 548 cpu_to_be32(1), 549 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 550 cpu_to_be32(3) 551 }; 552 uint32_t irq; 553 char *name; 554 int node; 555 556 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 557 io_regs[1] = cpu_to_be32(io_base); 558 559 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 560 561 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 562 node = fdt_add_subnode(fdt, lpc_off, name); 563 _FDT(node); 564 g_free(name); 565 566 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 567 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 568 sizeof(compatible)))); 569 570 /* Mark it as reserved to avoid Linux trying to claim it */ 571 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 572 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 573 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 574 fdt_get_phandle(fdt, lpc_off)))); 575 } 576 577 typedef struct ForeachPopulateArgs { 578 void *fdt; 579 int offset; 580 } ForeachPopulateArgs; 581 pnv_dt_isa_device(DeviceState * dev,void * opaque)582 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 583 { 584 ForeachPopulateArgs *args = opaque; 585 ISADevice *d = ISA_DEVICE(dev); 586 587 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 588 pnv_dt_rtc(d, args->fdt, args->offset); 589 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 590 pnv_dt_serial(d, args->fdt, args->offset); 591 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 592 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 593 } else { 594 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 595 d->ioport_id); 596 } 597 598 return 0; 599 } 600 601 /* 602 * The default LPC bus of a multichip system is on chip 0. It's 603 * recognized by the firmware (skiboot) using a "primary" property. 604 */ pnv_dt_isa(PnvMachineState * pnv,void * fdt)605 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 606 { 607 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 608 ForeachPopulateArgs args = { 609 .fdt = fdt, 610 .offset = isa_offset, 611 }; 612 uint32_t phandle; 613 614 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 615 616 phandle = qemu_fdt_alloc_phandle(fdt); 617 assert(phandle > 0); 618 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 619 620 /* 621 * ISA devices are not necessarily parented to the ISA bus so we 622 * can not use object_child_foreach() 623 */ 624 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 625 &args); 626 } 627 pnv_dt_power_mgt(PnvMachineState * pnv,void * fdt)628 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 629 { 630 int off; 631 632 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 633 off = fdt_add_subnode(fdt, off, "power-mgt"); 634 635 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 636 } 637 pnv_dt_create(MachineState * machine)638 static void *pnv_dt_create(MachineState *machine) 639 { 640 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 641 PnvMachineState *pnv = PNV_MACHINE(machine); 642 void *fdt; 643 char *buf; 644 int off; 645 int i; 646 647 fdt = g_malloc0(FDT_MAX_SIZE); 648 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 649 650 /* /qemu node */ 651 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 652 653 /* Root node */ 654 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 655 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 656 _FDT((fdt_setprop_string(fdt, 0, "model", 657 "IBM PowerNV (emulated by qemu)"))); 658 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 659 660 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 661 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 662 if (qemu_uuid_set) { 663 _FDT((fdt_setprop_string(fdt, 0, "system-id", buf))); 664 } 665 g_free(buf); 666 667 off = fdt_add_subnode(fdt, 0, "chosen"); 668 if (machine->kernel_cmdline) { 669 _FDT((fdt_setprop_string(fdt, off, "bootargs", 670 machine->kernel_cmdline))); 671 } 672 673 if (pnv->initrd_size) { 674 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 675 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 676 677 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 678 &start_prop, sizeof(start_prop)))); 679 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 680 &end_prop, sizeof(end_prop)))); 681 } 682 683 /* Populate device tree for each chip */ 684 for (i = 0; i < pnv->num_chips; i++) { 685 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 686 } 687 688 /* Populate ISA devices on chip 0 */ 689 pnv_dt_isa(pnv, fdt); 690 691 if (pnv->bmc) { 692 pnv_dt_bmc_sensors(pnv->bmc, fdt); 693 } 694 695 /* Create an extra node for power management on machines that support it */ 696 if (pmc->dt_power_mgt) { 697 pmc->dt_power_mgt(pnv, fdt); 698 } 699 700 return fdt; 701 } 702 pnv_powerdown_notify(Notifier * n,void * opaque)703 static void pnv_powerdown_notify(Notifier *n, void *opaque) 704 { 705 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 706 707 if (pnv->bmc) { 708 pnv_bmc_powerdown(pnv->bmc); 709 } 710 } 711 pnv_reset(MachineState * machine,ResetType type)712 static void pnv_reset(MachineState *machine, ResetType type) 713 { 714 PnvMachineState *pnv = PNV_MACHINE(machine); 715 IPMIBmc *bmc; 716 void *fdt; 717 718 qemu_devices_reset(type); 719 720 /* 721 * The machine should provide by default an internal BMC simulator. 722 * If not, try to use the BMC device that was provided on the command 723 * line. 724 */ 725 bmc = pnv_bmc_find(&error_fatal); 726 if (!pnv->bmc) { 727 if (!bmc) { 728 if (!qtest_enabled()) { 729 warn_report("machine has no BMC device. Use '-device " 730 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " 731 "to define one"); 732 } 733 } else { 734 pnv_bmc_set_pnor(bmc, pnv->pnor); 735 pnv->bmc = bmc; 736 } 737 } 738 739 if (machine->fdt) { 740 fdt = machine->fdt; 741 } else { 742 fdt = pnv_dt_create(machine); 743 /* Pack resulting tree */ 744 _FDT((fdt_pack(fdt))); 745 } 746 747 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 748 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 749 750 /* Update machine->fdt with latest fdt */ 751 if (machine->fdt != fdt) { 752 /* 753 * Set machine->fdt for 'dumpdtb' QMP/HMP command. Free 754 * the existing machine->fdt to avoid leaking it during 755 * a reset. 756 */ 757 g_free(machine->fdt); 758 machine->fdt = fdt; 759 } 760 } 761 pnv_chip_power8_isa_create(PnvChip * chip,Error ** errp)762 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 763 { 764 Pnv8Chip *chip8 = PNV8_CHIP(chip); 765 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_EXTERNAL); 766 767 qdev_connect_gpio_out_named(DEVICE(&chip8->lpc), "LPCHC", 0, irq); 768 769 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 770 } 771 pnv_chip_power8nvl_isa_create(PnvChip * chip,Error ** errp)772 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 773 { 774 Pnv8Chip *chip8 = PNV8_CHIP(chip); 775 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_LPC_I2C); 776 777 qdev_connect_gpio_out_named(DEVICE(&chip8->lpc), "LPCHC", 0, irq); 778 779 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 780 } 781 pnv_chip_power9_isa_create(PnvChip * chip,Error ** errp)782 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 783 { 784 Pnv9Chip *chip9 = PNV9_CHIP(chip); 785 qemu_irq irq; 786 787 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPCHC); 788 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "LPCHC", 0, irq); 789 790 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ0); 791 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 0, irq); 792 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ1); 793 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 1, irq); 794 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ2); 795 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 2, irq); 796 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ3); 797 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 3, irq); 798 799 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 800 } 801 pnv_chip_power10_isa_create(PnvChip * chip,Error ** errp)802 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 803 { 804 Pnv10Chip *chip10 = PNV10_CHIP(chip); 805 qemu_irq irq; 806 807 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPCHC); 808 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "LPCHC", 0, irq); 809 810 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ0); 811 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 0, irq); 812 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ1); 813 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 1, irq); 814 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ2); 815 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 2, irq); 816 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ3); 817 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 3, irq); 818 819 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 820 } 821 pnv_isa_create(PnvChip * chip,Error ** errp)822 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 823 { 824 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 825 } 826 pnv_chip_power8_pic_print_info(PnvChip * chip,GString * buf)827 static void pnv_chip_power8_pic_print_info(PnvChip *chip, GString *buf) 828 { 829 Pnv8Chip *chip8 = PNV8_CHIP(chip); 830 int i; 831 832 ics_pic_print_info(&chip8->psi.ics, buf); 833 834 for (i = 0; i < chip8->num_phbs; i++) { 835 PnvPHB *phb = chip8->phbs[i]; 836 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 837 838 pnv_phb3_msi_pic_print_info(&phb3->msis, buf); 839 ics_pic_print_info(&phb3->lsis, buf); 840 } 841 } 842 pnv_chip_power9_pic_print_info_child(Object * child,void * opaque)843 static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque) 844 { 845 GString *buf = opaque; 846 PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB); 847 848 if (!phb) { 849 return 0; 850 } 851 852 pnv_phb4_pic_print_info(PNV_PHB4(phb->backend), buf); 853 854 return 0; 855 } 856 pnv_chip_power9_pic_print_info(PnvChip * chip,GString * buf)857 static void pnv_chip_power9_pic_print_info(PnvChip *chip, GString *buf) 858 { 859 Pnv9Chip *chip9 = PNV9_CHIP(chip); 860 861 pnv_xive_pic_print_info(&chip9->xive, buf); 862 pnv_psi_pic_print_info(&chip9->psi, buf); 863 object_child_foreach_recursive(OBJECT(chip), 864 pnv_chip_power9_pic_print_info_child, buf); 865 } 866 pnv_chip_power8_xscom_core_base(PnvChip * chip,uint32_t core_id)867 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 868 uint32_t core_id) 869 { 870 return PNV_XSCOM_EX_BASE(core_id); 871 } 872 pnv_chip_power9_xscom_core_base(PnvChip * chip,uint32_t core_id)873 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 874 uint32_t core_id) 875 { 876 return PNV9_XSCOM_EC_BASE(core_id); 877 } 878 pnv_chip_power10_xscom_core_base(PnvChip * chip,uint32_t core_id)879 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 880 uint32_t core_id) 881 { 882 return PNV10_XSCOM_EC_BASE(core_id); 883 } 884 pnv_match_cpu(const char * default_type,const char * cpu_type)885 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 886 { 887 PowerPCCPUClass *ppc_default = 888 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 889 PowerPCCPUClass *ppc = 890 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 891 892 return ppc_default->pvr_match(ppc_default, ppc->pvr, false); 893 } 894 pnv_ipmi_bt_init(ISABus * bus,IPMIBmc * bmc,uint32_t irq)895 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 896 { 897 ISADevice *dev = isa_new("isa-ipmi-bt"); 898 899 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal); 900 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal); 901 isa_realize_and_unref(dev, bus, &error_fatal); 902 } 903 pnv_chip_power10_pic_print_info(PnvChip * chip,GString * buf)904 static void pnv_chip_power10_pic_print_info(PnvChip *chip, GString *buf) 905 { 906 Pnv10Chip *chip10 = PNV10_CHIP(chip); 907 908 pnv_xive2_pic_print_info(&chip10->xive, buf); 909 pnv_psi_pic_print_info(&chip10->psi, buf); 910 object_child_foreach_recursive(OBJECT(chip), 911 pnv_chip_power9_pic_print_info_child, buf); 912 } 913 914 /* Always give the first 1GB to chip 0 else we won't boot */ pnv_chip_get_ram_size(PnvMachineState * pnv,int chip_id)915 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id) 916 { 917 MachineState *machine = MACHINE(pnv); 918 uint64_t ram_per_chip; 919 920 assert(machine->ram_size >= 1 * GiB); 921 922 ram_per_chip = machine->ram_size / pnv->num_chips; 923 if (ram_per_chip >= 1 * GiB) { 924 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 925 } 926 927 assert(pnv->num_chips > 1); 928 929 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1); 930 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 931 } 932 pnv_init(MachineState * machine)933 static void pnv_init(MachineState *machine) 934 { 935 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 936 PnvMachineState *pnv = PNV_MACHINE(machine); 937 MachineClass *mc = MACHINE_GET_CLASS(machine); 938 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 939 int max_smt_threads = pmc->max_smt_threads; 940 char *fw_filename; 941 long fw_size; 942 uint64_t chip_ram_start = 0; 943 int i; 944 char *chip_typename; 945 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 946 DeviceState *dev; 947 948 if (kvm_enabled()) { 949 error_report("machine %s does not support the KVM accelerator", 950 mc->name); 951 exit(EXIT_FAILURE); 952 } 953 954 /* allocate RAM */ 955 if (machine->ram_size < mc->default_ram_size) { 956 char *sz = size_to_str(mc->default_ram_size); 957 error_report("Invalid RAM size, should be bigger than %s", sz); 958 g_free(sz); 959 exit(EXIT_FAILURE); 960 } 961 962 /* checks for invalid option combinations */ 963 if (machine->dtb && (strlen(machine->kernel_cmdline) != 0)) { 964 error_report("-append and -dtb cannot be used together, as passed" 965 " command line is ignored in case of custom dtb"); 966 exit(EXIT_FAILURE); 967 } 968 969 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 970 971 /* 972 * Create our simple PNOR device 973 */ 974 dev = qdev_new(TYPE_PNV_PNOR); 975 if (pnor) { 976 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor)); 977 } 978 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 979 pnv->pnor = PNV_PNOR(dev); 980 981 /* load skiboot firmware */ 982 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 983 if (!fw_filename) { 984 error_report("Could not find OPAL firmware '%s'", bios_name); 985 exit(1); 986 } 987 988 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 989 if (fw_size < 0) { 990 error_report("Could not load OPAL firmware '%s'", fw_filename); 991 exit(1); 992 } 993 g_free(fw_filename); 994 995 /* load kernel */ 996 if (machine->kernel_filename) { 997 long kernel_size; 998 999 kernel_size = load_image_targphys(machine->kernel_filename, 1000 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 1001 if (kernel_size < 0) { 1002 error_report("Could not load kernel '%s'", 1003 machine->kernel_filename); 1004 exit(1); 1005 } 1006 } 1007 1008 /* load initrd */ 1009 if (machine->initrd_filename) { 1010 pnv->initrd_base = INITRD_LOAD_ADDR; 1011 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 1012 pnv->initrd_base, INITRD_MAX_SIZE); 1013 if (pnv->initrd_size < 0) { 1014 error_report("Could not load initial ram disk '%s'", 1015 machine->initrd_filename); 1016 exit(1); 1017 } 1018 } 1019 1020 /* load dtb if passed */ 1021 if (machine->dtb) { 1022 int fdt_size; 1023 1024 warn_report("with manually passed dtb, some options like '-append'" 1025 " will get ignored and the dtb passed will be used as-is"); 1026 1027 /* read the file 'machine->dtb', and load it into 'fdt' buffer */ 1028 machine->fdt = load_device_tree(machine->dtb, &fdt_size); 1029 if (!machine->fdt) { 1030 error_report("Could not load dtb '%s'", machine->dtb); 1031 exit(1); 1032 } 1033 } 1034 1035 /* MSIs are supported on this platform */ 1036 msi_nonbroken = true; 1037 1038 /* 1039 * Check compatibility of the specified CPU with the machine 1040 * default. 1041 */ 1042 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 1043 error_report("invalid CPU model '%s' for %s machine", 1044 machine->cpu_type, mc->name); 1045 exit(1); 1046 } 1047 1048 /* Create the processor chips */ 1049 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 1050 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 1051 i, machine->cpu_type); 1052 if (!object_class_by_name(chip_typename)) { 1053 error_report("invalid chip model '%.*s' for %s machine", 1054 i, machine->cpu_type, mc->name); 1055 exit(1); 1056 } 1057 1058 /* Set lpar-per-core mode if lpar-per-thread is not supported */ 1059 if (!pmc->has_lpar_per_thread) { 1060 pnv->lpar_per_core = true; 1061 } 1062 1063 pnv->num_chips = 1064 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 1065 1066 if (pnv->big_core) { 1067 if (machine->smp.threads % 2 == 1) { 1068 error_report("Cannot support %d threads with big-core option " 1069 "because it must be an even number", 1070 machine->smp.threads); 1071 exit(1); 1072 } 1073 max_smt_threads *= 2; 1074 } 1075 1076 if (machine->smp.threads > max_smt_threads) { 1077 error_report("Cannot support more than %d threads/core " 1078 "on %s machine", max_smt_threads, mc->desc); 1079 if (pmc->max_smt_threads == 4) { 1080 error_report("(use big-core=on for 8 threads per core)"); 1081 } 1082 exit(1); 1083 } 1084 1085 if (pnv->big_core) { 1086 /* 1087 * powernv models PnvCore as a SMT4 core. Big-core requires 2xPnvCore 1088 * per core, so adjust topology here. pnv_dt_core() processor 1089 * device-tree and TCG SMT code make the 2 cores appear as one big core 1090 * from software point of view. pnv pervasive models and xscoms tend to 1091 * see the big core as 2 small core halves. 1092 */ 1093 machine->smp.cores *= 2; 1094 machine->smp.threads /= 2; 1095 } 1096 1097 if (!is_power_of_2(machine->smp.threads)) { 1098 error_report("Cannot support %d threads/core on a powernv " 1099 "machine because it must be a power of 2", 1100 machine->smp.threads); 1101 exit(1); 1102 } 1103 1104 /* 1105 * TODO: should we decide on how many chips we can create based 1106 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 1107 */ 1108 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) { 1109 error_report("invalid number of chips: '%d'", pnv->num_chips); 1110 error_printf( 1111 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n"); 1112 exit(1); 1113 } 1114 1115 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 1116 for (i = 0; i < pnv->num_chips; i++) { 1117 char chip_name[32]; 1118 Object *chip = OBJECT(qdev_new(chip_typename)); 1119 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i); 1120 1121 pnv->chips[i] = PNV_CHIP(chip); 1122 1123 /* Distribute RAM among the chips */ 1124 object_property_set_int(chip, "ram-start", chip_ram_start, 1125 &error_fatal); 1126 object_property_set_int(chip, "ram-size", chip_ram_size, 1127 &error_fatal); 1128 chip_ram_start += chip_ram_size; 1129 1130 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i); 1131 object_property_add_child(OBJECT(pnv), chip_name, chip); 1132 object_property_set_int(chip, "chip-id", i, &error_fatal); 1133 object_property_set_int(chip, "nr-cores", machine->smp.cores, 1134 &error_fatal); 1135 object_property_set_int(chip, "nr-threads", machine->smp.threads, 1136 &error_fatal); 1137 object_property_set_bool(chip, "big-core", pnv->big_core, 1138 &error_fatal); 1139 object_property_set_bool(chip, "lpar-per-core", pnv->lpar_per_core, 1140 &error_fatal); 1141 /* 1142 * The POWER8 machine use the XICS interrupt interface. 1143 * Propagate the XICS fabric to the chip and its controllers. 1144 */ 1145 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 1146 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort); 1147 } 1148 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 1149 object_property_set_link(chip, "xive-fabric", OBJECT(pnv), 1150 &error_abort); 1151 } 1152 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); 1153 } 1154 g_free(chip_typename); 1155 1156 /* Instantiate ISA bus on chip 0 */ 1157 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 1158 1159 /* Create serial port */ 1160 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1161 1162 /* Create an RTC ISA device too */ 1163 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 1164 1165 /* 1166 * Create the machine BMC simulator and the IPMI BT device for 1167 * communication with the BMC 1168 */ 1169 if (defaults_enabled()) { 1170 pnv->bmc = pnv_bmc_create(pnv->pnor); 1171 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 1172 } 1173 1174 /* 1175 * The PNOR is mapped on the LPC FW address space by the BMC. 1176 * Since we can not reach the remote BMC machine with LPC memops, 1177 * map it always for now. 1178 */ 1179 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET, 1180 &pnv->pnor->mmio); 1181 1182 /* 1183 * OpenPOWER systems use a IPMI SEL Event message to notify the 1184 * host to powerdown 1185 */ 1186 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 1187 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 1188 1189 /* 1190 * Create/Connect any machine-specific I2C devices 1191 */ 1192 if (pmc->i2c_init) { 1193 pmc->i2c_init(pnv); 1194 } 1195 } 1196 1197 /* 1198 * 0:21 Reserved - Read as zeros 1199 * 22:24 Chip ID 1200 * 25:28 Core number 1201 * 29:31 Thread ID 1202 */ pnv_get_pir_tir_p8(PnvChip * chip,uint32_t core_id,uint32_t thread_id,uint32_t * pir,uint32_t * tir)1203 static void pnv_get_pir_tir_p8(PnvChip *chip, 1204 uint32_t core_id, uint32_t thread_id, 1205 uint32_t *pir, uint32_t *tir) 1206 { 1207 if (pir) { 1208 *pir = (chip->chip_id << 7) | (core_id << 3) | thread_id; 1209 } 1210 if (tir) { 1211 *tir = thread_id; 1212 } 1213 } 1214 pnv_chip_power8_intc_create(PnvChip * chip,PowerPCCPU * cpu,Error ** errp)1215 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1216 Error **errp) 1217 { 1218 Pnv8Chip *chip8 = PNV8_CHIP(chip); 1219 Error *local_err = NULL; 1220 Object *obj; 1221 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1222 1223 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 1224 if (local_err) { 1225 error_propagate(errp, local_err); 1226 return; 1227 } 1228 1229 pnv_cpu->intc = obj; 1230 } 1231 1232 pnv_chip_power8_intc_reset(PnvChip * chip,PowerPCCPU * cpu)1233 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1234 { 1235 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1236 1237 icp_reset(ICP(pnv_cpu->intc)); 1238 } 1239 pnv_chip_power8_intc_destroy(PnvChip * chip,PowerPCCPU * cpu)1240 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1241 { 1242 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1243 1244 icp_destroy(ICP(pnv_cpu->intc)); 1245 pnv_cpu->intc = NULL; 1246 } 1247 pnv_chip_power8_intc_print_info(PnvChip * chip,PowerPCCPU * cpu,GString * buf)1248 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1249 GString *buf) 1250 { 1251 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), buf); 1252 } 1253 1254 /* 1255 * 0:48 Reserved - Read as zeroes 1256 * 49:52 Node ID 1257 * 53:55 Chip ID 1258 * 56 Reserved - Read as zero 1259 * 57:61 Core number 1260 * 62:63 Thread ID 1261 * 1262 * We only care about the lower bits. uint32_t is fine for the moment. 1263 */ pnv_get_pir_tir_p9(PnvChip * chip,uint32_t core_id,uint32_t thread_id,uint32_t * pir,uint32_t * tir)1264 static void pnv_get_pir_tir_p9(PnvChip *chip, 1265 uint32_t core_id, uint32_t thread_id, 1266 uint32_t *pir, uint32_t *tir) 1267 { 1268 if (chip->big_core) { 1269 /* Big-core interleaves thread ID between small-cores */ 1270 thread_id <<= 1; 1271 thread_id |= core_id & 1; 1272 core_id >>= 1; 1273 1274 if (pir) { 1275 *pir = (chip->chip_id << 8) | (core_id << 3) | thread_id; 1276 } 1277 } else { 1278 if (pir) { 1279 *pir = (chip->chip_id << 8) | (core_id << 2) | thread_id; 1280 } 1281 } 1282 if (tir) { 1283 *tir = thread_id; 1284 } 1285 } 1286 1287 /* 1288 * 0:48 Reserved - Read as zeroes 1289 * 49:52 Node ID 1290 * 53:55 Chip ID 1291 * 56 Reserved - Read as zero 1292 * 57:59 Quad ID 1293 * 60 Core Chiplet Pair ID 1294 * 61:63 Thread/Core Chiplet ID t0-t2 1295 * 1296 * We only care about the lower bits. uint32_t is fine for the moment. 1297 */ pnv_get_pir_tir_p10(PnvChip * chip,uint32_t core_id,uint32_t thread_id,uint32_t * pir,uint32_t * tir)1298 static void pnv_get_pir_tir_p10(PnvChip *chip, 1299 uint32_t core_id, uint32_t thread_id, 1300 uint32_t *pir, uint32_t *tir) 1301 { 1302 if (chip->big_core) { 1303 /* Big-core interleaves thread ID between small-cores */ 1304 thread_id <<= 1; 1305 thread_id |= core_id & 1; 1306 core_id >>= 1; 1307 1308 if (pir) { 1309 *pir = (chip->chip_id << 8) | (core_id << 3) | thread_id; 1310 } 1311 } else { 1312 if (pir) { 1313 *pir = (chip->chip_id << 8) | (core_id << 2) | thread_id; 1314 } 1315 } 1316 if (tir) { 1317 *tir = thread_id; 1318 } 1319 } 1320 pnv_chip_power9_intc_create(PnvChip * chip,PowerPCCPU * cpu,Error ** errp)1321 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1322 Error **errp) 1323 { 1324 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1325 Error *local_err = NULL; 1326 Object *obj; 1327 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1328 1329 /* 1330 * The core creates its interrupt presenter but the XIVE interrupt 1331 * controller object is initialized afterwards. Hopefully, it's 1332 * only used at runtime. 1333 */ 1334 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 1335 &local_err); 1336 if (local_err) { 1337 error_propagate(errp, local_err); 1338 return; 1339 } 1340 1341 pnv_cpu->intc = obj; 1342 } 1343 pnv_chip_power9_intc_reset(PnvChip * chip,PowerPCCPU * cpu)1344 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1345 { 1346 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1347 1348 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1349 } 1350 pnv_chip_power9_intc_destroy(PnvChip * chip,PowerPCCPU * cpu)1351 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1352 { 1353 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1354 1355 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1356 pnv_cpu->intc = NULL; 1357 } 1358 pnv_chip_power9_intc_print_info(PnvChip * chip,PowerPCCPU * cpu,GString * buf)1359 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1360 GString *buf) 1361 { 1362 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf); 1363 } 1364 pnv_chip_power10_intc_create(PnvChip * chip,PowerPCCPU * cpu,Error ** errp)1365 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1366 Error **errp) 1367 { 1368 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1369 Error *local_err = NULL; 1370 Object *obj; 1371 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1372 1373 /* 1374 * The core creates its interrupt presenter but the XIVE2 interrupt 1375 * controller object is initialized afterwards. Hopefully, it's 1376 * only used at runtime. 1377 */ 1378 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip10->xive), 1379 &local_err); 1380 if (local_err) { 1381 error_propagate(errp, local_err); 1382 return; 1383 } 1384 1385 pnv_cpu->intc = obj; 1386 } 1387 pnv_chip_power10_intc_reset(PnvChip * chip,PowerPCCPU * cpu)1388 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1389 { 1390 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1391 1392 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1393 } 1394 pnv_chip_power10_intc_destroy(PnvChip * chip,PowerPCCPU * cpu)1395 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1396 { 1397 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1398 1399 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1400 pnv_cpu->intc = NULL; 1401 } 1402 pnv_chip_power10_intc_print_info(PnvChip * chip,PowerPCCPU * cpu,GString * buf)1403 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1404 GString *buf) 1405 { 1406 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf); 1407 } 1408 1409 /* 1410 * Allowed core identifiers on a POWER8 Processor Chip : 1411 * 1412 * <EX0 reserved> 1413 * EX1 - Venice only 1414 * EX2 - Venice only 1415 * EX3 - Venice only 1416 * EX4 1417 * EX5 1418 * EX6 1419 * <EX7,8 reserved> <reserved> 1420 * EX9 - Venice only 1421 * EX10 - Venice only 1422 * EX11 - Venice only 1423 * EX12 1424 * EX13 1425 * EX14 1426 * <EX15 reserved> 1427 */ 1428 #define POWER8E_CORE_MASK (0x7070ull) 1429 #define POWER8_CORE_MASK (0x7e7eull) 1430 1431 /* 1432 * POWER9 has 24 cores, ids starting at 0x0 1433 */ 1434 #define POWER9_CORE_MASK (0xffffffffffffffull) 1435 1436 1437 #define POWER10_CORE_MASK (0xffffffffffffffull) 1438 pnv_chip_power8_instance_init(Object * obj)1439 static void pnv_chip_power8_instance_init(Object *obj) 1440 { 1441 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1442 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1443 int i; 1444 1445 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1446 (Object **)&chip8->xics, 1447 object_property_allow_set_link, 1448 OBJ_PROP_LINK_STRONG); 1449 1450 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI); 1451 1452 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC); 1453 1454 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC); 1455 1456 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); 1457 1458 if (defaults_enabled()) { 1459 chip8->num_phbs = pcc->num_phbs; 1460 1461 for (i = 0; i < chip8->num_phbs; i++) { 1462 Object *phb = object_new(TYPE_PNV_PHB); 1463 1464 /* 1465 * We need the chip to parent the PHB to allow the DT 1466 * to build correctly (via pnv_xscom_dt()). 1467 * 1468 * TODO: the PHB should be parented by a PEC device that, at 1469 * this moment, is not modelled powernv8/phb3. 1470 */ 1471 object_property_add_child(obj, "phb[*]", phb); 1472 chip8->phbs[i] = PNV_PHB(phb); 1473 } 1474 } 1475 1476 } 1477 pnv_chip_icp_realize(Pnv8Chip * chip8,Error ** errp)1478 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1479 { 1480 PnvChip *chip = PNV_CHIP(chip8); 1481 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1482 int i, j; 1483 char *name; 1484 1485 name = g_strdup_printf("icp-%x", chip->chip_id); 1486 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1487 g_free(name); 1488 memory_region_add_subregion(get_system_memory(), PNV_ICP_BASE(chip), 1489 &chip8->icp_mmio); 1490 1491 /* Map the ICP registers for each thread */ 1492 for (i = 0; i < chip->nr_cores; i++) { 1493 PnvCore *pnv_core = chip->cores[i]; 1494 int core_hwid = CPU_CORE(pnv_core)->core_id; 1495 1496 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1497 uint32_t pir; 1498 PnvICPState *icp; 1499 1500 pcc->get_pir_tir(chip, core_hwid, j, &pir, NULL); 1501 icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1502 1503 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1504 &icp->mmio); 1505 } 1506 } 1507 } 1508 pnv_chip_power8_realize(DeviceState * dev,Error ** errp)1509 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1510 { 1511 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1512 PnvChip *chip = PNV_CHIP(dev); 1513 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1514 Pnv8Psi *psi8 = &chip8->psi; 1515 Error *local_err = NULL; 1516 int i; 1517 1518 assert(chip8->xics); 1519 1520 /* XSCOM bridge is first */ 1521 pnv_xscom_init(chip, PNV_XSCOM_SIZE, PNV_XSCOM_BASE(chip)); 1522 1523 pcc->parent_realize(dev, &local_err); 1524 if (local_err) { 1525 error_propagate(errp, local_err); 1526 return; 1527 } 1528 1529 /* Processor Service Interface (PSI) Host Bridge */ 1530 object_property_set_int(OBJECT(psi8), "bar", PNV_PSIHB_BASE(chip), 1531 &error_fatal); 1532 object_property_set_link(OBJECT(psi8), ICS_PROP_XICS, 1533 OBJECT(chip8->xics), &error_abort); 1534 if (!qdev_realize(DEVICE(psi8), NULL, errp)) { 1535 return; 1536 } 1537 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1538 &PNV_PSI(psi8)->xscom_regs); 1539 1540 /* Create LPC controller */ 1541 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal); 1542 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1543 1544 chip->fw_mr = &chip8->lpc.isa_fw; 1545 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1546 (uint64_t) PNV_XSCOM_BASE(chip), 1547 PNV_XSCOM_LPC_BASE); 1548 1549 /* 1550 * Interrupt Management Area. This is the memory region holding 1551 * all the Interrupt Control Presenter (ICP) registers 1552 */ 1553 pnv_chip_icp_realize(chip8, &local_err); 1554 if (local_err) { 1555 error_propagate(errp, local_err); 1556 return; 1557 } 1558 1559 /* Create the simplified OCC model */ 1560 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) { 1561 return; 1562 } 1563 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1564 qdev_connect_gpio_out(DEVICE(&chip8->occ), 0, 1565 qdev_get_gpio_in(DEVICE(psi8), PSIHB_IRQ_OCC)); 1566 1567 /* OCC SRAM model */ 1568 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1569 &chip8->occ.sram_regs); 1570 1571 /* HOMER */ 1572 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip), 1573 &error_abort); 1574 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) { 1575 return; 1576 } 1577 /* Homer Xscom region */ 1578 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1579 1580 /* Homer mmio region */ 1581 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1582 &chip8->homer.regs); 1583 1584 /* PHB controllers */ 1585 for (i = 0; i < chip8->num_phbs; i++) { 1586 PnvPHB *phb = chip8->phbs[i]; 1587 1588 object_property_set_int(OBJECT(phb), "index", i, &error_fatal); 1589 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, 1590 &error_fatal); 1591 object_property_set_link(OBJECT(phb), "chip", OBJECT(chip), 1592 &error_fatal); 1593 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { 1594 return; 1595 } 1596 } 1597 } 1598 pnv_chip_power8_xscom_pcba(PnvChip * chip,uint64_t addr)1599 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1600 { 1601 addr &= (PNV_XSCOM_SIZE - 1); 1602 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1603 } 1604 pnv_chip_power8e_class_init(ObjectClass * klass,void * data)1605 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1606 { 1607 DeviceClass *dc = DEVICE_CLASS(klass); 1608 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1609 1610 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1611 k->cores_mask = POWER8E_CORE_MASK; 1612 k->num_phbs = 3; 1613 k->get_pir_tir = pnv_get_pir_tir_p8; 1614 k->intc_create = pnv_chip_power8_intc_create; 1615 k->intc_reset = pnv_chip_power8_intc_reset; 1616 k->intc_destroy = pnv_chip_power8_intc_destroy; 1617 k->intc_print_info = pnv_chip_power8_intc_print_info; 1618 k->isa_create = pnv_chip_power8_isa_create; 1619 k->dt_populate = pnv_chip_power8_dt_populate; 1620 k->pic_print_info = pnv_chip_power8_pic_print_info; 1621 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1622 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1623 dc->desc = "PowerNV Chip POWER8E"; 1624 1625 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1626 &k->parent_realize); 1627 } 1628 pnv_chip_power8_class_init(ObjectClass * klass,void * data)1629 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1630 { 1631 DeviceClass *dc = DEVICE_CLASS(klass); 1632 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1633 1634 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1635 k->cores_mask = POWER8_CORE_MASK; 1636 k->num_phbs = 3; 1637 k->get_pir_tir = pnv_get_pir_tir_p8; 1638 k->intc_create = pnv_chip_power8_intc_create; 1639 k->intc_reset = pnv_chip_power8_intc_reset; 1640 k->intc_destroy = pnv_chip_power8_intc_destroy; 1641 k->intc_print_info = pnv_chip_power8_intc_print_info; 1642 k->isa_create = pnv_chip_power8_isa_create; 1643 k->dt_populate = pnv_chip_power8_dt_populate; 1644 k->pic_print_info = pnv_chip_power8_pic_print_info; 1645 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1646 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1647 dc->desc = "PowerNV Chip POWER8"; 1648 1649 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1650 &k->parent_realize); 1651 } 1652 pnv_chip_power8nvl_class_init(ObjectClass * klass,void * data)1653 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1654 { 1655 DeviceClass *dc = DEVICE_CLASS(klass); 1656 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1657 1658 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1659 k->cores_mask = POWER8_CORE_MASK; 1660 k->num_phbs = 4; 1661 k->get_pir_tir = pnv_get_pir_tir_p8; 1662 k->intc_create = pnv_chip_power8_intc_create; 1663 k->intc_reset = pnv_chip_power8_intc_reset; 1664 k->intc_destroy = pnv_chip_power8_intc_destroy; 1665 k->intc_print_info = pnv_chip_power8_intc_print_info; 1666 k->isa_create = pnv_chip_power8nvl_isa_create; 1667 k->dt_populate = pnv_chip_power8_dt_populate; 1668 k->pic_print_info = pnv_chip_power8_pic_print_info; 1669 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1670 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1671 dc->desc = "PowerNV Chip POWER8NVL"; 1672 1673 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1674 &k->parent_realize); 1675 } 1676 pnv_chip_power9_instance_init(Object * obj)1677 static void pnv_chip_power9_instance_init(Object *obj) 1678 { 1679 PnvChip *chip = PNV_CHIP(obj); 1680 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1681 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1682 int i; 1683 1684 object_initialize_child(obj, "adu", &chip9->adu, TYPE_PNV_ADU); 1685 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE); 1686 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1687 "xive-fabric"); 1688 1689 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI); 1690 1691 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); 1692 1693 object_initialize_child(obj, "chiptod", &chip9->chiptod, TYPE_PNV9_CHIPTOD); 1694 1695 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); 1696 1697 object_initialize_child(obj, "sbe", &chip9->sbe, TYPE_PNV9_SBE); 1698 1699 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); 1700 1701 /* Number of PECs is the chip default */ 1702 chip->num_pecs = pcc->num_pecs; 1703 1704 for (i = 0; i < chip->num_pecs; i++) { 1705 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1706 TYPE_PNV_PHB4_PEC); 1707 } 1708 1709 for (i = 0; i < pcc->i2c_num_engines; i++) { 1710 object_initialize_child(obj, "i2c[*]", &chip9->i2c[i], TYPE_PNV_I2C); 1711 } 1712 } 1713 pnv_chip_quad_realize_one(PnvChip * chip,PnvQuad * eq,PnvCore * pnv_core,const char * type)1714 static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq, 1715 PnvCore *pnv_core, 1716 const char *type) 1717 { 1718 char eq_name[32]; 1719 int core_id = CPU_CORE(pnv_core)->core_id; 1720 1721 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1722 object_initialize_child_with_props(OBJECT(chip), eq_name, eq, 1723 sizeof(*eq), type, 1724 &error_fatal, NULL); 1725 1726 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal); 1727 qdev_realize(DEVICE(eq), NULL, &error_fatal); 1728 } 1729 pnv_chip_quad_realize(Pnv9Chip * chip9,Error ** errp)1730 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1731 { 1732 PnvChip *chip = PNV_CHIP(chip9); 1733 int i; 1734 1735 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1736 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1737 1738 for (i = 0; i < chip9->nr_quads; i++) { 1739 PnvQuad *eq = &chip9->quads[i]; 1740 1741 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], 1742 PNV_QUAD_TYPE_NAME("power9")); 1743 1744 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id), 1745 &eq->xscom_regs); 1746 } 1747 } 1748 pnv_chip_power9_pec_realize(PnvChip * chip,Error ** errp)1749 static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp) 1750 { 1751 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1752 int i; 1753 1754 for (i = 0; i < chip->num_pecs; i++) { 1755 PnvPhb4PecState *pec = &chip9->pecs[i]; 1756 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1757 uint32_t pec_nest_base; 1758 uint32_t pec_pci_base; 1759 1760 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1761 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1762 &error_fatal); 1763 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1764 &error_fatal); 1765 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1766 return; 1767 } 1768 1769 pec_nest_base = pecc->xscom_nest_base(pec); 1770 pec_pci_base = pecc->xscom_pci_base(pec); 1771 1772 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1773 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1774 } 1775 } 1776 pnv_chip_power9_realize(DeviceState * dev,Error ** errp)1777 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1778 { 1779 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1780 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1781 PnvChip *chip = PNV_CHIP(dev); 1782 Pnv9Psi *psi9 = &chip9->psi; 1783 Error *local_err = NULL; 1784 int i; 1785 1786 /* XSCOM bridge is first */ 1787 pnv_xscom_init(chip, PNV9_XSCOM_SIZE, PNV9_XSCOM_BASE(chip)); 1788 1789 pcc->parent_realize(dev, &local_err); 1790 if (local_err) { 1791 error_propagate(errp, local_err); 1792 return; 1793 } 1794 1795 /* ADU */ 1796 object_property_set_link(OBJECT(&chip9->adu), "lpc", OBJECT(&chip9->lpc), 1797 &error_abort); 1798 if (!qdev_realize(DEVICE(&chip9->adu), NULL, errp)) { 1799 return; 1800 } 1801 pnv_xscom_add_subregion(chip, PNV9_XSCOM_ADU_BASE, 1802 &chip9->adu.xscom_regs); 1803 1804 pnv_chip_quad_realize(chip9, &local_err); 1805 if (local_err) { 1806 error_propagate(errp, local_err); 1807 return; 1808 } 1809 1810 /* XIVE interrupt controller (POWER9) */ 1811 object_property_set_int(OBJECT(&chip9->xive), "ic-bar", 1812 PNV9_XIVE_IC_BASE(chip), &error_fatal); 1813 object_property_set_int(OBJECT(&chip9->xive), "vc-bar", 1814 PNV9_XIVE_VC_BASE(chip), &error_fatal); 1815 object_property_set_int(OBJECT(&chip9->xive), "pc-bar", 1816 PNV9_XIVE_PC_BASE(chip), &error_fatal); 1817 object_property_set_int(OBJECT(&chip9->xive), "tm-bar", 1818 PNV9_XIVE_TM_BASE(chip), &error_fatal); 1819 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip), 1820 &error_abort); 1821 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) { 1822 return; 1823 } 1824 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1825 &chip9->xive.xscom_regs); 1826 1827 /* Processor Service Interface (PSI) Host Bridge */ 1828 object_property_set_int(OBJECT(psi9), "bar", PNV9_PSIHB_BASE(chip), 1829 &error_fatal); 1830 /* This is the only device with 4k ESB pages */ 1831 object_property_set_int(OBJECT(psi9), "shift", XIVE_ESB_4K, 1832 &error_fatal); 1833 if (!qdev_realize(DEVICE(psi9), NULL, errp)) { 1834 return; 1835 } 1836 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1837 &PNV_PSI(psi9)->xscom_regs); 1838 1839 /* LPC */ 1840 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) { 1841 return; 1842 } 1843 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1844 &chip9->lpc.xscom_regs); 1845 1846 chip->fw_mr = &chip9->lpc.isa_fw; 1847 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1848 (uint64_t) PNV9_LPCM_BASE(chip)); 1849 1850 /* ChipTOD */ 1851 object_property_set_bool(OBJECT(&chip9->chiptod), "primary", 1852 chip->chip_id == 0, &error_abort); 1853 object_property_set_bool(OBJECT(&chip9->chiptod), "secondary", 1854 chip->chip_id == 1, &error_abort); 1855 object_property_set_link(OBJECT(&chip9->chiptod), "chip", OBJECT(chip), 1856 &error_abort); 1857 if (!qdev_realize(DEVICE(&chip9->chiptod), NULL, errp)) { 1858 return; 1859 } 1860 pnv_xscom_add_subregion(chip, PNV9_XSCOM_CHIPTOD_BASE, 1861 &chip9->chiptod.xscom_regs); 1862 1863 /* Create the simplified OCC model */ 1864 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { 1865 return; 1866 } 1867 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1868 qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in( 1869 DEVICE(psi9), PSIHB9_IRQ_OCC)); 1870 1871 /* OCC SRAM model */ 1872 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1873 &chip9->occ.sram_regs); 1874 1875 /* SBE */ 1876 if (!qdev_realize(DEVICE(&chip9->sbe), NULL, errp)) { 1877 return; 1878 } 1879 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_CTRL_BASE, 1880 &chip9->sbe.xscom_ctrl_regs); 1881 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_MBOX_BASE, 1882 &chip9->sbe.xscom_mbox_regs); 1883 qdev_connect_gpio_out(DEVICE(&chip9->sbe), 0, qdev_get_gpio_in( 1884 DEVICE(psi9), PSIHB9_IRQ_PSU)); 1885 1886 /* HOMER */ 1887 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), 1888 &error_abort); 1889 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) { 1890 return; 1891 } 1892 /* Homer Xscom region */ 1893 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1894 1895 /* Homer mmio region */ 1896 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1897 &chip9->homer.regs); 1898 1899 /* PEC PHBs */ 1900 pnv_chip_power9_pec_realize(chip, &local_err); 1901 if (local_err) { 1902 error_propagate(errp, local_err); 1903 return; 1904 } 1905 1906 /* 1907 * I2C 1908 */ 1909 for (i = 0; i < pcc->i2c_num_engines; i++) { 1910 Object *obj = OBJECT(&chip9->i2c[i]); 1911 1912 object_property_set_int(obj, "engine", i + 1, &error_fatal); 1913 object_property_set_int(obj, "num-busses", 1914 pcc->i2c_ports_per_engine[i], 1915 &error_fatal); 1916 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort); 1917 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 1918 return; 1919 } 1920 pnv_xscom_add_subregion(chip, PNV9_XSCOM_I2CM_BASE + 1921 (chip9->i2c[i].engine - 1) * 1922 PNV9_XSCOM_I2CM_SIZE, 1923 &chip9->i2c[i].xscom_regs); 1924 qdev_connect_gpio_out(DEVICE(&chip9->i2c[i]), 0, 1925 qdev_get_gpio_in(DEVICE(psi9), 1926 PSIHB9_IRQ_SBE_I2C)); 1927 } 1928 } 1929 pnv_chip_power9_xscom_pcba(PnvChip * chip,uint64_t addr)1930 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1931 { 1932 addr &= (PNV9_XSCOM_SIZE - 1); 1933 return addr >> 3; 1934 } 1935 pnv_chip_power9_class_init(ObjectClass * klass,void * data)1936 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1937 { 1938 DeviceClass *dc = DEVICE_CLASS(klass); 1939 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1940 static const int i2c_ports_per_engine[PNV9_CHIP_MAX_I2C] = {2, 13, 2, 2}; 1941 1942 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1943 k->cores_mask = POWER9_CORE_MASK; 1944 k->get_pir_tir = pnv_get_pir_tir_p9; 1945 k->intc_create = pnv_chip_power9_intc_create; 1946 k->intc_reset = pnv_chip_power9_intc_reset; 1947 k->intc_destroy = pnv_chip_power9_intc_destroy; 1948 k->intc_print_info = pnv_chip_power9_intc_print_info; 1949 k->isa_create = pnv_chip_power9_isa_create; 1950 k->dt_populate = pnv_chip_power9_dt_populate; 1951 k->pic_print_info = pnv_chip_power9_pic_print_info; 1952 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1953 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1954 dc->desc = "PowerNV Chip POWER9"; 1955 k->num_pecs = PNV9_CHIP_MAX_PEC; 1956 k->i2c_num_engines = PNV9_CHIP_MAX_I2C; 1957 k->i2c_ports_per_engine = i2c_ports_per_engine; 1958 1959 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1960 &k->parent_realize); 1961 } 1962 pnv_chip_power10_instance_init(Object * obj)1963 static void pnv_chip_power10_instance_init(Object *obj) 1964 { 1965 PnvChip *chip = PNV_CHIP(obj); 1966 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1967 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1968 int i; 1969 1970 object_initialize_child(obj, "adu", &chip10->adu, TYPE_PNV_ADU); 1971 object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2); 1972 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive), 1973 "xive-fabric"); 1974 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); 1975 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); 1976 object_initialize_child(obj, "chiptod", &chip10->chiptod, 1977 TYPE_PNV10_CHIPTOD); 1978 object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC); 1979 object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE); 1980 object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER); 1981 object_initialize_child(obj, "n1-chiplet", &chip10->n1_chiplet, 1982 TYPE_PNV_N1_CHIPLET); 1983 1984 chip->num_pecs = pcc->num_pecs; 1985 1986 for (i = 0; i < chip->num_pecs; i++) { 1987 object_initialize_child(obj, "pec[*]", &chip10->pecs[i], 1988 TYPE_PNV_PHB5_PEC); 1989 } 1990 1991 for (i = 0; i < pcc->i2c_num_engines; i++) { 1992 object_initialize_child(obj, "i2c[*]", &chip10->i2c[i], TYPE_PNV_I2C); 1993 } 1994 1995 for (i = 0; i < PNV10_CHIP_MAX_PIB_SPIC; i++) { 1996 object_initialize_child(obj, "pib_spic[*]", &chip10->pib_spic[i], 1997 TYPE_PNV_SPI); 1998 } 1999 } 2000 pnv_chip_power10_quad_realize(Pnv10Chip * chip10,Error ** errp)2001 static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp) 2002 { 2003 PnvChip *chip = PNV_CHIP(chip10); 2004 int i; 2005 2006 chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 2007 chip10->quads = g_new0(PnvQuad, chip10->nr_quads); 2008 2009 for (i = 0; i < chip10->nr_quads; i++) { 2010 PnvQuad *eq = &chip10->quads[i]; 2011 2012 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], 2013 PNV_QUAD_TYPE_NAME("power10")); 2014 2015 pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id), 2016 &eq->xscom_regs); 2017 2018 pnv_xscom_add_subregion(chip, PNV10_XSCOM_QME_BASE(eq->quad_id), 2019 &eq->xscom_qme_regs); 2020 } 2021 } 2022 pnv_chip_power10_phb_realize(PnvChip * chip,Error ** errp)2023 static void pnv_chip_power10_phb_realize(PnvChip *chip, Error **errp) 2024 { 2025 Pnv10Chip *chip10 = PNV10_CHIP(chip); 2026 int i; 2027 2028 for (i = 0; i < chip->num_pecs; i++) { 2029 PnvPhb4PecState *pec = &chip10->pecs[i]; 2030 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 2031 uint32_t pec_nest_base; 2032 uint32_t pec_pci_base; 2033 2034 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 2035 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 2036 &error_fatal); 2037 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 2038 &error_fatal); 2039 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 2040 return; 2041 } 2042 2043 pec_nest_base = pecc->xscom_nest_base(pec); 2044 pec_pci_base = pecc->xscom_pci_base(pec); 2045 2046 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 2047 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 2048 } 2049 } 2050 pnv_chip_power10_realize(DeviceState * dev,Error ** errp)2051 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 2052 { 2053 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 2054 PnvChip *chip = PNV_CHIP(dev); 2055 Pnv10Chip *chip10 = PNV10_CHIP(dev); 2056 Error *local_err = NULL; 2057 int i; 2058 2059 /* XSCOM bridge is first */ 2060 pnv_xscom_init(chip, PNV10_XSCOM_SIZE, PNV10_XSCOM_BASE(chip)); 2061 2062 pcc->parent_realize(dev, &local_err); 2063 if (local_err) { 2064 error_propagate(errp, local_err); 2065 return; 2066 } 2067 2068 /* ADU */ 2069 object_property_set_link(OBJECT(&chip10->adu), "lpc", OBJECT(&chip10->lpc), 2070 &error_abort); 2071 if (!qdev_realize(DEVICE(&chip10->adu), NULL, errp)) { 2072 return; 2073 } 2074 pnv_xscom_add_subregion(chip, PNV10_XSCOM_ADU_BASE, 2075 &chip10->adu.xscom_regs); 2076 2077 pnv_chip_power10_quad_realize(chip10, &local_err); 2078 if (local_err) { 2079 error_propagate(errp, local_err); 2080 return; 2081 } 2082 2083 /* XIVE2 interrupt controller (POWER10) */ 2084 object_property_set_int(OBJECT(&chip10->xive), "ic-bar", 2085 PNV10_XIVE2_IC_BASE(chip), &error_fatal); 2086 object_property_set_int(OBJECT(&chip10->xive), "esb-bar", 2087 PNV10_XIVE2_ESB_BASE(chip), &error_fatal); 2088 object_property_set_int(OBJECT(&chip10->xive), "end-bar", 2089 PNV10_XIVE2_END_BASE(chip), &error_fatal); 2090 object_property_set_int(OBJECT(&chip10->xive), "nvpg-bar", 2091 PNV10_XIVE2_NVPG_BASE(chip), &error_fatal); 2092 object_property_set_int(OBJECT(&chip10->xive), "nvc-bar", 2093 PNV10_XIVE2_NVC_BASE(chip), &error_fatal); 2094 object_property_set_int(OBJECT(&chip10->xive), "tm-bar", 2095 PNV10_XIVE2_TM_BASE(chip), &error_fatal); 2096 object_property_set_link(OBJECT(&chip10->xive), "chip", OBJECT(chip), 2097 &error_abort); 2098 if (!sysbus_realize(SYS_BUS_DEVICE(&chip10->xive), errp)) { 2099 return; 2100 } 2101 pnv_xscom_add_subregion(chip, PNV10_XSCOM_XIVE2_BASE, 2102 &chip10->xive.xscom_regs); 2103 2104 /* Processor Service Interface (PSI) Host Bridge */ 2105 object_property_set_int(OBJECT(&chip10->psi), "bar", 2106 PNV10_PSIHB_BASE(chip), &error_fatal); 2107 /* PSI can now be configured to use 64k ESB pages on POWER10 */ 2108 object_property_set_int(OBJECT(&chip10->psi), "shift", XIVE_ESB_64K, 2109 &error_fatal); 2110 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) { 2111 return; 2112 } 2113 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 2114 &PNV_PSI(&chip10->psi)->xscom_regs); 2115 2116 /* LPC */ 2117 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) { 2118 return; 2119 } 2120 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 2121 &chip10->lpc.xscom_regs); 2122 2123 chip->fw_mr = &chip10->lpc.isa_fw; 2124 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 2125 (uint64_t) PNV10_LPCM_BASE(chip)); 2126 2127 /* ChipTOD */ 2128 object_property_set_bool(OBJECT(&chip10->chiptod), "primary", 2129 chip->chip_id == 0, &error_abort); 2130 object_property_set_bool(OBJECT(&chip10->chiptod), "secondary", 2131 chip->chip_id == 1, &error_abort); 2132 object_property_set_link(OBJECT(&chip10->chiptod), "chip", OBJECT(chip), 2133 &error_abort); 2134 if (!qdev_realize(DEVICE(&chip10->chiptod), NULL, errp)) { 2135 return; 2136 } 2137 pnv_xscom_add_subregion(chip, PNV10_XSCOM_CHIPTOD_BASE, 2138 &chip10->chiptod.xscom_regs); 2139 2140 /* Create the simplified OCC model */ 2141 if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) { 2142 return; 2143 } 2144 pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE, 2145 &chip10->occ.xscom_regs); 2146 qdev_connect_gpio_out(DEVICE(&chip10->occ), 0, qdev_get_gpio_in( 2147 DEVICE(&chip10->psi), PSIHB9_IRQ_OCC)); 2148 2149 /* OCC SRAM model */ 2150 memory_region_add_subregion(get_system_memory(), 2151 PNV10_OCC_SENSOR_BASE(chip), 2152 &chip10->occ.sram_regs); 2153 2154 /* SBE */ 2155 if (!qdev_realize(DEVICE(&chip10->sbe), NULL, errp)) { 2156 return; 2157 } 2158 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_CTRL_BASE, 2159 &chip10->sbe.xscom_ctrl_regs); 2160 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_MBOX_BASE, 2161 &chip10->sbe.xscom_mbox_regs); 2162 qdev_connect_gpio_out(DEVICE(&chip10->sbe), 0, qdev_get_gpio_in( 2163 DEVICE(&chip10->psi), PSIHB9_IRQ_PSU)); 2164 2165 /* HOMER */ 2166 object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip), 2167 &error_abort); 2168 if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) { 2169 return; 2170 } 2171 /* Homer Xscom region */ 2172 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE, 2173 &chip10->homer.pba_regs); 2174 2175 /* Homer mmio region */ 2176 memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip), 2177 &chip10->homer.regs); 2178 2179 /* N1 chiplet */ 2180 if (!qdev_realize(DEVICE(&chip10->n1_chiplet), NULL, errp)) { 2181 return; 2182 } 2183 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_CHIPLET_CTRL_REGS_BASE, 2184 &chip10->n1_chiplet.nest_pervasive.xscom_ctrl_regs_mr); 2185 2186 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_EQ_BASE, 2187 &chip10->n1_chiplet.xscom_pb_eq_mr); 2188 2189 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_ES_BASE, 2190 &chip10->n1_chiplet.xscom_pb_es_mr); 2191 2192 /* PHBs */ 2193 pnv_chip_power10_phb_realize(chip, &local_err); 2194 if (local_err) { 2195 error_propagate(errp, local_err); 2196 return; 2197 } 2198 2199 2200 /* 2201 * I2C 2202 */ 2203 for (i = 0; i < pcc->i2c_num_engines; i++) { 2204 Object *obj = OBJECT(&chip10->i2c[i]); 2205 2206 object_property_set_int(obj, "engine", i + 1, &error_fatal); 2207 object_property_set_int(obj, "num-busses", 2208 pcc->i2c_ports_per_engine[i], 2209 &error_fatal); 2210 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort); 2211 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 2212 return; 2213 } 2214 pnv_xscom_add_subregion(chip, PNV10_XSCOM_I2CM_BASE + 2215 (chip10->i2c[i].engine - 1) * 2216 PNV10_XSCOM_I2CM_SIZE, 2217 &chip10->i2c[i].xscom_regs); 2218 qdev_connect_gpio_out(DEVICE(&chip10->i2c[i]), 0, 2219 qdev_get_gpio_in(DEVICE(&chip10->psi), 2220 PSIHB9_IRQ_SBE_I2C)); 2221 } 2222 /* PIB SPI Controller */ 2223 for (i = 0; i < PNV10_CHIP_MAX_PIB_SPIC; i++) { 2224 object_property_set_int(OBJECT(&chip10->pib_spic[i]), "spic_num", 2225 i, &error_fatal); 2226 /* pib_spic[2] connected to 25csm04 which implements 1 byte transfer */ 2227 object_property_set_int(OBJECT(&chip10->pib_spic[i]), "transfer_len", 2228 (i == 2) ? 1 : 4, &error_fatal); 2229 if (!sysbus_realize(SYS_BUS_DEVICE(OBJECT 2230 (&chip10->pib_spic[i])), errp)) { 2231 return; 2232 } 2233 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PIB_SPIC_BASE + 2234 i * PNV10_XSCOM_PIB_SPIC_SIZE, 2235 &chip10->pib_spic[i].xscom_spic_regs); 2236 } 2237 } 2238 pnv_rainier_i2c_init(PnvMachineState * pnv)2239 static void pnv_rainier_i2c_init(PnvMachineState *pnv) 2240 { 2241 int i; 2242 for (i = 0; i < pnv->num_chips; i++) { 2243 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2244 2245 /* 2246 * Add a PCA9552 I2C device for PCIe hotplug control 2247 * to engine 2, bus 1, address 0x63 2248 */ 2249 I2CSlave *dev = i2c_slave_create_simple(chip10->i2c[2].busses[1], 2250 "pca9552", 0x63); 2251 2252 /* 2253 * Connect PCA9552 GPIO pins 0-4 (SLOTx_EN) outputs to GPIO pins 5-9 2254 * (SLOTx_PG) inputs in order to fake the pgood state of PCIe slots 2255 * after hypervisor code sets a SLOTx_EN pin high. 2256 */ 2257 qdev_connect_gpio_out(DEVICE(dev), 0, qdev_get_gpio_in(DEVICE(dev), 5)); 2258 qdev_connect_gpio_out(DEVICE(dev), 1, qdev_get_gpio_in(DEVICE(dev), 6)); 2259 qdev_connect_gpio_out(DEVICE(dev), 2, qdev_get_gpio_in(DEVICE(dev), 7)); 2260 qdev_connect_gpio_out(DEVICE(dev), 3, qdev_get_gpio_in(DEVICE(dev), 8)); 2261 qdev_connect_gpio_out(DEVICE(dev), 4, qdev_get_gpio_in(DEVICE(dev), 9)); 2262 2263 /* 2264 * Add a PCA9554 I2C device for cable card presence detection 2265 * to engine 2, bus 1, address 0x25 2266 */ 2267 i2c_slave_create_simple(chip10->i2c[2].busses[1], "pca9554", 0x25); 2268 } 2269 } 2270 pnv_chip_power10_xscom_pcba(PnvChip * chip,uint64_t addr)2271 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 2272 { 2273 addr &= (PNV10_XSCOM_SIZE - 1); 2274 return addr >> 3; 2275 } 2276 pnv_chip_power10_class_init(ObjectClass * klass,void * data)2277 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 2278 { 2279 DeviceClass *dc = DEVICE_CLASS(klass); 2280 PnvChipClass *k = PNV_CHIP_CLASS(klass); 2281 static const int i2c_ports_per_engine[PNV10_CHIP_MAX_I2C] = {14, 14, 2, 16}; 2282 2283 k->chip_cfam_id = 0x220da04980000000ull; /* P10 DD2.0 (with NX) */ 2284 k->cores_mask = POWER10_CORE_MASK; 2285 k->get_pir_tir = pnv_get_pir_tir_p10; 2286 k->intc_create = pnv_chip_power10_intc_create; 2287 k->intc_reset = pnv_chip_power10_intc_reset; 2288 k->intc_destroy = pnv_chip_power10_intc_destroy; 2289 k->intc_print_info = pnv_chip_power10_intc_print_info; 2290 k->isa_create = pnv_chip_power10_isa_create; 2291 k->dt_populate = pnv_chip_power10_dt_populate; 2292 k->pic_print_info = pnv_chip_power10_pic_print_info; 2293 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 2294 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 2295 dc->desc = "PowerNV Chip POWER10"; 2296 k->num_pecs = PNV10_CHIP_MAX_PEC; 2297 k->i2c_num_engines = PNV10_CHIP_MAX_I2C; 2298 k->i2c_ports_per_engine = i2c_ports_per_engine; 2299 2300 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 2301 &k->parent_realize); 2302 } 2303 pnv_chip_core_sanitize(PnvMachineState * pnv,PnvChip * chip,Error ** errp)2304 static void pnv_chip_core_sanitize(PnvMachineState *pnv, PnvChip *chip, 2305 Error **errp) 2306 { 2307 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 2308 int cores_max; 2309 2310 /* 2311 * No custom mask for this chip, let's use the default one from * 2312 * the chip class 2313 */ 2314 if (!chip->cores_mask) { 2315 chip->cores_mask = pcc->cores_mask; 2316 } 2317 2318 /* filter alien core ids ! some are reserved */ 2319 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 2320 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 2321 chip->cores_mask); 2322 return; 2323 } 2324 chip->cores_mask &= pcc->cores_mask; 2325 2326 /* Ensure small-cores a paired up in big-core mode */ 2327 if (pnv->big_core) { 2328 uint64_t even_cores = chip->cores_mask & 0x5555555555555555ULL; 2329 uint64_t odd_cores = chip->cores_mask & 0xaaaaaaaaaaaaaaaaULL; 2330 2331 if (even_cores ^ (odd_cores >> 1)) { 2332 error_setg(errp, "warning: unpaired cores in big-core mode !"); 2333 return; 2334 } 2335 } 2336 2337 /* now that we have a sane layout, let check the number of cores */ 2338 cores_max = ctpop64(chip->cores_mask); 2339 if (chip->nr_cores > cores_max) { 2340 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 2341 cores_max); 2342 return; 2343 } 2344 } 2345 pnv_chip_core_realize(PnvChip * chip,Error ** errp)2346 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 2347 { 2348 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 2349 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(pnv); 2350 Error *error = NULL; 2351 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 2352 const char *typename = pnv_chip_core_typename(chip); 2353 int i, core_hwid; 2354 2355 if (!object_class_by_name(typename)) { 2356 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 2357 return; 2358 } 2359 2360 /* Cores */ 2361 pnv_chip_core_sanitize(pnv, chip, &error); 2362 if (error) { 2363 error_propagate(errp, error); 2364 return; 2365 } 2366 2367 chip->cores = g_new0(PnvCore *, chip->nr_cores); 2368 2369 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 2370 && (i < chip->nr_cores); core_hwid++) { 2371 char core_name[32]; 2372 PnvCore *pnv_core; 2373 uint64_t xscom_core_base; 2374 2375 if (!(chip->cores_mask & (1ull << core_hwid))) { 2376 continue; 2377 } 2378 2379 pnv_core = PNV_CORE(object_new(typename)); 2380 2381 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 2382 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core)); 2383 chip->cores[i] = pnv_core; 2384 object_property_set_int(OBJECT(pnv_core), "nr-threads", 2385 chip->nr_threads, &error_fatal); 2386 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID, 2387 core_hwid, &error_fatal); 2388 object_property_set_int(OBJECT(pnv_core), "hwid", core_hwid, 2389 &error_fatal); 2390 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr, 2391 &error_fatal); 2392 object_property_set_bool(OBJECT(pnv_core), "big-core", chip->big_core, 2393 &error_fatal); 2394 object_property_set_bool(OBJECT(pnv_core), "quirk-tb-big-core", 2395 pmc->quirk_tb_big_core, &error_fatal); 2396 object_property_set_bool(OBJECT(pnv_core), "lpar-per-core", 2397 chip->lpar_per_core, &error_fatal); 2398 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), 2399 &error_abort); 2400 2401 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); 2402 2403 /* Each core has an XSCOM MMIO region */ 2404 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 2405 2406 pnv_xscom_add_subregion(chip, xscom_core_base, 2407 &pnv_core->xscom_regs); 2408 i++; 2409 } 2410 } 2411 pnv_chip_realize(DeviceState * dev,Error ** errp)2412 static void pnv_chip_realize(DeviceState *dev, Error **errp) 2413 { 2414 PnvChip *chip = PNV_CHIP(dev); 2415 Error *error = NULL; 2416 2417 /* Cores */ 2418 pnv_chip_core_realize(chip, &error); 2419 if (error) { 2420 error_propagate(errp, error); 2421 return; 2422 } 2423 } 2424 2425 static Property pnv_chip_properties[] = { 2426 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 2427 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 2428 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 2429 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 2430 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 2431 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 2432 DEFINE_PROP_BOOL("big-core", PnvChip, big_core, false), 2433 DEFINE_PROP_BOOL("lpar-per-core", PnvChip, lpar_per_core, false), 2434 DEFINE_PROP_END_OF_LIST(), 2435 }; 2436 pnv_chip_class_init(ObjectClass * klass,void * data)2437 static void pnv_chip_class_init(ObjectClass *klass, void *data) 2438 { 2439 DeviceClass *dc = DEVICE_CLASS(klass); 2440 2441 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 2442 dc->realize = pnv_chip_realize; 2443 device_class_set_props(dc, pnv_chip_properties); 2444 dc->desc = "PowerNV Chip"; 2445 } 2446 pnv_chip_find_core(PnvChip * chip,uint32_t core_id)2447 PnvCore *pnv_chip_find_core(PnvChip *chip, uint32_t core_id) 2448 { 2449 int i; 2450 2451 for (i = 0; i < chip->nr_cores; i++) { 2452 PnvCore *pc = chip->cores[i]; 2453 CPUCore *cc = CPU_CORE(pc); 2454 2455 if (cc->core_id == core_id) { 2456 return pc; 2457 } 2458 } 2459 return NULL; 2460 } 2461 pnv_chip_find_cpu(PnvChip * chip,uint32_t pir)2462 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 2463 { 2464 int i, j; 2465 2466 for (i = 0; i < chip->nr_cores; i++) { 2467 PnvCore *pc = chip->cores[i]; 2468 CPUCore *cc = CPU_CORE(pc); 2469 2470 for (j = 0; j < cc->nr_threads; j++) { 2471 if (ppc_cpu_pir(pc->threads[j]) == pir) { 2472 return pc->threads[j]; 2473 } 2474 } 2475 } 2476 return NULL; 2477 } 2478 pnv_chip_foreach_cpu(PnvChip * chip,void (* fn)(PnvChip * chip,PowerPCCPU * cpu,void * opaque),void * opaque)2479 static void pnv_chip_foreach_cpu(PnvChip *chip, 2480 void (*fn)(PnvChip *chip, PowerPCCPU *cpu, void *opaque), 2481 void *opaque) 2482 { 2483 int i, j; 2484 2485 for (i = 0; i < chip->nr_cores; i++) { 2486 PnvCore *pc = chip->cores[i]; 2487 2488 for (j = 0; j < CPU_CORE(pc)->nr_threads; j++) { 2489 fn(chip, pc->threads[j], opaque); 2490 } 2491 } 2492 } 2493 pnv_ics_get(XICSFabric * xi,int irq)2494 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 2495 { 2496 PnvMachineState *pnv = PNV_MACHINE(xi); 2497 int i, j; 2498 2499 for (i = 0; i < pnv->num_chips; i++) { 2500 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2501 2502 if (ics_valid_irq(&chip8->psi.ics, irq)) { 2503 return &chip8->psi.ics; 2504 } 2505 2506 for (j = 0; j < chip8->num_phbs; j++) { 2507 PnvPHB *phb = chip8->phbs[j]; 2508 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2509 2510 if (ics_valid_irq(&phb3->lsis, irq)) { 2511 return &phb3->lsis; 2512 } 2513 2514 if (ics_valid_irq(ICS(&phb3->msis), irq)) { 2515 return ICS(&phb3->msis); 2516 } 2517 } 2518 } 2519 return NULL; 2520 } 2521 pnv_get_chip(PnvMachineState * pnv,uint32_t chip_id)2522 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id) 2523 { 2524 int i; 2525 2526 for (i = 0; i < pnv->num_chips; i++) { 2527 PnvChip *chip = pnv->chips[i]; 2528 if (chip->chip_id == chip_id) { 2529 return chip; 2530 } 2531 } 2532 return NULL; 2533 } 2534 pnv_ics_resend(XICSFabric * xi)2535 static void pnv_ics_resend(XICSFabric *xi) 2536 { 2537 PnvMachineState *pnv = PNV_MACHINE(xi); 2538 int i, j; 2539 2540 for (i = 0; i < pnv->num_chips; i++) { 2541 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2542 2543 ics_resend(&chip8->psi.ics); 2544 2545 for (j = 0; j < chip8->num_phbs; j++) { 2546 PnvPHB *phb = chip8->phbs[j]; 2547 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2548 2549 ics_resend(&phb3->lsis); 2550 ics_resend(ICS(&phb3->msis)); 2551 } 2552 } 2553 } 2554 pnv_icp_get(XICSFabric * xi,int pir)2555 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 2556 { 2557 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 2558 2559 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 2560 } 2561 pnv_pic_intc_print_info(PnvChip * chip,PowerPCCPU * cpu,void * opaque)2562 static void pnv_pic_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 2563 void *opaque) 2564 { 2565 PNV_CHIP_GET_CLASS(chip)->intc_print_info(chip, cpu, opaque); 2566 } 2567 pnv_pic_print_info(InterruptStatsProvider * obj,GString * buf)2568 static void pnv_pic_print_info(InterruptStatsProvider *obj, GString *buf) 2569 { 2570 PnvMachineState *pnv = PNV_MACHINE(obj); 2571 int i; 2572 2573 for (i = 0; i < pnv->num_chips; i++) { 2574 PnvChip *chip = pnv->chips[i]; 2575 2576 /* First CPU presenters */ 2577 pnv_chip_foreach_cpu(chip, pnv_pic_intc_print_info, buf); 2578 2579 /* Then other devices, PHB, PSI, XIVE */ 2580 PNV_CHIP_GET_CLASS(chip)->pic_print_info(chip, buf); 2581 } 2582 } 2583 pnv_match_nvt(XiveFabric * xfb,uint8_t format,uint8_t nvt_blk,uint32_t nvt_idx,bool cam_ignore,uint8_t priority,uint32_t logic_serv,XiveTCTXMatch * match)2584 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 2585 uint8_t nvt_blk, uint32_t nvt_idx, 2586 bool cam_ignore, uint8_t priority, 2587 uint32_t logic_serv, 2588 XiveTCTXMatch *match) 2589 { 2590 PnvMachineState *pnv = PNV_MACHINE(xfb); 2591 int total_count = 0; 2592 int i; 2593 2594 for (i = 0; i < pnv->num_chips; i++) { 2595 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 2596 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 2597 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2598 int count; 2599 2600 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2601 priority, logic_serv, match); 2602 2603 if (count < 0) { 2604 return count; 2605 } 2606 2607 total_count += count; 2608 } 2609 2610 return total_count; 2611 } 2612 pnv10_xive_match_nvt(XiveFabric * xfb,uint8_t format,uint8_t nvt_blk,uint32_t nvt_idx,bool cam_ignore,uint8_t priority,uint32_t logic_serv,XiveTCTXMatch * match)2613 static int pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format, 2614 uint8_t nvt_blk, uint32_t nvt_idx, 2615 bool cam_ignore, uint8_t priority, 2616 uint32_t logic_serv, 2617 XiveTCTXMatch *match) 2618 { 2619 PnvMachineState *pnv = PNV_MACHINE(xfb); 2620 int total_count = 0; 2621 int i; 2622 2623 for (i = 0; i < pnv->num_chips; i++) { 2624 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2625 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive); 2626 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2627 int count; 2628 2629 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2630 priority, logic_serv, match); 2631 2632 if (count < 0) { 2633 return count; 2634 } 2635 2636 total_count += count; 2637 } 2638 2639 return total_count; 2640 } 2641 pnv_machine_get_big_core(Object * obj,Error ** errp)2642 static bool pnv_machine_get_big_core(Object *obj, Error **errp) 2643 { 2644 PnvMachineState *pnv = PNV_MACHINE(obj); 2645 return pnv->big_core; 2646 } 2647 pnv_machine_set_big_core(Object * obj,bool value,Error ** errp)2648 static void pnv_machine_set_big_core(Object *obj, bool value, Error **errp) 2649 { 2650 PnvMachineState *pnv = PNV_MACHINE(obj); 2651 pnv->big_core = value; 2652 } 2653 pnv_machine_get_lpar_per_core(Object * obj,Error ** errp)2654 static bool pnv_machine_get_lpar_per_core(Object *obj, Error **errp) 2655 { 2656 PnvMachineState *pnv = PNV_MACHINE(obj); 2657 return pnv->lpar_per_core; 2658 } 2659 pnv_machine_set_lpar_per_core(Object * obj,bool value,Error ** errp)2660 static void pnv_machine_set_lpar_per_core(Object *obj, bool value, Error **errp) 2661 { 2662 PnvMachineState *pnv = PNV_MACHINE(obj); 2663 pnv->lpar_per_core = value; 2664 } 2665 pnv_machine_get_hb(Object * obj,Error ** errp)2666 static bool pnv_machine_get_hb(Object *obj, Error **errp) 2667 { 2668 PnvMachineState *pnv = PNV_MACHINE(obj); 2669 2670 return !!pnv->fw_load_addr; 2671 } 2672 pnv_machine_set_hb(Object * obj,bool value,Error ** errp)2673 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 2674 { 2675 PnvMachineState *pnv = PNV_MACHINE(obj); 2676 2677 if (value) { 2678 pnv->fw_load_addr = 0x8000000; 2679 } 2680 } 2681 pnv_machine_power8_class_init(ObjectClass * oc,void * data)2682 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 2683 { 2684 MachineClass *mc = MACHINE_CLASS(oc); 2685 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 2686 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2687 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 2688 2689 static GlobalProperty phb_compat[] = { 2690 { TYPE_PNV_PHB, "version", "3" }, 2691 { TYPE_PNV_PHB_ROOT_PORT, "version", "3" }, 2692 }; 2693 2694 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 2695 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 2696 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2697 2698 xic->icp_get = pnv_icp_get; 2699 xic->ics_get = pnv_ics_get; 2700 xic->ics_resend = pnv_ics_resend; 2701 2702 pmc->compat = compat; 2703 pmc->compat_size = sizeof(compat); 2704 pmc->max_smt_threads = 8; 2705 /* POWER8 is always lpar-per-core mode */ 2706 pmc->has_lpar_per_thread = false; 2707 2708 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2709 } 2710 pnv_machine_power9_class_init(ObjectClass * oc,void * data)2711 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 2712 { 2713 MachineClass *mc = MACHINE_CLASS(oc); 2714 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2715 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2716 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 2717 2718 static GlobalProperty phb_compat[] = { 2719 { TYPE_PNV_PHB, "version", "4" }, 2720 { TYPE_PNV_PHB_ROOT_PORT, "version", "4" }, 2721 }; 2722 2723 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 2724 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.2"); 2725 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2726 2727 xfc->match_nvt = pnv_match_nvt; 2728 2729 pmc->compat = compat; 2730 pmc->compat_size = sizeof(compat); 2731 pmc->max_smt_threads = 4; 2732 pmc->has_lpar_per_thread = true; 2733 pmc->dt_power_mgt = pnv_dt_power_mgt; 2734 2735 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2736 2737 object_class_property_add_bool(oc, "big-core", 2738 pnv_machine_get_big_core, 2739 pnv_machine_set_big_core); 2740 object_class_property_set_description(oc, "big-core", 2741 "Use big-core (aka fused-core) mode"); 2742 2743 object_class_property_add_bool(oc, "lpar-per-core", 2744 pnv_machine_get_lpar_per_core, 2745 pnv_machine_set_lpar_per_core); 2746 object_class_property_set_description(oc, "lpar-per-core", 2747 "Use 1 LPAR per core mode"); 2748 } 2749 pnv_machine_p10_common_class_init(ObjectClass * oc,void * data)2750 static void pnv_machine_p10_common_class_init(ObjectClass *oc, void *data) 2751 { 2752 MachineClass *mc = MACHINE_CLASS(oc); 2753 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2754 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2755 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 2756 2757 static GlobalProperty phb_compat[] = { 2758 { TYPE_PNV_PHB, "version", "5" }, 2759 { TYPE_PNV_PHB_ROOT_PORT, "version", "5" }, 2760 }; 2761 2762 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); 2763 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2764 2765 mc->alias = "powernv"; 2766 2767 pmc->compat = compat; 2768 pmc->compat_size = sizeof(compat); 2769 pmc->max_smt_threads = 4; 2770 pmc->has_lpar_per_thread = true; 2771 pmc->quirk_tb_big_core = true; 2772 pmc->dt_power_mgt = pnv_dt_power_mgt; 2773 2774 xfc->match_nvt = pnv10_xive_match_nvt; 2775 2776 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2777 } 2778 pnv_machine_power10_class_init(ObjectClass * oc,void * data)2779 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 2780 { 2781 MachineClass *mc = MACHINE_CLASS(oc); 2782 2783 pnv_machine_p10_common_class_init(oc, data); 2784 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 2785 2786 /* 2787 * This is the parent of POWER10 Rainier class, so properies go here 2788 * rather than common init (which would add them to both parent and 2789 * child which is invalid). 2790 */ 2791 object_class_property_add_bool(oc, "big-core", 2792 pnv_machine_get_big_core, 2793 pnv_machine_set_big_core); 2794 object_class_property_set_description(oc, "big-core", 2795 "Use big-core (aka fused-core) mode"); 2796 2797 object_class_property_add_bool(oc, "lpar-per-core", 2798 pnv_machine_get_lpar_per_core, 2799 pnv_machine_set_lpar_per_core); 2800 object_class_property_set_description(oc, "lpar-per-core", 2801 "Use 1 LPAR per core mode"); 2802 } 2803 pnv_machine_p10_rainier_class_init(ObjectClass * oc,void * data)2804 static void pnv_machine_p10_rainier_class_init(ObjectClass *oc, void *data) 2805 { 2806 MachineClass *mc = MACHINE_CLASS(oc); 2807 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2808 2809 pnv_machine_p10_common_class_init(oc, data); 2810 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10 Rainier"; 2811 pmc->i2c_init = pnv_rainier_i2c_init; 2812 } 2813 pnv_cpu_do_nmi_on_cpu(CPUState * cs,run_on_cpu_data arg)2814 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) 2815 { 2816 CPUPPCState *env = cpu_env(cs); 2817 2818 cpu_synchronize_state(cs); 2819 ppc_cpu_do_system_reset(cs); 2820 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { 2821 /* 2822 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the 2823 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100 2824 * (PPC_BIT(43)). 2825 */ 2826 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { 2827 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason"); 2828 env->spr[SPR_SRR1] |= SRR1_WAKERESET; 2829 } 2830 } else { 2831 /* 2832 * For non-powersave system resets, SRR1[42:45] are defined to be 2833 * implementation-dependent. The POWER9 User Manual specifies that 2834 * an external (SCOM driven, which may come from a BMC nmi command or 2835 * another CPU requesting a NMI IPI) system reset exception should be 2836 * 0b0010 (PPC_BIT(44)). 2837 */ 2838 env->spr[SPR_SRR1] |= SRR1_WAKESCOM; 2839 } 2840 if (arg.host_int == 1) { 2841 cpu_resume(cs); 2842 } 2843 } 2844 2845 /* 2846 * Send a SRESET (NMI) interrupt to the CPU, and resume execution if it was 2847 * paused. 2848 */ pnv_cpu_do_nmi_resume(CPUState * cs)2849 void pnv_cpu_do_nmi_resume(CPUState *cs) 2850 { 2851 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_HOST_INT(1)); 2852 } 2853 pnv_cpu_do_nmi(PnvChip * chip,PowerPCCPU * cpu,void * opaque)2854 static void pnv_cpu_do_nmi(PnvChip *chip, PowerPCCPU *cpu, void *opaque) 2855 { 2856 async_run_on_cpu(CPU(cpu), pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_HOST_INT(0)); 2857 } 2858 pnv_nmi(NMIState * n,int cpu_index,Error ** errp)2859 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) 2860 { 2861 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 2862 int i; 2863 2864 for (i = 0; i < pnv->num_chips; i++) { 2865 pnv_chip_foreach_cpu(pnv->chips[i], pnv_cpu_do_nmi, NULL); 2866 } 2867 } 2868 pnv_machine_class_init(ObjectClass * oc,void * data)2869 static void pnv_machine_class_init(ObjectClass *oc, void *data) 2870 { 2871 MachineClass *mc = MACHINE_CLASS(oc); 2872 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 2873 NMIClass *nc = NMI_CLASS(oc); 2874 2875 mc->desc = "IBM PowerNV (Non-Virtualized)"; 2876 mc->init = pnv_init; 2877 mc->reset = pnv_reset; 2878 mc->max_cpus = MAX_CPUS; 2879 /* Pnv provides a AHCI device for storage */ 2880 mc->block_default_type = IF_IDE; 2881 mc->no_parallel = 1; 2882 mc->default_boot_order = NULL; 2883 /* 2884 * RAM defaults to less than 2048 for 32-bit hosts, and large 2885 * enough to fit the maximum initrd size at it's load address 2886 */ 2887 mc->default_ram_size = 1 * GiB; 2888 mc->default_ram_id = "pnv.ram"; 2889 ispc->print_info = pnv_pic_print_info; 2890 nc->nmi_monitor_handler = pnv_nmi; 2891 2892 object_class_property_add_bool(oc, "hb-mode", 2893 pnv_machine_get_hb, pnv_machine_set_hb); 2894 object_class_property_set_description(oc, "hb-mode", 2895 "Use a hostboot like boot loader"); 2896 } 2897 2898 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 2899 { \ 2900 .name = type, \ 2901 .class_init = class_initfn, \ 2902 .parent = TYPE_PNV8_CHIP, \ 2903 } 2904 2905 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 2906 { \ 2907 .name = type, \ 2908 .class_init = class_initfn, \ 2909 .parent = TYPE_PNV9_CHIP, \ 2910 } 2911 2912 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2913 { \ 2914 .name = type, \ 2915 .class_init = class_initfn, \ 2916 .parent = TYPE_PNV10_CHIP, \ 2917 } 2918 2919 static const TypeInfo types[] = { 2920 { 2921 .name = MACHINE_TYPE_NAME("powernv10-rainier"), 2922 .parent = MACHINE_TYPE_NAME("powernv10"), 2923 .class_init = pnv_machine_p10_rainier_class_init, 2924 }, 2925 { 2926 .name = MACHINE_TYPE_NAME("powernv10"), 2927 .parent = TYPE_PNV_MACHINE, 2928 .class_init = pnv_machine_power10_class_init, 2929 .interfaces = (InterfaceInfo[]) { 2930 { TYPE_XIVE_FABRIC }, 2931 { }, 2932 }, 2933 }, 2934 { 2935 .name = MACHINE_TYPE_NAME("powernv9"), 2936 .parent = TYPE_PNV_MACHINE, 2937 .class_init = pnv_machine_power9_class_init, 2938 .interfaces = (InterfaceInfo[]) { 2939 { TYPE_XIVE_FABRIC }, 2940 { }, 2941 }, 2942 }, 2943 { 2944 .name = MACHINE_TYPE_NAME("powernv8"), 2945 .parent = TYPE_PNV_MACHINE, 2946 .class_init = pnv_machine_power8_class_init, 2947 .interfaces = (InterfaceInfo[]) { 2948 { TYPE_XICS_FABRIC }, 2949 { }, 2950 }, 2951 }, 2952 { 2953 .name = TYPE_PNV_MACHINE, 2954 .parent = TYPE_MACHINE, 2955 .abstract = true, 2956 .instance_size = sizeof(PnvMachineState), 2957 .class_init = pnv_machine_class_init, 2958 .class_size = sizeof(PnvMachineClass), 2959 .interfaces = (InterfaceInfo[]) { 2960 { TYPE_INTERRUPT_STATS_PROVIDER }, 2961 { TYPE_NMI }, 2962 { }, 2963 }, 2964 }, 2965 { 2966 .name = TYPE_PNV_CHIP, 2967 .parent = TYPE_SYS_BUS_DEVICE, 2968 .class_init = pnv_chip_class_init, 2969 .instance_size = sizeof(PnvChip), 2970 .class_size = sizeof(PnvChipClass), 2971 .abstract = true, 2972 }, 2973 2974 /* 2975 * P10 chip and variants 2976 */ 2977 { 2978 .name = TYPE_PNV10_CHIP, 2979 .parent = TYPE_PNV_CHIP, 2980 .instance_init = pnv_chip_power10_instance_init, 2981 .instance_size = sizeof(Pnv10Chip), 2982 }, 2983 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 2984 2985 /* 2986 * P9 chip and variants 2987 */ 2988 { 2989 .name = TYPE_PNV9_CHIP, 2990 .parent = TYPE_PNV_CHIP, 2991 .instance_init = pnv_chip_power9_instance_init, 2992 .instance_size = sizeof(Pnv9Chip), 2993 }, 2994 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 2995 2996 /* 2997 * P8 chip and variants 2998 */ 2999 { 3000 .name = TYPE_PNV8_CHIP, 3001 .parent = TYPE_PNV_CHIP, 3002 .instance_init = pnv_chip_power8_instance_init, 3003 .instance_size = sizeof(Pnv8Chip), 3004 }, 3005 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 3006 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 3007 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 3008 pnv_chip_power8nvl_class_init), 3009 }; 3010 3011 DEFINE_TYPES(types) 3012