xref: /openbmc/linux/drivers/clk/samsung/clk-pll.h (revision f2819ea1)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
4  * Copyright (c) 2013 Linaro Ltd.
5  *
6  * Common Clock Framework support for all PLL's in Samsung platforms
7 */
8 
9 #ifndef __SAMSUNG_CLK_PLL_H
10 #define __SAMSUNG_CLK_PLL_H
11 
12 enum samsung_pll_type {
13 	pll_2126,
14 	pll_3000,
15 	pll_35xx,
16 	pll_36xx,
17 	pll_2550,
18 	pll_2650,
19 	pll_4500,
20 	pll_4502,
21 	pll_4508,
22 	pll_4600,
23 	pll_4650,
24 	pll_4650c,
25 	pll_6552,
26 	pll_6552_s3c2416,
27 	pll_6553,
28 	pll_2550x,
29 	pll_2550xx,
30 	pll_2650x,
31 	pll_2650xx,
32 	pll_1417x,
33 	pll_1450x,
34 	pll_1451x,
35 	pll_1452x,
36 	pll_1460x,
37 	pll_0818x,
38 	pll_0822x,
39 	pll_0831x,
40 	pll_142xx,
41 };
42 
43 #define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \
44 	((u64)(_fin) * (BIT(_ks) * (_m) + (_k)) / BIT(_ks) / ((_p) << (_s)))
45 #define PLL_VALID_RATE(_fin, _fout, _m, _p, _s, _k, _ks) ((_fout) + \
46 	BUILD_BUG_ON_ZERO(PLL_RATE(_fin, _m, _p, _s, _k, _ks) != (_fout)))
47 
48 #define PLL_35XX_RATE(_fin, _rate, _m, _p, _s)			\
49 	{							\
50 		.rate	=	PLL_VALID_RATE(_fin, _rate,	\
51 				_m, _p, _s, 0, 16),		\
52 		.mdiv	=	(_m),				\
53 		.pdiv	=	(_p),				\
54 		.sdiv	=	(_s),				\
55 	}
56 
57 #define PLL_36XX_RATE(_fin, _rate, _m, _p, _s, _k)		\
58 	{							\
59 		.rate	=	PLL_VALID_RATE(_fin, _rate,	\
60 				_m, _p, _s, _k, 16),		\
61 		.mdiv	=	(_m),				\
62 		.pdiv	=	(_p),				\
63 		.sdiv	=	(_s),				\
64 		.kdiv	=	(_k),				\
65 	}
66 
67 #define PLL_4508_RATE(_fin, _rate, _m, _p, _s, _afc)		\
68 	{							\
69 		.rate	=	PLL_VALID_RATE(_fin, _rate,	\
70 				_m, _p, _s - 1, 0, 16),		\
71 		.mdiv	=	(_m),				\
72 		.pdiv	=	(_p),				\
73 		.sdiv	=	(_s),				\
74 		.afc	=	(_afc),				\
75 	}
76 
77 #define PLL_4600_RATE(_fin, _rate, _m, _p, _s, _k, _vsel)	\
78 	{							\
79 		.rate	=	PLL_VALID_RATE(_fin, _rate,	\
80 				_m, _p, _s, _k, 16),		\
81 		.mdiv	=	(_m),				\
82 		.pdiv	=	(_p),				\
83 		.sdiv	=	(_s),				\
84 		.kdiv	=	(_k),				\
85 		.vsel	=	(_vsel),			\
86 	}
87 
88 #define PLL_4650_RATE(_fin, _rate, _m, _p, _s, _k, _mfr, _mrr, _vsel) \
89 	{							\
90 		.rate	=	PLL_VALID_RATE(_fin, _rate,	\
91 				_m, _p, _s, _k, 10),		\
92 		.mdiv	=	(_m),				\
93 		.pdiv	=	(_p),				\
94 		.sdiv	=	(_s),				\
95 		.kdiv	=	(_k),				\
96 		.mfr	=	(_mfr),				\
97 		.mrr	=	(_mrr),				\
98 		.vsel	=	(_vsel),			\
99 	}
100 
101 /* NOTE: Rate table should be kept sorted in descending order. */
102 
103 struct samsung_pll_rate_table {
104 	unsigned int rate;
105 	unsigned int pdiv;
106 	unsigned int mdiv;
107 	unsigned int sdiv;
108 	unsigned int kdiv;
109 	unsigned int afc;
110 	unsigned int mfr;
111 	unsigned int mrr;
112 	unsigned int vsel;
113 };
114 
115 #endif /* __SAMSUNG_CLK_PLL_H */
116