xref: /openbmc/qemu/hw/rtc/pl031.c (revision 4d28d57c)
1 /*
2  * ARM AMBA PrimeCell PL031 RTC
3  *
4  * Copyright (c) 2007 CodeSourcery
5  *
6  * This file is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * Contributions after 2012-01-13 are licensed under the terms of the
11  * GNU GPL, version 2 or (at your option) any later version.
12  */
13 
14 #include "qemu/osdep.h"
15 #include "hw/rtc/pl031.h"
16 #include "migration/vmstate.h"
17 #include "hw/irq.h"
18 #include "hw/qdev-properties.h"
19 #include "hw/sysbus.h"
20 #include "qemu/timer.h"
21 #include "sysemu/sysemu.h"
22 #include "sysemu/rtc.h"
23 #include "qemu/cutils.h"
24 #include "qemu/log.h"
25 #include "qemu/module.h"
26 #include "trace.h"
27 #include "qapi/qapi-events-misc.h"
28 
29 #define RTC_DR      0x00    /* Data read register */
30 #define RTC_MR      0x04    /* Match register */
31 #define RTC_LR      0x08    /* Data load register */
32 #define RTC_CR      0x0c    /* Control register */
33 #define RTC_IMSC    0x10    /* Interrupt mask and set register */
34 #define RTC_RIS     0x14    /* Raw interrupt status register */
35 #define RTC_MIS     0x18    /* Masked interrupt status register */
36 #define RTC_ICR     0x1c    /* Interrupt clear register */
37 
38 static const unsigned char pl031_id[] = {
39     0x31, 0x10, 0x14, 0x00,         /* Device ID        */
40     0x0d, 0xf0, 0x05, 0xb1          /* Cell ID      */
41 };
42 
pl031_update(PL031State * s)43 static void pl031_update(PL031State *s)
44 {
45     uint32_t flags = s->is & s->im;
46 
47     trace_pl031_irq_state(flags);
48     qemu_set_irq(s->irq, flags);
49 }
50 
pl031_interrupt(void * opaque)51 static void pl031_interrupt(void * opaque)
52 {
53     PL031State *s = (PL031State *)opaque;
54 
55     s->is = 1;
56     trace_pl031_alarm_raised();
57     pl031_update(s);
58 }
59 
pl031_get_count(PL031State * s)60 static uint32_t pl031_get_count(PL031State *s)
61 {
62     int64_t now = qemu_clock_get_ns(rtc_clock);
63     return s->tick_offset + now / NANOSECONDS_PER_SECOND;
64 }
65 
pl031_set_alarm(PL031State * s)66 static void pl031_set_alarm(PL031State *s)
67 {
68     uint32_t ticks;
69 
70     /* The timer wraps around.  This subtraction also wraps in the same way,
71        and gives correct results when alarm < now_ticks.  */
72     ticks = s->mr - pl031_get_count(s);
73     trace_pl031_set_alarm(ticks);
74     if (ticks == 0) {
75         timer_del(s->timer);
76         pl031_interrupt(s);
77     } else {
78         int64_t now = qemu_clock_get_ns(rtc_clock);
79         timer_mod(s->timer, now + (int64_t)ticks * NANOSECONDS_PER_SECOND);
80     }
81 }
82 
pl031_read(void * opaque,hwaddr offset,unsigned size)83 static uint64_t pl031_read(void *opaque, hwaddr offset,
84                            unsigned size)
85 {
86     PL031State *s = (PL031State *)opaque;
87     uint64_t r;
88 
89     switch (offset) {
90     case RTC_DR:
91         r = pl031_get_count(s);
92         break;
93     case RTC_MR:
94         r = s->mr;
95         break;
96     case RTC_IMSC:
97         r = s->im;
98         break;
99     case RTC_RIS:
100         r = s->is;
101         break;
102     case RTC_LR:
103         r = s->lr;
104         break;
105     case RTC_CR:
106         /* RTC is permanently enabled.  */
107         r = 1;
108         break;
109     case RTC_MIS:
110         r = s->is & s->im;
111         break;
112     case 0xfe0 ... 0xfff:
113         r = pl031_id[(offset - 0xfe0) >> 2];
114         break;
115     case RTC_ICR:
116         qemu_log_mask(LOG_GUEST_ERROR,
117                       "pl031: read of write-only register at offset 0x%x\n",
118                       (int)offset);
119         r = 0;
120         break;
121     default:
122         qemu_log_mask(LOG_GUEST_ERROR,
123                       "pl031_read: Bad offset 0x%x\n", (int)offset);
124         r = 0;
125         break;
126     }
127 
128     trace_pl031_read(offset, r);
129     return r;
130 }
131 
pl031_write(void * opaque,hwaddr offset,uint64_t value,unsigned size)132 static void pl031_write(void * opaque, hwaddr offset,
133                         uint64_t value, unsigned size)
134 {
135     PL031State *s = (PL031State *)opaque;
136 
137     trace_pl031_write(offset, value);
138 
139     switch (offset) {
140     case RTC_LR: {
141         g_autofree const char *qom_path = object_get_canonical_path(opaque);
142         struct tm tm;
143 
144         s->lr = value;
145         s->tick_offset += value - pl031_get_count(s);
146 
147         qemu_get_timedate(&tm, s->tick_offset);
148         qapi_event_send_rtc_change(qemu_timedate_diff(&tm), qom_path);
149 
150         pl031_set_alarm(s);
151         break;
152     }
153     case RTC_MR:
154         s->mr = value;
155         pl031_set_alarm(s);
156         break;
157     case RTC_IMSC:
158         s->im = value & 1;
159         pl031_update(s);
160         break;
161     case RTC_ICR:
162         s->is &= ~value;
163         pl031_update(s);
164         break;
165     case RTC_CR:
166         /* Written value is ignored.  */
167         break;
168 
169     case RTC_DR:
170     case RTC_MIS:
171     case RTC_RIS:
172         qemu_log_mask(LOG_GUEST_ERROR,
173                       "pl031: write to read-only register at offset 0x%x\n",
174                       (int)offset);
175         break;
176 
177     default:
178         qemu_log_mask(LOG_GUEST_ERROR,
179                       "pl031_write: Bad offset 0x%x\n", (int)offset);
180         break;
181     }
182 }
183 
184 static const MemoryRegionOps pl031_ops = {
185     .read = pl031_read,
186     .write = pl031_write,
187     .endianness = DEVICE_NATIVE_ENDIAN,
188 };
189 
pl031_init(Object * obj)190 static void pl031_init(Object *obj)
191 {
192     PL031State *s = PL031(obj);
193     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
194     struct tm tm;
195 
196     memory_region_init_io(&s->iomem, obj, &pl031_ops, s, "pl031", 0x1000);
197     sysbus_init_mmio(dev, &s->iomem);
198 
199     sysbus_init_irq(dev, &s->irq);
200     qemu_get_timedate(&tm, 0);
201     s->tick_offset = mktimegm(&tm) -
202         qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND;
203 
204     s->timer = timer_new_ns(rtc_clock, pl031_interrupt, s);
205 }
206 
pl031_finalize(Object * obj)207 static void pl031_finalize(Object *obj)
208 {
209     PL031State *s = PL031(obj);
210 
211     timer_free(s->timer);
212 }
213 
pl031_pre_save(void * opaque)214 static int pl031_pre_save(void *opaque)
215 {
216     PL031State *s = opaque;
217 
218     /*
219      * The PL031 device model code uses the tick_offset field, which is
220      * the offset between what the guest RTC should read and what the
221      * QEMU rtc_clock reads:
222      *  guest_rtc = rtc_clock + tick_offset
223      * and so
224      *  tick_offset = guest_rtc - rtc_clock
225      *
226      * We want to migrate this offset, which sounds straightforward.
227      * Unfortunately older versions of QEMU migrated a conversion of this
228      * offset into an offset from the vm_clock. (This was in turn an
229      * attempt to be compatible with even older QEMU versions, but it
230      * has incorrect behaviour if the rtc_clock is not the same as the
231      * vm_clock.) So we put the actual tick_offset into a migration
232      * subsection, and the backwards-compatible time-relative-to-vm_clock
233      * in the main migration state.
234      *
235      * Calculate base time relative to QEMU_CLOCK_VIRTUAL:
236      */
237     int64_t delta = qemu_clock_get_ns(rtc_clock) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
238     s->tick_offset_vmstate = s->tick_offset + delta / NANOSECONDS_PER_SECOND;
239 
240     return 0;
241 }
242 
pl031_pre_load(void * opaque)243 static int pl031_pre_load(void *opaque)
244 {
245     PL031State *s = opaque;
246 
247     s->tick_offset_migrated = false;
248     return 0;
249 }
250 
pl031_post_load(void * opaque,int version_id)251 static int pl031_post_load(void *opaque, int version_id)
252 {
253     PL031State *s = opaque;
254 
255     /*
256      * If we got the tick_offset subsection, then we can just use
257      * the value in that. Otherwise the source is an older QEMU and
258      * has given us the offset from the vm_clock; convert it back to
259      * an offset from the rtc_clock. This will cause time to incorrectly
260      * go backwards compared to the host RTC, but this is unavoidable.
261      */
262 
263     if (!s->tick_offset_migrated) {
264         int64_t delta = qemu_clock_get_ns(rtc_clock) -
265             qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
266         s->tick_offset = s->tick_offset_vmstate -
267             delta / NANOSECONDS_PER_SECOND;
268     }
269     pl031_set_alarm(s);
270     return 0;
271 }
272 
pl031_tick_offset_post_load(void * opaque,int version_id)273 static int pl031_tick_offset_post_load(void *opaque, int version_id)
274 {
275     PL031State *s = opaque;
276 
277     s->tick_offset_migrated = true;
278     return 0;
279 }
280 
pl031_tick_offset_needed(void * opaque)281 static bool pl031_tick_offset_needed(void *opaque)
282 {
283     PL031State *s = opaque;
284 
285     return s->migrate_tick_offset;
286 }
287 
288 static const VMStateDescription vmstate_pl031_tick_offset = {
289     .name = "pl031/tick-offset",
290     .version_id = 1,
291     .minimum_version_id = 1,
292     .needed = pl031_tick_offset_needed,
293     .post_load = pl031_tick_offset_post_load,
294     .fields = (const VMStateField[]) {
295         VMSTATE_UINT32(tick_offset, PL031State),
296         VMSTATE_END_OF_LIST()
297     }
298 };
299 
300 static const VMStateDescription vmstate_pl031 = {
301     .name = "pl031",
302     .version_id = 1,
303     .minimum_version_id = 1,
304     .pre_save = pl031_pre_save,
305     .pre_load = pl031_pre_load,
306     .post_load = pl031_post_load,
307     .fields = (const VMStateField[]) {
308         VMSTATE_UINT32(tick_offset_vmstate, PL031State),
309         VMSTATE_UINT32(mr, PL031State),
310         VMSTATE_UINT32(lr, PL031State),
311         VMSTATE_UINT32(cr, PL031State),
312         VMSTATE_UINT32(im, PL031State),
313         VMSTATE_UINT32(is, PL031State),
314         VMSTATE_END_OF_LIST()
315     },
316     .subsections = (const VMStateDescription * const []) {
317         &vmstate_pl031_tick_offset,
318         NULL
319     }
320 };
321 
322 static Property pl031_properties[] = {
323     /*
324      * True to correctly migrate the tick offset of the RTC. False to
325      * obtain backward migration compatibility with older QEMU versions,
326      * at the expense of the guest RTC going backwards compared with the
327      * host RTC when the VM is saved/restored if using -rtc host.
328      * (Even if set to 'true' older QEMU can migrate forward to newer QEMU;
329      * 'false' also permits newer QEMU to migrate to older QEMU.)
330      */
331     DEFINE_PROP_BOOL("migrate-tick-offset",
332                      PL031State, migrate_tick_offset, true),
333     DEFINE_PROP_END_OF_LIST()
334 };
335 
pl031_class_init(ObjectClass * klass,void * data)336 static void pl031_class_init(ObjectClass *klass, void *data)
337 {
338     DeviceClass *dc = DEVICE_CLASS(klass);
339 
340     dc->vmsd = &vmstate_pl031;
341     device_class_set_props(dc, pl031_properties);
342 }
343 
344 static const TypeInfo pl031_info = {
345     .name          = TYPE_PL031,
346     .parent        = TYPE_SYS_BUS_DEVICE,
347     .instance_size = sizeof(PL031State),
348     .instance_init = pl031_init,
349     .instance_finalize = pl031_finalize,
350     .class_init    = pl031_class_init,
351 };
352 
pl031_register_types(void)353 static void pl031_register_types(void)
354 {
355     type_register_static(&pl031_info);
356 }
357 
358 type_init(pl031_register_types)
359