1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
4 */
5
6 #include <common.h>
7 #include <dm.h>
8 #include <errno.h>
9 #include <asm/io.h>
10 #include <dm/pinctrl.h>
11 #include <mach/ar71xx_regs.h>
12
13 DECLARE_GLOBAL_DATA_PTR;
14
15 enum periph_id {
16 PERIPH_ID_UART0,
17 PERIPH_ID_SPI0,
18 PERIPH_ID_NONE = -1,
19 };
20
21 struct ar933x_pinctrl_priv {
22 void __iomem *regs;
23 };
24
pinctrl_ar933x_spi_config(struct ar933x_pinctrl_priv * priv,int cs)25 static void pinctrl_ar933x_spi_config(struct ar933x_pinctrl_priv *priv, int cs)
26 {
27 switch (cs) {
28 case 0:
29 clrsetbits_be32(priv->regs + AR71XX_GPIO_REG_OE,
30 AR933X_GPIO(4), AR933X_GPIO(3) |
31 AR933X_GPIO(5) | AR933X_GPIO(2));
32 setbits_be32(priv->regs + AR71XX_GPIO_REG_FUNC,
33 AR933X_GPIO_FUNC_SPI_EN |
34 AR933X_GPIO_FUNC_RES_TRUE);
35 break;
36 }
37 }
38
pinctrl_ar933x_uart_config(struct ar933x_pinctrl_priv * priv,int uart_id)39 static void pinctrl_ar933x_uart_config(struct ar933x_pinctrl_priv *priv, int uart_id)
40 {
41 switch (uart_id) {
42 case PERIPH_ID_UART0:
43 clrsetbits_be32(priv->regs + AR71XX_GPIO_REG_OE,
44 AR933X_GPIO(9), AR933X_GPIO(10));
45 setbits_be32(priv->regs + AR71XX_GPIO_REG_FUNC,
46 AR933X_GPIO_FUNC_UART_EN |
47 AR933X_GPIO_FUNC_RES_TRUE);
48 break;
49 }
50 }
51
ar933x_pinctrl_request(struct udevice * dev,int func,int flags)52 static int ar933x_pinctrl_request(struct udevice *dev, int func, int flags)
53 {
54 struct ar933x_pinctrl_priv *priv = dev_get_priv(dev);
55
56 debug("%s: func=%x, flags=%x\n", __func__, func, flags);
57 switch (func) {
58 case PERIPH_ID_SPI0:
59 pinctrl_ar933x_spi_config(priv, flags);
60 break;
61 case PERIPH_ID_UART0:
62 pinctrl_ar933x_uart_config(priv, func);
63 break;
64 default:
65 return -EINVAL;
66 }
67
68 return 0;
69 }
70
ar933x_pinctrl_get_periph_id(struct udevice * dev,struct udevice * periph)71 static int ar933x_pinctrl_get_periph_id(struct udevice *dev,
72 struct udevice *periph)
73 {
74 u32 cell[2];
75 int ret;
76
77 ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
78 "interrupts", cell, ARRAY_SIZE(cell));
79 if (ret < 0)
80 return -EINVAL;
81
82 switch (cell[0]) {
83 case 128:
84 return PERIPH_ID_UART0;
85 case 129:
86 return PERIPH_ID_SPI0;
87 }
88 return -ENOENT;
89 }
90
ar933x_pinctrl_set_state_simple(struct udevice * dev,struct udevice * periph)91 static int ar933x_pinctrl_set_state_simple(struct udevice *dev,
92 struct udevice *periph)
93 {
94 int func;
95
96 func = ar933x_pinctrl_get_periph_id(dev, periph);
97 if (func < 0)
98 return func;
99 return ar933x_pinctrl_request(dev, func, 0);
100 }
101
102 static struct pinctrl_ops ar933x_pinctrl_ops = {
103 .set_state_simple = ar933x_pinctrl_set_state_simple,
104 .request = ar933x_pinctrl_request,
105 .get_periph_id = ar933x_pinctrl_get_periph_id,
106 };
107
ar933x_pinctrl_probe(struct udevice * dev)108 static int ar933x_pinctrl_probe(struct udevice *dev)
109 {
110 struct ar933x_pinctrl_priv *priv = dev_get_priv(dev);
111 fdt_addr_t addr;
112
113 addr = devfdt_get_addr(dev);
114 if (addr == FDT_ADDR_T_NONE)
115 return -EINVAL;
116
117 priv->regs = map_physmem(addr,
118 AR71XX_GPIO_SIZE,
119 MAP_NOCACHE);
120 return 0;
121 }
122
123 static const struct udevice_id ar933x_pinctrl_ids[] = {
124 { .compatible = "qca,ar933x-pinctrl" },
125 { }
126 };
127
128 U_BOOT_DRIVER(pinctrl_ar933x) = {
129 .name = "pinctrl_ar933x",
130 .id = UCLASS_PINCTRL,
131 .of_match = ar933x_pinctrl_ids,
132 .priv_auto_alloc_size = sizeof(struct ar933x_pinctrl_priv),
133 .ops = &ar933x_pinctrl_ops,
134 .probe = ar933x_pinctrl_probe,
135 };
136