1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2015 Google, Inc
4 * Copyright 2014 Rockchip Inc.
5 */
6
7 #include <common.h>
8 #include <clk.h>
9 #include <display.h>
10 #include <dm.h>
11 #include <edid.h>
12 #include <regmap.h>
13 #include <syscon.h>
14 #include <video.h>
15 #include <asm/gpio.h>
16 #include <asm/hardware.h>
17 #include <asm/io.h>
18 #include <asm/arch/clock.h>
19 #include <asm/arch/edp_rk3288.h>
20 #include <asm/arch/vop_rk3288.h>
21 #include <dm/device-internal.h>
22 #include <dm/uclass-internal.h>
23 #include <power/regulator.h>
24 #include "rk_vop.h"
25
26 DECLARE_GLOBAL_DATA_PTR;
27
28 enum vop_pol {
29 HSYNC_POSITIVE = 0,
30 VSYNC_POSITIVE = 1,
31 DEN_NEGATIVE = 2,
32 DCLK_INVERT = 3
33 };
34
rkvop_enable(struct rk3288_vop * regs,ulong fbbase,int fb_bits_per_pixel,const struct display_timing * edid)35 static void rkvop_enable(struct rk3288_vop *regs, ulong fbbase,
36 int fb_bits_per_pixel,
37 const struct display_timing *edid)
38 {
39 u32 lb_mode;
40 u32 rgb_mode;
41 u32 hactive = edid->hactive.typ;
42 u32 vactive = edid->vactive.typ;
43
44 writel(V_ACT_WIDTH(hactive - 1) | V_ACT_HEIGHT(vactive - 1),
45 ®s->win0_act_info);
46
47 writel(V_DSP_XST(edid->hsync_len.typ + edid->hback_porch.typ) |
48 V_DSP_YST(edid->vsync_len.typ + edid->vback_porch.typ),
49 ®s->win0_dsp_st);
50
51 writel(V_DSP_WIDTH(hactive - 1) |
52 V_DSP_HEIGHT(vactive - 1),
53 ®s->win0_dsp_info);
54
55 clrsetbits_le32(®s->win0_color_key, M_WIN0_KEY_EN | M_WIN0_KEY_COLOR,
56 V_WIN0_KEY_EN(0) | V_WIN0_KEY_COLOR(0));
57
58 switch (fb_bits_per_pixel) {
59 case 16:
60 rgb_mode = RGB565;
61 writel(V_RGB565_VIRWIDTH(hactive), ®s->win0_vir);
62 break;
63 case 24:
64 rgb_mode = RGB888;
65 writel(V_RGB888_VIRWIDTH(hactive), ®s->win0_vir);
66 break;
67 case 32:
68 default:
69 rgb_mode = ARGB8888;
70 writel(V_ARGB888_VIRWIDTH(hactive), ®s->win0_vir);
71 break;
72 }
73
74 if (hactive > 2560)
75 lb_mode = LB_RGB_3840X2;
76 else if (hactive > 1920)
77 lb_mode = LB_RGB_2560X4;
78 else if (hactive > 1280)
79 lb_mode = LB_RGB_1920X5;
80 else
81 lb_mode = LB_RGB_1280X8;
82
83 clrsetbits_le32(®s->win0_ctrl0,
84 M_WIN0_LB_MODE | M_WIN0_DATA_FMT | M_WIN0_EN,
85 V_WIN0_LB_MODE(lb_mode) | V_WIN0_DATA_FMT(rgb_mode) |
86 V_WIN0_EN(1));
87
88 writel(fbbase, ®s->win0_yrgb_mst);
89 writel(0x01, ®s->reg_cfg_done); /* enable reg config */
90 }
91
rkvop_set_pin_polarity(struct udevice * dev,enum vop_modes mode,u32 polarity)92 static void rkvop_set_pin_polarity(struct udevice *dev,
93 enum vop_modes mode, u32 polarity)
94 {
95 struct rkvop_driverdata *ops =
96 (struct rkvop_driverdata *)dev_get_driver_data(dev);
97
98 if (ops->set_pin_polarity)
99 ops->set_pin_polarity(dev, mode, polarity);
100 }
101
rkvop_enable_output(struct udevice * dev,enum vop_modes mode)102 static void rkvop_enable_output(struct udevice *dev, enum vop_modes mode)
103 {
104 struct rk_vop_priv *priv = dev_get_priv(dev);
105 struct rk3288_vop *regs = priv->regs;
106
107 /* remove from standby */
108 clrbits_le32(®s->sys_ctrl, V_STANDBY_EN(1));
109
110 switch (mode) {
111 case VOP_MODE_HDMI:
112 clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN,
113 V_HDMI_OUT_EN(1));
114 break;
115
116 case VOP_MODE_EDP:
117 clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN,
118 V_EDP_OUT_EN(1));
119 break;
120
121 case VOP_MODE_LVDS:
122 clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN,
123 V_RGB_OUT_EN(1));
124 break;
125
126 case VOP_MODE_MIPI:
127 clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN,
128 V_MIPI_OUT_EN(1));
129 break;
130
131 default:
132 debug("%s: unsupported output mode %x\n", __func__, mode);
133 }
134 }
135
rkvop_mode_set(struct udevice * dev,const struct display_timing * edid,enum vop_modes mode)136 static void rkvop_mode_set(struct udevice *dev,
137 const struct display_timing *edid,
138 enum vop_modes mode)
139 {
140 struct rk_vop_priv *priv = dev_get_priv(dev);
141 struct rk3288_vop *regs = priv->regs;
142 struct rkvop_driverdata *data =
143 (struct rkvop_driverdata *)dev_get_driver_data(dev);
144
145 u32 hactive = edid->hactive.typ;
146 u32 vactive = edid->vactive.typ;
147 u32 hsync_len = edid->hsync_len.typ;
148 u32 hback_porch = edid->hback_porch.typ;
149 u32 vsync_len = edid->vsync_len.typ;
150 u32 vback_porch = edid->vback_porch.typ;
151 u32 hfront_porch = edid->hfront_porch.typ;
152 u32 vfront_porch = edid->vfront_porch.typ;
153 int mode_flags;
154 u32 pin_polarity;
155
156 pin_polarity = BIT(DCLK_INVERT);
157 if (edid->flags & DISPLAY_FLAGS_HSYNC_HIGH)
158 pin_polarity |= BIT(HSYNC_POSITIVE);
159 if (edid->flags & DISPLAY_FLAGS_VSYNC_HIGH)
160 pin_polarity |= BIT(VSYNC_POSITIVE);
161
162 rkvop_set_pin_polarity(dev, mode, pin_polarity);
163 rkvop_enable_output(dev, mode);
164
165 mode_flags = 0; /* RGB888 */
166 if ((data->features & VOP_FEATURE_OUTPUT_10BIT) &&
167 (mode == VOP_MODE_HDMI || mode == VOP_MODE_EDP))
168 mode_flags = 15; /* RGBaaa */
169
170 clrsetbits_le32(®s->dsp_ctrl0, M_DSP_OUT_MODE,
171 V_DSP_OUT_MODE(mode_flags));
172
173 writel(V_HSYNC(hsync_len) |
174 V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch),
175 ®s->dsp_htotal_hs_end);
176
177 writel(V_HEAP(hsync_len + hback_porch + hactive) |
178 V_HASP(hsync_len + hback_porch),
179 ®s->dsp_hact_st_end);
180
181 writel(V_VSYNC(vsync_len) |
182 V_VERPRD(vsync_len + vback_porch + vactive + vfront_porch),
183 ®s->dsp_vtotal_vs_end);
184
185 writel(V_VAEP(vsync_len + vback_porch + vactive)|
186 V_VASP(vsync_len + vback_porch),
187 ®s->dsp_vact_st_end);
188
189 writel(V_HEAP(hsync_len + hback_porch + hactive) |
190 V_HASP(hsync_len + hback_porch),
191 ®s->post_dsp_hact_info);
192
193 writel(V_VAEP(vsync_len + vback_porch + vactive)|
194 V_VASP(vsync_len + vback_porch),
195 ®s->post_dsp_vact_info);
196
197 writel(0x01, ®s->reg_cfg_done); /* enable reg config */
198 }
199
200 /**
201 * rk_display_init() - Try to enable the given display device
202 *
203 * This function performs many steps:
204 * - Finds the display device being referenced by @ep_node
205 * - Puts the VOP's ID into its uclass platform data
206 * - Probes the device to set it up
207 * - Reads the EDID timing information
208 * - Sets up the VOP clocks, etc. for the selected pixel clock and display mode
209 * - Enables the display (the display device handles this and will do different
210 * things depending on the display type)
211 * - Tells the uclass about the display resolution so that the console will
212 * appear correctly
213 *
214 * @dev: VOP device that we want to connect to the display
215 * @fbbase: Frame buffer address
216 * @ep_node: Device tree node to process - this is the offset of an endpoint
217 * node within the VOP's 'port' list.
218 * @return 0 if OK, -ve if something went wrong
219 */
rk_display_init(struct udevice * dev,ulong fbbase,ofnode ep_node)220 static int rk_display_init(struct udevice *dev, ulong fbbase, ofnode ep_node)
221 {
222 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
223 struct rk_vop_priv *priv = dev_get_priv(dev);
224 int vop_id, remote_vop_id;
225 struct rk3288_vop *regs = priv->regs;
226 struct display_timing timing;
227 struct udevice *disp;
228 int ret;
229 u32 remote_phandle;
230 struct display_plat *disp_uc_plat;
231 struct clk clk;
232 enum video_log2_bpp l2bpp;
233 ofnode remote;
234
235 debug("%s(%s, %lu, %s)\n", __func__,
236 dev_read_name(dev), fbbase, ofnode_get_name(ep_node));
237
238 vop_id = ofnode_read_s32_default(ep_node, "reg", -1);
239 debug("vop_id=%d\n", vop_id);
240 ret = ofnode_read_u32(ep_node, "remote-endpoint", &remote_phandle);
241 if (ret)
242 return ret;
243
244 remote = ofnode_get_by_phandle(remote_phandle);
245 if (!ofnode_valid(remote))
246 return -EINVAL;
247 remote_vop_id = ofnode_read_u32_default(remote, "reg", -1);
248 debug("remote vop_id=%d\n", remote_vop_id);
249
250 /*
251 * The remote-endpoint references into a subnode of the encoder
252 * (i.e. HDMI, MIPI, etc.) with the DTS looking something like
253 * the following (assume 'hdmi_in_vopl' to be referenced):
254 *
255 * hdmi: hdmi@ff940000 {
256 * ports {
257 * hdmi_in: port {
258 * hdmi_in_vopb: endpoint@0 { ... };
259 * hdmi_in_vopl: endpoint@1 { ... };
260 * }
261 * }
262 * }
263 *
264 * The original code had 3 steps of "walking the parent", but
265 * a much better (as in: less likely to break if the DTS
266 * changes) way of doing this is to "find the enclosing device
267 * of UCLASS_DISPLAY".
268 */
269 while (ofnode_valid(remote)) {
270 remote = ofnode_get_parent(remote);
271 if (!ofnode_valid(remote)) {
272 debug("%s(%s): no UCLASS_DISPLAY for remote-endpoint\n",
273 __func__, dev_read_name(dev));
274 return -EINVAL;
275 }
276
277 uclass_find_device_by_ofnode(UCLASS_DISPLAY, remote, &disp);
278 if (disp)
279 break;
280 };
281
282 disp_uc_plat = dev_get_uclass_platdata(disp);
283 debug("Found device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat);
284 if (display_in_use(disp)) {
285 debug(" - device in use\n");
286 return -EBUSY;
287 }
288
289 disp_uc_plat->source_id = remote_vop_id;
290 disp_uc_plat->src_dev = dev;
291
292 ret = device_probe(disp);
293 if (ret) {
294 debug("%s: device '%s' display won't probe (ret=%d)\n",
295 __func__, dev->name, ret);
296 return ret;
297 }
298
299 ret = display_read_timing(disp, &timing);
300 if (ret) {
301 debug("%s: Failed to read timings\n", __func__);
302 return ret;
303 }
304
305 ret = clk_get_by_index(dev, 1, &clk);
306 if (!ret)
307 ret = clk_set_rate(&clk, timing.pixelclock.typ);
308 if (IS_ERR_VALUE(ret)) {
309 debug("%s: Failed to set pixel clock: ret=%d\n", __func__, ret);
310 return ret;
311 }
312
313 /* Set bitwidth for vop display according to vop mode */
314 switch (vop_id) {
315 case VOP_MODE_EDP:
316 case VOP_MODE_LVDS:
317 l2bpp = VIDEO_BPP16;
318 break;
319 case VOP_MODE_HDMI:
320 case VOP_MODE_MIPI:
321 l2bpp = VIDEO_BPP32;
322 break;
323 default:
324 l2bpp = VIDEO_BPP16;
325 }
326
327 rkvop_mode_set(dev, &timing, vop_id);
328 rkvop_enable(regs, fbbase, 1 << l2bpp, &timing);
329
330 ret = display_enable(disp, 1 << l2bpp, &timing);
331 if (ret)
332 return ret;
333
334 uc_priv->xsize = timing.hactive.typ;
335 uc_priv->ysize = timing.vactive.typ;
336 uc_priv->bpix = l2bpp;
337 debug("fb=%lx, size=%d %d\n", fbbase, uc_priv->xsize, uc_priv->ysize);
338
339 return 0;
340 }
341
rk_vop_probe_regulators(struct udevice * dev,const char * const * names,int cnt)342 void rk_vop_probe_regulators(struct udevice *dev,
343 const char * const *names, int cnt)
344 {
345 int i, ret;
346 const char *name;
347 struct udevice *reg;
348
349 for (i = 0; i < cnt; ++i) {
350 name = names[i];
351 debug("%s: probing regulator '%s'\n", dev->name, name);
352
353 ret = regulator_autoset_by_name(name, ®);
354 if (!ret)
355 ret = regulator_set_enable(reg, true);
356 }
357 }
358
rk_vop_probe(struct udevice * dev)359 int rk_vop_probe(struct udevice *dev)
360 {
361 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
362 struct rk_vop_priv *priv = dev_get_priv(dev);
363 int ret = 0;
364 ofnode port, node;
365
366 /* Before relocation we don't need to do anything */
367 if (!(gd->flags & GD_FLG_RELOC))
368 return 0;
369
370 priv->regs = (struct rk3288_vop *)dev_read_addr(dev);
371
372 /*
373 * Try all the ports until we find one that works. In practice this
374 * tries EDP first if available, then HDMI.
375 *
376 * Note that rockchip_vop_set_clk() always uses NPLL as the source
377 * clock so it is currently not possible to use more than one display
378 * device simultaneously.
379 */
380 port = dev_read_subnode(dev, "port");
381 if (!ofnode_valid(port)) {
382 debug("%s(%s): 'port' subnode not found\n",
383 __func__, dev_read_name(dev));
384 return -EINVAL;
385 }
386
387 for (node = ofnode_first_subnode(port);
388 ofnode_valid(node);
389 node = dev_read_next_subnode(node)) {
390 ret = rk_display_init(dev, plat->base, node);
391 if (ret)
392 debug("Device failed: ret=%d\n", ret);
393 if (!ret)
394 break;
395 }
396 video_set_flush_dcache(dev, 1);
397
398 return ret;
399 }
400
rk_vop_bind(struct udevice * dev)401 int rk_vop_bind(struct udevice *dev)
402 {
403 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
404
405 plat->size = 4 * (CONFIG_VIDEO_ROCKCHIP_MAX_XRES *
406 CONFIG_VIDEO_ROCKCHIP_MAX_YRES);
407
408 return 0;
409 }
410