1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2015 - 2022 Beijing WangXun Technology Co., Ltd. */
3 
4 #ifndef _TXGBE_TYPE_H_
5 #define _TXGBE_TYPE_H_
6 
7 #include <linux/property.h>
8 
9 /* Device IDs */
10 #define TXGBE_DEV_ID_SP1000                     0x1001
11 #define TXGBE_DEV_ID_WX1820                     0x2001
12 
13 /* Subsystem IDs */
14 /* SFP */
15 #define TXGBE_ID_SP1000_SFP                     0x0000
16 #define TXGBE_ID_WX1820_SFP                     0x2000
17 #define TXGBE_ID_SFP                            0x00
18 
19 /* copper */
20 #define TXGBE_ID_SP1000_XAUI                    0x1010
21 #define TXGBE_ID_WX1820_XAUI                    0x2010
22 #define TXGBE_ID_XAUI                           0x10
23 #define TXGBE_ID_SP1000_SGMII                   0x1020
24 #define TXGBE_ID_WX1820_SGMII                   0x2020
25 #define TXGBE_ID_SGMII                          0x20
26 /* backplane */
27 #define TXGBE_ID_SP1000_KR_KX_KX4               0x1030
28 #define TXGBE_ID_WX1820_KR_KX_KX4               0x2030
29 #define TXGBE_ID_KR_KX_KX4                      0x30
30 /* MAC Interface */
31 #define TXGBE_ID_SP1000_MAC_XAUI                0x1040
32 #define TXGBE_ID_WX1820_MAC_XAUI                0x2040
33 #define TXGBE_ID_MAC_XAUI                       0x40
34 #define TXGBE_ID_SP1000_MAC_SGMII               0x1060
35 #define TXGBE_ID_WX1820_MAC_SGMII               0x2060
36 #define TXGBE_ID_MAC_SGMII                      0x60
37 
38 /* Combined interface*/
39 #define TXGBE_ID_SFI_XAUI			0x50
40 
41 /* Revision ID */
42 #define TXGBE_SP_MPW  1
43 
44 /**************** SP Registers ****************************/
45 /* chip control Registers */
46 #define TXGBE_MIS_PRB_CTL                       0x10010
47 #define TXGBE_MIS_PRB_CTL_LAN_UP(_i)            BIT(1 - (_i))
48 /* FMGR Registers */
49 #define TXGBE_SPI_ILDR_STATUS                   0x10120
50 #define TXGBE_SPI_ILDR_STATUS_PERST             BIT(0) /* PCIE_PERST is done */
51 #define TXGBE_SPI_ILDR_STATUS_PWRRST            BIT(1) /* Power on reset is done */
52 #define TXGBE_SPI_ILDR_STATUS_LAN_SW_RST(_i)    BIT((_i) + 9) /* lan soft reset done */
53 
54 /* Sensors for PVT(Process Voltage Temperature) */
55 #define TXGBE_TS_CTL                            0x10300
56 #define TXGBE_TS_CTL_EVAL_MD                    BIT(31)
57 
58 /* GPIO register bit */
59 #define TXGBE_GPIOBIT_0                         BIT(0) /* I:tx fault */
60 #define TXGBE_GPIOBIT_1                         BIT(1) /* O:tx disabled */
61 #define TXGBE_GPIOBIT_2                         BIT(2) /* I:sfp module absent */
62 #define TXGBE_GPIOBIT_3                         BIT(3) /* I:rx signal lost */
63 #define TXGBE_GPIOBIT_4                         BIT(4) /* O:rate select, 1G(0) 10G(1) */
64 #define TXGBE_GPIOBIT_5                         BIT(5) /* O:rate select, 1G(0) 10G(1) */
65 
66 /* Extended Interrupt Enable Set */
67 #define TXGBE_PX_MISC_ETH_LKDN                  BIT(8)
68 #define TXGBE_PX_MISC_DEV_RST                   BIT(10)
69 #define TXGBE_PX_MISC_ETH_EVENT                 BIT(17)
70 #define TXGBE_PX_MISC_ETH_LK                    BIT(18)
71 #define TXGBE_PX_MISC_ETH_AN                    BIT(19)
72 #define TXGBE_PX_MISC_INT_ERR                   BIT(20)
73 #define TXGBE_PX_MISC_GPIO                      BIT(26)
74 #define TXGBE_PX_MISC_IEN_MASK                            \
75 	(TXGBE_PX_MISC_ETH_LKDN | TXGBE_PX_MISC_DEV_RST | \
76 	 TXGBE_PX_MISC_ETH_EVENT | TXGBE_PX_MISC_ETH_LK | \
77 	 TXGBE_PX_MISC_ETH_AN | TXGBE_PX_MISC_INT_ERR |   \
78 	 TXGBE_PX_MISC_GPIO)
79 
80 /* Port cfg registers */
81 #define TXGBE_CFG_PORT_ST                       0x14404
82 #define TXGBE_CFG_PORT_ST_LINK_UP               BIT(0)
83 
84 /* I2C registers */
85 #define TXGBE_I2C_BASE                          0x14900
86 
87 /************************************** ETH PHY ******************************/
88 #define TXGBE_XPCS_IDA_ADDR                     0x13000
89 #define TXGBE_XPCS_IDA_DATA                     0x13004
90 
91 /* Part Number String Length */
92 #define TXGBE_PBANUM_LENGTH                     32
93 
94 /* Checksum and EEPROM pointers */
95 #define TXGBE_EEPROM_LAST_WORD                  0x800
96 #define TXGBE_EEPROM_CHECKSUM                   0x2F
97 #define TXGBE_EEPROM_SUM                        0xBABA
98 #define TXGBE_EEPROM_VERSION_L                  0x1D
99 #define TXGBE_EEPROM_VERSION_H                  0x1E
100 #define TXGBE_ISCSI_BOOT_CONFIG                 0x07
101 #define TXGBE_PBANUM0_PTR                       0x05
102 #define TXGBE_PBANUM1_PTR                       0x06
103 #define TXGBE_PBANUM_PTR_GUARD                  0xFAFA
104 
105 #define TXGBE_MAX_MSIX_VECTORS          64
106 #define TXGBE_MAX_FDIR_INDICES          63
107 
108 #define TXGBE_MAX_RX_QUEUES   (TXGBE_MAX_FDIR_INDICES + 1)
109 #define TXGBE_MAX_TX_QUEUES   (TXGBE_MAX_FDIR_INDICES + 1)
110 
111 #define TXGBE_SP_MAX_TX_QUEUES  128
112 #define TXGBE_SP_MAX_RX_QUEUES  128
113 #define TXGBE_SP_RAR_ENTRIES    128
114 #define TXGBE_SP_MC_TBL_SIZE    128
115 #define TXGBE_SP_VFT_TBL_SIZE   128
116 #define TXGBE_SP_RX_PB_SIZE     512
117 #define TXGBE_SP_TDB_PB_SZ      (160 * 1024) /* 160KB Packet Buffer */
118 
119 /* TX/RX descriptor defines */
120 #define TXGBE_DEFAULT_TXD               512
121 #define TXGBE_DEFAULT_TX_WORK           256
122 
123 #if (PAGE_SIZE < 8192)
124 #define TXGBE_DEFAULT_RXD               512
125 #define TXGBE_DEFAULT_RX_WORK           256
126 #else
127 #define TXGBE_DEFAULT_RXD               256
128 #define TXGBE_DEFAULT_RX_WORK           128
129 #endif
130 
131 #define TXGBE_INTR_MISC(A)    BIT((A)->num_q_vectors)
132 #define TXGBE_INTR_QALL(A)    (TXGBE_INTR_MISC(A) - 1)
133 
134 #define TXGBE_MAX_EITR        GENMASK(11, 3)
135 
136 extern char txgbe_driver_name[];
137 
netdev_to_txgbe(struct net_device * netdev)138 static inline struct txgbe *netdev_to_txgbe(struct net_device *netdev)
139 {
140 	struct wx *wx = netdev_priv(netdev);
141 
142 	return wx->priv;
143 }
144 
145 #define NODE_PROP(_NAME, _PROP)			\
146 	(const struct software_node) {		\
147 		.name = _NAME,			\
148 		.properties = _PROP,		\
149 	}
150 
151 enum txgbe_swnodes {
152 	SWNODE_GPIO = 0,
153 	SWNODE_I2C,
154 	SWNODE_SFP,
155 	SWNODE_PHYLINK,
156 	SWNODE_MAX
157 };
158 
159 struct txgbe_nodes {
160 	char gpio_name[32];
161 	char i2c_name[32];
162 	char sfp_name[32];
163 	char phylink_name[32];
164 	struct property_entry gpio_props[1];
165 	struct property_entry i2c_props[3];
166 	struct property_entry sfp_props[8];
167 	struct property_entry phylink_props[2];
168 	struct software_node_ref_args i2c_ref[1];
169 	struct software_node_ref_args gpio0_ref[1];
170 	struct software_node_ref_args gpio1_ref[1];
171 	struct software_node_ref_args gpio2_ref[1];
172 	struct software_node_ref_args gpio3_ref[1];
173 	struct software_node_ref_args gpio4_ref[1];
174 	struct software_node_ref_args gpio5_ref[1];
175 	struct software_node_ref_args sfp_ref[1];
176 	struct software_node swnodes[SWNODE_MAX];
177 	const struct software_node *group[SWNODE_MAX + 1];
178 };
179 
180 struct txgbe {
181 	struct wx *wx;
182 	struct txgbe_nodes nodes;
183 	struct dw_xpcs *xpcs;
184 	struct phylink *phylink;
185 	struct platform_device *sfp_dev;
186 	struct platform_device *i2c_dev;
187 	struct clk_lookup *clock;
188 	struct clk *clk;
189 	struct gpio_chip *gpio;
190 };
191 
192 #endif /* _TXGBE_TYPE_H_ */
193