1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2007
4 * Sascha Hauer, Pengutronix
5 *
6 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 */
8
9 #include <common.h>
10 #include <linux/errno.h>
11 #include <asm/io.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/sys_proto.h>
15 #include <asm/bootm.h>
16 #include <asm/mach-imx/boot_mode.h>
17 #include <asm/mach-imx/dma.h>
18 #include <asm/mach-imx/hab.h>
19 #include <stdbool.h>
20 #include <asm/arch/mxc_hdmi.h>
21 #include <asm/arch/crm_regs.h>
22 #include <dm.h>
23 #include <imx_thermal.h>
24 #include <mmc.h>
25
26 enum ldo_reg {
27 LDO_ARM,
28 LDO_SOC,
29 LDO_PU,
30 };
31
32 struct scu_regs {
33 u32 ctrl;
34 u32 config;
35 u32 status;
36 u32 invalidate;
37 u32 fpga_rev;
38 };
39
40 #if defined(CONFIG_IMX_THERMAL)
41 static const struct imx_thermal_plat imx6_thermal_plat = {
42 .regs = (void *)ANATOP_BASE_ADDR,
43 .fuse_bank = 1,
44 .fuse_word = 6,
45 };
46
47 U_BOOT_DEVICE(imx6_thermal) = {
48 .name = "imx_thermal",
49 .platdata = &imx6_thermal_plat,
50 };
51 #endif
52
53 #if defined(CONFIG_SECURE_BOOT)
54 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
55 .bank = 0,
56 .word = 6,
57 };
58 #endif
59
get_nr_cpus(void)60 u32 get_nr_cpus(void)
61 {
62 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
63 return readl(&scu->config) & 3;
64 }
65
get_cpu_rev(void)66 u32 get_cpu_rev(void)
67 {
68 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
69 u32 reg = readl(&anatop->digprog_sololite);
70 u32 type = ((reg >> 16) & 0xff);
71 u32 major, cfg = 0;
72
73 if (type != MXC_CPU_MX6SL) {
74 reg = readl(&anatop->digprog);
75 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
76 cfg = readl(&scu->config) & 3;
77 type = ((reg >> 16) & 0xff);
78 if (type == MXC_CPU_MX6DL) {
79 if (!cfg)
80 type = MXC_CPU_MX6SOLO;
81 }
82
83 if (type == MXC_CPU_MX6Q) {
84 if (cfg == 1)
85 type = MXC_CPU_MX6D;
86 }
87
88 }
89 major = ((reg >> 8) & 0xff);
90 if ((major >= 1) &&
91 ((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D))) {
92 major--;
93 type = MXC_CPU_MX6QP;
94 if (cfg == 1)
95 type = MXC_CPU_MX6DP;
96 }
97 reg &= 0xff; /* mx6 silicon revision */
98 return (type << 12) | (reg + (0x10 * (major + 1)));
99 }
100
101 /*
102 * OCOTP_CFG3[17:16] (see Fusemap Description Table offset 0x440)
103 * defines a 2-bit SPEED_GRADING
104 */
105 #define OCOTP_CFG3_SPEED_SHIFT 16
106 #define OCOTP_CFG3_SPEED_800MHZ 0
107 #define OCOTP_CFG3_SPEED_850MHZ 1
108 #define OCOTP_CFG3_SPEED_1GHZ 2
109 #define OCOTP_CFG3_SPEED_1P2GHZ 3
110
111 /*
112 * For i.MX6UL
113 */
114 #define OCOTP_CFG3_SPEED_528MHZ 1
115 #define OCOTP_CFG3_SPEED_696MHZ 2
116
117 /*
118 * For i.MX6ULL
119 */
120 #define OCOTP_CFG3_SPEED_792MHZ 2
121 #define OCOTP_CFG3_SPEED_900MHZ 3
122
get_cpu_speed_grade_hz(void)123 u32 get_cpu_speed_grade_hz(void)
124 {
125 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
126 struct fuse_bank *bank = &ocotp->bank[0];
127 struct fuse_bank0_regs *fuse =
128 (struct fuse_bank0_regs *)bank->fuse_regs;
129 uint32_t val;
130
131 val = readl(&fuse->cfg3);
132 val >>= OCOTP_CFG3_SPEED_SHIFT;
133 val &= 0x3;
134
135 if (is_mx6ul()) {
136 if (val == OCOTP_CFG3_SPEED_528MHZ)
137 return 528000000;
138 else if (val == OCOTP_CFG3_SPEED_696MHZ)
139 return 696000000;
140 else
141 return 0;
142 }
143
144 if (is_mx6ull()) {
145 if (val == OCOTP_CFG3_SPEED_528MHZ)
146 return 528000000;
147 else if (val == OCOTP_CFG3_SPEED_792MHZ)
148 return 792000000;
149 else if (val == OCOTP_CFG3_SPEED_900MHZ)
150 return 900000000;
151 else
152 return 0;
153 }
154
155 switch (val) {
156 /* Valid for IMX6DQ */
157 case OCOTP_CFG3_SPEED_1P2GHZ:
158 if (is_mx6dq() || is_mx6dqp())
159 return 1200000000;
160 /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
161 case OCOTP_CFG3_SPEED_1GHZ:
162 return 996000000;
163 /* Valid for IMX6DQ */
164 case OCOTP_CFG3_SPEED_850MHZ:
165 if (is_mx6dq() || is_mx6dqp())
166 return 852000000;
167 /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
168 case OCOTP_CFG3_SPEED_800MHZ:
169 return 792000000;
170 }
171 return 0;
172 }
173
174 /*
175 * OCOTP_MEM0[7:6] (see Fusemap Description Table offset 0x480)
176 * defines a 2-bit Temperature Grade
177 *
178 * return temperature grade and min/max temperature in Celsius
179 */
180 #define OCOTP_MEM0_TEMP_SHIFT 6
181
get_cpu_temp_grade(int * minc,int * maxc)182 u32 get_cpu_temp_grade(int *minc, int *maxc)
183 {
184 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
185 struct fuse_bank *bank = &ocotp->bank[1];
186 struct fuse_bank1_regs *fuse =
187 (struct fuse_bank1_regs *)bank->fuse_regs;
188 uint32_t val;
189
190 val = readl(&fuse->mem0);
191 val >>= OCOTP_MEM0_TEMP_SHIFT;
192 val &= 0x3;
193
194 if (minc && maxc) {
195 if (val == TEMP_AUTOMOTIVE) {
196 *minc = -40;
197 *maxc = 125;
198 } else if (val == TEMP_INDUSTRIAL) {
199 *minc = -40;
200 *maxc = 105;
201 } else if (val == TEMP_EXTCOMMERCIAL) {
202 *minc = -20;
203 *maxc = 105;
204 } else {
205 *minc = 0;
206 *maxc = 95;
207 }
208 }
209 return val;
210 }
211
212 #ifdef CONFIG_REVISION_TAG
get_board_rev(void)213 u32 __weak get_board_rev(void)
214 {
215 u32 cpurev = get_cpu_rev();
216 u32 type = ((cpurev >> 12) & 0xff);
217 if (type == MXC_CPU_MX6SOLO)
218 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
219
220 if (type == MXC_CPU_MX6D)
221 cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
222
223 return cpurev;
224 }
225 #endif
226
clear_ldo_ramp(void)227 static void clear_ldo_ramp(void)
228 {
229 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
230 int reg;
231
232 /* ROM may modify LDO ramp up time according to fuse setting, so in
233 * order to be in the safe side we neeed to reset these settings to
234 * match the reset value: 0'b00
235 */
236 reg = readl(&anatop->ana_misc2);
237 reg &= ~(0x3f << 24);
238 writel(reg, &anatop->ana_misc2);
239 }
240
241 /*
242 * Set the PMU_REG_CORE register
243 *
244 * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
245 * Possible values are from 0.725V to 1.450V in steps of
246 * 0.025V (25mV).
247 */
set_ldo_voltage(enum ldo_reg ldo,u32 mv)248 static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
249 {
250 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
251 u32 val, step, old, reg = readl(&anatop->reg_core);
252 u8 shift;
253
254 /* No LDO_SOC/PU/ARM */
255 if (is_mx6sll())
256 return 0;
257
258 if (mv < 725)
259 val = 0x00; /* Power gated off */
260 else if (mv > 1450)
261 val = 0x1F; /* Power FET switched full on. No regulation */
262 else
263 val = (mv - 700) / 25;
264
265 clear_ldo_ramp();
266
267 switch (ldo) {
268 case LDO_SOC:
269 shift = 18;
270 break;
271 case LDO_PU:
272 shift = 9;
273 break;
274 case LDO_ARM:
275 shift = 0;
276 break;
277 default:
278 return -EINVAL;
279 }
280
281 old = (reg & (0x1F << shift)) >> shift;
282 step = abs(val - old);
283 if (step == 0)
284 return 0;
285
286 reg = (reg & ~(0x1F << shift)) | (val << shift);
287 writel(reg, &anatop->reg_core);
288
289 /*
290 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
291 * step
292 */
293 udelay(3 * step);
294
295 return 0;
296 }
297
set_ahb_rate(u32 val)298 static void set_ahb_rate(u32 val)
299 {
300 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
301 u32 reg, div;
302
303 div = get_periph_clk() / val - 1;
304 reg = readl(&mxc_ccm->cbcdr);
305
306 writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
307 (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
308 }
309
clear_mmdc_ch_mask(void)310 static void clear_mmdc_ch_mask(void)
311 {
312 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
313 u32 reg;
314 reg = readl(&mxc_ccm->ccdr);
315
316 /* Clear MMDC channel mask */
317 if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl() || is_mx6sll())
318 reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
319 else
320 reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
321 writel(reg, &mxc_ccm->ccdr);
322 }
323
324 #define OCOTP_MEM0_REFTOP_TRIM_SHIFT 8
325
init_bandgap(void)326 static void init_bandgap(void)
327 {
328 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
329 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
330 struct fuse_bank *bank = &ocotp->bank[1];
331 struct fuse_bank1_regs *fuse =
332 (struct fuse_bank1_regs *)bank->fuse_regs;
333 uint32_t val;
334
335 /*
336 * Ensure the bandgap has stabilized.
337 */
338 while (!(readl(&anatop->ana_misc0) & 0x80))
339 ;
340 /*
341 * For best noise performance of the analog blocks using the
342 * outputs of the bandgap, the reftop_selfbiasoff bit should
343 * be set.
344 */
345 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
346 /*
347 * On i.MX6ULL,we need to set VBGADJ bits according to the
348 * REFTOP_TRIM[3:0] in fuse table
349 * 000 - set REFTOP_VBGADJ[2:0] to 3b'110,
350 * 110 - set REFTOP_VBGADJ[2:0] to 3b'000,
351 * 001 - set REFTOP_VBGADJ[2:0] to 3b'001,
352 * 010 - set REFTOP_VBGADJ[2:0] to 3b'010,
353 * 011 - set REFTOP_VBGADJ[2:0] to 3b'011,
354 * 100 - set REFTOP_VBGADJ[2:0] to 3b'100,
355 * 101 - set REFTOP_VBGADJ[2:0] to 3b'101,
356 * 111 - set REFTOP_VBGADJ[2:0] to 3b'111,
357 */
358 if (is_mx6ull()) {
359 val = readl(&fuse->mem0);
360 val >>= OCOTP_MEM0_REFTOP_TRIM_SHIFT;
361 val &= 0x7;
362
363 writel(val << BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT,
364 &anatop->ana_misc0_set);
365 }
366 }
367
arch_cpu_init(void)368 int arch_cpu_init(void)
369 {
370 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
371
372 init_aips();
373
374 /* Need to clear MMDC_CHx_MASK to make warm reset work. */
375 clear_mmdc_ch_mask();
376
377 /*
378 * Disable self-bias circuit in the analog bandap.
379 * The self-bias circuit is used by the bandgap during startup.
380 * This bit should be set after the bandgap has initialized.
381 */
382 init_bandgap();
383
384 if (!is_mx6ul() && !is_mx6ull()) {
385 /*
386 * When low freq boot is enabled, ROM will not set AHB
387 * freq, so we need to ensure AHB freq is 132MHz in such
388 * scenario.
389 *
390 * To i.MX6UL, when power up, default ARM core and
391 * AHB rate is 396M and 132M.
392 */
393 if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
394 set_ahb_rate(132000000);
395 }
396
397 if (is_mx6ul()) {
398 if (is_soc_rev(CHIP_REV_1_0) == 0) {
399 /*
400 * According to the design team's requirement on
401 * i.MX6UL,the PMIC_STBY_REQ PAD should be configured
402 * as open drain 100K (0x0000b8a0).
403 * Only exists on TO1.0
404 */
405 writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c);
406 } else {
407 /*
408 * From TO1.1, SNVS adds internal pull up control
409 * for POR_B, the register filed is GPBIT[1:0],
410 * after system boot up, it can be set to 2b'01
411 * to disable internal pull up.It can save about
412 * 30uA power in SNVS mode.
413 */
414 writel((readl(MX6UL_SNVS_LP_BASE_ADDR + 0x10) &
415 (~0x1400)) | 0x400,
416 MX6UL_SNVS_LP_BASE_ADDR + 0x10);
417 }
418 }
419
420 if (is_mx6ull()) {
421 /*
422 * GPBIT[1:0] is suggested to set to 2'b11:
423 * 2'b00 : always PUP100K
424 * 2'b01 : PUP100K when PMIC_ON_REQ or SOC_NOT_FAIL
425 * 2'b10 : always disable PUP100K
426 * 2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL
427 * register offset is different from i.MX6UL, since
428 * i.MX6UL is fixed by ECO.
429 */
430 writel(readl(MX6UL_SNVS_LP_BASE_ADDR) |
431 0x3, MX6UL_SNVS_LP_BASE_ADDR);
432 }
433
434 /* Set perclk to source from OSC 24MHz */
435 if (is_mx6sl())
436 setbits_le32(&ccm->cscmr1, MXC_CCM_CSCMR1_PER_CLK_SEL_MASK);
437
438 imx_wdog_disable_powerdown(); /* Disable PDE bit of WMCR register */
439
440 if (is_mx6sx())
441 setbits_le32(&ccm->cscdr1, MXC_CCM_CSCDR1_UART_CLK_SEL);
442
443 init_src();
444
445 return 0;
446 }
447
448 #ifdef CONFIG_ENV_IS_IN_MMC
board_mmc_get_env_dev(int devno)449 __weak int board_mmc_get_env_dev(int devno)
450 {
451 return CONFIG_SYS_MMC_ENV_DEV;
452 }
453
mmc_get_boot_dev(void)454 static int mmc_get_boot_dev(void)
455 {
456 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
457 u32 soc_sbmr = readl(&src_regs->sbmr1);
458 u32 bootsel;
459 int devno;
460
461 /*
462 * Refer to
463 * "i.MX 6Dual/6Quad Applications Processor Reference Manual"
464 * Chapter "8.5.3.1 Expansion Device eFUSE Configuration"
465 * i.MX6SL/SX/UL has same layout.
466 */
467 bootsel = (soc_sbmr & 0x000000FF) >> 6;
468
469 /* No boot from sd/mmc */
470 if (bootsel != 1)
471 return -1;
472
473 /* BOOT_CFG2[3] and BOOT_CFG2[4] */
474 devno = (soc_sbmr & 0x00001800) >> 11;
475
476 return devno;
477 }
478
mmc_get_env_dev(void)479 int mmc_get_env_dev(void)
480 {
481 int devno = mmc_get_boot_dev();
482
483 /* If not boot from sd/mmc, use default value */
484 if (devno < 0)
485 return CONFIG_SYS_MMC_ENV_DEV;
486
487 return board_mmc_get_env_dev(devno);
488 }
489
490 #ifdef CONFIG_SYS_MMC_ENV_PART
board_mmc_get_env_part(int devno)491 __weak int board_mmc_get_env_part(int devno)
492 {
493 return CONFIG_SYS_MMC_ENV_PART;
494 }
495
mmc_get_env_part(struct mmc * mmc)496 uint mmc_get_env_part(struct mmc *mmc)
497 {
498 int devno = mmc_get_boot_dev();
499
500 /* If not boot from sd/mmc, use default value */
501 if (devno < 0)
502 return CONFIG_SYS_MMC_ENV_PART;
503
504 return board_mmc_get_env_part(devno);
505 }
506 #endif
507 #endif
508
board_postclk_init(void)509 int board_postclk_init(void)
510 {
511 /* NO LDO SOC on i.MX6SLL */
512 if (is_mx6sll())
513 return 0;
514
515 set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
516
517 return 0;
518 }
519
520 #ifndef CONFIG_SPL_BUILD
521 /*
522 * cfg_val will be used for
523 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
524 * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
525 * instead of SBMR1 to determine the boot device.
526 */
527 const struct boot_mode soc_boot_modes[] = {
528 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
529 /* reserved value should start rom usb */
530 #if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
531 {"usb", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
532 #else
533 {"usb", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
534 #endif
535 {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
536 {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
537 {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
538 {"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
539 {"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
540 /* 4 bit bus width */
541 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
542 {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
543 {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
544 {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
545 {NULL, 0},
546 };
547 #endif
548
reset_misc(void)549 void reset_misc(void)
550 {
551 #ifndef CONFIG_SPL_BUILD
552 #ifdef CONFIG_VIDEO_MXS
553 lcdif_power_down();
554 #endif
555 #endif
556 }
557
s_init(void)558 void s_init(void)
559 {
560 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
561 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
562 u32 mask480;
563 u32 mask528;
564 u32 reg, periph1, periph2;
565
566 if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sll())
567 return;
568
569 /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
570 * to make sure PFD is working right, otherwise, PFDs may
571 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
572 * workaround in ROM code, as bus clock need it
573 */
574
575 mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
576 ANATOP_PFD_CLKGATE_MASK(1) |
577 ANATOP_PFD_CLKGATE_MASK(2) |
578 ANATOP_PFD_CLKGATE_MASK(3);
579 mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
580 ANATOP_PFD_CLKGATE_MASK(3);
581
582 reg = readl(&ccm->cbcmr);
583 periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
584 >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
585 periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
586 >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
587
588 /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
589 if ((periph2 != 0x2) && (periph1 != 0x2))
590 mask528 |= ANATOP_PFD_CLKGATE_MASK(0);
591
592 if ((periph2 != 0x1) && (periph1 != 0x1) &&
593 (periph2 != 0x3) && (periph1 != 0x3))
594 mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
595
596 writel(mask480, &anatop->pfd_480_set);
597 writel(mask528, &anatop->pfd_528_set);
598 writel(mask480, &anatop->pfd_480_clr);
599 writel(mask528, &anatop->pfd_528_clr);
600 }
601
602 #ifdef CONFIG_IMX_HDMI
imx_enable_hdmi_phy(void)603 void imx_enable_hdmi_phy(void)
604 {
605 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
606 u8 reg;
607 reg = readb(&hdmi->phy_conf0);
608 reg |= HDMI_PHY_CONF0_PDZ_MASK;
609 writeb(reg, &hdmi->phy_conf0);
610 udelay(3000);
611 reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
612 writeb(reg, &hdmi->phy_conf0);
613 udelay(3000);
614 reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
615 writeb(reg, &hdmi->phy_conf0);
616 writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
617 }
618
imx_setup_hdmi(void)619 void imx_setup_hdmi(void)
620 {
621 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
622 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
623 int reg, count;
624 u8 val;
625
626 /* Turn on HDMI PHY clock */
627 reg = readl(&mxc_ccm->CCGR2);
628 reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
629 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
630 writel(reg, &mxc_ccm->CCGR2);
631 writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
632 reg = readl(&mxc_ccm->chsccdr);
633 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
634 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
635 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
636 reg |= (CHSCCDR_PODF_DIVIDE_BY_3
637 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
638 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
639 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
640 writel(reg, &mxc_ccm->chsccdr);
641
642 /* Clear the overflow condition */
643 if (readb(&hdmi->ih_fc_stat2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK) {
644 /* TMDS software reset */
645 writeb((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, &hdmi->mc_swrstz);
646 val = readb(&hdmi->fc_invidconf);
647 /* Need minimum 3 times to write to clear the register */
648 for (count = 0 ; count < 5 ; count++)
649 writeb(val, &hdmi->fc_invidconf);
650 }
651 }
652 #endif
653
654
655 /*
656 * gpr_init() function is common for boards using MX6S, MX6DL, MX6D,
657 * MX6Q and MX6QP processors
658 */
gpr_init(void)659 void gpr_init(void)
660 {
661 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
662
663 /*
664 * If this function is used in a common MX6 spl implementation
665 * we have to ensure that it is only called for suitable cpu types,
666 * otherwise it breaks hardware parts like enet1, can1, can2, etc.
667 */
668 if (!is_mx6dqp() && !is_mx6dq() && !is_mx6sdl())
669 return;
670
671 /* enable AXI cache for VDOA/VPU/IPU */
672 writel(0xF00000CF, &iomux->gpr[4]);
673 if (is_mx6dqp()) {
674 /* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
675 writel(0x77177717, &iomux->gpr[6]);
676 writel(0x77177717, &iomux->gpr[7]);
677 } else {
678 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
679 writel(0x007F007F, &iomux->gpr[6]);
680 writel(0x007F007F, &iomux->gpr[7]);
681 }
682 }
683