1 /*
2 * Performance events - AMD IBS
3 *
4 * Copyright (C) 2011 Advanced Micro Devices, Inc., Robert Richter
5 *
6 * For licencing details see kernel-base/COPYING
7 */
8
9 #include <linux/perf_event.h>
10 #include <linux/init.h>
11 #include <linux/export.h>
12 #include <linux/pci.h>
13 #include <linux/ptrace.h>
14 #include <linux/syscore_ops.h>
15 #include <linux/sched/clock.h>
16
17 #include <asm/apic.h>
18
19 #include "../perf_event.h"
20
21 static u32 ibs_caps;
22
23 #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD)
24
25 #include <linux/kprobes.h>
26 #include <linux/hardirq.h>
27
28 #include <asm/nmi.h>
29 #include <asm/amd-ibs.h>
30
31 #define IBS_FETCH_CONFIG_MASK (IBS_FETCH_RAND_EN | IBS_FETCH_MAX_CNT)
32 #define IBS_OP_CONFIG_MASK IBS_OP_MAX_CNT
33
34
35 /*
36 * IBS states:
37 *
38 * ENABLED; tracks the pmu::add(), pmu::del() state, when set the counter is taken
39 * and any further add()s must fail.
40 *
41 * STARTED/STOPPING/STOPPED; deal with pmu::start(), pmu::stop() state but are
42 * complicated by the fact that the IBS hardware can send late NMIs (ie. after
43 * we've cleared the EN bit).
44 *
45 * In order to consume these late NMIs we have the STOPPED state, any NMI that
46 * happens after we've cleared the EN state will clear this bit and report the
47 * NMI handled (this is fundamentally racy in the face or multiple NMI sources,
48 * someone else can consume our BIT and our NMI will go unhandled).
49 *
50 * And since we cannot set/clear this separate bit together with the EN bit,
51 * there are races; if we cleared STARTED early, an NMI could land in
52 * between clearing STARTED and clearing the EN bit (in fact multiple NMIs
53 * could happen if the period is small enough), and consume our STOPPED bit
54 * and trigger streams of unhandled NMIs.
55 *
56 * If, however, we clear STARTED late, an NMI can hit between clearing the
57 * EN bit and clearing STARTED, still see STARTED set and process the event.
58 * If this event will have the VALID bit clear, we bail properly, but this
59 * is not a given. With VALID set we can end up calling pmu::stop() again
60 * (the throttle logic) and trigger the WARNs in there.
61 *
62 * So what we do is set STOPPING before clearing EN to avoid the pmu::stop()
63 * nesting, and clear STARTED late, so that we have a well defined state over
64 * the clearing of the EN bit.
65 *
66 * XXX: we could probably be using !atomic bitops for all this.
67 */
68
69 enum ibs_states {
70 IBS_ENABLED = 0,
71 IBS_STARTED = 1,
72 IBS_STOPPING = 2,
73 IBS_STOPPED = 3,
74
75 IBS_MAX_STATES,
76 };
77
78 struct cpu_perf_ibs {
79 struct perf_event *event;
80 unsigned long state[BITS_TO_LONGS(IBS_MAX_STATES)];
81 };
82
83 struct perf_ibs {
84 struct pmu pmu;
85 unsigned int msr;
86 u64 config_mask;
87 u64 cnt_mask;
88 u64 enable_mask;
89 u64 valid_mask;
90 u64 max_period;
91 unsigned long offset_mask[1];
92 int offset_max;
93 unsigned int fetch_count_reset_broken : 1;
94 unsigned int fetch_ignore_if_zero_rip : 1;
95 struct cpu_perf_ibs __percpu *pcpu;
96
97 u64 (*get_count)(u64 config);
98 };
99
100 static int
perf_event_set_period(struct hw_perf_event * hwc,u64 min,u64 max,u64 * hw_period)101 perf_event_set_period(struct hw_perf_event *hwc, u64 min, u64 max, u64 *hw_period)
102 {
103 s64 left = local64_read(&hwc->period_left);
104 s64 period = hwc->sample_period;
105 int overflow = 0;
106
107 /*
108 * If we are way outside a reasonable range then just skip forward:
109 */
110 if (unlikely(left <= -period)) {
111 left = period;
112 local64_set(&hwc->period_left, left);
113 hwc->last_period = period;
114 overflow = 1;
115 }
116
117 if (unlikely(left < (s64)min)) {
118 left += period;
119 local64_set(&hwc->period_left, left);
120 hwc->last_period = period;
121 overflow = 1;
122 }
123
124 /*
125 * If the hw period that triggers the sw overflow is too short
126 * we might hit the irq handler. This biases the results.
127 * Thus we shorten the next-to-last period and set the last
128 * period to the max period.
129 */
130 if (left > max) {
131 left -= max;
132 if (left > max)
133 left = max;
134 else if (left < min)
135 left = min;
136 }
137
138 *hw_period = (u64)left;
139
140 return overflow;
141 }
142
143 static int
perf_event_try_update(struct perf_event * event,u64 new_raw_count,int width)144 perf_event_try_update(struct perf_event *event, u64 new_raw_count, int width)
145 {
146 struct hw_perf_event *hwc = &event->hw;
147 int shift = 64 - width;
148 u64 prev_raw_count;
149 u64 delta;
150
151 /*
152 * Careful: an NMI might modify the previous event value.
153 *
154 * Our tactic to handle this is to first atomically read and
155 * exchange a new raw count - then add that new-prev delta
156 * count to the generic event atomically:
157 */
158 prev_raw_count = local64_read(&hwc->prev_count);
159 if (!local64_try_cmpxchg(&hwc->prev_count,
160 &prev_raw_count, new_raw_count))
161 return 0;
162
163 /*
164 * Now we have the new raw value and have updated the prev
165 * timestamp already. We can now calculate the elapsed delta
166 * (event-)time and add that to the generic event.
167 *
168 * Careful, not all hw sign-extends above the physical width
169 * of the count.
170 */
171 delta = (new_raw_count << shift) - (prev_raw_count << shift);
172 delta >>= shift;
173
174 local64_add(delta, &event->count);
175 local64_sub(delta, &hwc->period_left);
176
177 return 1;
178 }
179
180 static struct perf_ibs perf_ibs_fetch;
181 static struct perf_ibs perf_ibs_op;
182
get_ibs_pmu(int type)183 static struct perf_ibs *get_ibs_pmu(int type)
184 {
185 if (perf_ibs_fetch.pmu.type == type)
186 return &perf_ibs_fetch;
187 if (perf_ibs_op.pmu.type == type)
188 return &perf_ibs_op;
189 return NULL;
190 }
191
192 /*
193 * core pmu config -> IBS config
194 *
195 * perf record -a -e cpu-cycles:p ... # use ibs op counting cycle count
196 * perf record -a -e r076:p ... # same as -e cpu-cycles:p
197 * perf record -a -e r0C1:p ... # use ibs op counting micro-ops
198 *
199 * IbsOpCntCtl (bit 19) of IBS Execution Control Register (IbsOpCtl,
200 * MSRC001_1033) is used to select either cycle or micro-ops counting
201 * mode.
202 */
core_pmu_ibs_config(struct perf_event * event,u64 * config)203 static int core_pmu_ibs_config(struct perf_event *event, u64 *config)
204 {
205 switch (event->attr.type) {
206 case PERF_TYPE_HARDWARE:
207 switch (event->attr.config) {
208 case PERF_COUNT_HW_CPU_CYCLES:
209 *config = 0;
210 return 0;
211 }
212 break;
213 case PERF_TYPE_RAW:
214 switch (event->attr.config) {
215 case 0x0076:
216 *config = 0;
217 return 0;
218 case 0x00C1:
219 *config = IBS_OP_CNT_CTL;
220 return 0;
221 }
222 break;
223 default:
224 return -ENOENT;
225 }
226
227 return -EOPNOTSUPP;
228 }
229
230 /*
231 * The rip of IBS samples has skid 0. Thus, IBS supports precise
232 * levels 1 and 2 and the PERF_EFLAGS_EXACT is set. In rare cases the
233 * rip is invalid when IBS was not able to record the rip correctly.
234 * We clear PERF_EFLAGS_EXACT and take the rip from pt_regs then.
235 */
forward_event_to_ibs(struct perf_event * event)236 int forward_event_to_ibs(struct perf_event *event)
237 {
238 u64 config = 0;
239
240 if (!event->attr.precise_ip || event->attr.precise_ip > 2)
241 return -EOPNOTSUPP;
242
243 if (!core_pmu_ibs_config(event, &config)) {
244 event->attr.type = perf_ibs_op.pmu.type;
245 event->attr.config = config;
246 }
247 return -ENOENT;
248 }
249
250 /*
251 * Grouping of IBS events is not possible since IBS can have only
252 * one event active at any point in time.
253 */
validate_group(struct perf_event * event)254 static int validate_group(struct perf_event *event)
255 {
256 struct perf_event *sibling;
257
258 if (event->group_leader == event)
259 return 0;
260
261 if (event->group_leader->pmu == event->pmu)
262 return -EINVAL;
263
264 for_each_sibling_event(sibling, event->group_leader) {
265 if (sibling->pmu == event->pmu)
266 return -EINVAL;
267 }
268 return 0;
269 }
270
perf_ibs_init(struct perf_event * event)271 static int perf_ibs_init(struct perf_event *event)
272 {
273 struct hw_perf_event *hwc = &event->hw;
274 struct perf_ibs *perf_ibs;
275 u64 config;
276 int ret;
277
278 perf_ibs = get_ibs_pmu(event->attr.type);
279 if (!perf_ibs)
280 return -ENOENT;
281
282 config = event->attr.config;
283
284 if (event->pmu != &perf_ibs->pmu)
285 return -ENOENT;
286
287 if (config & ~perf_ibs->config_mask)
288 return -EINVAL;
289
290 ret = validate_group(event);
291 if (ret)
292 return ret;
293
294 if (hwc->sample_period) {
295 if (config & perf_ibs->cnt_mask)
296 /* raw max_cnt may not be set */
297 return -EINVAL;
298 if (!event->attr.sample_freq && hwc->sample_period & 0x0f)
299 /*
300 * lower 4 bits can not be set in ibs max cnt,
301 * but allowing it in case we adjust the
302 * sample period to set a frequency.
303 */
304 return -EINVAL;
305 hwc->sample_period &= ~0x0FULL;
306 if (!hwc->sample_period)
307 hwc->sample_period = 0x10;
308 } else {
309 u64 period = 0;
310
311 if (perf_ibs == &perf_ibs_op) {
312 period = (config & IBS_OP_MAX_CNT) << 4;
313 if (ibs_caps & IBS_CAPS_OPCNTEXT)
314 period |= config & IBS_OP_MAX_CNT_EXT_MASK;
315 } else {
316 period = (config & IBS_FETCH_MAX_CNT) << 4;
317 }
318
319 config &= ~perf_ibs->cnt_mask;
320 event->attr.sample_period = period;
321 hwc->sample_period = period;
322 }
323
324 if (!hwc->sample_period)
325 return -EINVAL;
326
327 /*
328 * If we modify hwc->sample_period, we also need to update
329 * hwc->last_period and hwc->period_left.
330 */
331 hwc->last_period = hwc->sample_period;
332 local64_set(&hwc->period_left, hwc->sample_period);
333
334 hwc->config_base = perf_ibs->msr;
335 hwc->config = config;
336
337 return 0;
338 }
339
perf_ibs_set_period(struct perf_ibs * perf_ibs,struct hw_perf_event * hwc,u64 * period)340 static int perf_ibs_set_period(struct perf_ibs *perf_ibs,
341 struct hw_perf_event *hwc, u64 *period)
342 {
343 int overflow;
344
345 /* ignore lower 4 bits in min count: */
346 overflow = perf_event_set_period(hwc, 1<<4, perf_ibs->max_period, period);
347 local64_set(&hwc->prev_count, 0);
348
349 return overflow;
350 }
351
get_ibs_fetch_count(u64 config)352 static u64 get_ibs_fetch_count(u64 config)
353 {
354 union ibs_fetch_ctl fetch_ctl = (union ibs_fetch_ctl)config;
355
356 return fetch_ctl.fetch_cnt << 4;
357 }
358
get_ibs_op_count(u64 config)359 static u64 get_ibs_op_count(u64 config)
360 {
361 union ibs_op_ctl op_ctl = (union ibs_op_ctl)config;
362 u64 count = 0;
363
364 /*
365 * If the internal 27-bit counter rolled over, the count is MaxCnt
366 * and the lower 7 bits of CurCnt are randomized.
367 * Otherwise CurCnt has the full 27-bit current counter value.
368 */
369 if (op_ctl.op_val) {
370 count = op_ctl.opmaxcnt << 4;
371 if (ibs_caps & IBS_CAPS_OPCNTEXT)
372 count += op_ctl.opmaxcnt_ext << 20;
373 } else if (ibs_caps & IBS_CAPS_RDWROPCNT) {
374 count = op_ctl.opcurcnt;
375 }
376
377 return count;
378 }
379
380 static void
perf_ibs_event_update(struct perf_ibs * perf_ibs,struct perf_event * event,u64 * config)381 perf_ibs_event_update(struct perf_ibs *perf_ibs, struct perf_event *event,
382 u64 *config)
383 {
384 u64 count = perf_ibs->get_count(*config);
385
386 /*
387 * Set width to 64 since we do not overflow on max width but
388 * instead on max count. In perf_ibs_set_period() we clear
389 * prev count manually on overflow.
390 */
391 while (!perf_event_try_update(event, count, 64)) {
392 rdmsrl(event->hw.config_base, *config);
393 count = perf_ibs->get_count(*config);
394 }
395 }
396
perf_ibs_enable_event(struct perf_ibs * perf_ibs,struct hw_perf_event * hwc,u64 config)397 static inline void perf_ibs_enable_event(struct perf_ibs *perf_ibs,
398 struct hw_perf_event *hwc, u64 config)
399 {
400 u64 tmp = hwc->config | config;
401
402 if (perf_ibs->fetch_count_reset_broken)
403 wrmsrl(hwc->config_base, tmp & ~perf_ibs->enable_mask);
404
405 wrmsrl(hwc->config_base, tmp | perf_ibs->enable_mask);
406 }
407
408 /*
409 * Erratum #420 Instruction-Based Sampling Engine May Generate
410 * Interrupt that Cannot Be Cleared:
411 *
412 * Must clear counter mask first, then clear the enable bit. See
413 * Revision Guide for AMD Family 10h Processors, Publication #41322.
414 */
perf_ibs_disable_event(struct perf_ibs * perf_ibs,struct hw_perf_event * hwc,u64 config)415 static inline void perf_ibs_disable_event(struct perf_ibs *perf_ibs,
416 struct hw_perf_event *hwc, u64 config)
417 {
418 config &= ~perf_ibs->cnt_mask;
419 if (boot_cpu_data.x86 == 0x10)
420 wrmsrl(hwc->config_base, config);
421 config &= ~perf_ibs->enable_mask;
422 wrmsrl(hwc->config_base, config);
423 }
424
425 /*
426 * We cannot restore the ibs pmu state, so we always needs to update
427 * the event while stopping it and then reset the state when starting
428 * again. Thus, ignoring PERF_EF_RELOAD and PERF_EF_UPDATE flags in
429 * perf_ibs_start()/perf_ibs_stop() and instead always do it.
430 */
perf_ibs_start(struct perf_event * event,int flags)431 static void perf_ibs_start(struct perf_event *event, int flags)
432 {
433 struct hw_perf_event *hwc = &event->hw;
434 struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
435 struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
436 u64 period, config = 0;
437
438 if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
439 return;
440
441 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
442 hwc->state = 0;
443
444 perf_ibs_set_period(perf_ibs, hwc, &period);
445 if (perf_ibs == &perf_ibs_op && (ibs_caps & IBS_CAPS_OPCNTEXT)) {
446 config |= period & IBS_OP_MAX_CNT_EXT_MASK;
447 period &= ~IBS_OP_MAX_CNT_EXT_MASK;
448 }
449 config |= period >> 4;
450
451 /*
452 * Set STARTED before enabling the hardware, such that a subsequent NMI
453 * must observe it.
454 */
455 set_bit(IBS_STARTED, pcpu->state);
456 clear_bit(IBS_STOPPING, pcpu->state);
457 perf_ibs_enable_event(perf_ibs, hwc, config);
458
459 perf_event_update_userpage(event);
460 }
461
perf_ibs_stop(struct perf_event * event,int flags)462 static void perf_ibs_stop(struct perf_event *event, int flags)
463 {
464 struct hw_perf_event *hwc = &event->hw;
465 struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
466 struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
467 u64 config;
468 int stopping;
469
470 if (test_and_set_bit(IBS_STOPPING, pcpu->state))
471 return;
472
473 stopping = test_bit(IBS_STARTED, pcpu->state);
474
475 if (!stopping && (hwc->state & PERF_HES_UPTODATE))
476 return;
477
478 rdmsrl(hwc->config_base, config);
479
480 if (stopping) {
481 /*
482 * Set STOPPED before disabling the hardware, such that it
483 * must be visible to NMIs the moment we clear the EN bit,
484 * at which point we can generate an !VALID sample which
485 * we need to consume.
486 */
487 set_bit(IBS_STOPPED, pcpu->state);
488 perf_ibs_disable_event(perf_ibs, hwc, config);
489 /*
490 * Clear STARTED after disabling the hardware; if it were
491 * cleared before an NMI hitting after the clear but before
492 * clearing the EN bit might think it a spurious NMI and not
493 * handle it.
494 *
495 * Clearing it after, however, creates the problem of the NMI
496 * handler seeing STARTED but not having a valid sample.
497 */
498 clear_bit(IBS_STARTED, pcpu->state);
499 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
500 hwc->state |= PERF_HES_STOPPED;
501 }
502
503 if (hwc->state & PERF_HES_UPTODATE)
504 return;
505
506 /*
507 * Clear valid bit to not count rollovers on update, rollovers
508 * are only updated in the irq handler.
509 */
510 config &= ~perf_ibs->valid_mask;
511
512 perf_ibs_event_update(perf_ibs, event, &config);
513 hwc->state |= PERF_HES_UPTODATE;
514 }
515
perf_ibs_add(struct perf_event * event,int flags)516 static int perf_ibs_add(struct perf_event *event, int flags)
517 {
518 struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
519 struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
520
521 if (test_and_set_bit(IBS_ENABLED, pcpu->state))
522 return -ENOSPC;
523
524 event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
525
526 pcpu->event = event;
527
528 if (flags & PERF_EF_START)
529 perf_ibs_start(event, PERF_EF_RELOAD);
530
531 return 0;
532 }
533
perf_ibs_del(struct perf_event * event,int flags)534 static void perf_ibs_del(struct perf_event *event, int flags)
535 {
536 struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
537 struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
538
539 if (!test_and_clear_bit(IBS_ENABLED, pcpu->state))
540 return;
541
542 perf_ibs_stop(event, PERF_EF_UPDATE);
543
544 pcpu->event = NULL;
545
546 perf_event_update_userpage(event);
547 }
548
perf_ibs_read(struct perf_event * event)549 static void perf_ibs_read(struct perf_event *event) { }
550
551 /*
552 * We need to initialize with empty group if all attributes in the
553 * group are dynamic.
554 */
555 static struct attribute *attrs_empty[] = {
556 NULL,
557 };
558
559 static struct attribute_group empty_format_group = {
560 .name = "format",
561 .attrs = attrs_empty,
562 };
563
564 static struct attribute_group empty_caps_group = {
565 .name = "caps",
566 .attrs = attrs_empty,
567 };
568
569 static const struct attribute_group *empty_attr_groups[] = {
570 &empty_format_group,
571 &empty_caps_group,
572 NULL,
573 };
574
575 PMU_FORMAT_ATTR(rand_en, "config:57");
576 PMU_FORMAT_ATTR(cnt_ctl, "config:19");
577 PMU_EVENT_ATTR_STRING(l3missonly, fetch_l3missonly, "config:59");
578 PMU_EVENT_ATTR_STRING(l3missonly, op_l3missonly, "config:16");
579 PMU_EVENT_ATTR_STRING(zen4_ibs_extensions, zen4_ibs_extensions, "1");
580
581 static umode_t
zen4_ibs_extensions_is_visible(struct kobject * kobj,struct attribute * attr,int i)582 zen4_ibs_extensions_is_visible(struct kobject *kobj, struct attribute *attr, int i)
583 {
584 return ibs_caps & IBS_CAPS_ZEN4 ? attr->mode : 0;
585 }
586
587 static struct attribute *rand_en_attrs[] = {
588 &format_attr_rand_en.attr,
589 NULL,
590 };
591
592 static struct attribute *fetch_l3missonly_attrs[] = {
593 &fetch_l3missonly.attr.attr,
594 NULL,
595 };
596
597 static struct attribute *zen4_ibs_extensions_attrs[] = {
598 &zen4_ibs_extensions.attr.attr,
599 NULL,
600 };
601
602 static struct attribute_group group_rand_en = {
603 .name = "format",
604 .attrs = rand_en_attrs,
605 };
606
607 static struct attribute_group group_fetch_l3missonly = {
608 .name = "format",
609 .attrs = fetch_l3missonly_attrs,
610 .is_visible = zen4_ibs_extensions_is_visible,
611 };
612
613 static struct attribute_group group_zen4_ibs_extensions = {
614 .name = "caps",
615 .attrs = zen4_ibs_extensions_attrs,
616 .is_visible = zen4_ibs_extensions_is_visible,
617 };
618
619 static const struct attribute_group *fetch_attr_groups[] = {
620 &group_rand_en,
621 &empty_caps_group,
622 NULL,
623 };
624
625 static const struct attribute_group *fetch_attr_update[] = {
626 &group_fetch_l3missonly,
627 &group_zen4_ibs_extensions,
628 NULL,
629 };
630
631 static umode_t
cnt_ctl_is_visible(struct kobject * kobj,struct attribute * attr,int i)632 cnt_ctl_is_visible(struct kobject *kobj, struct attribute *attr, int i)
633 {
634 return ibs_caps & IBS_CAPS_OPCNT ? attr->mode : 0;
635 }
636
637 static struct attribute *cnt_ctl_attrs[] = {
638 &format_attr_cnt_ctl.attr,
639 NULL,
640 };
641
642 static struct attribute *op_l3missonly_attrs[] = {
643 &op_l3missonly.attr.attr,
644 NULL,
645 };
646
647 static struct attribute_group group_cnt_ctl = {
648 .name = "format",
649 .attrs = cnt_ctl_attrs,
650 .is_visible = cnt_ctl_is_visible,
651 };
652
653 static struct attribute_group group_op_l3missonly = {
654 .name = "format",
655 .attrs = op_l3missonly_attrs,
656 .is_visible = zen4_ibs_extensions_is_visible,
657 };
658
659 static const struct attribute_group *op_attr_update[] = {
660 &group_cnt_ctl,
661 &group_op_l3missonly,
662 &group_zen4_ibs_extensions,
663 NULL,
664 };
665
666 static struct perf_ibs perf_ibs_fetch = {
667 .pmu = {
668 .task_ctx_nr = perf_hw_context,
669
670 .event_init = perf_ibs_init,
671 .add = perf_ibs_add,
672 .del = perf_ibs_del,
673 .start = perf_ibs_start,
674 .stop = perf_ibs_stop,
675 .read = perf_ibs_read,
676 .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
677 },
678 .msr = MSR_AMD64_IBSFETCHCTL,
679 .config_mask = IBS_FETCH_CONFIG_MASK,
680 .cnt_mask = IBS_FETCH_MAX_CNT,
681 .enable_mask = IBS_FETCH_ENABLE,
682 .valid_mask = IBS_FETCH_VAL,
683 .max_period = IBS_FETCH_MAX_CNT << 4,
684 .offset_mask = { MSR_AMD64_IBSFETCH_REG_MASK },
685 .offset_max = MSR_AMD64_IBSFETCH_REG_COUNT,
686
687 .get_count = get_ibs_fetch_count,
688 };
689
690 static struct perf_ibs perf_ibs_op = {
691 .pmu = {
692 .task_ctx_nr = perf_hw_context,
693
694 .event_init = perf_ibs_init,
695 .add = perf_ibs_add,
696 .del = perf_ibs_del,
697 .start = perf_ibs_start,
698 .stop = perf_ibs_stop,
699 .read = perf_ibs_read,
700 .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
701 },
702 .msr = MSR_AMD64_IBSOPCTL,
703 .config_mask = IBS_OP_CONFIG_MASK,
704 .cnt_mask = IBS_OP_MAX_CNT | IBS_OP_CUR_CNT |
705 IBS_OP_CUR_CNT_RAND,
706 .enable_mask = IBS_OP_ENABLE,
707 .valid_mask = IBS_OP_VAL,
708 .max_period = IBS_OP_MAX_CNT << 4,
709 .offset_mask = { MSR_AMD64_IBSOP_REG_MASK },
710 .offset_max = MSR_AMD64_IBSOP_REG_COUNT,
711
712 .get_count = get_ibs_op_count,
713 };
714
perf_ibs_get_mem_op(union ibs_op_data3 * op_data3,struct perf_sample_data * data)715 static void perf_ibs_get_mem_op(union ibs_op_data3 *op_data3,
716 struct perf_sample_data *data)
717 {
718 union perf_mem_data_src *data_src = &data->data_src;
719
720 data_src->mem_op = PERF_MEM_OP_NA;
721
722 if (op_data3->ld_op)
723 data_src->mem_op = PERF_MEM_OP_LOAD;
724 else if (op_data3->st_op)
725 data_src->mem_op = PERF_MEM_OP_STORE;
726 }
727
728 /*
729 * Processors having CPUID_Fn8000001B_EAX[11] aka IBS_CAPS_ZEN4 has
730 * more fine granular DataSrc encodings. Others have coarse.
731 */
perf_ibs_data_src(union ibs_op_data2 * op_data2)732 static u8 perf_ibs_data_src(union ibs_op_data2 *op_data2)
733 {
734 if (ibs_caps & IBS_CAPS_ZEN4)
735 return (op_data2->data_src_hi << 3) | op_data2->data_src_lo;
736
737 return op_data2->data_src_lo;
738 }
739
740 #define L(x) (PERF_MEM_S(LVL, x) | PERF_MEM_S(LVL, HIT))
741 #define LN(x) PERF_MEM_S(LVLNUM, x)
742 #define REM PERF_MEM_S(REMOTE, REMOTE)
743 #define HOPS(x) PERF_MEM_S(HOPS, x)
744
745 static u64 g_data_src[8] = {
746 [IBS_DATA_SRC_LOC_CACHE] = L(L3) | L(REM_CCE1) | LN(ANY_CACHE) | HOPS(0),
747 [IBS_DATA_SRC_DRAM] = L(LOC_RAM) | LN(RAM),
748 [IBS_DATA_SRC_REM_CACHE] = L(REM_CCE2) | LN(ANY_CACHE) | REM | HOPS(1),
749 [IBS_DATA_SRC_IO] = L(IO) | LN(IO),
750 };
751
752 #define RMT_NODE_BITS (1 << IBS_DATA_SRC_DRAM)
753 #define RMT_NODE_APPLICABLE(x) (RMT_NODE_BITS & (1 << x))
754
755 static u64 g_zen4_data_src[32] = {
756 [IBS_DATA_SRC_EXT_LOC_CACHE] = L(L3) | LN(L3),
757 [IBS_DATA_SRC_EXT_NEAR_CCX_CACHE] = L(REM_CCE1) | LN(ANY_CACHE) | REM | HOPS(0),
758 [IBS_DATA_SRC_EXT_DRAM] = L(LOC_RAM) | LN(RAM),
759 [IBS_DATA_SRC_EXT_FAR_CCX_CACHE] = L(REM_CCE2) | LN(ANY_CACHE) | REM | HOPS(1),
760 [IBS_DATA_SRC_EXT_PMEM] = LN(PMEM),
761 [IBS_DATA_SRC_EXT_IO] = L(IO) | LN(IO),
762 [IBS_DATA_SRC_EXT_EXT_MEM] = LN(CXL),
763 };
764
765 #define ZEN4_RMT_NODE_BITS ((1 << IBS_DATA_SRC_EXT_DRAM) | \
766 (1 << IBS_DATA_SRC_EXT_PMEM) | \
767 (1 << IBS_DATA_SRC_EXT_EXT_MEM))
768 #define ZEN4_RMT_NODE_APPLICABLE(x) (ZEN4_RMT_NODE_BITS & (1 << x))
769
perf_ibs_get_mem_lvl(union ibs_op_data2 * op_data2,union ibs_op_data3 * op_data3,struct perf_sample_data * data)770 static __u64 perf_ibs_get_mem_lvl(union ibs_op_data2 *op_data2,
771 union ibs_op_data3 *op_data3,
772 struct perf_sample_data *data)
773 {
774 union perf_mem_data_src *data_src = &data->data_src;
775 u8 ibs_data_src = perf_ibs_data_src(op_data2);
776
777 data_src->mem_lvl = 0;
778 data_src->mem_lvl_num = 0;
779
780 /*
781 * DcMiss, L2Miss, DataSrc, DcMissLat etc. are all invalid for Uncached
782 * memory accesses. So, check DcUcMemAcc bit early.
783 */
784 if (op_data3->dc_uc_mem_acc && ibs_data_src != IBS_DATA_SRC_EXT_IO)
785 return L(UNC) | LN(UNC);
786
787 /* L1 Hit */
788 if (op_data3->dc_miss == 0)
789 return L(L1) | LN(L1);
790
791 /* L2 Hit */
792 if (op_data3->l2_miss == 0) {
793 /* Erratum #1293 */
794 if (boot_cpu_data.x86 != 0x19 || boot_cpu_data.x86_model > 0xF ||
795 !(op_data3->sw_pf || op_data3->dc_miss_no_mab_alloc))
796 return L(L2) | LN(L2);
797 }
798
799 /*
800 * OP_DATA2 is valid only for load ops. Skip all checks which
801 * uses OP_DATA2[DataSrc].
802 */
803 if (data_src->mem_op != PERF_MEM_OP_LOAD)
804 goto check_mab;
805
806 if (ibs_caps & IBS_CAPS_ZEN4) {
807 u64 val = g_zen4_data_src[ibs_data_src];
808
809 if (!val)
810 goto check_mab;
811
812 /* HOPS_1 because IBS doesn't provide remote socket detail */
813 if (op_data2->rmt_node && ZEN4_RMT_NODE_APPLICABLE(ibs_data_src)) {
814 if (ibs_data_src == IBS_DATA_SRC_EXT_DRAM)
815 val = L(REM_RAM1) | LN(RAM) | REM | HOPS(1);
816 else
817 val |= REM | HOPS(1);
818 }
819
820 return val;
821 } else {
822 u64 val = g_data_src[ibs_data_src];
823
824 if (!val)
825 goto check_mab;
826
827 /* HOPS_1 because IBS doesn't provide remote socket detail */
828 if (op_data2->rmt_node && RMT_NODE_APPLICABLE(ibs_data_src)) {
829 if (ibs_data_src == IBS_DATA_SRC_DRAM)
830 val = L(REM_RAM1) | LN(RAM) | REM | HOPS(1);
831 else
832 val |= REM | HOPS(1);
833 }
834
835 return val;
836 }
837
838 check_mab:
839 /*
840 * MAB (Miss Address Buffer) Hit. MAB keeps track of outstanding
841 * DC misses. However, such data may come from any level in mem
842 * hierarchy. IBS provides detail about both MAB as well as actual
843 * DataSrc simultaneously. Prioritize DataSrc over MAB, i.e. set
844 * MAB only when IBS fails to provide DataSrc.
845 */
846 if (op_data3->dc_miss_no_mab_alloc)
847 return L(LFB) | LN(LFB);
848
849 /* Don't set HIT with NA */
850 return PERF_MEM_S(LVL, NA) | LN(NA);
851 }
852
perf_ibs_cache_hit_st_valid(void)853 static bool perf_ibs_cache_hit_st_valid(void)
854 {
855 /* 0: Uninitialized, 1: Valid, -1: Invalid */
856 static int cache_hit_st_valid;
857
858 if (unlikely(!cache_hit_st_valid)) {
859 if (boot_cpu_data.x86 == 0x19 &&
860 (boot_cpu_data.x86_model <= 0xF ||
861 (boot_cpu_data.x86_model >= 0x20 &&
862 boot_cpu_data.x86_model <= 0x5F))) {
863 cache_hit_st_valid = -1;
864 } else {
865 cache_hit_st_valid = 1;
866 }
867 }
868
869 return cache_hit_st_valid == 1;
870 }
871
perf_ibs_get_mem_snoop(union ibs_op_data2 * op_data2,struct perf_sample_data * data)872 static void perf_ibs_get_mem_snoop(union ibs_op_data2 *op_data2,
873 struct perf_sample_data *data)
874 {
875 union perf_mem_data_src *data_src = &data->data_src;
876 u8 ibs_data_src;
877
878 data_src->mem_snoop = PERF_MEM_SNOOP_NA;
879
880 if (!perf_ibs_cache_hit_st_valid() ||
881 data_src->mem_op != PERF_MEM_OP_LOAD ||
882 data_src->mem_lvl & PERF_MEM_LVL_L1 ||
883 data_src->mem_lvl & PERF_MEM_LVL_L2 ||
884 op_data2->cache_hit_st)
885 return;
886
887 ibs_data_src = perf_ibs_data_src(op_data2);
888
889 if (ibs_caps & IBS_CAPS_ZEN4) {
890 if (ibs_data_src == IBS_DATA_SRC_EXT_LOC_CACHE ||
891 ibs_data_src == IBS_DATA_SRC_EXT_NEAR_CCX_CACHE ||
892 ibs_data_src == IBS_DATA_SRC_EXT_FAR_CCX_CACHE)
893 data_src->mem_snoop = PERF_MEM_SNOOP_HITM;
894 } else if (ibs_data_src == IBS_DATA_SRC_LOC_CACHE) {
895 data_src->mem_snoop = PERF_MEM_SNOOP_HITM;
896 }
897 }
898
perf_ibs_get_tlb_lvl(union ibs_op_data3 * op_data3,struct perf_sample_data * data)899 static void perf_ibs_get_tlb_lvl(union ibs_op_data3 *op_data3,
900 struct perf_sample_data *data)
901 {
902 union perf_mem_data_src *data_src = &data->data_src;
903
904 data_src->mem_dtlb = PERF_MEM_TLB_NA;
905
906 if (!op_data3->dc_lin_addr_valid)
907 return;
908
909 if (!op_data3->dc_l1tlb_miss) {
910 data_src->mem_dtlb = PERF_MEM_TLB_L1 | PERF_MEM_TLB_HIT;
911 return;
912 }
913
914 if (!op_data3->dc_l2tlb_miss) {
915 data_src->mem_dtlb = PERF_MEM_TLB_L2 | PERF_MEM_TLB_HIT;
916 return;
917 }
918
919 data_src->mem_dtlb = PERF_MEM_TLB_L2 | PERF_MEM_TLB_MISS;
920 }
921
perf_ibs_get_mem_lock(union ibs_op_data3 * op_data3,struct perf_sample_data * data)922 static void perf_ibs_get_mem_lock(union ibs_op_data3 *op_data3,
923 struct perf_sample_data *data)
924 {
925 union perf_mem_data_src *data_src = &data->data_src;
926
927 data_src->mem_lock = PERF_MEM_LOCK_NA;
928
929 if (op_data3->dc_locked_op)
930 data_src->mem_lock = PERF_MEM_LOCK_LOCKED;
931 }
932
933 #define ibs_op_msr_idx(msr) (msr - MSR_AMD64_IBSOPCTL)
934
perf_ibs_get_data_src(struct perf_ibs_data * ibs_data,struct perf_sample_data * data,union ibs_op_data2 * op_data2,union ibs_op_data3 * op_data3)935 static void perf_ibs_get_data_src(struct perf_ibs_data *ibs_data,
936 struct perf_sample_data *data,
937 union ibs_op_data2 *op_data2,
938 union ibs_op_data3 *op_data3)
939 {
940 union perf_mem_data_src *data_src = &data->data_src;
941
942 data_src->val |= perf_ibs_get_mem_lvl(op_data2, op_data3, data);
943 perf_ibs_get_mem_snoop(op_data2, data);
944 perf_ibs_get_tlb_lvl(op_data3, data);
945 perf_ibs_get_mem_lock(op_data3, data);
946 }
947
perf_ibs_get_op_data2(struct perf_ibs_data * ibs_data,union ibs_op_data3 * op_data3)948 static __u64 perf_ibs_get_op_data2(struct perf_ibs_data *ibs_data,
949 union ibs_op_data3 *op_data3)
950 {
951 __u64 val = ibs_data->regs[ibs_op_msr_idx(MSR_AMD64_IBSOPDATA2)];
952
953 /* Erratum #1293 */
954 if (boot_cpu_data.x86 == 0x19 && boot_cpu_data.x86_model <= 0xF &&
955 (op_data3->sw_pf || op_data3->dc_miss_no_mab_alloc)) {
956 /*
957 * OP_DATA2 has only two fields on Zen3: DataSrc and RmtNode.
958 * DataSrc=0 is 'No valid status' and RmtNode is invalid when
959 * DataSrc=0.
960 */
961 val = 0;
962 }
963 return val;
964 }
965
perf_ibs_parse_ld_st_data(__u64 sample_type,struct perf_ibs_data * ibs_data,struct perf_sample_data * data)966 static void perf_ibs_parse_ld_st_data(__u64 sample_type,
967 struct perf_ibs_data *ibs_data,
968 struct perf_sample_data *data)
969 {
970 union ibs_op_data3 op_data3;
971 union ibs_op_data2 op_data2;
972 union ibs_op_data op_data;
973
974 data->data_src.val = PERF_MEM_NA;
975 op_data3.val = ibs_data->regs[ibs_op_msr_idx(MSR_AMD64_IBSOPDATA3)];
976
977 perf_ibs_get_mem_op(&op_data3, data);
978 if (data->data_src.mem_op != PERF_MEM_OP_LOAD &&
979 data->data_src.mem_op != PERF_MEM_OP_STORE)
980 return;
981
982 op_data2.val = perf_ibs_get_op_data2(ibs_data, &op_data3);
983
984 if (sample_type & PERF_SAMPLE_DATA_SRC) {
985 perf_ibs_get_data_src(ibs_data, data, &op_data2, &op_data3);
986 data->sample_flags |= PERF_SAMPLE_DATA_SRC;
987 }
988
989 if (sample_type & PERF_SAMPLE_WEIGHT_TYPE && op_data3.dc_miss &&
990 data->data_src.mem_op == PERF_MEM_OP_LOAD) {
991 op_data.val = ibs_data->regs[ibs_op_msr_idx(MSR_AMD64_IBSOPDATA)];
992
993 if (sample_type & PERF_SAMPLE_WEIGHT_STRUCT) {
994 data->weight.var1_dw = op_data3.dc_miss_lat;
995 data->weight.var2_w = op_data.tag_to_ret_ctr;
996 } else if (sample_type & PERF_SAMPLE_WEIGHT) {
997 data->weight.full = op_data3.dc_miss_lat;
998 }
999 data->sample_flags |= PERF_SAMPLE_WEIGHT_TYPE;
1000 }
1001
1002 if (sample_type & PERF_SAMPLE_ADDR && op_data3.dc_lin_addr_valid) {
1003 data->addr = ibs_data->regs[ibs_op_msr_idx(MSR_AMD64_IBSDCLINAD)];
1004 data->sample_flags |= PERF_SAMPLE_ADDR;
1005 }
1006
1007 if (sample_type & PERF_SAMPLE_PHYS_ADDR && op_data3.dc_phy_addr_valid) {
1008 data->phys_addr = ibs_data->regs[ibs_op_msr_idx(MSR_AMD64_IBSDCPHYSAD)];
1009 data->sample_flags |= PERF_SAMPLE_PHYS_ADDR;
1010 }
1011 }
1012
perf_ibs_get_offset_max(struct perf_ibs * perf_ibs,u64 sample_type,int check_rip)1013 static int perf_ibs_get_offset_max(struct perf_ibs *perf_ibs, u64 sample_type,
1014 int check_rip)
1015 {
1016 if (sample_type & PERF_SAMPLE_RAW ||
1017 (perf_ibs == &perf_ibs_op &&
1018 (sample_type & PERF_SAMPLE_DATA_SRC ||
1019 sample_type & PERF_SAMPLE_WEIGHT_TYPE ||
1020 sample_type & PERF_SAMPLE_ADDR ||
1021 sample_type & PERF_SAMPLE_PHYS_ADDR)))
1022 return perf_ibs->offset_max;
1023 else if (check_rip)
1024 return 3;
1025 return 1;
1026 }
1027
perf_ibs_handle_irq(struct perf_ibs * perf_ibs,struct pt_regs * iregs)1028 static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs)
1029 {
1030 struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
1031 struct perf_event *event = pcpu->event;
1032 struct hw_perf_event *hwc;
1033 struct perf_sample_data data;
1034 struct perf_raw_record raw;
1035 struct pt_regs regs;
1036 struct perf_ibs_data ibs_data;
1037 int offset, size, check_rip, offset_max, throttle = 0;
1038 unsigned int msr;
1039 u64 *buf, *config, period, new_config = 0;
1040
1041 if (!test_bit(IBS_STARTED, pcpu->state)) {
1042 fail:
1043 /*
1044 * Catch spurious interrupts after stopping IBS: After
1045 * disabling IBS there could be still incoming NMIs
1046 * with samples that even have the valid bit cleared.
1047 * Mark all this NMIs as handled.
1048 */
1049 if (test_and_clear_bit(IBS_STOPPED, pcpu->state))
1050 return 1;
1051
1052 return 0;
1053 }
1054
1055 if (WARN_ON_ONCE(!event))
1056 goto fail;
1057
1058 hwc = &event->hw;
1059 msr = hwc->config_base;
1060 buf = ibs_data.regs;
1061 rdmsrl(msr, *buf);
1062 if (!(*buf++ & perf_ibs->valid_mask))
1063 goto fail;
1064
1065 config = &ibs_data.regs[0];
1066 perf_ibs_event_update(perf_ibs, event, config);
1067 perf_sample_data_init(&data, 0, hwc->last_period);
1068 if (!perf_ibs_set_period(perf_ibs, hwc, &period))
1069 goto out; /* no sw counter overflow */
1070
1071 ibs_data.caps = ibs_caps;
1072 size = 1;
1073 offset = 1;
1074 check_rip = (perf_ibs == &perf_ibs_op && (ibs_caps & IBS_CAPS_RIPINVALIDCHK));
1075
1076 offset_max = perf_ibs_get_offset_max(perf_ibs, event->attr.sample_type, check_rip);
1077
1078 do {
1079 rdmsrl(msr + offset, *buf++);
1080 size++;
1081 offset = find_next_bit(perf_ibs->offset_mask,
1082 perf_ibs->offset_max,
1083 offset + 1);
1084 } while (offset < offset_max);
1085 /*
1086 * Read IbsBrTarget, IbsOpData4, and IbsExtdCtl separately
1087 * depending on their availability.
1088 * Can't add to offset_max as they are staggered
1089 */
1090 if (event->attr.sample_type & PERF_SAMPLE_RAW) {
1091 if (perf_ibs == &perf_ibs_op) {
1092 if (ibs_caps & IBS_CAPS_BRNTRGT) {
1093 rdmsrl(MSR_AMD64_IBSBRTARGET, *buf++);
1094 size++;
1095 }
1096 if (ibs_caps & IBS_CAPS_OPDATA4) {
1097 rdmsrl(MSR_AMD64_IBSOPDATA4, *buf++);
1098 size++;
1099 }
1100 }
1101 if (perf_ibs == &perf_ibs_fetch && (ibs_caps & IBS_CAPS_FETCHCTLEXTD)) {
1102 rdmsrl(MSR_AMD64_ICIBSEXTDCTL, *buf++);
1103 size++;
1104 }
1105 }
1106 ibs_data.size = sizeof(u64) * size;
1107
1108 regs = *iregs;
1109 if (check_rip && (ibs_data.regs[2] & IBS_RIP_INVALID)) {
1110 regs.flags &= ~PERF_EFLAGS_EXACT;
1111 } else {
1112 /* Workaround for erratum #1197 */
1113 if (perf_ibs->fetch_ignore_if_zero_rip && !(ibs_data.regs[1]))
1114 goto out;
1115
1116 set_linear_ip(®s, ibs_data.regs[1]);
1117 regs.flags |= PERF_EFLAGS_EXACT;
1118 }
1119
1120 if (event->attr.sample_type & PERF_SAMPLE_RAW) {
1121 raw = (struct perf_raw_record){
1122 .frag = {
1123 .size = sizeof(u32) + ibs_data.size,
1124 .data = ibs_data.data,
1125 },
1126 };
1127 perf_sample_save_raw_data(&data, event, &raw);
1128 }
1129
1130 if (perf_ibs == &perf_ibs_op)
1131 perf_ibs_parse_ld_st_data(event->attr.sample_type, &ibs_data, &data);
1132
1133 /*
1134 * rip recorded by IbsOpRip will not be consistent with rsp and rbp
1135 * recorded as part of interrupt regs. Thus we need to use rip from
1136 * interrupt regs while unwinding call stack.
1137 */
1138 if (event->attr.sample_type & PERF_SAMPLE_CALLCHAIN)
1139 perf_sample_save_callchain(&data, event, iregs);
1140
1141 throttle = perf_event_overflow(event, &data, ®s);
1142 out:
1143 if (throttle) {
1144 perf_ibs_stop(event, 0);
1145 } else {
1146 if (perf_ibs == &perf_ibs_op) {
1147 if (ibs_caps & IBS_CAPS_OPCNTEXT) {
1148 new_config = period & IBS_OP_MAX_CNT_EXT_MASK;
1149 period &= ~IBS_OP_MAX_CNT_EXT_MASK;
1150 }
1151 if ((ibs_caps & IBS_CAPS_RDWROPCNT) && (*config & IBS_OP_CNT_CTL))
1152 new_config |= *config & IBS_OP_CUR_CNT_RAND;
1153 }
1154 new_config |= period >> 4;
1155
1156 perf_ibs_enable_event(perf_ibs, hwc, new_config);
1157 }
1158
1159 perf_event_update_userpage(event);
1160
1161 return 1;
1162 }
1163
1164 static int
perf_ibs_nmi_handler(unsigned int cmd,struct pt_regs * regs)1165 perf_ibs_nmi_handler(unsigned int cmd, struct pt_regs *regs)
1166 {
1167 u64 stamp = sched_clock();
1168 int handled = 0;
1169
1170 handled += perf_ibs_handle_irq(&perf_ibs_fetch, regs);
1171 handled += perf_ibs_handle_irq(&perf_ibs_op, regs);
1172
1173 if (handled)
1174 inc_irq_stat(apic_perf_irqs);
1175
1176 perf_sample_event_took(sched_clock() - stamp);
1177
1178 return handled;
1179 }
1180 NOKPROBE_SYMBOL(perf_ibs_nmi_handler);
1181
perf_ibs_pmu_init(struct perf_ibs * perf_ibs,char * name)1182 static __init int perf_ibs_pmu_init(struct perf_ibs *perf_ibs, char *name)
1183 {
1184 struct cpu_perf_ibs __percpu *pcpu;
1185 int ret;
1186
1187 pcpu = alloc_percpu(struct cpu_perf_ibs);
1188 if (!pcpu)
1189 return -ENOMEM;
1190
1191 perf_ibs->pcpu = pcpu;
1192
1193 ret = perf_pmu_register(&perf_ibs->pmu, name, -1);
1194 if (ret) {
1195 perf_ibs->pcpu = NULL;
1196 free_percpu(pcpu);
1197 }
1198
1199 return ret;
1200 }
1201
perf_ibs_fetch_init(void)1202 static __init int perf_ibs_fetch_init(void)
1203 {
1204 /*
1205 * Some chips fail to reset the fetch count when it is written; instead
1206 * they need a 0-1 transition of IbsFetchEn.
1207 */
1208 if (boot_cpu_data.x86 >= 0x16 && boot_cpu_data.x86 <= 0x18)
1209 perf_ibs_fetch.fetch_count_reset_broken = 1;
1210
1211 if (boot_cpu_data.x86 == 0x19 && boot_cpu_data.x86_model < 0x10)
1212 perf_ibs_fetch.fetch_ignore_if_zero_rip = 1;
1213
1214 if (ibs_caps & IBS_CAPS_ZEN4)
1215 perf_ibs_fetch.config_mask |= IBS_FETCH_L3MISSONLY;
1216
1217 perf_ibs_fetch.pmu.attr_groups = fetch_attr_groups;
1218 perf_ibs_fetch.pmu.attr_update = fetch_attr_update;
1219
1220 return perf_ibs_pmu_init(&perf_ibs_fetch, "ibs_fetch");
1221 }
1222
perf_ibs_op_init(void)1223 static __init int perf_ibs_op_init(void)
1224 {
1225 if (ibs_caps & IBS_CAPS_OPCNT)
1226 perf_ibs_op.config_mask |= IBS_OP_CNT_CTL;
1227
1228 if (ibs_caps & IBS_CAPS_OPCNTEXT) {
1229 perf_ibs_op.max_period |= IBS_OP_MAX_CNT_EXT_MASK;
1230 perf_ibs_op.config_mask |= IBS_OP_MAX_CNT_EXT_MASK;
1231 perf_ibs_op.cnt_mask |= (IBS_OP_MAX_CNT_EXT_MASK |
1232 IBS_OP_CUR_CNT_EXT_MASK);
1233 }
1234
1235 if (ibs_caps & IBS_CAPS_ZEN4)
1236 perf_ibs_op.config_mask |= IBS_OP_L3MISSONLY;
1237
1238 perf_ibs_op.pmu.attr_groups = empty_attr_groups;
1239 perf_ibs_op.pmu.attr_update = op_attr_update;
1240
1241 return perf_ibs_pmu_init(&perf_ibs_op, "ibs_op");
1242 }
1243
perf_event_ibs_init(void)1244 static __init int perf_event_ibs_init(void)
1245 {
1246 int ret;
1247
1248 ret = perf_ibs_fetch_init();
1249 if (ret)
1250 return ret;
1251
1252 ret = perf_ibs_op_init();
1253 if (ret)
1254 goto err_op;
1255
1256 ret = register_nmi_handler(NMI_LOCAL, perf_ibs_nmi_handler, 0, "perf_ibs");
1257 if (ret)
1258 goto err_nmi;
1259
1260 pr_info("perf: AMD IBS detected (0x%08x)\n", ibs_caps);
1261 return 0;
1262
1263 err_nmi:
1264 perf_pmu_unregister(&perf_ibs_op.pmu);
1265 free_percpu(perf_ibs_op.pcpu);
1266 perf_ibs_op.pcpu = NULL;
1267 err_op:
1268 perf_pmu_unregister(&perf_ibs_fetch.pmu);
1269 free_percpu(perf_ibs_fetch.pcpu);
1270 perf_ibs_fetch.pcpu = NULL;
1271
1272 return ret;
1273 }
1274
1275 #else /* defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD) */
1276
perf_event_ibs_init(void)1277 static __init int perf_event_ibs_init(void)
1278 {
1279 return 0;
1280 }
1281
1282 #endif
1283
1284 /* IBS - apic initialization, for perf and oprofile */
1285
__get_ibs_caps(void)1286 static __init u32 __get_ibs_caps(void)
1287 {
1288 u32 caps;
1289 unsigned int max_level;
1290
1291 if (!boot_cpu_has(X86_FEATURE_IBS))
1292 return 0;
1293
1294 /* check IBS cpuid feature flags */
1295 max_level = cpuid_eax(0x80000000);
1296 if (max_level < IBS_CPUID_FEATURES)
1297 return IBS_CAPS_DEFAULT;
1298
1299 caps = cpuid_eax(IBS_CPUID_FEATURES);
1300 if (!(caps & IBS_CAPS_AVAIL))
1301 /* cpuid flags not valid */
1302 return IBS_CAPS_DEFAULT;
1303
1304 return caps;
1305 }
1306
get_ibs_caps(void)1307 u32 get_ibs_caps(void)
1308 {
1309 return ibs_caps;
1310 }
1311
1312 EXPORT_SYMBOL(get_ibs_caps);
1313
get_eilvt(int offset)1314 static inline int get_eilvt(int offset)
1315 {
1316 return !setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 1);
1317 }
1318
put_eilvt(int offset)1319 static inline int put_eilvt(int offset)
1320 {
1321 return !setup_APIC_eilvt(offset, 0, 0, 1);
1322 }
1323
1324 /*
1325 * Check and reserve APIC extended interrupt LVT offset for IBS if available.
1326 */
ibs_eilvt_valid(void)1327 static inline int ibs_eilvt_valid(void)
1328 {
1329 int offset;
1330 u64 val;
1331 int valid = 0;
1332
1333 preempt_disable();
1334
1335 rdmsrl(MSR_AMD64_IBSCTL, val);
1336 offset = val & IBSCTL_LVT_OFFSET_MASK;
1337
1338 if (!(val & IBSCTL_LVT_OFFSET_VALID)) {
1339 pr_err(FW_BUG "cpu %d, invalid IBS interrupt offset %d (MSR%08X=0x%016llx)\n",
1340 smp_processor_id(), offset, MSR_AMD64_IBSCTL, val);
1341 goto out;
1342 }
1343
1344 if (!get_eilvt(offset)) {
1345 pr_err(FW_BUG "cpu %d, IBS interrupt offset %d not available (MSR%08X=0x%016llx)\n",
1346 smp_processor_id(), offset, MSR_AMD64_IBSCTL, val);
1347 goto out;
1348 }
1349
1350 valid = 1;
1351 out:
1352 preempt_enable();
1353
1354 return valid;
1355 }
1356
setup_ibs_ctl(int ibs_eilvt_off)1357 static int setup_ibs_ctl(int ibs_eilvt_off)
1358 {
1359 struct pci_dev *cpu_cfg;
1360 int nodes;
1361 u32 value = 0;
1362
1363 nodes = 0;
1364 cpu_cfg = NULL;
1365 do {
1366 cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
1367 PCI_DEVICE_ID_AMD_10H_NB_MISC,
1368 cpu_cfg);
1369 if (!cpu_cfg)
1370 break;
1371 ++nodes;
1372 pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
1373 | IBSCTL_LVT_OFFSET_VALID);
1374 pci_read_config_dword(cpu_cfg, IBSCTL, &value);
1375 if (value != (ibs_eilvt_off | IBSCTL_LVT_OFFSET_VALID)) {
1376 pci_dev_put(cpu_cfg);
1377 pr_debug("Failed to setup IBS LVT offset, IBSCTL = 0x%08x\n",
1378 value);
1379 return -EINVAL;
1380 }
1381 } while (1);
1382
1383 if (!nodes) {
1384 pr_debug("No CPU node configured for IBS\n");
1385 return -ENODEV;
1386 }
1387
1388 return 0;
1389 }
1390
1391 /*
1392 * This runs only on the current cpu. We try to find an LVT offset and
1393 * setup the local APIC. For this we must disable preemption. On
1394 * success we initialize all nodes with this offset. This updates then
1395 * the offset in the IBS_CTL per-node msr. The per-core APIC setup of
1396 * the IBS interrupt vector is handled by perf_ibs_cpu_notifier that
1397 * is using the new offset.
1398 */
force_ibs_eilvt_setup(void)1399 static void force_ibs_eilvt_setup(void)
1400 {
1401 int offset;
1402 int ret;
1403
1404 preempt_disable();
1405 /* find the next free available EILVT entry, skip offset 0 */
1406 for (offset = 1; offset < APIC_EILVT_NR_MAX; offset++) {
1407 if (get_eilvt(offset))
1408 break;
1409 }
1410 preempt_enable();
1411
1412 if (offset == APIC_EILVT_NR_MAX) {
1413 pr_debug("No EILVT entry available\n");
1414 return;
1415 }
1416
1417 ret = setup_ibs_ctl(offset);
1418 if (ret)
1419 goto out;
1420
1421 if (!ibs_eilvt_valid())
1422 goto out;
1423
1424 pr_info("LVT offset %d assigned\n", offset);
1425
1426 return;
1427 out:
1428 preempt_disable();
1429 put_eilvt(offset);
1430 preempt_enable();
1431 return;
1432 }
1433
ibs_eilvt_setup(void)1434 static void ibs_eilvt_setup(void)
1435 {
1436 /*
1437 * Force LVT offset assignment for family 10h: The offsets are
1438 * not assigned by the BIOS for this family, so the OS is
1439 * responsible for doing it. If the OS assignment fails, fall
1440 * back to BIOS settings and try to setup this.
1441 */
1442 if (boot_cpu_data.x86 == 0x10)
1443 force_ibs_eilvt_setup();
1444 }
1445
get_ibs_lvt_offset(void)1446 static inline int get_ibs_lvt_offset(void)
1447 {
1448 u64 val;
1449
1450 rdmsrl(MSR_AMD64_IBSCTL, val);
1451 if (!(val & IBSCTL_LVT_OFFSET_VALID))
1452 return -EINVAL;
1453
1454 return val & IBSCTL_LVT_OFFSET_MASK;
1455 }
1456
setup_APIC_ibs(void)1457 static void setup_APIC_ibs(void)
1458 {
1459 int offset;
1460
1461 offset = get_ibs_lvt_offset();
1462 if (offset < 0)
1463 goto failed;
1464
1465 if (!setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 0))
1466 return;
1467 failed:
1468 pr_warn("perf: IBS APIC setup failed on cpu #%d\n",
1469 smp_processor_id());
1470 }
1471
clear_APIC_ibs(void)1472 static void clear_APIC_ibs(void)
1473 {
1474 int offset;
1475
1476 offset = get_ibs_lvt_offset();
1477 if (offset >= 0)
1478 setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_FIX, 1);
1479 }
1480
x86_pmu_amd_ibs_starting_cpu(unsigned int cpu)1481 static int x86_pmu_amd_ibs_starting_cpu(unsigned int cpu)
1482 {
1483 setup_APIC_ibs();
1484 return 0;
1485 }
1486
1487 #ifdef CONFIG_PM
1488
perf_ibs_suspend(void)1489 static int perf_ibs_suspend(void)
1490 {
1491 clear_APIC_ibs();
1492 return 0;
1493 }
1494
perf_ibs_resume(void)1495 static void perf_ibs_resume(void)
1496 {
1497 ibs_eilvt_setup();
1498 setup_APIC_ibs();
1499 }
1500
1501 static struct syscore_ops perf_ibs_syscore_ops = {
1502 .resume = perf_ibs_resume,
1503 .suspend = perf_ibs_suspend,
1504 };
1505
perf_ibs_pm_init(void)1506 static void perf_ibs_pm_init(void)
1507 {
1508 register_syscore_ops(&perf_ibs_syscore_ops);
1509 }
1510
1511 #else
1512
perf_ibs_pm_init(void)1513 static inline void perf_ibs_pm_init(void) { }
1514
1515 #endif
1516
x86_pmu_amd_ibs_dying_cpu(unsigned int cpu)1517 static int x86_pmu_amd_ibs_dying_cpu(unsigned int cpu)
1518 {
1519 clear_APIC_ibs();
1520 return 0;
1521 }
1522
amd_ibs_init(void)1523 static __init int amd_ibs_init(void)
1524 {
1525 u32 caps;
1526
1527 caps = __get_ibs_caps();
1528 if (!caps)
1529 return -ENODEV; /* ibs not supported by the cpu */
1530
1531 ibs_eilvt_setup();
1532
1533 if (!ibs_eilvt_valid())
1534 return -EINVAL;
1535
1536 perf_ibs_pm_init();
1537
1538 ibs_caps = caps;
1539 /* make ibs_caps visible to other cpus: */
1540 smp_mb();
1541 /*
1542 * x86_pmu_amd_ibs_starting_cpu will be called from core on
1543 * all online cpus.
1544 */
1545 cpuhp_setup_state(CPUHP_AP_PERF_X86_AMD_IBS_STARTING,
1546 "perf/x86/amd/ibs:starting",
1547 x86_pmu_amd_ibs_starting_cpu,
1548 x86_pmu_amd_ibs_dying_cpu);
1549
1550 return perf_event_ibs_init();
1551 }
1552
1553 /* Since we need the pci subsystem to init ibs we can't do this earlier: */
1554 device_initcall(amd_ibs_init);
1555