xref: /openbmc/u-boot/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h (revision 719afeb0b3c60af82f701f122978b935aa6a5217)
1  /* SPDX-License-Identifier: GPL-2.0 */
2  /*
3   * Copyright (C) 2016-2017 Intel Corporation
4   */
5  
6  #ifndef _RESET_MANAGER_ARRIA10_H_
7  #define _RESET_MANAGER_ARRIA10_H_
8  
9  #include <dt-bindings/reset/altr,rst-mgr-a10.h>
10  
11  void socfpga_watchdog_disable(void);
12  void socfpga_reset_deassert_noc_ddr_scheduler(void);
13  int socfpga_reset_deassert_bridges_handoff(void);
14  void socfpga_reset_deassert_osc1wd0(void);
15  int socfpga_bridges_reset(void);
16  
17  struct socfpga_reset_manager {
18  	u32	stat;
19  	u32	ramstat;
20  	u32	miscstat;
21  	u32	ctrl;
22  	u32	hdsken;
23  	u32	hdskreq;
24  	u32	hdskack;
25  	u32	counts;
26  	u32	mpumodrst;
27  	u32	per0modrst;
28  	u32	per1modrst;
29  	u32	brgmodrst;
30  	u32	sysmodrst;
31  	u32	coldmodrst;
32  	u32	nrstmodrst;
33  	u32	dbgmodrst;
34  	u32	mpuwarmmask;
35  	u32	per0warmmask;
36  	u32	per1warmmask;
37  	u32	brgwarmmask;
38  	u32	syswarmmask;
39  	u32	nrstwarmmask;
40  	u32	l3warmmask;
41  	u32	tststa;
42  	u32	tstscratch;
43  	u32	hdsktimeout;
44  	u32	hmcintr;
45  	u32	hmcintren;
46  	u32	hmcintrens;
47  	u32	hmcintrenr;
48  	u32	hmcgpout;
49  	u32	hmcgpin;
50  };
51  
52  /*
53   * SocFPGA Arria10 reset IDs, bank mapping is as follows:
54   * 0 ... mpumodrst
55   * 1 ... per0modrst
56   * 2 ... per1modrst
57   * 3 ... brgmodrst
58   * 4 ... sysmodrst
59   */
60  #define RSTMGR_EMAC0		RSTMGR_DEFINE(1, 0)
61  #define RSTMGR_EMAC1		RSTMGR_DEFINE(1, 1)
62  #define RSTMGR_EMAC2		RSTMGR_DEFINE(1, 2)
63  #define RSTMGR_NAND		RSTMGR_DEFINE(1, 5)
64  #define RSTMGR_QSPI		RSTMGR_DEFINE(1, 6)
65  #define RSTMGR_SDMMC		RSTMGR_DEFINE(1, 7)
66  #define RSTMGR_DMA		RSTMGR_DEFINE(1, 16)
67  #define RSTMGR_SPIM0		RSTMGR_DEFINE(1, 17)
68  #define RSTMGR_SPIM1		RSTMGR_DEFINE(1, 18)
69  #define RSTMGR_L4WD0		RSTMGR_DEFINE(2, 0)
70  #define RSTMGR_L4WD1		RSTMGR_DEFINE(2, 1)
71  #define RSTMGR_L4SYSTIMER0	RSTMGR_DEFINE(2, 2)
72  #define RSTMGR_L4SYSTIMER1	RSTMGR_DEFINE(2, 3)
73  #define RSTMGR_SPTIMER0		RSTMGR_DEFINE(2, 4)
74  #define RSTMGR_SPTIMER1		RSTMGR_DEFINE(2, 5)
75  #define RSTMGR_UART0		RSTMGR_DEFINE(2, 16)
76  #define RSTMGR_UART1		RSTMGR_DEFINE(2, 17)
77  #define RSTMGR_DDRSCH		RSTMGR_DEFINE(3, 6)
78  
79  #define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET_MSK	BIT(1)
80  #define ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK	BIT(0)
81  #define ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSK	BIT(1)
82  #define ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSK	BIT(2)
83  #define ALT_RSTMGR_PER0MODRST_USB0_SET_MSK	BIT(3)
84  #define ALT_RSTMGR_PER0MODRST_USB1_SET_MSK	BIT(4)
85  #define ALT_RSTMGR_PER0MODRST_NAND_SET_MSK	BIT(5)
86  #define ALT_RSTMGR_PER0MODRST_QSPI_SET_MSK	BIT(6)
87  #define ALT_RSTMGR_PER0MODRST_SDMMC_SET_MSK	BIT(7)
88  #define ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK	BIT(8)
89  #define ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK	BIT(9)
90  #define ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK	BIT(10)
91  #define ALT_RSTMGR_PER0MODRST_USBECC0_SET_MSK	BIT(11)
92  #define ALT_RSTMGR_PER0MODRST_USBECC1_SET_MSK	BIT(12)
93  #define ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK	BIT(13)
94  #define ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK	BIT(14)
95  #define ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK	BIT(15)
96  #define ALT_RSTMGR_PER0MODRST_DMA_SET_MSK	BIT(16)
97  #define ALT_RSTMGR_PER0MODRST_SPIM0_SET_MSK	BIT(17)
98  #define ALT_RSTMGR_PER0MODRST_SPIM1_SET_MSK	BIT(18)
99  #define ALT_RSTMGR_PER0MODRST_SPIS0_SET_MSK	BIT(19)
100  #define ALT_RSTMGR_PER0MODRST_SPIS1_SET_MSK	BIT(20)
101  #define ALT_RSTMGR_PER0MODRST_DMAECC_SET_MSK	BIT(21)
102  #define ALT_RSTMGR_PER0MODRST_EMACPTP_SET_MSK	BIT(22)
103  #define ALT_RSTMGR_PER0MODRST_DMAIF0_SET_MSK	BIT(24)
104  #define ALT_RSTMGR_PER0MODRST_DMAIF1_SET_MSK	BIT(25)
105  #define ALT_RSTMGR_PER0MODRST_DMAIF2_SET_MSK	BIT(26)
106  #define ALT_RSTMGR_PER0MODRST_DMAIF3_SET_MSK	BIT(27)
107  #define ALT_RSTMGR_PER0MODRST_DMAIF4_SET_MSK	BIT(28)
108  #define ALT_RSTMGR_PER0MODRST_DMAIF5_SET_MSK	BIT(29)
109  #define ALT_RSTMGR_PER0MODRST_DMAIF6_SET_MSK	BIT(30)
110  #define ALT_RSTMGR_PER0MODRST_DMAIF7_SET_MSK	BIT(31)
111  
112  #define ALT_RSTMGR_PER1MODRST_WD0_SET_MSK	BIT(0)
113  #define ALT_RSTMGR_PER1MODRST_WD1_SET_MSK	BIT(1)
114  #define ALT_RSTMGR_PER1MODRST_L4SYSTMR0_SET_MSK	BIT(2)
115  #define ALT_RSTMGR_PER1MODRST_L4SYSTMR1_SET_MSK	BIT(3)
116  #define ALT_RSTMGR_PER1MODRST_SPTMR0_SET_MSK	BIT(4)
117  #define ALT_RSTMGR_PER1MODRST_SPTMR1_SET_MSK	BIT(5)
118  #define ALT_RSTMGR_PER1MODRST_I2C0_SET_MSK	BIT(8)
119  #define ALT_RSTMGR_PER1MODRST_I2C1_SET_MSK	BIT(9)
120  #define ALT_RSTMGR_PER1MODRST_I2C2_SET_MSK	BIT(10)
121  #define ALT_RSTMGR_PER1MODRST_I2C3_SET_MSK	BIT(11)
122  #define ALT_RSTMGR_PER1MODRST_I2C4_SET_MSK	BIT(12)
123  #define ALT_RSTMGR_PER1MODRST_UART0_SET_MSK	BIT(16)
124  #define ALT_RSTMGR_PER1MODRST_UART1_SET_MSK	BIT(17)
125  #define ALT_RSTMGR_PER1MODRST_GPIO0_SET_MSK	BIT(24)
126  #define ALT_RSTMGR_PER1MODRST_GPIO1_SET_MSK	BIT(25)
127  #define ALT_RSTMGR_PER1MODRST_GPIO2_SET_MSK	BIT(26)
128  
129  #define ALT_RSTMGR_BRGMODRST_H2F_SET_MSK	BIT(0)
130  #define ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK	BIT(1)
131  #define ALT_RSTMGR_BRGMODRST_F2H_SET_MSK	BIT(2)
132  #define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK	BIT(3)
133  #define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK	BIT(4)
134  #define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK	BIT(5)
135  #define ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK	BIT(6)
136  
137  #define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_SET_MSK	BIT(0)
138  #define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_SET_MSK	BIT(1)
139  #define ALT_RSTMGR_HDSKEN_FPGAHSEN_SET_MSK	BIT(2)
140  #define ALT_RSTMGR_HDSKEN_ETRSTALLEN_SET_MSK	BIT(3)
141  
142  #endif /* _RESET_MANAGER_ARRIA10_H_ */
143