1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * logicore_dp_tx.c
4 *
5 * Driver for XILINX LogiCore DisplayPort v6.1 TX (Source)
6 * based on Xilinx dp_v3_1 driver sources, updated to dp_v4_0
7 *
8 * (C) Copyright 2016
9 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
10 */
11
12 #include <common.h>
13 #include <clk.h>
14 #include <display.h>
15 #include <dm.h>
16 #include <errno.h>
17
18 #include "axi.h"
19 #include "logicore_dp_dpcd.h"
20 #include "logicore_dp_tx.h"
21 #include "logicore_dp_tx_regif.h"
22
23 /* Default AXI clock frequency value */
24 #define S_AXI_CLK_DEFAULT 100000000
25
26 /* Default DP phy clock value */
27 #define PHY_CLOCK_SELECT_DEFAULT PHY_CLOCK_SELECT_540GBPS
28
29 /* The maximum voltage swing level is 3 */
30 #define MAXIMUM_VS_LEVEL 3
31 /* The maximum pre-emphasis level is 3 */
32 #define MAXIMUM_PE_LEVEL 3
33
34 /* Error out if an AUX request yields a defer reply more than 50 times */
35 #define AUX_MAX_DEFER_COUNT 50
36 /* Error out if an AUX request times out more than 50 times awaiting a reply */
37 #define AUX_MAX_TIMEOUT_COUNT 50
38 /* Error out if checking for a connected device times out more than 50 times */
39 #define IS_CONNECTED_MAX_TIMEOUT_COUNT 50
40
41 /**
42 * enum link_training_states - States for link training state machine
43 * @TS_CLOCK_RECOVERY: State for clock recovery
44 * @TS_CHANNEL_EQUALIZATION: State for channel equalization
45 * @TS_ADJUST_LINK_RATE: State where link rate is reduced in reaction to
46 * failed link training
47 * @TS_ADJUST_LANE_COUNT: State where lane count is reduced in reaction to
48 * failed link training
49 * @TS_FAILURE: State of link training failure
50 * @TS_SUCCESS:: State for successfully completed link training
51 */
52 enum link_training_states {
53 TS_CLOCK_RECOVERY,
54 TS_CHANNEL_EQUALIZATION,
55 TS_ADJUST_LINK_RATE,
56 TS_ADJUST_LANE_COUNT,
57 TS_FAILURE,
58 TS_SUCCESS
59 };
60
61 /**
62 * struct aux_transaction - Description of an AUX channel transaction
63 * @cmd_code: Command code of the transaction
64 * @num_bytes: The number of bytes in the transaction's payload data
65 * @address: The DPCD address of the transaction
66 * @data: Payload data of the AUX channel transaction
67 */
68 struct aux_transaction {
69 u16 cmd_code;
70 u8 num_bytes;
71 u32 address;
72 u8 *data;
73 };
74
75 /**
76 * struct main_stream_attributes - Main stream attributes
77 * @pixel_clock_hz: Pixel clock of the stream (in Hz)
78 * @misc_0: Miscellaneous stream attributes 0 as specified
79 * by the DisplayPort 1.2 specification
80 * @misc_1: Miscellaneous stream attributes 1 as specified
81 * by the DisplayPort 1.2 specification
82 * @n_vid: N value for the video stream
83 * @m_vid: M value used to recover the video clock from the
84 * link clock
85 * @user_pixel_width: Width of the user data input port
86 * @data_per_lane: Used to translate the number of pixels per line
87 * to the native internal 16-bit datapath
88 * @avg_bytes_per_tu: Average number of bytes per transfer unit,
89 * scaled up by a factor of 1000
90 * @transfer_unit_size: Size of the transfer unit in the framing logic
91 * In MST mode, this is also the number of time
92 * slots that are alloted in the payload ID table
93 * @init_wait: Number of initial wait cycles at the start of a
94 * new line by the framing logic
95 * @bits_per_color: Bits per color component
96 * @component_format: The component format currently in use by the
97 * video stream
98 * @dynamic_range: The dynamic range currently in use by the video
99 * stream
100 * @y_cb_cr_colorimetry: The YCbCr colorimetry currently in use by the
101 * video stream
102 * @synchronous_clock_mode: Synchronous clock mode is currently in use by
103 * the video stream
104 * @override_user_pixel_width: If set to 1, the value stored for
105 * user_pixel_width will be used as the pixel width
106 * @h_start: Horizontal blank start (pixels)
107 * @h_active: Horizontal active resolution (pixels)
108 * @h_sync_width: Horizontal sync width (pixels)
109 * @h_total: Horizontal total (pixels)
110 * @h_sync_polarity: Horizontal sync polarity (0=neg|1=pos)
111 * @v_start: Vertical blank start (in lines)
112 * @v_active: Vertical active resolution (lines)
113 * @v_sync_width: Vertical sync width (lines)
114 * @v_total: Vertical total (lines)
115 * @v_sync_polarity: Vertical sync polarity (0=neg|1=pos)
116 *
117 * All porch parameters have been removed, because our videodata is
118 * hstart/vstart based, and there is no benefit in keeping the porches
119 */
120 struct main_stream_attributes {
121 u32 pixel_clock_hz;
122 u32 misc_0;
123 u32 misc_1;
124 u32 n_vid;
125 //u32 m_vid;
126 u32 user_pixel_width;
127 u32 data_per_lane;
128 u32 avg_bytes_per_tu;
129 u32 transfer_unit_size;
130 u32 init_wait;
131 u32 bits_per_color;
132 u8 component_format;
133 u8 dynamic_range;
134 u8 y_cb_cr_colorimetry;
135 u8 synchronous_clock_mode;
136 u8 override_user_pixel_width;
137 u32 h_start;
138 u16 h_active;
139 u16 h_sync_width;
140 u16 h_total;
141 bool h_sync_polarity;
142 u32 v_start;
143 u16 v_active;
144 u16 v_sync_width;
145 u16 v_total;
146 bool v_sync_polarity;
147 };
148
149 /**
150 * struct link_config - Description of link configuration
151 * @lane_count: Currently selected lane count for this link
152 * @link_rate: Currently selected link rate for this link
153 * @scrambler_en: Flag to determine whether the scrambler is
154 * enabled for this link
155 * @enhanced_framing_mode: Flag to determine whether enhanced framing
156 * mode is active for this link
157 * @max_lane_count: Maximum lane count for this link
158 * @max_link_rate: Maximum link rate for this link
159 * @support_enhanced_framing_mode: Flag to indicate whether the link supports
160 * enhanced framing mode
161 * @vs_level: Voltage swing for each lane
162 * @pe_level: Pre-emphasis/cursor level for each lane
163 */
164 struct link_config {
165 u8 lane_count;
166 u8 link_rate;
167 bool scrambler_en;
168 bool enhanced_framing_mode;
169 u8 max_lane_count;
170 u8 max_link_rate;
171 bool support_enhanced_framing_mode;
172 u8 vs_level;
173 u8 pe_level;
174 };
175
176 /**
177 * struct dp_tx - Private data structure of LogiCore DP TX devices
178 *
179 * @base: Address of register base of device
180 * @s_axi_clk: The AXI clock frequency in Hz
181 * @train_adaptive: Use adaptive link trainig (i.e. successively reduce
182 * link rate and/or lane count) for this device
183 * @max_link_rate: Maximum link rate for this device
184 * @max_lane_count: Maximum lane count for this device
185 * @dpcd_rx_caps: RX device's status registers, see below
186 * @lane_status_ajd_reqs: Lane status and adjustment requests information for
187 * this device
188 * @link_config: The link configuration for this device
189 * @main_stream_attributes: MSA set for this device
190 *
191 * dpcd_rx_caps is a raw read of the RX device's status registers. The first 4
192 * bytes correspond to the lane status associated with clock recovery, channel
193 * equalization, symbol lock, and interlane alignment. The remaining 2 bytes
194 * represent the pre-emphasis and voltage swing level adjustments requested by
195 * the RX device.
196 */
197 struct dp_tx {
198 u32 base;
199 u32 s_axi_clk;
200 bool train_adaptive;
201 u8 max_link_rate;
202 u8 max_lane_count;
203 u8 dpcd_rx_caps[16];
204 u8 lane_status_ajd_reqs[6];
205 struct link_config link_config;
206 struct main_stream_attributes main_stream_attributes;
207 };
208
209 /*
210 * Internal API
211 */
212
213 /**
214 * get_reg() - Read a register of a LogiCore DP TX device
215 * @dev: The LogiCore DP TX device in question
216 * @reg: The offset of the register to read
217 *
218 * Return: The read register value
219 */
get_reg(struct udevice * dev,u32 reg)220 static u32 get_reg(struct udevice *dev, u32 reg)
221 {
222 struct dp_tx *dp_tx = dev_get_priv(dev);
223 u32 value = 0;
224 int res;
225
226 /* TODO(mario.six@gdsys.cc): error handling */
227 res = axi_read(dev->parent, dp_tx->base + reg, &value, AXI_SIZE_32);
228 if (res < 0)
229 printf("%s() failed; res = %d\n", __func__, res);
230
231 return value;
232 }
233
234 /**
235 * set_reg() - Write a register of a LogiCore DP TX device
236 * @dev: The LogiCore DP TX device in question
237 * @reg: The offset of the register to write
238 * @value: The value to write to the register
239 */
set_reg(struct udevice * dev,u32 reg,u32 value)240 static void set_reg(struct udevice *dev, u32 reg, u32 value)
241 {
242 struct dp_tx *dp_tx = dev_get_priv(dev);
243
244 axi_write(dev->parent, dp_tx->base + reg, &value, AXI_SIZE_32);
245 }
246
247 /**
248 * is_connected() - Check if there is a connected RX device
249 * @dev: The LogiCore DP TX device in question
250 *
251 * The Xilinx original calls msleep_interruptible at least once, ignoring
252 * status.
253 *
254 * Return: true if a connected RX device was detected, false otherwise
255 */
is_connected(struct udevice * dev)256 static bool is_connected(struct udevice *dev)
257 {
258 u8 retries = 0;
259
260 do {
261 int status = get_reg(dev, REG_INTERRUPT_SIG_STATE) &
262 INTERRUPT_SIG_STATE_HPD_STATE_MASK;
263 if (status)
264 return true;
265
266 udelay(1000);
267 } while (retries++ < IS_CONNECTED_MAX_TIMEOUT_COUNT);
268
269 return false;
270 }
271
272 /**
273 * wait_phy_ready() - Wait for the DisplayPort PHY to come out of reset
274 * @dev: The LogiCore DP TX device in question
275 * @mask: Bit mask specifying which bit in the status register should be waited
276 * for
277 *
278 * Return: 0 if wait succeeded, -ve if error occurred
279 */
wait_phy_ready(struct udevice * dev,u32 mask)280 static int wait_phy_ready(struct udevice *dev, u32 mask)
281 {
282 u16 timeout = 20000;
283 u32 phy_status;
284
285 /* Wait until the PHY is ready. */
286 do {
287 phy_status = get_reg(dev, REG_PHY_STATUS) & mask;
288
289 /* Protect against an infinite loop. */
290 if (!timeout--)
291 return -ETIMEDOUT;
292
293 udelay(20);
294 } while (phy_status != mask);
295
296 return 0;
297 }
298
299 /* AUX channel access */
300
301 /**
302 * aux_wait_ready() - Wait until another request is no longer in progress
303 * @dev: The LogiCore DP TX device in question
304 *
305 * Return: 0 if wait succeeded, -ve if error occurred
306 */
aux_wait_ready(struct udevice * dev)307 static int aux_wait_ready(struct udevice *dev)
308 {
309 int status;
310 u32 timeout = 100;
311
312 /* Wait until the DisplayPort TX core is ready. */
313 do {
314 status = get_reg(dev, REG_INTERRUPT_SIG_STATE);
315
316 /* Protect against an infinite loop. */
317 if (!timeout--)
318 return -ETIMEDOUT;
319 udelay(20);
320 } while (status & REPLY_STATUS_REPLY_IN_PROGRESS_MASK);
321
322 return 0;
323 }
324
325 /**
326 * aux_wait_reply() - Wait for reply on AUX channel
327 * @dev: The LogiCore DP TX device in question
328 *
329 * Wait for a reply indicating that the most recent AUX request
330 * has been received by the RX device.
331 *
332 * Return: 0 if wait succeeded, -ve if error occurred
333 */
aux_wait_reply(struct udevice * dev)334 static int aux_wait_reply(struct udevice *dev)
335 {
336 u32 timeout = 100;
337
338 while (timeout > 0) {
339 int status = get_reg(dev, REG_REPLY_STATUS);
340
341 /* Check for error. */
342 if (status & REPLY_STATUS_REPLY_ERROR_MASK)
343 return -ETIMEDOUT;
344
345 /* Check for a reply. */
346 if ((status & REPLY_STATUS_REPLY_RECEIVED_MASK) &&
347 !(status &
348 REPLY_STATUS_REQUEST_IN_PROGRESS_MASK) &&
349 !(status &
350 REPLY_STATUS_REPLY_IN_PROGRESS_MASK)) {
351 return 0;
352 }
353
354 timeout--;
355 udelay(20);
356 }
357
358 return -ETIMEDOUT;
359 }
360
361 /**
362 * aux_request_send() - Send request on the AUX channel
363 * @dev: The LogiCore DP TX device in question
364 * @request: The request to send
365 *
366 * Submit the supplied AUX request to the RX device over the AUX
367 * channel by writing the command, the destination address, (the write buffer
368 * for write commands), and the data size to the DisplayPort TX core.
369 *
370 * This is the lower-level sending routine, which is called by aux_request().
371 *
372 * Return: 0 if request was sent successfully, -ve on error
373 */
aux_request_send(struct udevice * dev,struct aux_transaction * request)374 static int aux_request_send(struct udevice *dev,
375 struct aux_transaction *request)
376 {
377 u32 timeout_count;
378 int status;
379 u8 index;
380
381 /* Ensure that any pending AUX transactions have completed. */
382 timeout_count = 0;
383 do {
384 status = get_reg(dev, REG_REPLY_STATUS);
385
386 udelay(20);
387 timeout_count++;
388 if (timeout_count >= AUX_MAX_TIMEOUT_COUNT)
389 return -ETIMEDOUT;
390 } while ((status & REPLY_STATUS_REQUEST_IN_PROGRESS_MASK) ||
391 (status & REPLY_STATUS_REPLY_IN_PROGRESS_MASK));
392
393 set_reg(dev, REG_AUX_ADDRESS, request->address);
394
395 if (request->cmd_code == AUX_CMD_WRITE ||
396 request->cmd_code == AUX_CMD_I2C_WRITE ||
397 request->cmd_code == AUX_CMD_I2C_WRITE_MOT) {
398 /* Feed write data into the DisplayPort TX core's write FIFO. */
399 for (index = 0; index < request->num_bytes; index++) {
400 set_reg(dev,
401 REG_AUX_WRITE_FIFO, request->data[index]);
402 }
403 }
404
405 /* Submit the command and the data size. */
406 set_reg(dev, REG_AUX_CMD,
407 ((request->cmd_code << AUX_CMD_SHIFT) |
408 ((request->num_bytes - 1) &
409 AUX_CMD_NBYTES_TRANSFER_MASK)));
410
411 /* Check for a reply from the RX device to the submitted request. */
412 status = aux_wait_reply(dev);
413 if (status)
414 /* Waiting for a reply timed out. */
415 return -ETIMEDOUT;
416
417 /* Analyze the reply. */
418 status = get_reg(dev, REG_AUX_REPLY_CODE);
419 if (status == AUX_REPLY_CODE_DEFER ||
420 status == AUX_REPLY_CODE_I2C_DEFER) {
421 /* The request was deferred. */
422 return -EAGAIN;
423 } else if ((status == AUX_REPLY_CODE_NACK) ||
424 (status == AUX_REPLY_CODE_I2C_NACK)) {
425 /* The request was not acknowledged. */
426 return -EIO;
427 }
428
429 /* The request was acknowledged. */
430
431 if (request->cmd_code == AUX_CMD_READ ||
432 request->cmd_code == AUX_CMD_I2C_READ ||
433 request->cmd_code == AUX_CMD_I2C_READ_MOT) {
434 /* Wait until all data has been received. */
435 timeout_count = 0;
436 do {
437 status = get_reg(dev, REG_REPLY_DATA_COUNT);
438
439 udelay(100);
440 timeout_count++;
441 if (timeout_count >= AUX_MAX_TIMEOUT_COUNT)
442 return -ETIMEDOUT;
443 } while (status != request->num_bytes);
444
445 /* Obtain the read data from the reply FIFO. */
446 for (index = 0; index < request->num_bytes; index++)
447 request->data[index] = get_reg(dev, REG_AUX_REPLY_DATA);
448 }
449
450 return 0;
451 }
452
453 /**
454 * aux_request() - Submit request on the AUX channel
455 * @dev: The LogiCore DP TX device in question
456 * @request: The request to submit
457 *
458 * Submit the supplied AUX request to the RX device over the AUX
459 * channel. If waiting for a reply times out, or if the DisplayPort TX core
460 * indicates that the request was deferred, the request is sent again (up to a
461 * maximum specified by AUX_MAX_DEFER_COUNT|AUX_MAX_TIMEOUT_COUNT).
462 *
463 * Return: 0 if request was submitted successfully, -ve on error
464 */
aux_request(struct udevice * dev,struct aux_transaction * request)465 static int aux_request(struct udevice *dev, struct aux_transaction *request)
466 {
467 u32 defer_count = 0;
468 u32 timeout_count = 0;
469
470 while ((defer_count < AUX_MAX_DEFER_COUNT) &&
471 (timeout_count < AUX_MAX_TIMEOUT_COUNT)) {
472 int status = aux_wait_ready(dev);
473
474 if (status) {
475 /* The RX device isn't ready yet. */
476 timeout_count++;
477 continue;
478 }
479
480 status = aux_request_send(dev, request);
481 if (status == -EAGAIN) {
482 /* The request was deferred. */
483 defer_count++;
484 } else if (status == -ETIMEDOUT) {
485 /* Waiting for a reply timed out. */
486 timeout_count++;
487 } else {
488 /*
489 * -EIO indicates that the request was NACK'ed,
490 * 0 indicates that the request was ACK'ed.
491 */
492 return status;
493 }
494
495 udelay(100);
496 }
497
498 /* The request was not successfully received by the RX device. */
499 return -ETIMEDOUT;
500 }
501
502 /**
503 * aux_common() - Common (read/write) AUX communication transmission
504 * @dev: The LogiCore DP TX device in question
505 * @cmd_type: Command code of the transaction
506 * @address: The DPCD address of the transaction
507 * @num_bytes: Number of bytes in the payload data
508 * @data: The payload data of the AUX command
509 *
510 * Common sequence of submitting an AUX command for AUX read, AUX write,
511 * I2C-over-AUX read, and I2C-over-AUX write transactions. If required, the
512 * reads and writes are split into multiple requests, each acting on a maximum
513 * of 16 bytes.
514 *
515 * Return: 0 if OK, -ve on error
516 */
aux_common(struct udevice * dev,u32 cmd_type,u32 address,u32 num_bytes,u8 * data)517 static int aux_common(struct udevice *dev, u32 cmd_type, u32 address,
518 u32 num_bytes, u8 *data)
519 {
520 struct aux_transaction request;
521 u32 bytes_left;
522
523 /*
524 * Set the start address for AUX transactions. For I2C transactions,
525 * this is the address of the I2C bus.
526 */
527 request.address = address;
528
529 bytes_left = num_bytes;
530 while (bytes_left) {
531 int status;
532
533 request.cmd_code = cmd_type;
534
535 if (cmd_type == AUX_CMD_READ ||
536 cmd_type == AUX_CMD_WRITE) {
537 /* Increment address for normal AUX transactions. */
538 request.address = address + (num_bytes - bytes_left);
539 }
540
541 /* Increment the pointer to the supplied data buffer. */
542 request.data = &data[num_bytes - bytes_left];
543
544 request.num_bytes = (bytes_left > 16) ? 16 : bytes_left;
545 bytes_left -= request.num_bytes;
546
547 if (cmd_type == AUX_CMD_I2C_READ && bytes_left) {
548 /*
549 * Middle of a transaction I2C read request. Override
550 * the command code that was set to cmd_type.
551 */
552 request.cmd_code = AUX_CMD_I2C_READ_MOT;
553 } else if ((cmd_type == AUX_CMD_I2C_WRITE) && bytes_left) {
554 /*
555 * Middle of a transaction I2C write request. Override
556 * the command code that was set to cmd_type.
557 */
558 request.cmd_code = AUX_CMD_I2C_WRITE_MOT;
559 }
560
561 status = aux_request(dev, &request);
562 if (status)
563 return status;
564 }
565
566 return 0;
567 }
568
569 /**
570 * aux_read() - Issue AUX read request
571 * @dev: The LogiCore DP TX device in question
572 * @dpcd_address: The DPCD address to read from
573 * @bytes_to_read: Number of bytes to read
574 * @read_data: Buffer to receive the read data
575 *
576 * Issue a read request over the AUX channel that will read from the RX
577 * device's DisplayPort Configuration data (DPCD) address space. The read
578 * message will be divided into multiple transactions which read a maximum of
579 * 16 bytes each.
580 *
581 * Return: 0 if read operation was successful, -ve on error
582 */
aux_read(struct udevice * dev,u32 dpcd_address,u32 bytes_to_read,void * read_data)583 static int aux_read(struct udevice *dev, u32 dpcd_address, u32 bytes_to_read,
584 void *read_data)
585 {
586 int status;
587
588 if (!is_connected(dev))
589 return -ENODEV;
590
591 /* Send AUX read transaction. */
592 status = aux_common(dev, AUX_CMD_READ, dpcd_address,
593 bytes_to_read, (u8 *)read_data);
594
595 return status;
596 }
597
598 /**
599 * aux_write() - Issue AUX write request
600 * @dev: The LogiCore DP TX device in question
601 * @dpcd_address: The DPCD address to write to
602 * @bytes_to_write: Number of bytes to write
603 * @write_data: Buffer containig data to be written
604 *
605 * Issue a write request over the AUX channel that will write to
606 * the RX device's DisplayPort Configuration data (DPCD) address space. The
607 * write message will be divided into multiple transactions which write a
608 * maximum of 16 bytes each.
609 *
610 * Return: 0 if write operation was successful, -ve on error
611 */
aux_write(struct udevice * dev,u32 dpcd_address,u32 bytes_to_write,void * write_data)612 static int aux_write(struct udevice *dev, u32 dpcd_address, u32 bytes_to_write,
613 void *write_data)
614 {
615 int status;
616
617 if (!is_connected(dev))
618 return -ENODEV;
619
620 /* Send AUX write transaction. */
621 status = aux_common(dev, AUX_CMD_WRITE, dpcd_address,
622 bytes_to_write, (u8 *)write_data);
623
624 return status;
625 }
626
627 /* Core initialization */
628
629 /**
630 * initialize() - Initialize a LogiCore DP TX device
631 * @dev: The LogiCore DP TX device in question
632 *
633 * Return: Always 0
634 */
initialize(struct udevice * dev)635 static int initialize(struct udevice *dev)
636 {
637 struct dp_tx *dp_tx = dev_get_priv(dev);
638 u32 val;
639 u32 phy_config;
640 unsigned int k;
641
642 /* place the PHY (and GTTXRESET) into reset. */
643 phy_config = get_reg(dev, REG_PHY_CONFIG);
644 set_reg(dev, REG_PHY_CONFIG, phy_config | PHY_CONFIG_GT_ALL_RESET_MASK);
645
646 /* reset the video streams and AUX logic. */
647 set_reg(dev, REG_SOFT_RESET,
648 SOFT_RESET_VIDEO_STREAM_ALL_MASK |
649 SOFT_RESET_AUX_MASK);
650
651 /* disable the DisplayPort TX core. */
652 set_reg(dev, REG_ENABLE, 0);
653
654 /* set the clock divider. */
655 val = get_reg(dev, REG_AUX_CLK_DIVIDER);
656 val &= ~AUX_CLK_DIVIDER_VAL_MASK;
657 val |= dp_tx->s_axi_clk / 1000000;
658 set_reg(dev, REG_AUX_CLK_DIVIDER, val);
659
660 /* set the DisplayPort TX core's clock speed. */
661 set_reg(dev, REG_PHY_CLOCK_SELECT, PHY_CLOCK_SELECT_DEFAULT);
662
663 /* bring the PHY (and GTTXRESET) out of reset. */
664 set_reg(dev, REG_PHY_CONFIG,
665 phy_config & ~PHY_CONFIG_GT_ALL_RESET_MASK);
666
667 /* enable the DisplayPort TX core. */
668 set_reg(dev, REG_ENABLE, 1);
669
670 /* Unmask Hot-Plug-Detect (HPD) interrupts. */
671 set_reg(dev, REG_INTERRUPT_MASK,
672 ~INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK &
673 ~INTERRUPT_MASK_HPD_EVENT_MASK &
674 ~INTERRUPT_MASK_HPD_IRQ_MASK);
675
676 for (k = 0; k < 4; k++) {
677 /* Disable pre-cursor levels. */
678 set_reg(dev, REG_PHY_PRECURSOR_LANE_0 + 4 * k, 0);
679
680 /* Write default voltage swing levels to the TX registers. */
681 set_reg(dev, REG_PHY_VOLTAGE_DIFF_LANE_0 + 4 * k, 0);
682
683 /* Write default pre-emphasis levels to the TX registers. */
684 set_reg(dev, REG_PHY_POSTCURSOR_LANE_0 + 4 * k, 0);
685 }
686
687 return 0;
688 }
689
690 /**
691 * is_link_rate_valid() - Check if given link rate is valif for device
692 * @dev: The LogiCore DP TX device in question
693 * @link_rate: The link rate to be checked for validity
694 *
695 * Return: true if he supplied link rate is valid, false otherwise
696 */
is_link_rate_valid(struct udevice * dev,u8 link_rate)697 static bool is_link_rate_valid(struct udevice *dev, u8 link_rate)
698 {
699 struct dp_tx *dp_tx = dev_get_priv(dev);
700 bool valid = true;
701
702 if (link_rate != LINK_BW_SET_162GBPS &&
703 link_rate != LINK_BW_SET_270GBPS &&
704 link_rate != LINK_BW_SET_540GBPS)
705 valid = false;
706 else if (link_rate > dp_tx->link_config.max_link_rate)
707 valid = false;
708
709 return valid;
710 }
711
712 /**
713 * is_lane_count_valid() - Check if given lane count is valif for device
714 * @dev: The LogiCore DP TX device in question
715 * @lane_count: The lane count to be checked for validity
716 *
717 * Return: true if he supplied lane count is valid, false otherwise
718 */
is_lane_count_valid(struct udevice * dev,u8 lane_count)719 static bool is_lane_count_valid(struct udevice *dev, u8 lane_count)
720 {
721 struct dp_tx *dp_tx = dev_get_priv(dev);
722 bool valid = true;
723
724 if (lane_count != LANE_COUNT_SET_1 &&
725 lane_count != LANE_COUNT_SET_2 &&
726 lane_count != LANE_COUNT_SET_4)
727 valid = false;
728 else if (lane_count > dp_tx->link_config.max_lane_count)
729 valid = false;
730
731 return valid;
732 }
733
734 /**
735 * get_rx_capabilities() - Check if capabilities of RX device are valid for TX
736 * device
737 * @dev: The LogiCore DP TX device in question
738 *
739 * Return: 0 if the capabilities of the RX device are valid for the TX device,
740 * -ve if not, of an error occurred during capability determination
741 */
get_rx_capabilities(struct udevice * dev)742 static int get_rx_capabilities(struct udevice *dev)
743 {
744 struct dp_tx *dp_tx = dev_get_priv(dev);
745 int status;
746 u8 rx_max_link_rate;
747 u8 rx_max_lane_count;
748
749 if (!is_connected(dev))
750 return -ENODEV;
751
752 status = aux_read(dev, DPCD_RECEIVER_CAP_FIELD_START, 16,
753 dp_tx->dpcd_rx_caps);
754 if (status)
755 return -EIO;
756
757 rx_max_link_rate = dp_tx->dpcd_rx_caps[DPCD_MAX_LINK_RATE];
758 rx_max_lane_count = dp_tx->dpcd_rx_caps[DPCD_MAX_LANE_COUNT] &
759 DPCD_MAX_LANE_COUNT_MASK;
760
761 dp_tx->link_config.max_link_rate =
762 (rx_max_link_rate > dp_tx->max_link_rate) ?
763 dp_tx->max_link_rate : rx_max_link_rate;
764 if (!is_link_rate_valid(dev, rx_max_link_rate))
765 return -EINVAL;
766
767 dp_tx->link_config.max_lane_count =
768 (rx_max_lane_count > dp_tx->max_lane_count) ?
769 dp_tx->max_lane_count : rx_max_lane_count;
770 if (!is_lane_count_valid(dev, rx_max_lane_count))
771 return -EINVAL;
772
773 dp_tx->link_config.support_enhanced_framing_mode =
774 dp_tx->dpcd_rx_caps[DPCD_MAX_LANE_COUNT] &
775 DPCD_ENHANCED_FRAME_SUPPORT_MASK;
776
777 return 0;
778 }
779
780 /**
781 * enable_main_link() - Switch on main link for a device
782 * @dev: The LogiCore DP TX device in question
783 */
enable_main_link(struct udevice * dev)784 static void enable_main_link(struct udevice *dev)
785 {
786 /* reset the scrambler. */
787 set_reg(dev, REG_FORCE_SCRAMBLER_RESET, 0x1);
788
789 /* enable the main stream. */
790 set_reg(dev, REG_ENABLE_MAIN_STREAM, 0x1);
791 }
792
793 /**
794 * disable_main_link() - Switch off main link for a device
795 * @dev: The LogiCore DP TX device in question
796 */
disable_main_link(struct udevice * dev)797 static void disable_main_link(struct udevice *dev)
798 {
799 /* reset the scrambler. */
800 set_reg(dev, REG_FORCE_SCRAMBLER_RESET, 0x1);
801
802 /* Disable the main stream. */
803 set_reg(dev, REG_ENABLE_MAIN_STREAM, 0x0);
804 }
805
806 /**
807 * reset_dp_phy() - Reset a device
808 * @dev: The LogiCore DP TX device in question
809 * @reset: Bit mask determining which bits in the device's config register
810 * should be set for the reset
811 */
reset_dp_phy(struct udevice * dev,u32 reset)812 static void reset_dp_phy(struct udevice *dev, u32 reset)
813 {
814 struct dp_tx *dp_tx = dev_get_priv(dev);
815 u32 val;
816
817 set_reg(dev, REG_ENABLE, 0x0);
818
819 val = get_reg(dev, REG_PHY_CONFIG);
820
821 /* Apply reset. */
822 set_reg(dev, REG_PHY_CONFIG, val | reset);
823
824 /* Remove reset. */
825 set_reg(dev, REG_PHY_CONFIG, val);
826
827 /* Wait for the PHY to be ready. */
828 wait_phy_ready(dev, phy_status_lanes_ready_mask(dp_tx->max_lane_count));
829
830 set_reg(dev, REG_ENABLE, 0x1);
831 }
832
833 /**
834 * set_enhanced_frame_mode() - Enable/Disable enhanced frame mode
835 * @dev: The LogiCore DP TX device in question
836 * @enable: Flag to determine whether to enable (1) or disable (0) the enhanced
837 * frame mode
838 *
839 * Enable or disable the enhanced framing symbol sequence for
840 * both the DisplayPort TX core and the RX device.
841 *
842 * Return: 0 if enabling/disabling the enhanced frame mode was successful, -ve
843 * on error
844 */
set_enhanced_frame_mode(struct udevice * dev,u8 enable)845 static int set_enhanced_frame_mode(struct udevice *dev, u8 enable)
846 {
847 struct dp_tx *dp_tx = dev_get_priv(dev);
848 int status;
849 u8 val;
850
851 if (!is_connected(dev))
852 return -ENODEV;
853
854 if (dp_tx->link_config.support_enhanced_framing_mode)
855 dp_tx->link_config.enhanced_framing_mode = enable;
856 else
857 dp_tx->link_config.enhanced_framing_mode = false;
858
859 /* Write enhanced frame mode enable to the DisplayPort TX core. */
860 set_reg(dev, REG_ENHANCED_FRAME_EN,
861 dp_tx->link_config.enhanced_framing_mode);
862
863 /* Write enhanced frame mode enable to the RX device. */
864 status = aux_read(dev, DPCD_LANE_COUNT_SET, 0x1, &val);
865 if (status)
866 return -EIO;
867
868 if (dp_tx->link_config.enhanced_framing_mode)
869 val |= DPCD_ENHANCED_FRAME_EN_MASK;
870 else
871 val &= ~DPCD_ENHANCED_FRAME_EN_MASK;
872
873 status = aux_write(dev, DPCD_LANE_COUNT_SET, 0x1, &val);
874 if (status)
875 return -EIO;
876
877 return 0;
878 }
879
880 /**
881 * set_lane_count() - Set the lane count
882 * @dev: The LogiCore DP TX device in question
883 * @lane_count: Lane count to set
884 *
885 * Set the number of lanes to be used by the main link for both
886 * the DisplayPort TX core and the RX device.
887 *
888 * Return: 0 if setting the lane count was successful, -ve on error
889 */
set_lane_count(struct udevice * dev,u8 lane_count)890 static int set_lane_count(struct udevice *dev, u8 lane_count)
891 {
892 struct dp_tx *dp_tx = dev_get_priv(dev);
893 int status;
894 u8 val;
895
896 if (!is_connected(dev))
897 return -ENODEV;
898
899 printf(" set lane count to %u\n", lane_count);
900
901 dp_tx->link_config.lane_count = lane_count;
902
903 /* Write the new lane count to the DisplayPort TX core. */
904 set_reg(dev, REG_LANE_COUNT_SET, dp_tx->link_config.lane_count);
905
906 /* Write the new lane count to the RX device. */
907 status = aux_read(dev, DPCD_LANE_COUNT_SET, 0x1, &val);
908 if (status)
909 return -EIO;
910 val &= ~DPCD_LANE_COUNT_SET_MASK;
911 val |= dp_tx->link_config.lane_count;
912
913 status = aux_write(dev, DPCD_LANE_COUNT_SET, 0x1, &val);
914 if (status)
915 return -EIO;
916
917 return 0;
918 }
919
920 /**
921 * set_clk_speed() - Set DP phy clock speed
922 * @dev: The LogiCore DP TX device in question
923 * @speed: The clock frquency to set (one of PHY_CLOCK_SELECT_*)
924 *
925 * Set the clock frequency for the DisplayPort PHY corresponding to a desired
926 * data rate.
927 *
928 * Return: 0 if setting the DP phy clock speed was successful, -ve on error
929 */
set_clk_speed(struct udevice * dev,u32 speed)930 static int set_clk_speed(struct udevice *dev, u32 speed)
931 {
932 struct dp_tx *dp_tx = dev_get_priv(dev);
933 int status;
934 u32 val;
935 u32 mask;
936
937 /* Disable the DisplayPort TX core first. */
938 val = get_reg(dev, REG_ENABLE);
939 set_reg(dev, REG_ENABLE, 0x0);
940
941 /* Change speed of the feedback clock. */
942 set_reg(dev, REG_PHY_CLOCK_SELECT, speed);
943
944 /* Re-enable the DisplayPort TX core if it was previously enabled. */
945 if (val)
946 set_reg(dev, REG_ENABLE, 0x1);
947
948 /* Wait until the PHY is ready. */
949 mask = phy_status_lanes_ready_mask(dp_tx->max_lane_count);
950 status = wait_phy_ready(dev, mask);
951 if (status)
952 return -EIO;
953
954 return 0;
955 }
956
957 /**
958 * set_link_rate() - Set the link rate
959 * @dev: The LogiCore DP TX device in question
960 * @link_rate: The link rate to set (one of LINK_BW_SET_*)
961 *
962 * Set the data rate to be used by the main link for both the DisplayPort TX
963 * core and the RX device.
964 *
965 * Return: 0 if setting the link rate was successful, -ve on error
966 */
set_link_rate(struct udevice * dev,u8 link_rate)967 static int set_link_rate(struct udevice *dev, u8 link_rate)
968 {
969 struct dp_tx *dp_tx = dev_get_priv(dev);
970 int status;
971
972 /* Write a corresponding clock frequency to the DisplayPort TX core. */
973 switch (link_rate) {
974 case LINK_BW_SET_162GBPS:
975 printf(" set link rate to 1.62 Gb/s\n");
976 status = set_clk_speed(dev, PHY_CLOCK_SELECT_162GBPS);
977 break;
978 case LINK_BW_SET_270GBPS:
979 printf(" set link rate to 2.70 Gb/s\n");
980 status = set_clk_speed(dev, PHY_CLOCK_SELECT_270GBPS);
981 break;
982 case LINK_BW_SET_540GBPS:
983 printf(" set link rate to 5.40 Gb/s\n");
984 status = set_clk_speed(dev, PHY_CLOCK_SELECT_540GBPS);
985 break;
986 default:
987 return -EINVAL;
988 }
989 if (status)
990 return -EIO;
991
992 dp_tx->link_config.link_rate = link_rate;
993
994 /* Write new link rate to the DisplayPort TX core. */
995 set_reg(dev, REG_LINK_BW_SET, dp_tx->link_config.link_rate);
996
997 /* Write new link rate to the RX device. */
998 status = aux_write(dev, DPCD_LINK_BW_SET, 1,
999 &dp_tx->link_config.link_rate);
1000 if (status)
1001 return -EIO;
1002
1003 return 0;
1004 }
1005
1006 /* Link training */
1007
1008 /**
1009 * get_training_delay() - Get training delay
1010 * @dev: The LogiCore DP TX device in question
1011 * @training_state: The training state for which the required training delay
1012 * should be queried
1013 *
1014 * Determine what the RX device's required training delay is for
1015 * link training.
1016 *
1017 * Return: The training delay in us
1018 */
get_training_delay(struct udevice * dev,int training_state)1019 static int get_training_delay(struct udevice *dev, int training_state)
1020 {
1021 struct dp_tx *dp_tx = dev_get_priv(dev);
1022 u16 delay;
1023
1024 switch (dp_tx->dpcd_rx_caps[DPCD_TRAIN_AUX_RD_INTERVAL]) {
1025 case DPCD_TRAIN_AUX_RD_INT_100_400US:
1026 if (training_state == TS_CLOCK_RECOVERY)
1027 /* delay for the clock recovery phase. */
1028 delay = 100;
1029 else
1030 /* delay for the channel equalization phase. */
1031 delay = 400;
1032 break;
1033 case DPCD_TRAIN_AUX_RD_INT_4MS:
1034 delay = 4000;
1035 break;
1036 case DPCD_TRAIN_AUX_RD_INT_8MS:
1037 delay = 8000;
1038 break;
1039 case DPCD_TRAIN_AUX_RD_INT_12MS:
1040 delay = 12000;
1041 break;
1042 case DPCD_TRAIN_AUX_RD_INT_16MS:
1043 delay = 16000;
1044 break;
1045 default:
1046 /* Default to 20 ms. */
1047 delay = 20000;
1048 break;
1049 }
1050
1051 return delay;
1052 }
1053
1054 /**
1055 * set_vswing_preemp() - Build AUX data to set voltage swing and pre-emphasis
1056 * @dev: The LogiCore DP TX device in question
1057 * @aux_data: Buffer to receive the built AUX data
1058 *
1059 * Build AUX data to set current voltage swing and pre-emphasis level settings;
1060 * the necessary data is taken from the link_config structure.
1061 */
set_vswing_preemp(struct udevice * dev,u8 * aux_data)1062 static void set_vswing_preemp(struct udevice *dev, u8 *aux_data)
1063 {
1064 struct dp_tx *dp_tx = dev_get_priv(dev);
1065 u8 data;
1066 u8 vs_level_rx = dp_tx->link_config.vs_level;
1067 u8 pe_level_rx = dp_tx->link_config.pe_level;
1068
1069 /* Set up the data buffer for writing to the RX device. */
1070 data = (pe_level_rx << DPCD_TRAINING_LANEX_SET_PE_SHIFT) | vs_level_rx;
1071 /* The maximum voltage swing has been reached. */
1072 if (vs_level_rx == MAXIMUM_VS_LEVEL)
1073 data |= DPCD_TRAINING_LANEX_SET_MAX_VS_MASK;
1074
1075 /* The maximum pre-emphasis level has been reached. */
1076 if (pe_level_rx == MAXIMUM_PE_LEVEL)
1077 data |= DPCD_TRAINING_LANEX_SET_MAX_PE_MASK;
1078 memset(aux_data, data, 4);
1079 }
1080
1081 /**
1082 * adj_vswing_preemp() - Adjust voltage swing and pre-emphasis
1083 * @dev: The LogiCore DP TX device in question
1084 *
1085 * Set new voltage swing and pre-emphasis levels using the
1086 * adjustment requests obtained from the RX device.
1087 *
1088 * Return: 0 if voltage swing and pre-emphasis could be adjusted successfully,
1089 * -ve on error
1090 */
adj_vswing_preemp(struct udevice * dev)1091 static int adj_vswing_preemp(struct udevice *dev)
1092 {
1093 struct dp_tx *dp_tx = dev_get_priv(dev);
1094 int status;
1095 u8 index;
1096 u8 vs_level_adj_req[4];
1097 u8 pe_level_adj_req[4];
1098 u8 aux_data[4];
1099 u8 *ajd_reqs = &dp_tx->lane_status_ajd_reqs[4];
1100
1101 /*
1102 * Analyze the adjustment requests for changes in voltage swing and
1103 * pre-emphasis levels.
1104 */
1105 vs_level_adj_req[0] = ajd_reqs[0] & DPCD_ADJ_REQ_LANE_0_2_VS_MASK;
1106 vs_level_adj_req[1] = (ajd_reqs[0] & DPCD_ADJ_REQ_LANE_1_3_VS_MASK) >>
1107 DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT;
1108 vs_level_adj_req[2] = ajd_reqs[1] & DPCD_ADJ_REQ_LANE_0_2_VS_MASK;
1109 vs_level_adj_req[3] = (ajd_reqs[1] & DPCD_ADJ_REQ_LANE_1_3_VS_MASK) >>
1110 DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT;
1111 pe_level_adj_req[0] = (ajd_reqs[0] & DPCD_ADJ_REQ_LANE_0_2_PE_MASK) >>
1112 DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT;
1113 pe_level_adj_req[1] = (ajd_reqs[0] & DPCD_ADJ_REQ_LANE_1_3_PE_MASK) >>
1114 DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT;
1115 pe_level_adj_req[2] = (ajd_reqs[1] & DPCD_ADJ_REQ_LANE_0_2_PE_MASK) >>
1116 DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT;
1117 pe_level_adj_req[3] = (ajd_reqs[1] & DPCD_ADJ_REQ_LANE_1_3_PE_MASK) >>
1118 DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT;
1119
1120 /*
1121 * Change the drive settings to match the adjustment requests. Use the
1122 * greatest level requested.
1123 */
1124 dp_tx->link_config.vs_level = 0;
1125 dp_tx->link_config.pe_level = 0;
1126 for (index = 0; index < dp_tx->link_config.lane_count; index++) {
1127 if (vs_level_adj_req[index] > dp_tx->link_config.vs_level)
1128 dp_tx->link_config.vs_level = vs_level_adj_req[index];
1129 if (pe_level_adj_req[index] > dp_tx->link_config.pe_level)
1130 dp_tx->link_config.pe_level = pe_level_adj_req[index];
1131 }
1132
1133 /*
1134 * Verify that the voltage swing and pre-emphasis combination is
1135 * allowed. Some combinations will result in a differential peak-to-peak
1136 * voltage that is outside the permissible range. See the VESA
1137 * DisplayPort v1.2 Specification, section 3.1.5.2.
1138 * The valid combinations are:
1139 * PE=0 PE=1 PE=2 PE=3
1140 * VS=0 valid valid valid valid
1141 * VS=1 valid valid valid
1142 * VS=2 valid valid
1143 * VS=3 valid
1144 *
1145 * NOTE:
1146 * Xilinix dp_v3_1 driver seems to have an off by one error when
1147 * limiting pe_level which is fixed here.
1148 */
1149 if (dp_tx->link_config.pe_level > (3 - dp_tx->link_config.vs_level))
1150 dp_tx->link_config.pe_level = 3 - dp_tx->link_config.vs_level;
1151
1152 /*
1153 * Make the adjustments to both the DisplayPort TX core and the RX
1154 * device.
1155 */
1156 set_vswing_preemp(dev, aux_data);
1157 /*
1158 * Write the voltage swing and pre-emphasis levels for each lane to the
1159 * RX device.
1160 */
1161 status = aux_write(dev, DPCD_TRAINING_LANE0_SET, 4, aux_data);
1162 if (status)
1163 return -EIO;
1164
1165 return 0;
1166 }
1167
1168 /**
1169 * get_lane_status_adj_reqs() - Read lane status and adjustment requests
1170 * information from the device
1171 * @dev: The LogiCore DP TX device in question
1172 *
1173 * Do a burst AUX read from the RX device over the AUX channel. The contents of
1174 * the status registers will be stored for later use by check_clock_recovery,
1175 * check_channel_equalization, and adj_vswing_preemp.
1176 *
1177 * Return: 0 if the status information were read successfully, -ve on error
1178 */
get_lane_status_adj_reqs(struct udevice * dev)1179 static int get_lane_status_adj_reqs(struct udevice *dev)
1180 {
1181 struct dp_tx *dp_tx = dev_get_priv(dev);
1182 int status;
1183
1184 /*
1185 * Read and store 4 bytes of lane status and 2 bytes of adjustment
1186 * requests.
1187 */
1188 status = aux_read(dev, DPCD_STATUS_LANE_0_1, 6,
1189 dp_tx->lane_status_ajd_reqs);
1190 if (status)
1191 return -EIO;
1192
1193 return 0;
1194 }
1195
1196 /**
1197 * check_clock_recovery() - Check clock recovery success
1198 * @dev: The LogiCore DP TX device in question
1199 * @lane_count: The number of lanes for which to check clock recovery success
1200 *
1201 * Check if the RX device's DisplayPort Configuration data (DPCD) indicates
1202 * that the clock recovery sequence during link training was successful - the
1203 * RX device's link clock and data recovery unit has realized and maintained
1204 * the frequency lock for all lanes currently in use.
1205 *
1206 * Return: 0 if clock recovery was successful on all lanes in question, -ve if
1207 * not
1208 */
check_clock_recovery(struct udevice * dev,u8 lane_count)1209 static int check_clock_recovery(struct udevice *dev, u8 lane_count)
1210 {
1211 struct dp_tx *dp_tx = dev_get_priv(dev);
1212 u8 *lane_status = dp_tx->lane_status_ajd_reqs;
1213
1214 /* Check that all LANEx_CR_DONE bits are set. */
1215 switch (lane_count) {
1216 case LANE_COUNT_SET_4:
1217 if (!(lane_status[1] & DPCD_STATUS_LANE_3_CR_DONE_MASK))
1218 goto out_fail;
1219 if (!(lane_status[1] & DPCD_STATUS_LANE_2_CR_DONE_MASK))
1220 goto out_fail;
1221 /* Drop through and check lane 1. */
1222 case LANE_COUNT_SET_2:
1223 if (!(lane_status[0] & DPCD_STATUS_LANE_1_CR_DONE_MASK))
1224 goto out_fail;
1225 /* Drop through and check lane 0. */
1226 case LANE_COUNT_SET_1:
1227 if (!(lane_status[0] & DPCD_STATUS_LANE_0_CR_DONE_MASK))
1228 goto out_fail;
1229 default:
1230 /* All (lane_count) lanes have achieved clock recovery. */
1231 break;
1232 }
1233
1234 return 0;
1235
1236 out_fail:
1237 return -EIO;
1238 }
1239
1240 /**
1241 * check_channel_equalization() - Check channel equalization success
1242 * @dev: The LogiCore DP TX device in question
1243 * @lane_count: The number of lanes for which to check channel equalization
1244 * success
1245 *
1246 * Check if the RX device's DisplayPort Configuration data (DPCD) indicates
1247 * that the channel equalization sequence during link training was successful -
1248 * the RX device has achieved channel equalization, symbol lock, and interlane
1249 * alignment for all lanes currently in use.
1250 *
1251 * Return: 0 if channel equalization was successful on all lanes in question,
1252 * -ve if not
1253 */
check_channel_equalization(struct udevice * dev,u8 lane_count)1254 static int check_channel_equalization(struct udevice *dev, u8 lane_count)
1255 {
1256 struct dp_tx *dp_tx = dev_get_priv(dev);
1257 u8 *lane_status = dp_tx->lane_status_ajd_reqs;
1258
1259 /* Check that all LANEx_CHANNEL_EQ_DONE bits are set. */
1260 switch (lane_count) {
1261 case LANE_COUNT_SET_4:
1262 if (!(lane_status[1] & DPCD_STATUS_LANE_3_CE_DONE_MASK))
1263 goto out_fail;
1264 if (!(lane_status[1] & DPCD_STATUS_LANE_2_CE_DONE_MASK))
1265 goto out_fail;
1266 /* Drop through and check lane 1. */
1267 case LANE_COUNT_SET_2:
1268 if (!(lane_status[0] & DPCD_STATUS_LANE_1_CE_DONE_MASK))
1269 goto out_fail;
1270 /* Drop through and check lane 0. */
1271 case LANE_COUNT_SET_1:
1272 if (!(lane_status[0] & DPCD_STATUS_LANE_0_CE_DONE_MASK))
1273 goto out_fail;
1274 default:
1275 /* All (lane_count) lanes have achieved channel equalization. */
1276 break;
1277 }
1278
1279 /* Check that all LANEx_SYMBOL_LOCKED bits are set. */
1280 switch (lane_count) {
1281 case LANE_COUNT_SET_4:
1282 if (!(lane_status[1] & DPCD_STATUS_LANE_3_SL_DONE_MASK))
1283 goto out_fail;
1284 if (!(lane_status[1] & DPCD_STATUS_LANE_2_SL_DONE_MASK))
1285 goto out_fail;
1286 /* Drop through and check lane 1. */
1287 case LANE_COUNT_SET_2:
1288 if (!(lane_status[0] & DPCD_STATUS_LANE_1_SL_DONE_MASK))
1289 goto out_fail;
1290 /* Drop through and check lane 0. */
1291 case LANE_COUNT_SET_1:
1292 if (!(lane_status[0] & DPCD_STATUS_LANE_0_SL_DONE_MASK))
1293 goto out_fail;
1294 default:
1295 /* All (lane_count) lanes have achieved symbol lock. */
1296 break;
1297 }
1298
1299 /* Check that interlane alignment is done. */
1300 if (!(lane_status[2] & DPCD_LANE_ALIGN_STATUS_UPDATED_IA_DONE_MASK))
1301 goto out_fail;
1302
1303 return 0;
1304
1305 out_fail:
1306 return -EIO;
1307 }
1308
1309 /**
1310 * set_training_pattern() - Set training pattern for link training
1311 * @dev: The LogiCore DP TX device in question
1312 * @pattern: The training pattern to set
1313 *
1314 * Set the training pattern to be used during link training for both the
1315 * DisplayPort TX core and the RX device.
1316 *
1317 * Return: 0 if the training pattern could be set successfully, -ve if not
1318 */
set_training_pattern(struct udevice * dev,u32 pattern)1319 static int set_training_pattern(struct udevice *dev, u32 pattern)
1320 {
1321 struct dp_tx *dp_tx = dev_get_priv(dev);
1322 int status;
1323 u8 aux_data[5];
1324
1325 /* Write to the DisplayPort TX core. */
1326 set_reg(dev, REG_TRAINING_PATTERN_SET, pattern);
1327
1328 aux_data[0] = pattern;
1329
1330 /* Write scrambler disable to the DisplayPort TX core. */
1331 switch (pattern) {
1332 case TRAINING_PATTERN_SET_OFF:
1333 set_reg(dev, REG_SCRAMBLING_DISABLE, 0);
1334 dp_tx->link_config.scrambler_en = 1;
1335 break;
1336 case TRAINING_PATTERN_SET_TP1:
1337 case TRAINING_PATTERN_SET_TP2:
1338 case TRAINING_PATTERN_SET_TP3:
1339 aux_data[0] |= DPCD_TP_SET_SCRAMB_DIS_MASK;
1340 set_reg(dev, REG_SCRAMBLING_DISABLE, 1);
1341 dp_tx->link_config.scrambler_en = 0;
1342 break;
1343 default:
1344 break;
1345 }
1346
1347 /*
1348 * Make the adjustments to both the DisplayPort TX core and the RX
1349 * device.
1350 */
1351 set_vswing_preemp(dev, &aux_data[1]);
1352 /*
1353 * Write the voltage swing and pre-emphasis levels for each lane to the
1354 * RX device.
1355 */
1356 if (pattern == TRAINING_PATTERN_SET_OFF)
1357 status = aux_write(dev, DPCD_TP_SET, 1, aux_data);
1358 else
1359 status = aux_write(dev, DPCD_TP_SET, 5, aux_data);
1360 if (status)
1361 return -EIO;
1362
1363 return 0;
1364 }
1365
1366 /**
1367 * training_state_clock_recovery() - Run clock recovery part of link training
1368 * @dev: The LogiCore DP TX device in question
1369 *
1370 * Run the clock recovery sequence as part of link training. The
1371 * sequence is as follows:
1372 *
1373 * 0) Start signaling at the minimum voltage swing, pre-emphasis, and
1374 * post- cursor levels.
1375 * 1) Transmit training pattern 1 over the main link with symbol
1376 * scrambling disabled.
1377 * 2) The clock recovery loop. If clock recovery is unsuccessful after
1378 * MaxIterations loop iterations, return.
1379 * 2a) Wait for at least the period of time specified in the RX device's
1380 * DisplayPort Configuration data (DPCD) register,
1381 * TRAINING_AUX_RD_INTERVAL.
1382 * 2b) Check if all lanes have achieved clock recovery lock. If so,
1383 * return.
1384 * 2c) Check if the same voltage swing level has been used 5 consecutive
1385 * times or if the maximum level has been reached. If so, return.
1386 * 2d) Adjust the voltage swing, pre-emphasis, and post-cursor levels as
1387 * requested by the RX device.
1388 * 2e) Loop back to 2a.
1389 *
1390 * For a more detailed description of the clock recovery sequence, see section
1391 * 3.5.1.2.1 of the DisplayPort 1.2a specification document.
1392 *
1393 * Return: The next state machine state to advance to
1394 */
training_state_clock_recovery(struct udevice * dev)1395 static unsigned int training_state_clock_recovery(struct udevice *dev)
1396 {
1397 struct dp_tx *dp_tx = dev_get_priv(dev);
1398 int status;
1399 u32 delay_us;
1400 u8 prev_vs_level = 0;
1401 u8 same_vs_level_count = 0;
1402
1403 /*
1404 * Obtain the required delay for clock recovery as specified by the
1405 * RX device.
1406 */
1407 delay_us = get_training_delay(dev, TS_CLOCK_RECOVERY);
1408
1409 /* Start CRLock. */
1410
1411 /* Transmit training pattern 1. */
1412 /* Disable the scrambler. */
1413 /* Start from minimal voltage swing and pre-emphasis levels. */
1414 dp_tx->link_config.vs_level = 0;
1415 dp_tx->link_config.pe_level = 0;
1416 status = set_training_pattern(dev, TRAINING_PATTERN_SET_TP1);
1417 if (status)
1418 return TS_FAILURE;
1419
1420 while (1) {
1421 /* Wait delay specified in TRAINING_AUX_RD_INTERVAL. */
1422 udelay(delay_us);
1423
1424 /* Get lane and adjustment requests. */
1425 status = get_lane_status_adj_reqs(dev);
1426 if (status)
1427 return TS_FAILURE;
1428
1429 /*
1430 * Check if all lanes have realized and maintained the frequency
1431 * lock and get adjustment requests.
1432 */
1433 status = check_clock_recovery(dev,
1434 dp_tx->link_config.lane_count);
1435 if (!status)
1436 return TS_CHANNEL_EQUALIZATION;
1437
1438 /*
1439 * Check if the same voltage swing for each lane has been used 5
1440 * consecutive times.
1441 */
1442 if (prev_vs_level == dp_tx->link_config.vs_level) {
1443 same_vs_level_count++;
1444 } else {
1445 same_vs_level_count = 0;
1446 prev_vs_level = dp_tx->link_config.vs_level;
1447 }
1448 if (same_vs_level_count >= 5)
1449 break;
1450
1451 /* Only try maximum voltage swing once. */
1452 if (dp_tx->link_config.vs_level == MAXIMUM_VS_LEVEL)
1453 break;
1454
1455 /* Adjust the drive settings as requested by the RX device. */
1456 status = adj_vswing_preemp(dev);
1457 if (status)
1458 /* The AUX write failed. */
1459 return TS_FAILURE;
1460 }
1461
1462 return TS_ADJUST_LINK_RATE;
1463 }
1464
1465 /**
1466 * training_state_channel_equalization() - Run channel equalization part of
1467 * link training
1468 * @dev: The LogiCore DP TX device in question
1469 *
1470 * Run the channel equalization sequence as part of link
1471 * training. The sequence is as follows:
1472 *
1473 * 0) Start signaling with the same drive settings used at the end of the
1474 * clock recovery sequence.
1475 * 1) Transmit training pattern 2 (or 3) over the main link with symbol
1476 * scrambling disabled.
1477 * 2) The channel equalization loop. If channel equalization is
1478 * unsuccessful after 5 loop iterations, return.
1479 * 2a) Wait for at least the period of time specified in the RX device's
1480 * DisplayPort Configuration data (DPCD) register,
1481 * TRAINING_AUX_RD_INTERVAL.
1482 * 2b) Check if all lanes have achieved channel equalization, symbol lock,
1483 * and interlane alignment. If so, return.
1484 * 2c) Check if the same voltage swing level has been used 5 consecutive
1485 * times or if the maximum level has been reached. If so, return.
1486 * 2d) Adjust the voltage swing, pre-emphasis, and post-cursor levels as
1487 * requested by the RX device.
1488 * 2e) Loop back to 2a.
1489 *
1490 * For a more detailed description of the channel equalization sequence, see
1491 * section 3.5.1.2.2 of the DisplayPort 1.2a specification document.
1492 *
1493 * Return: The next state machine state to advance to
1494 */
training_state_channel_equalization(struct udevice * dev)1495 static int training_state_channel_equalization(struct udevice *dev)
1496 {
1497 struct dp_tx *dp_tx = dev_get_priv(dev);
1498 int status;
1499 u32 delay_us;
1500 u32 iteration_count = 0;
1501
1502 /*
1503 * Obtain the required delay for channel equalization as specified by
1504 * the RX device.
1505 */
1506 delay_us = get_training_delay(dev, TS_CHANNEL_EQUALIZATION);
1507
1508 /* Start channel equalization. */
1509
1510 /* Write the current drive settings. */
1511 /* Transmit training pattern 2/3. */
1512 if (dp_tx->dpcd_rx_caps[DPCD_MAX_LANE_COUNT] & DPCD_TPS3_SUPPORT_MASK)
1513 status = set_training_pattern(dev, TRAINING_PATTERN_SET_TP3);
1514 else
1515 status = set_training_pattern(dev, TRAINING_PATTERN_SET_TP2);
1516
1517 if (status)
1518 return TS_FAILURE;
1519
1520 while (iteration_count < 5) {
1521 /* Wait delay specified in TRAINING_AUX_RD_INTERVAL. */
1522 udelay(delay_us);
1523
1524 /* Get lane and adjustment requests. */
1525 status = get_lane_status_adj_reqs(dev);
1526 if (status)
1527 /* The AUX read failed. */
1528 return TS_FAILURE;
1529
1530 /* Check that all lanes still have their clocks locked. */
1531 status = check_clock_recovery(dev,
1532 dp_tx->link_config.lane_count);
1533 if (status)
1534 break;
1535
1536 /*
1537 * Check if all lanes have accomplished channel equalization,
1538 * symbol lock, and interlane alignment.
1539 */
1540 status =
1541 check_channel_equalization(dev,
1542 dp_tx->link_config.lane_count);
1543 if (!status)
1544 return TS_SUCCESS;
1545
1546 /* Adjust the drive settings as requested by the RX device. */
1547 status = adj_vswing_preemp(dev);
1548 if (status)
1549 /* The AUX write failed. */
1550 return TS_FAILURE;
1551
1552 iteration_count++;
1553 }
1554
1555 /*
1556 * Tried 5 times with no success. Try a reduced bitrate first, then
1557 * reduce the number of lanes.
1558 */
1559 return TS_ADJUST_LINK_RATE;
1560 }
1561
1562 /**
1563 * training_state_adjust_link_rate() - Downshift data rate and/or lane count
1564 * @dev: The LogiCore DP TX device in question
1565 *
1566 * This function is reached if either the clock recovery or the channel
1567 * equalization process failed during training. As a result, the data rate will
1568 * be downshifted, and training will be re-attempted (starting with clock
1569 * recovery) at the reduced data rate. If the data rate is already at 1.62
1570 * Gbps, a downshift in lane count will be attempted.
1571 *
1572 * Return: The next state machine state to advance to
1573 */
training_state_adjust_link_rate(struct udevice * dev)1574 static int training_state_adjust_link_rate(struct udevice *dev)
1575 {
1576 struct dp_tx *dp_tx = dev_get_priv(dev);
1577 int status;
1578
1579 switch (dp_tx->link_config.link_rate) {
1580 case LINK_BW_SET_540GBPS:
1581 status = set_link_rate(dev, LINK_BW_SET_270GBPS);
1582 if (status) {
1583 status = TS_FAILURE;
1584 break;
1585 }
1586 status = TS_CLOCK_RECOVERY;
1587 break;
1588 case LINK_BW_SET_270GBPS:
1589 status = set_link_rate(dev, LINK_BW_SET_162GBPS);
1590 if (status) {
1591 status = TS_FAILURE;
1592 break;
1593 }
1594 status = TS_CLOCK_RECOVERY;
1595 break;
1596 default:
1597 /*
1598 * Already at the lowest link rate. Try reducing the lane
1599 * count next.
1600 */
1601 status = TS_ADJUST_LANE_COUNT;
1602 break;
1603 }
1604
1605 return status;
1606 }
1607
1608 /**
1609 * trainig_state_adjust_lane_count - Downshift lane count
1610 * @dev: The LogiCore DP TX device in question
1611 *
1612 * This function is reached if either the clock recovery or the channel
1613 * equalization process failed during training, and a minimal data rate of 1.62
1614 * Gbps was being used. As a result, the number of lanes in use will be
1615 * reduced, and training will be re-attempted (starting with clock recovery) at
1616 * this lower lane count.
1617 *
1618 * Return: The next state machine state to advance to
1619 */
trainig_state_adjust_lane_count(struct udevice * dev)1620 static int trainig_state_adjust_lane_count(struct udevice *dev)
1621 {
1622 struct dp_tx *dp_tx = dev_get_priv(dev);
1623 int status;
1624
1625 switch (dp_tx->link_config.lane_count) {
1626 case LANE_COUNT_SET_4:
1627 status = set_lane_count(dev, LANE_COUNT_SET_2);
1628 if (status) {
1629 status = TS_FAILURE;
1630 break;
1631 }
1632
1633 status = set_link_rate(dev, dp_tx->link_config.max_link_rate);
1634 if (status) {
1635 status = TS_FAILURE;
1636 break;
1637 }
1638 status = TS_CLOCK_RECOVERY;
1639 break;
1640 case LANE_COUNT_SET_2:
1641 status = set_lane_count(dev, LANE_COUNT_SET_1);
1642 if (status) {
1643 status = TS_FAILURE;
1644 break;
1645 }
1646
1647 status = set_link_rate(dev, dp_tx->link_config.max_link_rate);
1648 if (status) {
1649 status = TS_FAILURE;
1650 break;
1651 }
1652 status = TS_CLOCK_RECOVERY;
1653 break;
1654 default:
1655 /*
1656 * Already at the lowest lane count. Training has failed at the
1657 * lowest lane count and link rate.
1658 */
1659 status = TS_FAILURE;
1660 break;
1661 }
1662
1663 return status;
1664 }
1665
1666 /**
1667 * check_link_status() - Check status of link
1668 * @dev: The LogiCore DP TX device in question
1669 * @lane_count: The lane count to use for the check
1670 *
1671 * Check if the receiver's DisplayPort Configuration data (DPCD) indicates the
1672 * receiver has achieved and maintained clock recovery, channel equalization,
1673 * symbol lock, and interlane alignment for all lanes currently in use.
1674 *
1675 * Return: 0 if the link status is OK, -ve if a error occurred during checking
1676 */
check_link_status(struct udevice * dev,u8 lane_count)1677 static int check_link_status(struct udevice *dev, u8 lane_count)
1678 {
1679 u8 retry_count = 0;
1680
1681 if (!is_connected(dev))
1682 return -ENODEV;
1683
1684 /* Retrieve AUX info. */
1685 do {
1686 int status;
1687
1688 /* Get lane and adjustment requests. */
1689 status = get_lane_status_adj_reqs(dev);
1690 if (status)
1691 return -EIO;
1692
1693 /* Check if the link needs training. */
1694 if ((check_clock_recovery(dev, lane_count) == 0) &&
1695 (check_channel_equalization(dev, lane_count) == 0))
1696 return 0;
1697
1698 retry_count++;
1699 } while (retry_count < 5); /* Retry up to 5 times. */
1700
1701 return -EIO;
1702 }
1703
1704 /**
1705 * run_training() - Run link training
1706 * @dev: The LogiCore DP TX device in question
1707 *
1708 * Run the link training process. It is implemented as a state machine, with
1709 * each state returning the next state. First, the clock recovery sequence will
1710 * be run; if successful, the channel equalization sequence will run. If either
1711 * the clock recovery or channel equalization sequence failed, the link rate or
1712 * the number of lanes used will be reduced and training will be re-attempted.
1713 * If training fails at the minimal data rate, 1.62 Gbps with a single lane,
1714 * training will no longer re-attempt and fail.
1715 *
1716 * ### Here be dragons ###
1717 * There are undocumented timeout constraints in the link training process. In
1718 * DP v1.2a spec, Chapter 3.5.1.2.2 a 10ms limit for the complete training
1719 * process is mentioned. Which individual timeouts are derived and implemented
1720 * by sink manufacturers is unknown. So each step should be as short as
1721 * possible and link training should start as soon as possible after HPD.
1722 *
1723 * Return: 0 if the training sequence ran successfully, -ve if a error occurred
1724 * or the training failed
1725 */
run_training(struct udevice * dev)1726 static int run_training(struct udevice *dev)
1727 {
1728 struct dp_tx *dp_tx = dev_get_priv(dev);
1729 int status;
1730 int training_state = TS_CLOCK_RECOVERY;
1731
1732 while (1) {
1733 switch (training_state) {
1734 case TS_CLOCK_RECOVERY:
1735 training_state =
1736 training_state_clock_recovery(dev);
1737 break;
1738 case TS_CHANNEL_EQUALIZATION:
1739 training_state =
1740 training_state_channel_equalization(dev);
1741 break;
1742 case TS_ADJUST_LINK_RATE:
1743 training_state =
1744 training_state_adjust_link_rate(dev);
1745 break;
1746 case TS_ADJUST_LANE_COUNT:
1747 training_state =
1748 trainig_state_adjust_lane_count(dev);
1749 break;
1750 default:
1751 break;
1752 }
1753
1754 if (training_state == TS_SUCCESS)
1755 break;
1756 else if (training_state == TS_FAILURE)
1757 return -EIO;
1758
1759 if (training_state == TS_ADJUST_LINK_RATE ||
1760 training_state == TS_ADJUST_LANE_COUNT) {
1761 if (!dp_tx->train_adaptive)
1762 return -EIO;
1763
1764 status = set_training_pattern(dev,
1765 TRAINING_PATTERN_SET_OFF);
1766 if (status)
1767 return -EIO;
1768 }
1769 }
1770
1771 /* Final status check. */
1772 status = check_link_status(dev, dp_tx->link_config.lane_count);
1773 if (status)
1774 return -EIO;
1775
1776 return 0;
1777 }
1778
1779 /* Link policy maker */
1780
1781 /**
1782 * cfg_main_link_max() - Determine best common capabilities
1783 * @dev: The LogiCore DP TX device in question
1784 *
1785 * Determine the common capabilities between the DisplayPort TX core and the RX
1786 * device.
1787 *
1788 * Return: 0 if the determination succeeded, -ve on error
1789 */
cfg_main_link_max(struct udevice * dev)1790 static int cfg_main_link_max(struct udevice *dev)
1791 {
1792 struct dp_tx *dp_tx = dev_get_priv(dev);
1793 int status;
1794
1795 if (!is_connected(dev))
1796 return -ENODEV;
1797
1798 /*
1799 * Configure the main link to the maximum common link rate between the
1800 * DisplayPort TX core and the RX device.
1801 */
1802 status = set_link_rate(dev, dp_tx->link_config.max_link_rate);
1803 if (status)
1804 return status;
1805
1806 /*
1807 * Configure the main link to the maximum common lane count between the
1808 * DisplayPort TX core and the RX device.
1809 */
1810 status = set_lane_count(dev, dp_tx->link_config.max_lane_count);
1811 if (status)
1812 return status;
1813
1814 return 0;
1815 }
1816
1817 /**
1818 * establish_link() - Establish a link
1819 * @dev: The LogiCore DP TX device in question
1820 *
1821 * Check if the link needs training and run the training sequence if training
1822 * is required.
1823 *
1824 * Return: 0 if the link was established successfully, -ve on error
1825 */
establish_link(struct udevice * dev)1826 static int establish_link(struct udevice *dev)
1827 {
1828 struct dp_tx *dp_tx = dev_get_priv(dev);
1829 int status;
1830 int status2;
1831 u32 mask;
1832
1833 reset_dp_phy(dev, PHY_CONFIG_PHY_RESET_MASK);
1834
1835 /* Disable main link during training. */
1836 disable_main_link(dev);
1837
1838 /* Wait for the PHY to be ready. */
1839 mask = phy_status_lanes_ready_mask(dp_tx->max_lane_count);
1840 status = wait_phy_ready(dev, mask);
1841 if (status)
1842 return -EIO;
1843
1844 /* Train main link. */
1845 status = run_training(dev);
1846
1847 /* Turn off the training pattern and enable scrambler. */
1848 status2 = set_training_pattern(dev, TRAINING_PATTERN_SET_OFF);
1849 if (status || status2)
1850 return -EIO;
1851
1852 return 0;
1853 }
1854
1855 /*
1856 * Stream policy maker
1857 */
1858
1859 /**
1860 * cfg_msa_recalculate() - Calculate MSA parameters
1861 * @dev: The LogiCore DP TX device in question
1862 *
1863 * Calculate the following Main Stream Attributes (MSA):
1864 * - Transfer unit size
1865 * - User pixel width
1866 * - Horizontal total clock
1867 * - Vertical total clock
1868 * - misc_0
1869 * - misc_1
1870 * - Data per lane
1871 * - Average number of bytes per transfer unit
1872 * - Number of initial wait cycles
1873 *
1874 * These values are derived from:
1875 * - Bits per color
1876 * - Horizontal resolution
1877 * - Vertical resolution
1878 * - Horizontal blank start
1879 * - Vertical blank start
1880 * - Pixel clock (in KHz)
1881 * - Horizontal sync polarity
1882 * - Vertical sync polarity
1883 * - Horizontal sync pulse width
1884 * - Vertical sync pulse width
1885 */
cfg_msa_recalculate(struct udevice * dev)1886 static void cfg_msa_recalculate(struct udevice *dev)
1887 {
1888 struct dp_tx *dp_tx = dev_get_priv(dev);
1889 u32 video_bw;
1890 u32 link_bw;
1891 u32 words_per_line;
1892 u8 bits_per_pixel;
1893 struct main_stream_attributes *msa_config;
1894 struct link_config *link_config;
1895
1896 msa_config = &dp_tx->main_stream_attributes;
1897 link_config = &dp_tx->link_config;
1898
1899 /*
1900 * Set the user pixel width to handle clocks that exceed the
1901 * capabilities of the DisplayPort TX core.
1902 */
1903 if (msa_config->override_user_pixel_width == 0) {
1904 if (msa_config->pixel_clock_hz > 300000000 &&
1905 link_config->lane_count == LANE_COUNT_SET_4) {
1906 msa_config->user_pixel_width = 4;
1907 } /*
1908 * Xilinx driver used 75 MHz as a limit here, 150 MHZ should
1909 * be more sane
1910 */
1911 else if ((msa_config->pixel_clock_hz > 150000000) &&
1912 (link_config->lane_count != LANE_COUNT_SET_1)) {
1913 msa_config->user_pixel_width = 2;
1914 } else {
1915 msa_config->user_pixel_width = 1;
1916 }
1917 }
1918
1919 /* Compute the rest of the MSA values. */
1920 msa_config->n_vid = 27 * 1000 * link_config->link_rate;
1921
1922 /* Miscellaneous attributes. */
1923 if (msa_config->bits_per_color == 6)
1924 msa_config->misc_0 = MAIN_STREAMX_MISC0_BDC_6BPC;
1925 else if (msa_config->bits_per_color == 8)
1926 msa_config->misc_0 = MAIN_STREAMX_MISC0_BDC_8BPC;
1927 else if (msa_config->bits_per_color == 10)
1928 msa_config->misc_0 = MAIN_STREAMX_MISC0_BDC_10BPC;
1929 else if (msa_config->bits_per_color == 12)
1930 msa_config->misc_0 = MAIN_STREAMX_MISC0_BDC_12BPC;
1931 else if (msa_config->bits_per_color == 16)
1932 msa_config->misc_0 = MAIN_STREAMX_MISC0_BDC_16BPC;
1933
1934 msa_config->misc_0 = (msa_config->misc_0 <<
1935 MAIN_STREAMX_MISC0_BDC_SHIFT) |
1936 (msa_config->y_cb_cr_colorimetry <<
1937 MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT) |
1938 (msa_config->dynamic_range <<
1939 MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT) |
1940 (msa_config->component_format <<
1941 MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT) |
1942 (msa_config->synchronous_clock_mode);
1943
1944 msa_config->misc_1 = 0;
1945
1946 /*
1947 * Determine the number of bits per pixel for the specified color
1948 * component format.
1949 */
1950 if (msa_config->component_format ==
1951 MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR422)
1952 /* YCbCr422 color component format. */
1953 bits_per_pixel = msa_config->bits_per_color * 2;
1954 else
1955 /* RGB or YCbCr 4:4:4 color component format. */
1956 bits_per_pixel = msa_config->bits_per_color * 3;
1957
1958 /* Calculate the data per lane. */
1959 words_per_line = (msa_config->h_active * bits_per_pixel);
1960 if (words_per_line % 16)
1961 words_per_line += 16;
1962 words_per_line /= 16;
1963
1964 msa_config->data_per_lane = words_per_line - link_config->lane_count;
1965 if (words_per_line % link_config->lane_count)
1966 msa_config->data_per_lane += (words_per_line %
1967 link_config->lane_count);
1968
1969 /*
1970 * Allocate a fixed size for single-stream transport (SST)
1971 * operation.
1972 */
1973 msa_config->transfer_unit_size = 64;
1974
1975 /*
1976 * Calculate the average number of bytes per transfer unit.
1977 * Note: Both the integer and the fractional part is stored in
1978 * avg_bytes_per_tu.
1979 */
1980 video_bw = ((msa_config->pixel_clock_hz / 1000) * bits_per_pixel) / 8;
1981 link_bw = (link_config->lane_count * link_config->link_rate * 27);
1982 msa_config->avg_bytes_per_tu = (video_bw *
1983 msa_config->transfer_unit_size) /
1984 link_bw;
1985
1986 /*
1987 * The number of initial wait cycles at the start of a new line
1988 * by the framing logic. This allows enough data to be buffered
1989 * in the input FIFO before video is sent.
1990 */
1991 if ((msa_config->avg_bytes_per_tu / 1000) <= 4)
1992 msa_config->init_wait = 64;
1993 else
1994 msa_config->init_wait = msa_config->transfer_unit_size -
1995 (msa_config->avg_bytes_per_tu / 1000);
1996 }
1997
1998 /**
1999 * set_line_reset() - Enable/Disable end-of-line-reset
2000 * @dev: The LogiCore DP TX device in question
2001 *
2002 * Disable/enable the end-of-line-reset to the internal video pipe in case of
2003 * reduced blanking as required.
2004 */
set_line_reset(struct udevice * dev)2005 static void set_line_reset(struct udevice *dev)
2006 {
2007 struct dp_tx *dp_tx = dev_get_priv(dev);
2008 u32 reg_val;
2009 u16 h_blank;
2010 u16 h_reduced_blank;
2011 struct main_stream_attributes *msa_config =
2012 &dp_tx->main_stream_attributes;
2013
2014 h_blank = msa_config->h_total - msa_config->h_active;
2015 /* Reduced blanking starts at ceil(0.2 * HTotal). */
2016 h_reduced_blank = 2 * msa_config->h_total;
2017 if (h_reduced_blank % 10)
2018 h_reduced_blank += 10;
2019 h_reduced_blank /= 10;
2020
2021 /* CVT spec. states h_blank is either 80 or 160 for reduced blanking. */
2022 reg_val = get_reg(dev, REG_LINE_RESET_DISABLE);
2023 if (h_blank < h_reduced_blank &&
2024 (h_blank == 80 || h_blank == 160)) {
2025 reg_val |= LINE_RESET_DISABLE_MASK;
2026 } else {
2027 reg_val &= ~LINE_RESET_DISABLE_MASK;
2028 }
2029 set_reg(dev, REG_LINE_RESET_DISABLE, reg_val);
2030 }
2031
2032 /**
2033 * clear_msa_values() - Clear MSA values
2034 * @dev: The LogiCore DP TX device in question
2035 *
2036 * Clear the main stream attributes registers of the DisplayPort TX core.
2037 */
clear_msa_values(struct udevice * dev)2038 static void clear_msa_values(struct udevice *dev)
2039 {
2040 set_reg(dev, REG_MAIN_STREAM_HTOTAL, 0);
2041 set_reg(dev, REG_MAIN_STREAM_VTOTAL, 0);
2042 set_reg(dev, REG_MAIN_STREAM_POLARITY, 0);
2043 set_reg(dev, REG_MAIN_STREAM_HSWIDTH, 0);
2044 set_reg(dev, REG_MAIN_STREAM_VSWIDTH, 0);
2045 set_reg(dev, REG_MAIN_STREAM_HRES, 0);
2046 set_reg(dev, REG_MAIN_STREAM_VRES, 0);
2047 set_reg(dev, REG_MAIN_STREAM_HSTART, 0);
2048 set_reg(dev, REG_MAIN_STREAM_VSTART, 0);
2049 set_reg(dev, REG_MAIN_STREAM_MISC0, 0);
2050 set_reg(dev, REG_MAIN_STREAM_MISC1, 0);
2051 set_reg(dev, REG_USER_PIXEL_WIDTH, 0);
2052 set_reg(dev, REG_USER_DATA_COUNT_PER_LANE, 0);
2053 set_reg(dev, REG_M_VID, 0);
2054 set_reg(dev, REG_N_VID, 0);
2055
2056 set_reg(dev, REG_STREAM1, 0);
2057 set_reg(dev, REG_TU_SIZE, 0);
2058 set_reg(dev, REG_MIN_BYTES_PER_TU, 0);
2059 set_reg(dev, REG_FRAC_BYTES_PER_TU, 0);
2060 set_reg(dev, REG_INIT_WAIT, 0);
2061 }
2062
2063 /**
2064 * set_msa_values() - Set MSA values
2065 * @dev: The LogiCore DP TX device in question
2066 *
2067 * Set the main stream attributes registers of the DisplayPort TX
2068 * core with the values specified in the main stream attributes configuration
2069 * structure.
2070 */
set_msa_values(struct udevice * dev)2071 static void set_msa_values(struct udevice *dev)
2072 {
2073 struct dp_tx *dp_tx = dev_get_priv(dev);
2074 struct main_stream_attributes *msa_config =
2075 &dp_tx->main_stream_attributes;
2076
2077 printf(" set MSA %u x %u\n", msa_config->h_active,
2078 msa_config->v_active);
2079
2080 set_reg(dev, REG_MAIN_STREAM_HTOTAL, msa_config->h_total);
2081 set_reg(dev, REG_MAIN_STREAM_VTOTAL, msa_config->v_total);
2082 set_reg(dev, REG_MAIN_STREAM_POLARITY,
2083 msa_config->h_sync_polarity |
2084 (msa_config->v_sync_polarity <<
2085 MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT));
2086 set_reg(dev, REG_MAIN_STREAM_HSWIDTH, msa_config->h_sync_width);
2087 set_reg(dev, REG_MAIN_STREAM_VSWIDTH, msa_config->v_sync_width);
2088 set_reg(dev, REG_MAIN_STREAM_HRES, msa_config->h_active);
2089 set_reg(dev, REG_MAIN_STREAM_VRES, msa_config->v_active);
2090 set_reg(dev, REG_MAIN_STREAM_HSTART, msa_config->h_start);
2091 set_reg(dev, REG_MAIN_STREAM_VSTART, msa_config->v_start);
2092 set_reg(dev, REG_MAIN_STREAM_MISC0, msa_config->misc_0);
2093 set_reg(dev, REG_MAIN_STREAM_MISC1, msa_config->misc_1);
2094 set_reg(dev, REG_USER_PIXEL_WIDTH, msa_config->user_pixel_width);
2095
2096 set_reg(dev, REG_M_VID, msa_config->pixel_clock_hz / 1000);
2097 set_reg(dev, REG_N_VID, msa_config->n_vid);
2098 set_reg(dev, REG_USER_DATA_COUNT_PER_LANE, msa_config->data_per_lane);
2099
2100 set_line_reset(dev);
2101
2102 set_reg(dev, REG_TU_SIZE, msa_config->transfer_unit_size);
2103 set_reg(dev, REG_MIN_BYTES_PER_TU, msa_config->avg_bytes_per_tu / 1000);
2104 set_reg(dev, REG_FRAC_BYTES_PER_TU,
2105 (msa_config->avg_bytes_per_tu % 1000) * 1024 / 1000);
2106 set_reg(dev, REG_INIT_WAIT, msa_config->init_wait);
2107 }
2108
2109 /*
2110 * external API
2111 */
2112
2113 /**
2114 * logicore_dp_tx_set_msa() - Set given MSA values on device
2115 * @dev: The LogiCore DP TX device in question
2116 * @msa: The MSA values to set for the device
2117 */
logicore_dp_tx_set_msa(struct udevice * dev,struct logicore_dp_tx_msa * msa)2118 static void logicore_dp_tx_set_msa(struct udevice *dev,
2119 struct logicore_dp_tx_msa *msa)
2120 {
2121 struct dp_tx *dp_tx = dev_get_priv(dev);
2122
2123 memset(&dp_tx->main_stream_attributes, 0,
2124 sizeof(struct main_stream_attributes));
2125
2126 dp_tx->main_stream_attributes.pixel_clock_hz = msa->pixel_clock_hz;
2127 dp_tx->main_stream_attributes.bits_per_color = msa->bits_per_color;
2128 dp_tx->main_stream_attributes.h_active = msa->h_active;
2129 dp_tx->main_stream_attributes.h_start = msa->h_start;
2130 dp_tx->main_stream_attributes.h_sync_polarity = msa->h_sync_polarity;
2131 dp_tx->main_stream_attributes.h_sync_width = msa->h_sync_width;
2132 dp_tx->main_stream_attributes.h_total = msa->h_total;
2133 dp_tx->main_stream_attributes.v_active = msa->v_active;
2134 dp_tx->main_stream_attributes.v_start = msa->v_start;
2135 dp_tx->main_stream_attributes.v_sync_polarity = msa->v_sync_polarity;
2136 dp_tx->main_stream_attributes.v_sync_width = msa->v_sync_width;
2137 dp_tx->main_stream_attributes.v_total = msa->v_total;
2138 dp_tx->main_stream_attributes.override_user_pixel_width =
2139 msa->override_user_pixel_width;
2140 dp_tx->main_stream_attributes.user_pixel_width = msa->user_pixel_width;
2141 dp_tx->main_stream_attributes.synchronous_clock_mode = 0;
2142 }
2143
2144 /**
2145 * logicore_dp_tx_video_enable() - Enable video output
2146 * @dev: The LogiCore DP TX device in question
2147 * @msa: The MSA values to set for the device
2148 *
2149 * Return: 0 if the video was enabled successfully, -ve on error
2150 */
logicore_dp_tx_video_enable(struct udevice * dev,struct logicore_dp_tx_msa * msa)2151 static int logicore_dp_tx_video_enable(struct udevice *dev,
2152 struct logicore_dp_tx_msa *msa)
2153 {
2154 struct dp_tx *dp_tx = dev_get_priv(dev);
2155 int res;
2156 u8 power = 0x01;
2157
2158 if (!is_connected(dev)) {
2159 printf(" no DP sink connected\n");
2160 return -EIO;
2161 }
2162
2163 initialize(dev);
2164
2165 disable_main_link(dev);
2166
2167 logicore_dp_tx_set_msa(dev, msa);
2168
2169 get_rx_capabilities(dev);
2170
2171 printf(" DP sink connected\n");
2172 aux_write(dev, DPCD_SET_POWER_DP_PWR_VOLTAGE, 1, &power);
2173 set_enhanced_frame_mode(dev, true);
2174 cfg_main_link_max(dev);
2175 res = establish_link(dev);
2176 printf(" establish_link: %s, vs: %d, pe: %d\n",
2177 res ? "failed" : "ok", dp_tx->link_config.vs_level,
2178 dp_tx->link_config.pe_level);
2179
2180 cfg_msa_recalculate(dev);
2181
2182 clear_msa_values(dev);
2183 set_msa_values(dev);
2184
2185 enable_main_link(dev);
2186
2187 return 0;
2188 }
2189
2190 /*
2191 * Driver functions
2192 */
2193
logicore_dp_tx_enable(struct udevice * dev,int panel_bpp,const struct display_timing * timing)2194 static int logicore_dp_tx_enable(struct udevice *dev, int panel_bpp,
2195 const struct display_timing *timing)
2196 {
2197 struct clk pixclock;
2198 struct logicore_dp_tx_msa *msa;
2199 struct logicore_dp_tx_msa mode_640_480_60 = {
2200 .pixel_clock_hz = 25175000,
2201 .bits_per_color = 8,
2202 .h_active = 640,
2203 .h_start = 144,
2204 .h_sync_polarity = false,
2205 .h_sync_width = 96,
2206 .h_total = 800,
2207 .v_active = 480,
2208 .v_start = 35,
2209 .v_sync_polarity = false,
2210 .v_sync_width = 2,
2211 .v_total = 525,
2212 .override_user_pixel_width = false,
2213 .user_pixel_width = 0,
2214 };
2215
2216 struct logicore_dp_tx_msa mode_720_400_70 = {
2217 .pixel_clock_hz = 28300000,
2218 .bits_per_color = 8,
2219 .h_active = 720,
2220 .h_start = 162,
2221 .h_sync_polarity = false,
2222 .h_sync_width = 108,
2223 .h_total = 900,
2224 .v_active = 400,
2225 .v_start = 37,
2226 .v_sync_polarity = true,
2227 .v_sync_width = 2,
2228 .v_total = 449,
2229 .override_user_pixel_width = false,
2230 .user_pixel_width = 0,
2231 };
2232
2233 struct logicore_dp_tx_msa mode_1024_768_60 = {
2234 .pixel_clock_hz = 65000000,
2235 .bits_per_color = 8,
2236 .h_active = 1024,
2237 .h_start = 296,
2238 .h_sync_polarity = false,
2239 .h_sync_width = 136,
2240 .h_total = 1344,
2241 .v_active = 768,
2242 .v_start = 35,
2243 .v_sync_polarity = false,
2244 .v_sync_width = 2,
2245 .v_total = 806,
2246 .override_user_pixel_width = false,
2247 .user_pixel_width = 0,
2248 };
2249
2250 if (timing->hactive.typ == 1024 && timing->vactive.typ == 768)
2251 msa = &mode_1024_768_60;
2252 else if (timing->hactive.typ == 720 && timing->vactive.typ == 400)
2253 msa = &mode_720_400_70;
2254 else
2255 msa = &mode_640_480_60;
2256
2257 if (clk_get_by_index(dev, 0, &pixclock)) {
2258 printf("%s: Could not get pixelclock\n", dev->name);
2259 return -1;
2260 }
2261 clk_set_rate(&pixclock, msa->pixel_clock_hz);
2262
2263 return logicore_dp_tx_video_enable(dev, msa);
2264 }
2265
logicore_dp_tx_probe(struct udevice * dev)2266 static int logicore_dp_tx_probe(struct udevice *dev)
2267 {
2268 struct dp_tx *dp_tx = dev_get_priv(dev);
2269
2270 dp_tx->s_axi_clk = S_AXI_CLK_DEFAULT;
2271 dp_tx->train_adaptive = false;
2272 dp_tx->max_link_rate = DPCD_MAX_LINK_RATE_540GBPS;
2273 dp_tx->max_lane_count = DPCD_MAX_LANE_COUNT_4;
2274
2275 dp_tx->base = dev_read_u32_default(dev, "reg", -1);
2276
2277 return 0;
2278 }
2279
2280 static const struct dm_display_ops logicore_dp_tx_ops = {
2281 .enable = logicore_dp_tx_enable,
2282 };
2283
2284 static const struct udevice_id logicore_dp_tx_ids[] = {
2285 { .compatible = "gdsys,logicore_dp_tx" },
2286 { /* sentinel */ }
2287 };
2288
2289 U_BOOT_DRIVER(logicore_dp_tx) = {
2290 .name = "logicore_dp_tx",
2291 .id = UCLASS_DISPLAY,
2292 .of_match = logicore_dp_tx_ids,
2293 .probe = logicore_dp_tx_probe,
2294 .priv_auto_alloc_size = sizeof(struct dp_tx),
2295 .ops = &logicore_dp_tx_ops,
2296 };
2297