1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2023 Advanced Micro Devices, Inc */
3 
4 #ifndef _PDSC_H_
5 #define _PDSC_H_
6 
7 #include <linux/debugfs.h>
8 #include <net/devlink.h>
9 
10 #include <linux/pds/pds_common.h>
11 #include <linux/pds/pds_core_if.h>
12 #include <linux/pds/pds_adminq.h>
13 #include <linux/pds/pds_intr.h>
14 
15 #define PDSC_DRV_DESCRIPTION	"AMD/Pensando Core Driver"
16 
17 #define PDSC_WATCHDOG_SECS	5
18 #define PDSC_QUEUE_NAME_MAX_SZ  16
19 #define PDSC_ADMINQ_MIN_LENGTH	16	/* must be a power of two */
20 #define PDSC_NOTIFYQ_LENGTH	64	/* must be a power of two */
21 #define PDSC_TEARDOWN_RECOVERY	false
22 #define PDSC_TEARDOWN_REMOVING	true
23 #define PDSC_SETUP_RECOVERY	false
24 #define PDSC_SETUP_INIT		true
25 
26 struct pdsc_dev_bar {
27 	void __iomem *vaddr;
28 	phys_addr_t bus_addr;
29 	unsigned long len;
30 	int res_index;
31 };
32 
33 struct pdsc;
34 
35 struct pdsc_vf {
36 	struct pds_auxiliary_dev *padev;
37 	struct pdsc *vf;
38 	u16     index;
39 	__le16  vif_types[PDS_DEV_TYPE_MAX];
40 };
41 
42 struct pdsc_devinfo {
43 	u8 asic_type;
44 	u8 asic_rev;
45 	char fw_version[PDS_CORE_DEVINFO_FWVERS_BUFLEN + 1];
46 	char serial_num[PDS_CORE_DEVINFO_SERIAL_BUFLEN + 1];
47 };
48 
49 struct pdsc_queue {
50 	struct pdsc_q_info *info;
51 	u64 dbval;
52 	u16 head_idx;
53 	u16 tail_idx;
54 	u8 hw_type;
55 	unsigned int index;
56 	unsigned int num_descs;
57 	u64 dbell_count;
58 	u64 features;
59 	unsigned int type;
60 	unsigned int hw_index;
61 	union {
62 		void *base;
63 		struct pds_core_admin_cmd *adminq;
64 	};
65 	dma_addr_t base_pa;	/* must be page aligned */
66 	unsigned int desc_size;
67 	unsigned int pid;
68 	char name[PDSC_QUEUE_NAME_MAX_SZ];
69 };
70 
71 #define PDSC_INTR_NAME_MAX_SZ		32
72 
73 struct pdsc_intr_info {
74 	char name[PDSC_INTR_NAME_MAX_SZ];
75 	unsigned int index;
76 	unsigned int vector;
77 	void *data;
78 };
79 
80 struct pdsc_cq_info {
81 	void *comp;
82 };
83 
84 struct pdsc_buf_info {
85 	struct page *page;
86 	dma_addr_t dma_addr;
87 	u32 page_offset;
88 	u32 len;
89 };
90 
91 struct pdsc_q_info {
92 	union {
93 		void *desc;
94 		struct pdsc_admin_cmd *adminq_desc;
95 	};
96 	unsigned int bytes;
97 	unsigned int nbufs;
98 	struct pdsc_buf_info bufs[PDS_CORE_MAX_FRAGS];
99 	struct pdsc_wait_context *wc;
100 	void *dest;
101 };
102 
103 struct pdsc_cq {
104 	struct pdsc_cq_info *info;
105 	struct pdsc_queue *bound_q;
106 	struct pdsc_intr_info *bound_intr;
107 	u16 tail_idx;
108 	bool done_color;
109 	unsigned int num_descs;
110 	unsigned int desc_size;
111 	void *base;
112 	dma_addr_t base_pa;	/* must be page aligned */
113 } ____cacheline_aligned_in_smp;
114 
115 struct pdsc_qcq {
116 	struct pdsc *pdsc;
117 	void *q_base;
118 	dma_addr_t q_base_pa;	/* might not be page aligned */
119 	void *cq_base;
120 	dma_addr_t cq_base_pa;	/* might not be page aligned */
121 	u32 q_size;
122 	u32 cq_size;
123 	bool armed;
124 	unsigned int flags;
125 
126 	struct work_struct work;
127 	struct pdsc_queue q;
128 	struct pdsc_cq cq;
129 	int intx;
130 
131 	u32 accum_work;
132 	struct dentry *dentry;
133 };
134 
135 struct pdsc_viftype {
136 	char *name;
137 	bool supported;
138 	bool enabled;
139 	int dl_id;
140 	int vif_id;
141 	struct pds_auxiliary_dev *padev;
142 };
143 
144 /* No state flags set means we are in a steady running state */
145 enum pdsc_state_flags {
146 	PDSC_S_FW_DEAD,		    /* stopped, wait on startup or recovery */
147 	PDSC_S_INITING_DRIVER,	    /* initial startup from probe */
148 	PDSC_S_STOPPING_DRIVER,	    /* driver remove */
149 
150 	/* leave this as last */
151 	PDSC_S_STATE_SIZE
152 };
153 
154 struct pdsc {
155 	struct pci_dev *pdev;
156 	struct dentry *dentry;
157 	struct device *dev;
158 	struct pdsc_dev_bar bars[PDS_CORE_BARS_MAX];
159 	struct pdsc_vf *vfs;
160 	int num_vfs;
161 	int vf_id;
162 	int hw_index;
163 	int uid;
164 
165 	unsigned long state;
166 	u8 fw_status;
167 	u8 fw_generation;
168 	unsigned long last_fw_time;
169 	u32 last_hb;
170 	struct timer_list wdtimer;
171 	unsigned int wdtimer_period;
172 	struct work_struct health_work;
173 	struct devlink_health_reporter *fw_reporter;
174 	u32 fw_recoveries;
175 
176 	struct pdsc_devinfo dev_info;
177 	struct pds_core_dev_identity dev_ident;
178 	unsigned int nintrs;
179 	struct pdsc_intr_info *intr_info;	/* array of nintrs elements */
180 
181 	struct workqueue_struct *wq;
182 
183 	unsigned int devcmd_timeout;
184 	struct mutex devcmd_lock;	/* lock for dev_cmd operations */
185 	struct mutex config_lock;	/* lock for configuration operations */
186 	spinlock_t adminq_lock;		/* lock for adminq operations */
187 	refcount_t adminq_refcnt;
188 	struct pds_core_dev_info_regs __iomem *info_regs;
189 	struct pds_core_dev_cmd_regs __iomem *cmd_regs;
190 	struct pds_core_intr __iomem *intr_ctrl;
191 	u64 __iomem *intr_status;
192 	u64 __iomem *db_pages;
193 	dma_addr_t phy_db_pages;
194 	u64 __iomem *kern_dbpage;
195 
196 	struct pdsc_qcq adminqcq;
197 	struct pdsc_qcq notifyqcq;
198 	u64 last_eid;
199 	struct pdsc_viftype *viftype_status;
200 };
201 
202 /** enum pds_core_dbell_bits - bitwise composition of dbell values.
203  *
204  * @PDS_CORE_DBELL_QID_MASK:	unshifted mask of valid queue id bits.
205  * @PDS_CORE_DBELL_QID_SHIFT:	queue id shift amount in dbell value.
206  * @PDS_CORE_DBELL_QID:		macro to build QID component of dbell value.
207  *
208  * @PDS_CORE_DBELL_RING_MASK:	unshifted mask of valid ring bits.
209  * @PDS_CORE_DBELL_RING_SHIFT:	ring shift amount in dbell value.
210  * @PDS_CORE_DBELL_RING:	macro to build ring component of dbell value.
211  *
212  * @PDS_CORE_DBELL_RING_0:	ring zero dbell component value.
213  * @PDS_CORE_DBELL_RING_1:	ring one dbell component value.
214  * @PDS_CORE_DBELL_RING_2:	ring two dbell component value.
215  * @PDS_CORE_DBELL_RING_3:	ring three dbell component value.
216  *
217  * @PDS_CORE_DBELL_INDEX_MASK:	bit mask of valid index bits, no shift needed.
218  */
219 enum pds_core_dbell_bits {
220 	PDS_CORE_DBELL_QID_MASK		= 0xffffff,
221 	PDS_CORE_DBELL_QID_SHIFT		= 24,
222 
223 #define PDS_CORE_DBELL_QID(n) \
224 	(((u64)(n) & PDS_CORE_DBELL_QID_MASK) << PDS_CORE_DBELL_QID_SHIFT)
225 
226 	PDS_CORE_DBELL_RING_MASK		= 0x7,
227 	PDS_CORE_DBELL_RING_SHIFT		= 16,
228 
229 #define PDS_CORE_DBELL_RING(n) \
230 	(((u64)(n) & PDS_CORE_DBELL_RING_MASK) << PDS_CORE_DBELL_RING_SHIFT)
231 
232 	PDS_CORE_DBELL_RING_0		= 0,
233 	PDS_CORE_DBELL_RING_1		= PDS_CORE_DBELL_RING(1),
234 	PDS_CORE_DBELL_RING_2		= PDS_CORE_DBELL_RING(2),
235 	PDS_CORE_DBELL_RING_3		= PDS_CORE_DBELL_RING(3),
236 
237 	PDS_CORE_DBELL_INDEX_MASK		= 0xffff,
238 };
239 
pds_core_dbell_ring(u64 __iomem * db_page,enum pds_core_logical_qtype qtype,u64 val)240 static inline void pds_core_dbell_ring(u64 __iomem *db_page,
241 				       enum pds_core_logical_qtype qtype,
242 				       u64 val)
243 {
244 	writeq(val, &db_page[qtype]);
245 }
246 
247 int pdsc_fw_reporter_diagnose(struct devlink_health_reporter *reporter,
248 			      struct devlink_fmsg *fmsg,
249 			      struct netlink_ext_ack *extack);
250 int pdsc_dl_info_get(struct devlink *dl, struct devlink_info_req *req,
251 		     struct netlink_ext_ack *extack);
252 int pdsc_dl_flash_update(struct devlink *dl,
253 			 struct devlink_flash_update_params *params,
254 			 struct netlink_ext_ack *extack);
255 int pdsc_dl_enable_get(struct devlink *dl, u32 id,
256 		       struct devlink_param_gset_ctx *ctx);
257 int pdsc_dl_enable_set(struct devlink *dl, u32 id,
258 		       struct devlink_param_gset_ctx *ctx);
259 int pdsc_dl_enable_validate(struct devlink *dl, u32 id,
260 			    union devlink_param_value val,
261 			    struct netlink_ext_ack *extack);
262 
263 void __iomem *pdsc_map_dbpage(struct pdsc *pdsc, int page_num);
264 
265 void pdsc_debugfs_create(void);
266 void pdsc_debugfs_destroy(void);
267 void pdsc_debugfs_add_dev(struct pdsc *pdsc);
268 void pdsc_debugfs_del_dev(struct pdsc *pdsc);
269 void pdsc_debugfs_add_ident(struct pdsc *pdsc);
270 void pdsc_debugfs_add_viftype(struct pdsc *pdsc);
271 void pdsc_debugfs_add_irqs(struct pdsc *pdsc);
272 void pdsc_debugfs_add_qcq(struct pdsc *pdsc, struct pdsc_qcq *qcq);
273 void pdsc_debugfs_del_qcq(struct pdsc_qcq *qcq);
274 
275 int pdsc_err_to_errno(enum pds_core_status_code code);
276 bool pdsc_is_fw_running(struct pdsc *pdsc);
277 bool pdsc_is_fw_good(struct pdsc *pdsc);
278 int pdsc_devcmd(struct pdsc *pdsc, union pds_core_dev_cmd *cmd,
279 		union pds_core_dev_comp *comp, int max_seconds);
280 int pdsc_devcmd_locked(struct pdsc *pdsc, union pds_core_dev_cmd *cmd,
281 		       union pds_core_dev_comp *comp, int max_seconds);
282 int pdsc_devcmd_init(struct pdsc *pdsc);
283 int pdsc_devcmd_reset(struct pdsc *pdsc);
284 int pdsc_dev_init(struct pdsc *pdsc);
285 
286 int pdsc_intr_alloc(struct pdsc *pdsc, char *name,
287 		    irq_handler_t handler, void *data);
288 void pdsc_intr_free(struct pdsc *pdsc, int index);
289 void pdsc_qcq_free(struct pdsc *pdsc, struct pdsc_qcq *qcq);
290 int pdsc_qcq_alloc(struct pdsc *pdsc, unsigned int type, unsigned int index,
291 		   const char *name, unsigned int flags, unsigned int num_descs,
292 		   unsigned int desc_size, unsigned int cq_desc_size,
293 		   unsigned int pid, struct pdsc_qcq *qcq);
294 int pdsc_setup(struct pdsc *pdsc, bool init);
295 void pdsc_teardown(struct pdsc *pdsc, bool removing);
296 int pdsc_start(struct pdsc *pdsc);
297 void pdsc_stop(struct pdsc *pdsc);
298 void pdsc_health_thread(struct work_struct *work);
299 
300 int pdsc_register_notify(struct notifier_block *nb);
301 void pdsc_unregister_notify(struct notifier_block *nb);
302 void pdsc_notify(unsigned long event, void *data);
303 int pdsc_auxbus_dev_add(struct pdsc *cf, struct pdsc *pf);
304 int pdsc_auxbus_dev_del(struct pdsc *cf, struct pdsc *pf);
305 
306 void pdsc_process_adminq(struct pdsc_qcq *qcq);
307 void pdsc_work_thread(struct work_struct *work);
308 irqreturn_t pdsc_adminq_isr(int irq, void *data);
309 
310 int pdsc_firmware_update(struct pdsc *pdsc, const struct firmware *fw,
311 			 struct netlink_ext_ack *extack);
312 
313 void pdsc_fw_down(struct pdsc *pdsc);
314 void pdsc_fw_up(struct pdsc *pdsc);
315 
316 #endif /* _PDSC_H_ */
317