1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * pata_pdc202xx_old.c - Promise PDC202xx PATA for new ATA layer
4 * (C) 2005 Red Hat Inc
5 * Alan Cox <alan@lxorguk.ukuu.org.uk>
6 * (C) 2007,2009,2010 Bartlomiej Zolnierkiewicz
7 *
8 * Based in part on linux/drivers/ide/pci/pdc202xx_old.c
9 *
10 * First cut with LBA48/ATAPI
11 *
12 * TODO:
13 * Channel interlock/reset on both required ?
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/pci.h>
19 #include <linux/blkdev.h>
20 #include <linux/delay.h>
21 #include <scsi/scsi_host.h>
22 #include <linux/libata.h>
23
24 #define DRV_NAME "pata_pdc202xx_old"
25 #define DRV_VERSION "0.4.3"
26
pdc2026x_cable_detect(struct ata_port * ap)27 static int pdc2026x_cable_detect(struct ata_port *ap)
28 {
29 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
30 u16 cis;
31
32 pci_read_config_word(pdev, 0x50, &cis);
33 if (cis & (1 << (10 + ap->port_no)))
34 return ATA_CBL_PATA40;
35 return ATA_CBL_PATA80;
36 }
37
pdc202xx_exec_command(struct ata_port * ap,const struct ata_taskfile * tf)38 static void pdc202xx_exec_command(struct ata_port *ap,
39 const struct ata_taskfile *tf)
40 {
41 iowrite8(tf->command, ap->ioaddr.command_addr);
42 ndelay(400);
43 }
44
pdc202xx_irq_check(struct ata_port * ap)45 static bool pdc202xx_irq_check(struct ata_port *ap)
46 {
47 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
48 unsigned long master = pci_resource_start(pdev, 4);
49 u8 sc1d = inb(master + 0x1d);
50
51 if (ap->port_no) {
52 /*
53 * bit 7: error, bit 6: interrupting,
54 * bit 5: FIFO full, bit 4: FIFO empty
55 */
56 return sc1d & 0x40;
57 } else {
58 /*
59 * bit 3: error, bit 2: interrupting,
60 * bit 1: FIFO full, bit 0: FIFO empty
61 */
62 return sc1d & 0x04;
63 }
64 }
65
66 /**
67 * pdc202xx_configure_piomode - set chip PIO timing
68 * @ap: ATA interface
69 * @adev: ATA device
70 * @pio: PIO mode
71 *
72 * Called to do the PIO mode setup. Our timing registers are shared
73 * so a configure_dmamode call will undo any work we do here and vice
74 * versa
75 */
76
pdc202xx_configure_piomode(struct ata_port * ap,struct ata_device * adev,int pio)77 static void pdc202xx_configure_piomode(struct ata_port *ap, struct ata_device *adev, int pio)
78 {
79 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
80 int port = 0x60 + 8 * ap->port_no + 4 * adev->devno;
81 static const u16 pio_timing[5] = {
82 0x0913, 0x050C , 0x0308, 0x0206, 0x0104
83 };
84 u8 r_ap, r_bp;
85
86 pci_read_config_byte(pdev, port, &r_ap);
87 pci_read_config_byte(pdev, port + 1, &r_bp);
88 r_ap &= ~0x3F; /* Preserve ERRDY_EN, SYNC_IN */
89 r_bp &= ~0x1F;
90 r_ap |= (pio_timing[pio] >> 8);
91 r_bp |= (pio_timing[pio] & 0xFF);
92
93 if (ata_pio_need_iordy(adev))
94 r_ap |= 0x20; /* IORDY enable */
95 if (adev->class == ATA_DEV_ATA)
96 r_ap |= 0x10; /* FIFO enable */
97 pci_write_config_byte(pdev, port, r_ap);
98 pci_write_config_byte(pdev, port + 1, r_bp);
99 }
100
101 /**
102 * pdc202xx_set_piomode - set initial PIO mode data
103 * @ap: ATA interface
104 * @adev: ATA device
105 *
106 * Called to do the PIO mode setup. Our timing registers are shared
107 * but we want to set the PIO timing by default.
108 */
109
pdc202xx_set_piomode(struct ata_port * ap,struct ata_device * adev)110 static void pdc202xx_set_piomode(struct ata_port *ap, struct ata_device *adev)
111 {
112 pdc202xx_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
113 }
114
115 /**
116 * pdc202xx_set_dmamode - set DMA mode in chip
117 * @ap: ATA interface
118 * @adev: ATA device
119 *
120 * Load DMA cycle times into the chip ready for a DMA transfer
121 * to occur.
122 */
123
pdc202xx_set_dmamode(struct ata_port * ap,struct ata_device * adev)124 static void pdc202xx_set_dmamode(struct ata_port *ap, struct ata_device *adev)
125 {
126 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
127 int port = 0x60 + 8 * ap->port_no + 4 * adev->devno;
128 static u8 udma_timing[6][2] = {
129 { 0x60, 0x03 }, /* 33 Mhz Clock */
130 { 0x40, 0x02 },
131 { 0x20, 0x01 },
132 { 0x40, 0x02 }, /* 66 Mhz Clock */
133 { 0x20, 0x01 },
134 { 0x20, 0x01 }
135 };
136 static u8 mdma_timing[3][2] = {
137 { 0xe0, 0x0f },
138 { 0x60, 0x04 },
139 { 0x60, 0x03 },
140 };
141 u8 r_bp, r_cp;
142
143 pci_read_config_byte(pdev, port + 1, &r_bp);
144 pci_read_config_byte(pdev, port + 2, &r_cp);
145
146 r_bp &= ~0xE0;
147 r_cp &= ~0x0F;
148
149 if (adev->dma_mode >= XFER_UDMA_0) {
150 int speed = adev->dma_mode - XFER_UDMA_0;
151 r_bp |= udma_timing[speed][0];
152 r_cp |= udma_timing[speed][1];
153
154 } else {
155 int speed = adev->dma_mode - XFER_MW_DMA_0;
156 r_bp |= mdma_timing[speed][0];
157 r_cp |= mdma_timing[speed][1];
158 }
159 pci_write_config_byte(pdev, port + 1, r_bp);
160 pci_write_config_byte(pdev, port + 2, r_cp);
161
162 }
163
164 /**
165 * pdc2026x_bmdma_start - DMA engine begin
166 * @qc: ATA command
167 *
168 * In UDMA3 or higher we have to clock switch for the duration of the
169 * DMA transfer sequence.
170 *
171 * Note: The host lock held by the libata layer protects
172 * us from two channels both trying to set DMA bits at once
173 */
174
pdc2026x_bmdma_start(struct ata_queued_cmd * qc)175 static void pdc2026x_bmdma_start(struct ata_queued_cmd *qc)
176 {
177 struct ata_port *ap = qc->ap;
178 struct ata_device *adev = qc->dev;
179 struct ata_taskfile *tf = &qc->tf;
180 int sel66 = ap->port_no ? 0x08: 0x02;
181
182 void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr;
183 void __iomem *clock = master + 0x11;
184 void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no);
185
186 u32 len;
187
188 /* Check we keep host level locking here */
189 if (adev->dma_mode > XFER_UDMA_2)
190 iowrite8(ioread8(clock) | sel66, clock);
191 else
192 iowrite8(ioread8(clock) & ~sel66, clock);
193
194 /* The DMA clocks may have been trashed by a reset. FIXME: make conditional
195 and move to qc_issue ? */
196 pdc202xx_set_dmamode(ap, qc->dev);
197
198 /* Cases the state machine will not complete correctly without help */
199 if ((tf->flags & ATA_TFLAG_LBA48) || tf->protocol == ATAPI_PROT_DMA) {
200 len = qc->nbytes / 2;
201
202 if (tf->flags & ATA_TFLAG_WRITE)
203 len |= 0x06000000;
204 else
205 len |= 0x05000000;
206
207 iowrite32(len, atapi_reg);
208 }
209
210 /* Activate DMA */
211 ata_bmdma_start(qc);
212 }
213
214 /**
215 * pdc2026x_bmdma_stop - DMA engine stop
216 * @qc: ATA command
217 *
218 * After a DMA completes we need to put the clock back to 33MHz for
219 * PIO timings.
220 *
221 * Note: The host lock held by the libata layer protects
222 * us from two channels both trying to set DMA bits at once
223 */
224
pdc2026x_bmdma_stop(struct ata_queued_cmd * qc)225 static void pdc2026x_bmdma_stop(struct ata_queued_cmd *qc)
226 {
227 struct ata_port *ap = qc->ap;
228 struct ata_device *adev = qc->dev;
229 struct ata_taskfile *tf = &qc->tf;
230
231 int sel66 = ap->port_no ? 0x08: 0x02;
232 /* The clock bits are in the same register for both channels */
233 void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr;
234 void __iomem *clock = master + 0x11;
235 void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no);
236
237 /* Cases the state machine will not complete correctly */
238 if (tf->protocol == ATAPI_PROT_DMA || (tf->flags & ATA_TFLAG_LBA48)) {
239 iowrite32(0, atapi_reg);
240 iowrite8(ioread8(clock) & ~sel66, clock);
241 }
242 /* Flip back to 33Mhz for PIO */
243 if (adev->dma_mode > XFER_UDMA_2)
244 iowrite8(ioread8(clock) & ~sel66, clock);
245 ata_bmdma_stop(qc);
246 pdc202xx_set_piomode(ap, adev);
247 }
248
249 /**
250 * pdc2026x_dev_config - device setup hook
251 * @adev: newly found device
252 *
253 * Perform chip specific early setup. We need to lock the transfer
254 * sizes to 8bit to avoid making the state engine on the 2026x cards
255 * barf.
256 */
257
pdc2026x_dev_config(struct ata_device * adev)258 static void pdc2026x_dev_config(struct ata_device *adev)
259 {
260 adev->max_sectors = 256;
261 }
262
pdc2026x_port_start(struct ata_port * ap)263 static int pdc2026x_port_start(struct ata_port *ap)
264 {
265 void __iomem *bmdma = ap->ioaddr.bmdma_addr;
266 if (bmdma) {
267 /* Enable burst mode */
268 u8 burst = ioread8(bmdma + 0x1f);
269 iowrite8(burst | 0x01, bmdma + 0x1f);
270 }
271 return ata_bmdma_port_start(ap);
272 }
273
274 /**
275 * pdc2026x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command
276 * @qc: Metadata associated with taskfile to check
277 *
278 * Just say no - not supported on older Promise.
279 *
280 * LOCKING:
281 * None (inherited from caller).
282 *
283 * RETURNS: 0 when ATAPI DMA can be used
284 * 1 otherwise
285 */
286
pdc2026x_check_atapi_dma(struct ata_queued_cmd * qc)287 static int pdc2026x_check_atapi_dma(struct ata_queued_cmd *qc)
288 {
289 return 1;
290 }
291
292 static const struct scsi_host_template pdc202xx_sht = {
293 ATA_BMDMA_SHT(DRV_NAME),
294 };
295
296 static struct ata_port_operations pdc2024x_port_ops = {
297 .inherits = &ata_bmdma_port_ops,
298
299 .cable_detect = ata_cable_40wire,
300 .set_piomode = pdc202xx_set_piomode,
301 .set_dmamode = pdc202xx_set_dmamode,
302
303 .sff_exec_command = pdc202xx_exec_command,
304 .sff_irq_check = pdc202xx_irq_check,
305 };
306
307 static struct ata_port_operations pdc2026x_port_ops = {
308 .inherits = &pdc2024x_port_ops,
309
310 .check_atapi_dma = pdc2026x_check_atapi_dma,
311 .bmdma_start = pdc2026x_bmdma_start,
312 .bmdma_stop = pdc2026x_bmdma_stop,
313
314 .cable_detect = pdc2026x_cable_detect,
315 .dev_config = pdc2026x_dev_config,
316
317 .port_start = pdc2026x_port_start,
318
319 .sff_exec_command = pdc202xx_exec_command,
320 .sff_irq_check = pdc202xx_irq_check,
321 };
322
pdc202xx_init_one(struct pci_dev * dev,const struct pci_device_id * id)323 static int pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
324 {
325 static const struct ata_port_info info[3] = {
326 {
327 .flags = ATA_FLAG_SLAVE_POSS,
328 .pio_mask = ATA_PIO4,
329 .mwdma_mask = ATA_MWDMA2,
330 .udma_mask = ATA_UDMA2,
331 .port_ops = &pdc2024x_port_ops
332 },
333 {
334 .flags = ATA_FLAG_SLAVE_POSS,
335 .pio_mask = ATA_PIO4,
336 .mwdma_mask = ATA_MWDMA2,
337 .udma_mask = ATA_UDMA4,
338 .port_ops = &pdc2026x_port_ops
339 },
340 {
341 .flags = ATA_FLAG_SLAVE_POSS,
342 .pio_mask = ATA_PIO4,
343 .mwdma_mask = ATA_MWDMA2,
344 .udma_mask = ATA_UDMA5,
345 .port_ops = &pdc2026x_port_ops
346 }
347
348 };
349 const struct ata_port_info *ppi[] = { &info[id->driver_data], NULL };
350
351 if (dev->device == PCI_DEVICE_ID_PROMISE_20265) {
352 struct pci_dev *bridge = dev->bus->self;
353 /* Don't grab anything behind a Promise I2O RAID */
354 if (bridge && bridge->vendor == PCI_VENDOR_ID_INTEL) {
355 if (bridge->device == PCI_DEVICE_ID_INTEL_I960)
356 return -ENODEV;
357 if (bridge->device == PCI_DEVICE_ID_INTEL_I960RM)
358 return -ENODEV;
359 }
360 }
361 return ata_pci_bmdma_init_one(dev, ppi, &pdc202xx_sht, NULL, 0);
362 }
363
364 static const struct pci_device_id pdc202xx[] = {
365 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
366 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
367 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 },
368 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 },
369 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 },
370
371 { },
372 };
373
374 static struct pci_driver pdc202xx_pci_driver = {
375 .name = DRV_NAME,
376 .id_table = pdc202xx,
377 .probe = pdc202xx_init_one,
378 .remove = ata_pci_remove_one,
379 #ifdef CONFIG_PM_SLEEP
380 .suspend = ata_pci_device_suspend,
381 .resume = ata_pci_device_resume,
382 #endif
383 };
384
385 module_pci_driver(pdc202xx_pci_driver);
386
387 MODULE_AUTHOR("Alan Cox");
388 MODULE_DESCRIPTION("low-level driver for Promise 2024x and 20262-20267");
389 MODULE_LICENSE("GPL");
390 MODULE_DEVICE_TABLE(pci, pdc202xx);
391 MODULE_VERSION(DRV_VERSION);
392