xref: /openbmc/qemu/hw/pci-host/ppce500.c (revision e452053097371880910c744a5d42ae2df058a4a7)
1 /*
2  * QEMU PowerPC E500 embedded processors pci controller emulation
3  *
4  * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
5  *
6  * Author: Yu Liu,     <yu.liu@freescale.com>
7  *
8  * This file is derived from ppc4xx_pci.c,
9  * the copyright for that material belongs to the original owners.
10  *
11  * This is free software; you can redistribute it and/or modify
12  * it under the terms of  the GNU General  Public License as published by
13  * the Free Software Foundation;  either version 2 of the  License, or
14  * (at your option) any later version.
15  */
16 
17 #include "qemu/osdep.h"
18 #include "hw/irq.h"
19 #include "hw/qdev-properties.h"
20 #include "migration/vmstate.h"
21 #include "hw/pci/pci_device.h"
22 #include "hw/pci/pci_host.h"
23 #include "hw/pci-host/ppce500.h"
24 #include "qom/object.h"
25 
26 #ifdef DEBUG_PCI
27 #define pci_debug(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__)
28 #else
29 #define pci_debug(fmt, ...)
30 #endif
31 
32 #define PCIE500_CFGADDR       0x0
33 #define PCIE500_CFGDATA       0x4
34 #define PCIE500_REG_BASE      0xC00
35 #define PCIE500_ALL_SIZE      0x1000
36 #define PCIE500_REG_SIZE      (PCIE500_ALL_SIZE - PCIE500_REG_BASE)
37 
38 #define PCIE500_PCI_IOLEN     0x10000ULL
39 
40 #define PPCE500_PCI_CONFIG_ADDR         0x0
41 #define PPCE500_PCI_CONFIG_DATA         0x4
42 #define PPCE500_PCI_INTACK              0x8
43 
44 #define PPCE500_PCI_OW1                 (0xC20 - PCIE500_REG_BASE)
45 #define PPCE500_PCI_OW2                 (0xC40 - PCIE500_REG_BASE)
46 #define PPCE500_PCI_OW3                 (0xC60 - PCIE500_REG_BASE)
47 #define PPCE500_PCI_OW4                 (0xC80 - PCIE500_REG_BASE)
48 #define PPCE500_PCI_IW3                 (0xDA0 - PCIE500_REG_BASE)
49 #define PPCE500_PCI_IW2                 (0xDC0 - PCIE500_REG_BASE)
50 #define PPCE500_PCI_IW1                 (0xDE0 - PCIE500_REG_BASE)
51 
52 #define PPCE500_PCI_GASKET_TIMR         (0xE20 - PCIE500_REG_BASE)
53 
54 #define PCI_POTAR               0x0
55 #define PCI_POTEAR              0x4
56 #define PCI_POWBAR              0x8
57 #define PCI_POWAR               0x10
58 
59 #define PCI_PITAR               0x0
60 #define PCI_PIWBAR              0x8
61 #define PCI_PIWBEAR             0xC
62 #define PCI_PIWAR               0x10
63 
64 #define PPCE500_PCI_NR_POBS     5
65 #define PPCE500_PCI_NR_PIBS     3
66 
67 #define PIWAR_EN                0x80000000      /* Enable */
68 #define PIWAR_PF                0x20000000      /* prefetch */
69 #define PIWAR_TGI_LOCAL         0x00f00000      /* target - local memory */
70 #define PIWAR_READ_SNOOP        0x00050000
71 #define PIWAR_WRITE_SNOOP       0x00005000
72 #define PIWAR_SZ_MASK           0x0000003f
73 
74 struct  pci_outbound {
75     uint32_t potar;
76     uint32_t potear;
77     uint32_t powbar;
78     uint32_t powar;
79     MemoryRegion mem;
80 };
81 
82 struct pci_inbound {
83     uint32_t pitar;
84     uint32_t piwbar;
85     uint32_t piwbear;
86     uint32_t piwar;
87     MemoryRegion mem;
88 };
89 
90 #define TYPE_PPC_E500_PCI_HOST_BRIDGE "e500-pcihost"
91 
92 OBJECT_DECLARE_SIMPLE_TYPE(PPCE500PCIState, PPC_E500_PCI_HOST_BRIDGE)
93 
94 struct PPCE500PCIState {
95     PCIHostState parent_obj;
96 
97     struct pci_outbound pob[PPCE500_PCI_NR_POBS];
98     struct pci_inbound pib[PPCE500_PCI_NR_PIBS];
99     uint32_t gasket_time;
100     qemu_irq irq[PCI_NUM_PINS];
101     uint32_t irq_num[PCI_NUM_PINS];
102     uint32_t first_slot;
103     uint32_t first_pin_irq;
104     AddressSpace bm_as;
105     MemoryRegion bm;
106     /* mmio maps */
107     MemoryRegion container;
108     MemoryRegion iomem;
109     MemoryRegion pio;
110     MemoryRegion busmem;
111 };
112 
113 #define TYPE_PPC_E500_PCI_BRIDGE "e500-host-bridge"
114 OBJECT_DECLARE_SIMPLE_TYPE(PPCE500PCIBridgeState, PPC_E500_PCI_BRIDGE)
115 
116 struct PPCE500PCIBridgeState {
117     /*< private >*/
118     PCIDevice parent;
119     /*< public >*/
120 
121     MemoryRegion bar0;
122 };
123 
124 
pci_reg_read4(void * opaque,hwaddr addr,unsigned size)125 static uint64_t pci_reg_read4(void *opaque, hwaddr addr,
126                               unsigned size)
127 {
128     PPCE500PCIState *pci = opaque;
129     unsigned long win;
130     uint32_t value = 0;
131     int idx;
132 
133     win = addr & 0xfe0;
134 
135     switch (win) {
136     case PPCE500_PCI_OW1:
137     case PPCE500_PCI_OW2:
138     case PPCE500_PCI_OW3:
139     case PPCE500_PCI_OW4:
140         idx = (addr >> 5) & 0x7;
141         switch (addr & 0x1F) {
142         case PCI_POTAR:
143             value = pci->pob[idx].potar;
144             break;
145         case PCI_POTEAR:
146             value = pci->pob[idx].potear;
147             break;
148         case PCI_POWBAR:
149             value = pci->pob[idx].powbar;
150             break;
151         case PCI_POWAR:
152             value = pci->pob[idx].powar;
153             break;
154         default:
155             break;
156         }
157         break;
158 
159     case PPCE500_PCI_IW3:
160     case PPCE500_PCI_IW2:
161     case PPCE500_PCI_IW1:
162         idx = ((addr >> 5) & 0x3) - 1;
163         switch (addr & 0x1F) {
164         case PCI_PITAR:
165             value = pci->pib[idx].pitar;
166             break;
167         case PCI_PIWBAR:
168             value = pci->pib[idx].piwbar;
169             break;
170         case PCI_PIWBEAR:
171             value = pci->pib[idx].piwbear;
172             break;
173         case PCI_PIWAR:
174             value = pci->pib[idx].piwar;
175             break;
176         default:
177             break;
178         };
179         break;
180 
181     case PPCE500_PCI_GASKET_TIMR:
182         value = pci->gasket_time;
183         break;
184 
185     default:
186         break;
187     }
188 
189     pci_debug("%s: win:%lx(addr:" HWADDR_FMT_plx ") -> value:%x\n", __func__,
190               win, addr, value);
191     return value;
192 }
193 
194 /* DMA mapping */
e500_update_piw(PPCE500PCIState * pci,int idx)195 static void e500_update_piw(PPCE500PCIState *pci, int idx)
196 {
197     uint64_t tar = ((uint64_t)pci->pib[idx].pitar) << 12;
198     uint64_t wbar = ((uint64_t)pci->pib[idx].piwbar) << 12;
199     uint64_t war = pci->pib[idx].piwar;
200     uint64_t size = 2ULL << (war & PIWAR_SZ_MASK);
201     MemoryRegion *address_space_mem = get_system_memory();
202     MemoryRegion *mem = &pci->pib[idx].mem;
203     MemoryRegion *bm = &pci->bm;
204     char *name;
205 
206     if (memory_region_is_mapped(mem)) {
207         /* Before we modify anything, unmap and destroy the region */
208         memory_region_del_subregion(bm, mem);
209         object_unparent(OBJECT(mem));
210     }
211 
212     if (!(war & PIWAR_EN)) {
213         /* Not enabled, nothing to do */
214         return;
215     }
216 
217     name = g_strdup_printf("PCI Inbound Window %d", idx);
218     memory_region_init_alias(mem, OBJECT(pci), name, address_space_mem, tar,
219                              size);
220     memory_region_add_subregion_overlap(bm, wbar, mem, -1);
221     g_free(name);
222 
223     pci_debug("%s: Added window of size=%#lx from PCI=%#lx to CPU=%#lx\n",
224               __func__, size, wbar, tar);
225 }
226 
227 /* BAR mapping */
e500_update_pow(PPCE500PCIState * pci,int idx)228 static void e500_update_pow(PPCE500PCIState *pci, int idx)
229 {
230     uint64_t tar = ((uint64_t)pci->pob[idx].potar) << 12;
231     uint64_t wbar = ((uint64_t)pci->pob[idx].powbar) << 12;
232     uint64_t war = pci->pob[idx].powar;
233     uint64_t size = 2ULL << (war & PIWAR_SZ_MASK);
234     MemoryRegion *mem = &pci->pob[idx].mem;
235     MemoryRegion *address_space_mem = get_system_memory();
236     char *name;
237 
238     if (memory_region_is_mapped(mem)) {
239         /* Before we modify anything, unmap and destroy the region */
240         memory_region_del_subregion(address_space_mem, mem);
241         object_unparent(OBJECT(mem));
242     }
243 
244     if (!(war & PIWAR_EN)) {
245         /* Not enabled, nothing to do */
246         return;
247     }
248 
249     name = g_strdup_printf("PCI Outbound Window %d", idx);
250     memory_region_init_alias(mem, OBJECT(pci), name, &pci->busmem, tar,
251                              size);
252     memory_region_add_subregion(address_space_mem, wbar, mem);
253     g_free(name);
254 
255     pci_debug("%s: Added window of size=%#lx from CPU=%#lx to PCI=%#lx\n",
256               __func__, size, wbar, tar);
257 }
258 
pci_reg_write4(void * opaque,hwaddr addr,uint64_t value,unsigned size)259 static void pci_reg_write4(void *opaque, hwaddr addr,
260                            uint64_t value, unsigned size)
261 {
262     PPCE500PCIState *pci = opaque;
263     unsigned long win;
264     int idx;
265 
266     win = addr & 0xfe0;
267 
268     pci_debug("%s: value:%x -> win:%lx(addr:" HWADDR_FMT_plx ")\n",
269               __func__, (unsigned)value, win, addr);
270 
271     switch (win) {
272     case PPCE500_PCI_OW1:
273     case PPCE500_PCI_OW2:
274     case PPCE500_PCI_OW3:
275     case PPCE500_PCI_OW4:
276         idx = (addr >> 5) & 0x7;
277         switch (addr & 0x1F) {
278         case PCI_POTAR:
279             pci->pob[idx].potar = value;
280             e500_update_pow(pci, idx);
281             break;
282         case PCI_POTEAR:
283             pci->pob[idx].potear = value;
284             e500_update_pow(pci, idx);
285             break;
286         case PCI_POWBAR:
287             pci->pob[idx].powbar = value;
288             e500_update_pow(pci, idx);
289             break;
290         case PCI_POWAR:
291             pci->pob[idx].powar = value;
292             e500_update_pow(pci, idx);
293             break;
294         default:
295             break;
296         };
297         break;
298 
299     case PPCE500_PCI_IW3:
300     case PPCE500_PCI_IW2:
301     case PPCE500_PCI_IW1:
302         idx = ((addr >> 5) & 0x3) - 1;
303         switch (addr & 0x1F) {
304         case PCI_PITAR:
305             pci->pib[idx].pitar = value;
306             e500_update_piw(pci, idx);
307             break;
308         case PCI_PIWBAR:
309             pci->pib[idx].piwbar = value;
310             e500_update_piw(pci, idx);
311             break;
312         case PCI_PIWBEAR:
313             pci->pib[idx].piwbear = value;
314             e500_update_piw(pci, idx);
315             break;
316         case PCI_PIWAR:
317             pci->pib[idx].piwar = value;
318             e500_update_piw(pci, idx);
319             break;
320         default:
321             break;
322         };
323         break;
324 
325     case PPCE500_PCI_GASKET_TIMR:
326         pci->gasket_time = value;
327         break;
328 
329     default:
330         break;
331     };
332 }
333 
334 static const MemoryRegionOps e500_pci_reg_ops = {
335     .read = pci_reg_read4,
336     .write = pci_reg_write4,
337     .endianness = DEVICE_BIG_ENDIAN,
338 };
339 
mpc85xx_pci_map_irq(PCIDevice * pci_dev,int pin)340 static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int pin)
341 {
342     int devno = PCI_SLOT(pci_dev->devfn);
343     int ret;
344 
345     ret = ppce500_pci_map_irq_slot(devno, pin);
346 
347     pci_debug("%s: devfn %x irq %d -> %d  devno:%x\n", __func__,
348            pci_dev->devfn, pin, ret, devno);
349 
350     return ret;
351 }
352 
mpc85xx_pci_set_irq(void * opaque,int pin,int level)353 static void mpc85xx_pci_set_irq(void *opaque, int pin, int level)
354 {
355     PPCE500PCIState *s = opaque;
356     qemu_irq *pic = s->irq;
357 
358     pci_debug("%s: PCI irq %d, level:%d\n", __func__, pin , level);
359 
360     qemu_set_irq(pic[pin], level);
361 }
362 
e500_route_intx_pin_to_irq(void * opaque,int pin)363 static PCIINTxRoute e500_route_intx_pin_to_irq(void *opaque, int pin)
364 {
365     PCIINTxRoute route;
366     PPCE500PCIState *s = opaque;
367 
368     route.mode = PCI_INTX_ENABLED;
369     route.irq = s->irq_num[pin];
370 
371     pci_debug("%s: PCI irq-pin = %d, irq_num= %d\n", __func__, pin, route.irq);
372     return route;
373 }
374 
375 static const VMStateDescription vmstate_pci_outbound = {
376     .name = "pci_outbound",
377     .version_id = 0,
378     .minimum_version_id = 0,
379     .fields = (const VMStateField[]) {
380         VMSTATE_UINT32(potar, struct pci_outbound),
381         VMSTATE_UINT32(potear, struct pci_outbound),
382         VMSTATE_UINT32(powbar, struct pci_outbound),
383         VMSTATE_UINT32(powar, struct pci_outbound),
384         VMSTATE_END_OF_LIST()
385     }
386 };
387 
388 static const VMStateDescription vmstate_pci_inbound = {
389     .name = "pci_inbound",
390     .version_id = 0,
391     .minimum_version_id = 0,
392     .fields = (const VMStateField[]) {
393         VMSTATE_UINT32(pitar, struct pci_inbound),
394         VMSTATE_UINT32(piwbar, struct pci_inbound),
395         VMSTATE_UINT32(piwbear, struct pci_inbound),
396         VMSTATE_UINT32(piwar, struct pci_inbound),
397         VMSTATE_END_OF_LIST()
398     }
399 };
400 
401 static const VMStateDescription vmstate_ppce500_pci = {
402     .name = "ppce500_pci",
403     .version_id = 1,
404     .minimum_version_id = 1,
405     .fields = (const VMStateField[]) {
406         VMSTATE_STRUCT_ARRAY(pob, PPCE500PCIState, PPCE500_PCI_NR_POBS, 1,
407                              vmstate_pci_outbound, struct pci_outbound),
408         VMSTATE_STRUCT_ARRAY(pib, PPCE500PCIState, PPCE500_PCI_NR_PIBS, 1,
409                              vmstate_pci_inbound, struct pci_inbound),
410         VMSTATE_UINT32(gasket_time, PPCE500PCIState),
411         VMSTATE_END_OF_LIST()
412     }
413 };
414 
415 
e500_pcihost_bridge_realize(PCIDevice * d,Error ** errp)416 static void e500_pcihost_bridge_realize(PCIDevice *d, Error **errp)
417 {
418     PPCE500PCIBridgeState *b = PPC_E500_PCI_BRIDGE(d);
419     SysBusDevice *ccsr = SYS_BUS_DEVICE(
420         object_resolve_path_component(qdev_get_machine(), "e500-ccsr"));
421     MemoryRegion *ccsr_space = sysbus_mmio_get_region(ccsr, 0);
422 
423     memory_region_init_alias(&b->bar0, OBJECT(ccsr), "e500-pci-bar0",
424                              ccsr_space, 0, int128_get64(ccsr_space->size));
425     pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &b->bar0);
426 }
427 
e500_pcihost_set_iommu(PCIBus * bus,void * opaque,int devfn)428 static AddressSpace *e500_pcihost_set_iommu(PCIBus *bus, void *opaque,
429                                             int devfn)
430 {
431     PPCE500PCIState *s = opaque;
432 
433     return &s->bm_as;
434 }
435 
436 static const PCIIOMMUOps ppce500_iommu_ops = {
437     .get_address_space = e500_pcihost_set_iommu,
438 };
439 
e500_pcihost_realize(DeviceState * dev,Error ** errp)440 static void e500_pcihost_realize(DeviceState *dev, Error **errp)
441 {
442     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
443     PCIHostState *h;
444     PPCE500PCIState *s;
445     PCIBus *b;
446     int i;
447 
448     h = PCI_HOST_BRIDGE(dev);
449     s = PPC_E500_PCI_HOST_BRIDGE(dev);
450 
451     for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
452         sysbus_init_irq(sbd, &s->irq[i]);
453     }
454 
455     for (i = 0; i < PCI_NUM_PINS; i++) {
456         s->irq_num[i] = s->first_pin_irq + i;
457     }
458 
459     memory_region_init(&s->pio, OBJECT(s), "pci-pio", PCIE500_PCI_IOLEN);
460     memory_region_init(&s->busmem, OBJECT(s), "pci bus memory", UINT64_MAX);
461 
462     /* PIO lives at the bottom of our bus space */
463     memory_region_add_subregion_overlap(&s->busmem, 0, &s->pio, -2);
464 
465     b = pci_register_root_bus(dev, NULL, mpc85xx_pci_set_irq,
466                               mpc85xx_pci_map_irq, s, &s->busmem, &s->pio,
467                               PCI_DEVFN(s->first_slot, 0), 4, TYPE_PCI_BUS);
468     h->bus = b;
469 
470     /* Set up PCI view of memory */
471     memory_region_init(&s->bm, OBJECT(s), "bm-e500", UINT64_MAX);
472     memory_region_add_subregion(&s->bm, 0x0, &s->busmem);
473     address_space_init(&s->bm_as, &s->bm, "pci-bm");
474     pci_setup_iommu(b, &ppce500_iommu_ops, s);
475 
476     pci_create_simple(b, 0, TYPE_PPC_E500_PCI_BRIDGE);
477 
478     memory_region_init(&s->container, OBJECT(h), "pci-container", PCIE500_ALL_SIZE);
479     memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_be_ops, h,
480                           "pci-conf-idx", 4);
481     memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, h,
482                           "pci-conf-data", 4);
483     memory_region_init_io(&s->iomem, OBJECT(s), &e500_pci_reg_ops, s,
484                           "pci.reg", PCIE500_REG_SIZE);
485     memory_region_add_subregion(&s->container, PCIE500_CFGADDR, &h->conf_mem);
486     memory_region_add_subregion(&s->container, PCIE500_CFGDATA, &h->data_mem);
487     memory_region_add_subregion(&s->container, PCIE500_REG_BASE, &s->iomem);
488     sysbus_init_mmio(sbd, &s->container);
489     pci_bus_set_route_irq_fn(b, e500_route_intx_pin_to_irq);
490 }
491 
e500_host_bridge_class_init(ObjectClass * klass,const void * data)492 static void e500_host_bridge_class_init(ObjectClass *klass, const void *data)
493 {
494     DeviceClass *dc = DEVICE_CLASS(klass);
495     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
496 
497     k->realize = e500_pcihost_bridge_realize;
498     k->vendor_id = PCI_VENDOR_ID_FREESCALE;
499     k->device_id = PCI_DEVICE_ID_MPC8533E;
500     k->class_id = PCI_CLASS_PROCESSOR_POWERPC;
501     dc->desc = "Host bridge";
502     /*
503      * PCI-facing part of the host bridge, not usable without the
504      * host-facing part, which can't be device_add'ed, yet.
505      */
506     dc->user_creatable = false;
507 }
508 
509 static const Property pcihost_properties[] = {
510     DEFINE_PROP_UINT32("first_slot", PPCE500PCIState, first_slot, 0x11),
511     DEFINE_PROP_UINT32("first_pin_irq", PPCE500PCIState, first_pin_irq, 0x1),
512 };
513 
e500_pcihost_class_init(ObjectClass * klass,const void * data)514 static void e500_pcihost_class_init(ObjectClass *klass, const void *data)
515 {
516     DeviceClass *dc = DEVICE_CLASS(klass);
517 
518     dc->realize = e500_pcihost_realize;
519     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
520     device_class_set_props(dc, pcihost_properties);
521     dc->vmsd = &vmstate_ppce500_pci;
522 }
523 
524 static const TypeInfo e500_pci_types[] = {
525     {
526         .name          = TYPE_PPC_E500_PCI_BRIDGE,
527         .parent        = TYPE_PCI_DEVICE,
528         .instance_size = sizeof(PPCE500PCIBridgeState),
529         .class_init    = e500_host_bridge_class_init,
530         .interfaces    = (const InterfaceInfo[]) {
531             { INTERFACE_CONVENTIONAL_PCI_DEVICE },
532             { },
533         },
534     },
535     {
536         .name          = TYPE_PPC_E500_PCI_HOST_BRIDGE,
537         .parent        = TYPE_PCI_HOST_BRIDGE,
538         .instance_size = sizeof(PPCE500PCIState),
539         .class_init    = e500_pcihost_class_init,
540     },
541 };
542 
543 DEFINE_TYPES(e500_pci_types)
544