1 /*
2 * pcie_sriov.c:
3 *
4 * Implementation of SR/IOV emulation support.
5 *
6 * Copyright (c) 2015-2017 Knut Omang <knut.omang@oracle.com>
7 *
8 * This work is licensed under the terms of the GNU GPL, version 2 or later.
9 * See the COPYING file in the top-level directory.
10 *
11 */
12
13 #include "qemu/osdep.h"
14 #include "hw/pci/pci_device.h"
15 #include "hw/pci/pcie.h"
16 #include "hw/pci/pci_bus.h"
17 #include "hw/qdev-properties.h"
18 #include "qemu/range.h"
19 #include "qapi/error.h"
20 #include "trace.h"
21
22 static GHashTable *pfs;
23
unparent_vfs(PCIDevice * dev,uint16_t total_vfs)24 static void unparent_vfs(PCIDevice *dev, uint16_t total_vfs)
25 {
26 for (uint16_t i = 0; i < total_vfs; i++) {
27 PCIDevice *vf = dev->exp.sriov_pf.vf[i];
28 object_unparent(OBJECT(vf));
29 object_unref(OBJECT(vf));
30 }
31 g_free(dev->exp.sriov_pf.vf);
32 dev->exp.sriov_pf.vf = NULL;
33 }
34
register_vfs(PCIDevice * dev)35 static void register_vfs(PCIDevice *dev)
36 {
37 uint16_t num_vfs;
38 uint16_t i;
39 uint16_t sriov_cap = dev->exp.sriov_cap;
40
41 assert(sriov_cap > 0);
42 num_vfs = pci_get_word(dev->config + sriov_cap + PCI_SRIOV_NUM_VF);
43
44 trace_sriov_register_vfs(dev->name, PCI_SLOT(dev->devfn),
45 PCI_FUNC(dev->devfn), num_vfs);
46 for (i = 0; i < num_vfs; i++) {
47 pci_set_enabled(dev->exp.sriov_pf.vf[i], true);
48 }
49
50 pci_set_word(dev->wmask + sriov_cap + PCI_SRIOV_NUM_VF, 0);
51 }
52
unregister_vfs(PCIDevice * dev)53 static void unregister_vfs(PCIDevice *dev)
54 {
55 uint8_t *cfg = dev->config + dev->exp.sriov_cap;
56 uint16_t i;
57
58 trace_sriov_unregister_vfs(dev->name, PCI_SLOT(dev->devfn),
59 PCI_FUNC(dev->devfn));
60 for (i = 0; i < pci_get_word(cfg + PCI_SRIOV_TOTAL_VF); i++) {
61 pci_set_enabled(dev->exp.sriov_pf.vf[i], false);
62 }
63
64 pci_set_word(dev->wmask + dev->exp.sriov_cap + PCI_SRIOV_NUM_VF, 0xffff);
65 }
66
consume_config(PCIDevice * dev)67 static void consume_config(PCIDevice *dev)
68 {
69 uint8_t *cfg = dev->config + dev->exp.sriov_cap;
70
71 if (pci_get_word(cfg + PCI_SRIOV_CTRL) & PCI_SRIOV_CTRL_VFE) {
72 register_vfs(dev);
73 } else {
74 uint8_t *wmask = dev->wmask + dev->exp.sriov_cap;
75 uint16_t num_vfs = pci_get_word(cfg + PCI_SRIOV_NUM_VF);
76 uint16_t wmask_val = PCI_SRIOV_CTRL_MSE | PCI_SRIOV_CTRL_ARI;
77
78 unregister_vfs(dev);
79
80 if (num_vfs <= pci_get_word(cfg + PCI_SRIOV_TOTAL_VF)) {
81 wmask_val |= PCI_SRIOV_CTRL_VFE;
82 }
83
84 pci_set_word(wmask + PCI_SRIOV_CTRL, wmask_val);
85 }
86 }
87
pcie_sriov_pf_init_common(PCIDevice * dev,uint16_t offset,uint16_t vf_dev_id,uint16_t init_vfs,uint16_t total_vfs,uint16_t vf_offset,uint16_t vf_stride,Error ** errp)88 static bool pcie_sriov_pf_init_common(PCIDevice *dev, uint16_t offset,
89 uint16_t vf_dev_id, uint16_t init_vfs,
90 uint16_t total_vfs, uint16_t vf_offset,
91 uint16_t vf_stride, Error **errp)
92 {
93 int32_t devfn = dev->devfn + vf_offset;
94 uint8_t *cfg = dev->config + offset;
95 uint8_t *wmask;
96
97 if (!pci_is_express(dev)) {
98 error_setg(errp, "PCI Express is required for SR-IOV PF");
99 return false;
100 }
101
102 if (pci_is_vf(dev)) {
103 error_setg(errp, "a device cannot be a SR-IOV PF and a VF at the same time");
104 return false;
105 }
106
107 if (total_vfs &&
108 (uint32_t)devfn + (uint32_t)(total_vfs - 1) * vf_stride >= PCI_DEVFN_MAX) {
109 error_setg(errp, "VF addr overflows");
110 return false;
111 }
112
113 pcie_add_capability(dev, PCI_EXT_CAP_ID_SRIOV, 1,
114 offset, PCI_EXT_CAP_SRIOV_SIZEOF);
115 dev->exp.sriov_cap = offset;
116 dev->exp.sriov_pf.vf = NULL;
117
118 pci_set_word(cfg + PCI_SRIOV_VF_OFFSET, vf_offset);
119 pci_set_word(cfg + PCI_SRIOV_VF_STRIDE, vf_stride);
120
121 /*
122 * Mandatory page sizes to support.
123 * Device implementations can call pcie_sriov_pf_add_sup_pgsize()
124 * to set more bits:
125 */
126 pci_set_word(cfg + PCI_SRIOV_SUP_PGSIZE, SRIOV_SUP_PGSIZE_MINREQ);
127
128 /*
129 * Default is to use 4K pages, software can modify it
130 * to any of the supported bits
131 */
132 pci_set_word(cfg + PCI_SRIOV_SYS_PGSIZE, 0x1);
133
134 /* Set up device ID and initial/total number of VFs available */
135 pci_set_word(cfg + PCI_SRIOV_VF_DID, vf_dev_id);
136 pci_set_word(cfg + PCI_SRIOV_INITIAL_VF, init_vfs);
137 pci_set_word(cfg + PCI_SRIOV_TOTAL_VF, total_vfs);
138 pci_set_word(cfg + PCI_SRIOV_NUM_VF, 0);
139
140 /* Write enable control bits */
141 wmask = dev->wmask + offset;
142 pci_set_word(wmask + PCI_SRIOV_CTRL,
143 PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE | PCI_SRIOV_CTRL_ARI);
144 pci_set_word(wmask + PCI_SRIOV_NUM_VF, 0xffff);
145 pci_set_word(wmask + PCI_SRIOV_SYS_PGSIZE, 0x553);
146
147 qdev_prop_set_bit(&dev->qdev, "multifunction", true);
148
149 return true;
150 }
151
pcie_sriov_pf_init(PCIDevice * dev,uint16_t offset,const char * vfname,uint16_t vf_dev_id,uint16_t init_vfs,uint16_t total_vfs,uint16_t vf_offset,uint16_t vf_stride,Error ** errp)152 bool pcie_sriov_pf_init(PCIDevice *dev, uint16_t offset,
153 const char *vfname, uint16_t vf_dev_id,
154 uint16_t init_vfs, uint16_t total_vfs,
155 uint16_t vf_offset, uint16_t vf_stride,
156 Error **errp)
157 {
158 BusState *bus = qdev_get_parent_bus(&dev->qdev);
159 int32_t devfn = dev->devfn + vf_offset;
160
161 if (pfs && g_hash_table_contains(pfs, dev->qdev.id)) {
162 error_setg(errp, "attaching user-created SR-IOV VF unsupported");
163 return false;
164 }
165
166 if (!pcie_sriov_pf_init_common(dev, offset, vf_dev_id, init_vfs,
167 total_vfs, vf_offset, vf_stride, errp)) {
168 return false;
169 }
170
171 dev->exp.sriov_pf.vf = g_new(PCIDevice *, total_vfs);
172
173 for (uint16_t i = 0; i < total_vfs; i++) {
174 PCIDevice *vf = pci_new(devfn, vfname);
175 vf->exp.sriov_vf.pf = dev;
176 vf->exp.sriov_vf.vf_number = i;
177
178 if (!qdev_realize(&vf->qdev, bus, errp)) {
179 object_unparent(OBJECT(vf));
180 object_unref(vf);
181 unparent_vfs(dev, i);
182 return false;
183 }
184
185 /* set vid/did according to sr/iov spec - they are not used */
186 pci_config_set_vendor_id(vf->config, 0xffff);
187 pci_config_set_device_id(vf->config, 0xffff);
188
189 dev->exp.sriov_pf.vf[i] = vf;
190 devfn += vf_stride;
191 }
192
193 return true;
194 }
195
pcie_sriov_pf_exit(PCIDevice * dev)196 void pcie_sriov_pf_exit(PCIDevice *dev)
197 {
198 uint8_t *cfg = dev->config + dev->exp.sriov_cap;
199
200 if (dev->exp.sriov_pf.vf_user_created) {
201 uint16_t ven_id = pci_get_word(dev->config + PCI_VENDOR_ID);
202 uint16_t total_vfs = pci_get_word(dev->config + PCI_SRIOV_TOTAL_VF);
203 uint16_t vf_dev_id = pci_get_word(dev->config + PCI_SRIOV_VF_DID);
204
205 unregister_vfs(dev);
206
207 for (uint16_t i = 0; i < total_vfs; i++) {
208 dev->exp.sriov_pf.vf[i]->exp.sriov_vf.pf = NULL;
209
210 pci_config_set_vendor_id(dev->exp.sriov_pf.vf[i]->config, ven_id);
211 pci_config_set_device_id(dev->exp.sriov_pf.vf[i]->config, vf_dev_id);
212 }
213 } else {
214 unparent_vfs(dev, pci_get_word(cfg + PCI_SRIOV_TOTAL_VF));
215 }
216 }
217
pcie_sriov_pf_init_vf_bar(PCIDevice * dev,int region_num,uint8_t type,dma_addr_t size)218 void pcie_sriov_pf_init_vf_bar(PCIDevice *dev, int region_num,
219 uint8_t type, dma_addr_t size)
220 {
221 uint32_t addr;
222 uint64_t wmask;
223 uint16_t sriov_cap = dev->exp.sriov_cap;
224
225 assert(sriov_cap > 0);
226 assert(region_num >= 0);
227 assert(region_num < PCI_NUM_REGIONS);
228 assert(region_num != PCI_ROM_SLOT);
229
230 wmask = ~(size - 1);
231 addr = sriov_cap + PCI_SRIOV_BAR + region_num * 4;
232
233 pci_set_long(dev->config + addr, type);
234 if (!(type & PCI_BASE_ADDRESS_SPACE_IO) &&
235 type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
236 pci_set_quad(dev->wmask + addr, wmask);
237 pci_set_quad(dev->cmask + addr, ~0ULL);
238 } else {
239 pci_set_long(dev->wmask + addr, wmask & 0xffffffff);
240 pci_set_long(dev->cmask + addr, 0xffffffff);
241 }
242 dev->exp.sriov_pf.vf_bar_type[region_num] = type;
243 }
244
pcie_sriov_vf_register_bar(PCIDevice * dev,int region_num,MemoryRegion * memory)245 void pcie_sriov_vf_register_bar(PCIDevice *dev, int region_num,
246 MemoryRegion *memory)
247 {
248 uint8_t type;
249
250 assert(dev->exp.sriov_vf.pf);
251 type = dev->exp.sriov_vf.pf->exp.sriov_pf.vf_bar_type[region_num];
252
253 return pci_register_bar(dev, region_num, type, memory);
254 }
255
compare_vf_devfns(gconstpointer a,gconstpointer b)256 static gint compare_vf_devfns(gconstpointer a, gconstpointer b)
257 {
258 return (*(PCIDevice **)a)->devfn - (*(PCIDevice **)b)->devfn;
259 }
260
pcie_sriov_pf_init_from_user_created_vfs(PCIDevice * dev,uint16_t offset,Error ** errp)261 int16_t pcie_sriov_pf_init_from_user_created_vfs(PCIDevice *dev,
262 uint16_t offset,
263 Error **errp)
264 {
265 GPtrArray *pf;
266 PCIDevice **vfs;
267 BusState *bus = qdev_get_parent_bus(DEVICE(dev));
268 uint16_t ven_id = pci_get_word(dev->config + PCI_VENDOR_ID);
269 uint16_t size = PCI_EXT_CAP_SRIOV_SIZEOF;
270 uint16_t vf_dev_id;
271 uint16_t vf_offset;
272 uint16_t vf_stride;
273 uint16_t i;
274
275 if (!pfs || !dev->qdev.id) {
276 return 0;
277 }
278
279 pf = g_hash_table_lookup(pfs, dev->qdev.id);
280 if (!pf) {
281 return 0;
282 }
283
284 if (pf->len > UINT16_MAX) {
285 error_setg(errp, "too many VFs");
286 return -1;
287 }
288
289 g_ptr_array_sort(pf, compare_vf_devfns);
290 vfs = (void *)pf->pdata;
291
292 if (vfs[0]->devfn <= dev->devfn) {
293 error_setg(errp, "a VF function number is less than the PF function number");
294 return -1;
295 }
296
297 vf_dev_id = pci_get_word(vfs[0]->config + PCI_DEVICE_ID);
298 vf_offset = vfs[0]->devfn - dev->devfn;
299 vf_stride = pf->len < 2 ? 0 : vfs[1]->devfn - vfs[0]->devfn;
300
301 for (i = 0; i < pf->len; i++) {
302 if (bus != qdev_get_parent_bus(&vfs[i]->qdev)) {
303 error_setg(errp, "SR-IOV VF parent bus mismatches with PF");
304 return -1;
305 }
306
307 if (ven_id != pci_get_word(vfs[i]->config + PCI_VENDOR_ID)) {
308 error_setg(errp, "SR-IOV VF vendor ID mismatches with PF");
309 return -1;
310 }
311
312 if (vf_dev_id != pci_get_word(vfs[i]->config + PCI_DEVICE_ID)) {
313 error_setg(errp, "inconsistent SR-IOV VF device IDs");
314 return -1;
315 }
316
317 for (size_t j = 0; j < PCI_NUM_REGIONS; j++) {
318 if (vfs[i]->io_regions[j].size != vfs[0]->io_regions[j].size ||
319 vfs[i]->io_regions[j].type != vfs[0]->io_regions[j].type) {
320 error_setg(errp, "inconsistent SR-IOV BARs");
321 return -1;
322 }
323 }
324
325 if (vfs[i]->devfn - vfs[0]->devfn != vf_stride * i) {
326 error_setg(errp, "inconsistent SR-IOV stride");
327 return -1;
328 }
329 }
330
331 if (!pcie_sriov_pf_init_common(dev, offset, vf_dev_id, pf->len,
332 pf->len, vf_offset, vf_stride, errp)) {
333 return -1;
334 }
335
336 if (!pcie_find_capability(dev, PCI_EXT_CAP_ID_ARI)) {
337 pcie_ari_init(dev, offset + size);
338 size += PCI_ARI_SIZEOF;
339 }
340
341 for (i = 0; i < pf->len; i++) {
342 vfs[i]->exp.sriov_vf.pf = dev;
343 vfs[i]->exp.sriov_vf.vf_number = i;
344
345 /* set vid/did according to sr/iov spec - they are not used */
346 pci_config_set_vendor_id(vfs[i]->config, 0xffff);
347 pci_config_set_device_id(vfs[i]->config, 0xffff);
348 }
349
350 dev->exp.sriov_pf.vf = vfs;
351 dev->exp.sriov_pf.vf_user_created = true;
352
353 for (i = 0; i < PCI_NUM_REGIONS; i++) {
354 PCIIORegion *region = &vfs[0]->io_regions[i];
355
356 if (region->size) {
357 pcie_sriov_pf_init_vf_bar(dev, i, region->type, region->size);
358 }
359 }
360
361 return size;
362 }
363
pcie_sriov_register_device(PCIDevice * dev,Error ** errp)364 bool pcie_sriov_register_device(PCIDevice *dev, Error **errp)
365 {
366 if (!dev->exp.sriov_pf.vf && dev->qdev.id &&
367 pfs && g_hash_table_contains(pfs, dev->qdev.id)) {
368 error_setg(errp, "attaching user-created SR-IOV VF unsupported");
369 return false;
370 }
371
372 if (dev->sriov_pf) {
373 PCIDevice *pci_pf;
374 GPtrArray *pf;
375
376 if (!PCI_DEVICE_GET_CLASS(dev)->sriov_vf_user_creatable) {
377 error_setg(errp, "user cannot create SR-IOV VF with this device type");
378 return false;
379 }
380
381 if (!pci_is_express(dev)) {
382 error_setg(errp, "PCI Express is required for SR-IOV VF");
383 return false;
384 }
385
386 if (!pci_qdev_find_device(dev->sriov_pf, &pci_pf)) {
387 error_setg(errp, "PCI device specified as SR-IOV PF already exists");
388 return false;
389 }
390
391 if (!pfs) {
392 pfs = g_hash_table_new_full(g_str_hash, g_str_equal, g_free, NULL);
393 }
394
395 pf = g_hash_table_lookup(pfs, dev->sriov_pf);
396 if (!pf) {
397 pf = g_ptr_array_new();
398 g_hash_table_insert(pfs, g_strdup(dev->sriov_pf), pf);
399 }
400
401 g_ptr_array_add(pf, dev);
402 }
403
404 return true;
405 }
406
pcie_sriov_unregister_device(PCIDevice * dev)407 void pcie_sriov_unregister_device(PCIDevice *dev)
408 {
409 if (dev->sriov_pf && pfs) {
410 GPtrArray *pf = g_hash_table_lookup(pfs, dev->sriov_pf);
411
412 if (pf) {
413 g_ptr_array_remove_fast(pf, dev);
414
415 if (!pf->len) {
416 g_hash_table_remove(pfs, dev->sriov_pf);
417 g_ptr_array_free(pf, FALSE);
418 }
419 }
420 }
421 }
422
pcie_sriov_config_write(PCIDevice * dev,uint32_t address,uint32_t val,int len)423 void pcie_sriov_config_write(PCIDevice *dev, uint32_t address,
424 uint32_t val, int len)
425 {
426 uint32_t off;
427 uint16_t sriov_cap = dev->exp.sriov_cap;
428
429 if (!sriov_cap || address < sriov_cap) {
430 return;
431 }
432 off = address - sriov_cap;
433 if (off >= PCI_EXT_CAP_SRIOV_SIZEOF) {
434 return;
435 }
436
437 trace_sriov_config_write(dev->name, PCI_SLOT(dev->devfn),
438 PCI_FUNC(dev->devfn), off, val, len);
439
440 consume_config(dev);
441 }
442
pcie_sriov_pf_post_load(PCIDevice * dev)443 void pcie_sriov_pf_post_load(PCIDevice *dev)
444 {
445 if (dev->exp.sriov_cap) {
446 consume_config(dev);
447 }
448 }
449
450
451 /* Reset SR/IOV */
pcie_sriov_pf_reset(PCIDevice * dev)452 void pcie_sriov_pf_reset(PCIDevice *dev)
453 {
454 uint16_t sriov_cap = dev->exp.sriov_cap;
455 if (!sriov_cap) {
456 return;
457 }
458
459 pci_set_word(dev->config + sriov_cap + PCI_SRIOV_CTRL, 0);
460 unregister_vfs(dev);
461
462 pci_set_word(dev->config + sriov_cap + PCI_SRIOV_NUM_VF, 0);
463 pci_set_word(dev->wmask + sriov_cap + PCI_SRIOV_CTRL,
464 PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE | PCI_SRIOV_CTRL_ARI);
465
466 /*
467 * Default is to use 4K pages, software can modify it
468 * to any of the supported bits
469 */
470 pci_set_word(dev->config + sriov_cap + PCI_SRIOV_SYS_PGSIZE, 0x1);
471
472 for (uint16_t i = 0; i < PCI_NUM_REGIONS; i++) {
473 pci_set_quad(dev->config + sriov_cap + PCI_SRIOV_BAR + i * 4,
474 dev->exp.sriov_pf.vf_bar_type[i]);
475 }
476 }
477
478 /* Add optional supported page sizes to the mask of supported page sizes */
pcie_sriov_pf_add_sup_pgsize(PCIDevice * dev,uint16_t opt_sup_pgsize)479 void pcie_sriov_pf_add_sup_pgsize(PCIDevice *dev, uint16_t opt_sup_pgsize)
480 {
481 uint8_t *cfg = dev->config + dev->exp.sriov_cap;
482 uint8_t *wmask = dev->wmask + dev->exp.sriov_cap;
483
484 uint16_t sup_pgsize = pci_get_word(cfg + PCI_SRIOV_SUP_PGSIZE);
485
486 sup_pgsize |= opt_sup_pgsize;
487
488 /*
489 * Make sure the new bits are set, and that system page size
490 * also can be set to any of the new values according to spec:
491 */
492 pci_set_word(cfg + PCI_SRIOV_SUP_PGSIZE, sup_pgsize);
493 pci_set_word(wmask + PCI_SRIOV_SYS_PGSIZE, sup_pgsize);
494 }
495
496
pcie_sriov_vf_number(PCIDevice * dev)497 uint16_t pcie_sriov_vf_number(PCIDevice *dev)
498 {
499 assert(dev->exp.sriov_vf.pf);
500 return dev->exp.sriov_vf.vf_number;
501 }
502
pcie_sriov_get_pf(PCIDevice * dev)503 PCIDevice *pcie_sriov_get_pf(PCIDevice *dev)
504 {
505 return dev->exp.sriov_vf.pf;
506 }
507
pcie_sriov_get_vf_at_index(PCIDevice * dev,int n)508 PCIDevice *pcie_sriov_get_vf_at_index(PCIDevice *dev, int n)
509 {
510 assert(!pci_is_vf(dev));
511 if (n < pcie_sriov_num_vfs(dev)) {
512 return dev->exp.sriov_pf.vf[n];
513 }
514 return NULL;
515 }
516
pcie_sriov_num_vfs(PCIDevice * dev)517 uint16_t pcie_sriov_num_vfs(PCIDevice *dev)
518 {
519 uint16_t sriov_cap = dev->exp.sriov_cap;
520 uint8_t *cfg = dev->config + sriov_cap;
521
522 return sriov_cap &&
523 (pci_get_word(cfg + PCI_SRIOV_CTRL) & PCI_SRIOV_CTRL_VFE) ?
524 pci_get_word(cfg + PCI_SRIOV_NUM_VF) : 0;
525 }
526