1 /*
2 * pcie.c
3 *
4 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
5 * VA Linux Systems Japan K.K.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
23 #include "hw/pci/pci_bridge.h"
24 #include "hw/pci/pcie.h"
25 #include "hw/pci/msix.h"
26 #include "hw/pci/msi.h"
27 #include "hw/pci/pci_bus.h"
28 #include "hw/pci/pcie_regs.h"
29 #include "hw/pci/pcie_port.h"
30 #include "qemu/range.h"
31
32 //#define DEBUG_PCIE
33 #ifdef DEBUG_PCIE
34 # define PCIE_DPRINTF(fmt, ...) \
35 fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__)
36 #else
37 # define PCIE_DPRINTF(fmt, ...) do {} while (0)
38 #endif
39 #define PCIE_DEV_PRINTF(dev, fmt, ...) \
40 PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__)
41
pcie_sltctl_powered_off(uint16_t sltctl)42 static bool pcie_sltctl_powered_off(uint16_t sltctl)
43 {
44 return (sltctl & PCI_EXP_SLTCTL_PCC) == PCI_EXP_SLTCTL_PWR_OFF
45 && (sltctl & PCI_EXP_SLTCTL_PIC) == PCI_EXP_SLTCTL_PWR_IND_OFF;
46 }
47
48 /***************************************************************************
49 * pci express capability helper functions
50 */
51
52 static void
pcie_cap_v1_fill(PCIDevice * dev,uint8_t port,uint8_t type,uint8_t version)53 pcie_cap_v1_fill(PCIDevice *dev, uint8_t port, uint8_t type, uint8_t version)
54 {
55 uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
56 uint8_t *cmask = dev->cmask + dev->exp.exp_cap;
57
58 /* capability register
59 interrupt message number defaults to 0 */
60 pci_set_word(exp_cap + PCI_EXP_FLAGS,
61 ((type << PCI_EXP_FLAGS_TYPE_SHIFT) & PCI_EXP_FLAGS_TYPE) |
62 version);
63
64 /* device capability register
65 * table 7-12:
66 * roll based error reporting bit must be set by all
67 * Functions conforming to the ECN, PCI Express Base
68 * Specification, Revision 1.1., or subsequent PCI Express Base
69 * Specification revisions.
70 */
71 pci_set_long(exp_cap + PCI_EXP_DEVCAP, PCI_EXP_DEVCAP_RBER);
72
73 pci_set_long(exp_cap + PCI_EXP_LNKCAP,
74 (port << PCI_EXP_LNKCAP_PN_SHIFT) |
75 PCI_EXP_LNKCAP_ASPMS_0S |
76 QEMU_PCI_EXP_LNKCAP_MLW(QEMU_PCI_EXP_LNK_X1) |
77 QEMU_PCI_EXP_LNKCAP_MLS(QEMU_PCI_EXP_LNK_2_5GT));
78
79 pci_set_word(exp_cap + PCI_EXP_LNKSTA,
80 QEMU_PCI_EXP_LNKSTA_NLW(QEMU_PCI_EXP_LNK_X1) |
81 QEMU_PCI_EXP_LNKSTA_CLS(QEMU_PCI_EXP_LNK_2_5GT));
82
83 /* We changed link status bits over time, and changing them across
84 * migrations is generally fine as hardware changes them too.
85 * Let's not bother checking.
86 */
87 pci_set_word(cmask + PCI_EXP_LNKSTA, 0);
88 }
89
pcie_cap_fill_slot_lnk(PCIDevice * dev)90 static void pcie_cap_fill_slot_lnk(PCIDevice *dev)
91 {
92 PCIESlot *s = (PCIESlot *)object_dynamic_cast(OBJECT(dev), TYPE_PCIE_SLOT);
93 uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
94
95 /* Skip anything that isn't a PCIESlot */
96 if (!s) {
97 return;
98 }
99
100 /* Clear and fill LNKCAP from what was configured above */
101 pci_long_test_and_clear_mask(exp_cap + PCI_EXP_LNKCAP,
102 PCI_EXP_LNKCAP_MLW | PCI_EXP_LNKCAP_SLS);
103 pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP,
104 QEMU_PCI_EXP_LNKCAP_MLW(s->width) |
105 QEMU_PCI_EXP_LNKCAP_MLS(s->speed));
106
107 /*
108 * Link bandwidth notification is required for all root ports and
109 * downstream ports supporting links wider than x1 or multiple link
110 * speeds.
111 */
112 if (s->width > QEMU_PCI_EXP_LNK_X1 ||
113 s->speed > QEMU_PCI_EXP_LNK_2_5GT) {
114 pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP,
115 PCI_EXP_LNKCAP_LBNC);
116 }
117
118 if (s->speed > QEMU_PCI_EXP_LNK_2_5GT) {
119 /*
120 * Hot-plug capable downstream ports and downstream ports supporting
121 * link speeds greater than 5GT/s must hardwire PCI_EXP_LNKCAP_DLLLARC
122 * to 1b. PCI_EXP_LNKCAP_DLLLARC implies PCI_EXP_LNKSTA_DLLLA, which
123 * we also hardwire to 1b here. 2.5GT/s hot-plug slots should also
124 * technically implement this, but it's not done here for compatibility.
125 */
126 pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP,
127 PCI_EXP_LNKCAP_DLLLARC);
128 /* the PCI_EXP_LNKSTA_DLLLA will be set in the hotplug function */
129
130 /*
131 * Target Link Speed defaults to the highest link speed supported by
132 * the component. 2.5GT/s devices are permitted to hardwire to zero.
133 */
134 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_LNKCTL2,
135 PCI_EXP_LNKCTL2_TLS);
136 pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKCTL2,
137 QEMU_PCI_EXP_LNKCAP_MLS(s->speed) &
138 PCI_EXP_LNKCTL2_TLS);
139 }
140
141 /*
142 * 2.5 & 5.0GT/s can be fully described by LNKCAP, but 8.0GT/s is
143 * actually a reference to the highest bit supported in this register.
144 * We assume the device supports all link speeds.
145 */
146 if (s->speed > QEMU_PCI_EXP_LNK_5GT) {
147 pci_long_test_and_clear_mask(exp_cap + PCI_EXP_LNKCAP2, ~0U);
148 pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP2,
149 PCI_EXP_LNKCAP2_SLS_2_5GB |
150 PCI_EXP_LNKCAP2_SLS_5_0GB |
151 PCI_EXP_LNKCAP2_SLS_8_0GB);
152 if (s->speed > QEMU_PCI_EXP_LNK_8GT) {
153 pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP2,
154 PCI_EXP_LNKCAP2_SLS_16_0GB);
155 }
156 }
157 }
158
pcie_cap_init(PCIDevice * dev,uint8_t offset,uint8_t type,uint8_t port,Error ** errp)159 int pcie_cap_init(PCIDevice *dev, uint8_t offset,
160 uint8_t type, uint8_t port,
161 Error **errp)
162 {
163 /* PCIe cap v2 init */
164 int pos;
165 uint8_t *exp_cap;
166
167 assert(pci_is_express(dev));
168
169 pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset,
170 PCI_EXP_VER2_SIZEOF, errp);
171 if (pos < 0) {
172 return pos;
173 }
174 dev->exp.exp_cap = pos;
175 exp_cap = dev->config + pos;
176
177 /* Filling values common with v1 */
178 pcie_cap_v1_fill(dev, port, type, PCI_EXP_FLAGS_VER2);
179
180 /* Fill link speed and width options */
181 pcie_cap_fill_slot_lnk(dev);
182
183 /* Filling v2 specific values */
184 pci_set_long(exp_cap + PCI_EXP_DEVCAP2,
185 PCI_EXP_DEVCAP2_EFF | PCI_EXP_DEVCAP2_EETLPP);
186
187 pci_set_word(dev->wmask + pos + PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_EETLPPB);
188
189 if (dev->cap_present & QEMU_PCIE_EXTCAP_INIT) {
190 /* read-only to behave like a 'NULL' Extended Capability Header */
191 pci_set_long(dev->wmask + PCI_CONFIG_SPACE_SIZE, 0);
192 }
193
194 return pos;
195 }
196
pcie_cap_v1_init(PCIDevice * dev,uint8_t offset,uint8_t type,uint8_t port)197 int pcie_cap_v1_init(PCIDevice *dev, uint8_t offset, uint8_t type,
198 uint8_t port)
199 {
200 /* PCIe cap v1 init */
201 int pos;
202 Error *local_err = NULL;
203
204 assert(pci_is_express(dev));
205
206 pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset,
207 PCI_EXP_VER1_SIZEOF, &local_err);
208 if (pos < 0) {
209 error_report_err(local_err);
210 return pos;
211 }
212 dev->exp.exp_cap = pos;
213
214 pcie_cap_v1_fill(dev, port, type, PCI_EXP_FLAGS_VER1);
215
216 return pos;
217 }
218
219 static int
pcie_endpoint_cap_common_init(PCIDevice * dev,uint8_t offset,uint8_t cap_size)220 pcie_endpoint_cap_common_init(PCIDevice *dev, uint8_t offset, uint8_t cap_size)
221 {
222 uint8_t type = PCI_EXP_TYPE_ENDPOINT;
223 Error *local_err = NULL;
224 int ret;
225
226 /*
227 * Windows guests will report Code 10, device cannot start, if
228 * a regular Endpoint type is exposed on a root complex. These
229 * should instead be Root Complex Integrated Endpoints.
230 */
231 if (pci_bus_is_express(pci_get_bus(dev))
232 && pci_bus_is_root(pci_get_bus(dev))) {
233 type = PCI_EXP_TYPE_RC_END;
234 }
235
236 if (cap_size == PCI_EXP_VER1_SIZEOF) {
237 return pcie_cap_v1_init(dev, offset, type, 0);
238 } else {
239 ret = pcie_cap_init(dev, offset, type, 0, &local_err);
240
241 if (ret < 0) {
242 error_report_err(local_err);
243 }
244
245 return ret;
246 }
247 }
248
pcie_endpoint_cap_init(PCIDevice * dev,uint8_t offset)249 int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset)
250 {
251 return pcie_endpoint_cap_common_init(dev, offset, PCI_EXP_VER2_SIZEOF);
252 }
253
pcie_endpoint_cap_v1_init(PCIDevice * dev,uint8_t offset)254 int pcie_endpoint_cap_v1_init(PCIDevice *dev, uint8_t offset)
255 {
256 return pcie_endpoint_cap_common_init(dev, offset, PCI_EXP_VER1_SIZEOF);
257 }
258
pcie_cap_exit(PCIDevice * dev)259 void pcie_cap_exit(PCIDevice *dev)
260 {
261 pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER2_SIZEOF);
262 }
263
pcie_cap_v1_exit(PCIDevice * dev)264 void pcie_cap_v1_exit(PCIDevice *dev)
265 {
266 pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER1_SIZEOF);
267 }
268
pcie_cap_get_type(const PCIDevice * dev)269 uint8_t pcie_cap_get_type(const PCIDevice *dev)
270 {
271 uint32_t pos = dev->exp.exp_cap;
272 assert(pos > 0);
273 return (pci_get_word(dev->config + pos + PCI_EXP_FLAGS) &
274 PCI_EXP_FLAGS_TYPE) >> PCI_EXP_FLAGS_TYPE_SHIFT;
275 }
276
pcie_cap_get_version(const PCIDevice * dev)277 uint8_t pcie_cap_get_version(const PCIDevice *dev)
278 {
279 uint32_t pos = dev->exp.exp_cap;
280 assert(pos > 0);
281 return pci_get_word(dev->config + pos + PCI_EXP_FLAGS) & PCI_EXP_FLAGS_VERS;
282 }
283
284 /* MSI/MSI-X */
285 /* pci express interrupt message number */
286 /* 7.8.2 PCI Express Capabilities Register: Interrupt Message Number */
pcie_cap_flags_set_vector(PCIDevice * dev,uint8_t vector)287 void pcie_cap_flags_set_vector(PCIDevice *dev, uint8_t vector)
288 {
289 uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
290 assert(vector < 32);
291 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_FLAGS, PCI_EXP_FLAGS_IRQ);
292 pci_word_test_and_set_mask(exp_cap + PCI_EXP_FLAGS,
293 vector << PCI_EXP_FLAGS_IRQ_SHIFT);
294 }
295
pcie_cap_flags_get_vector(PCIDevice * dev)296 uint8_t pcie_cap_flags_get_vector(PCIDevice *dev)
297 {
298 return (pci_get_word(dev->config + dev->exp.exp_cap + PCI_EXP_FLAGS) &
299 PCI_EXP_FLAGS_IRQ) >> PCI_EXP_FLAGS_IRQ_SHIFT;
300 }
301
pcie_cap_deverr_init(PCIDevice * dev)302 void pcie_cap_deverr_init(PCIDevice *dev)
303 {
304 uint32_t pos = dev->exp.exp_cap;
305 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP,
306 PCI_EXP_DEVCAP_RBER);
307 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL,
308 PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE |
309 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
310 pci_long_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_DEVSTA,
311 PCI_EXP_DEVSTA_CED | PCI_EXP_DEVSTA_NFED |
312 PCI_EXP_DEVSTA_FED | PCI_EXP_DEVSTA_URD);
313 }
314
pcie_cap_deverr_reset(PCIDevice * dev)315 void pcie_cap_deverr_reset(PCIDevice *dev)
316 {
317 uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL;
318 pci_long_test_and_clear_mask(devctl,
319 PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE |
320 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
321 }
322
pcie_cap_lnkctl_init(PCIDevice * dev)323 void pcie_cap_lnkctl_init(PCIDevice *dev)
324 {
325 uint32_t pos = dev->exp.exp_cap;
326 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_LNKCTL,
327 PCI_EXP_LNKCTL_CCC | PCI_EXP_LNKCTL_ES);
328 }
329
pcie_cap_lnkctl_reset(PCIDevice * dev)330 void pcie_cap_lnkctl_reset(PCIDevice *dev)
331 {
332 uint8_t *lnkctl = dev->config + dev->exp.exp_cap + PCI_EXP_LNKCTL;
333 pci_long_test_and_clear_mask(lnkctl,
334 PCI_EXP_LNKCTL_CCC | PCI_EXP_LNKCTL_ES);
335 }
336
hotplug_event_update_event_status(PCIDevice * dev)337 static void hotplug_event_update_event_status(PCIDevice *dev)
338 {
339 uint32_t pos = dev->exp.exp_cap;
340 uint8_t *exp_cap = dev->config + pos;
341 uint16_t sltctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL);
342 uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
343
344 dev->exp.hpev_notified = (sltctl & PCI_EXP_SLTCTL_HPIE) &&
345 (sltsta & sltctl & PCI_EXP_HP_EV_SUPPORTED);
346 }
347
hotplug_event_notify(PCIDevice * dev)348 static void hotplug_event_notify(PCIDevice *dev)
349 {
350 bool prev = dev->exp.hpev_notified;
351
352 hotplug_event_update_event_status(dev);
353
354 if (prev == dev->exp.hpev_notified) {
355 return;
356 }
357
358 /* Note: the logic above does not take into account whether interrupts
359 * are masked. The result is that interrupt will be sent when it is
360 * subsequently unmasked. This appears to be legal: Section 6.7.3.4:
361 * The Port may optionally send an MSI when there are hot-plug events that
362 * occur while interrupt generation is disabled, and interrupt generation is
363 * subsequently enabled. */
364 if (msix_enabled(dev)) {
365 msix_notify(dev, pcie_cap_flags_get_vector(dev));
366 } else if (msi_enabled(dev)) {
367 msi_notify(dev, pcie_cap_flags_get_vector(dev));
368 } else if (pci_intx(dev) != -1) {
369 pci_set_irq(dev, dev->exp.hpev_notified);
370 }
371 }
372
hotplug_event_clear(PCIDevice * dev)373 static void hotplug_event_clear(PCIDevice *dev)
374 {
375 hotplug_event_update_event_status(dev);
376 if (!msix_enabled(dev) && !msi_enabled(dev) && pci_intx(dev) != -1 &&
377 !dev->exp.hpev_notified) {
378 pci_irq_deassert(dev);
379 }
380 }
381
pcie_cap_slot_enable_power(PCIDevice * dev)382 void pcie_cap_slot_enable_power(PCIDevice *dev)
383 {
384 uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
385 uint32_t sltcap = pci_get_long(exp_cap + PCI_EXP_SLTCAP);
386
387 if (sltcap & PCI_EXP_SLTCAP_PCP) {
388 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,
389 PCI_EXP_SLTCTL_PCC);
390 }
391 }
392
pcie_set_power_device(PCIBus * bus,PCIDevice * dev,void * opaque)393 static void pcie_set_power_device(PCIBus *bus, PCIDevice *dev, void *opaque)
394 {
395 bool *power = opaque;
396
397 pci_set_power(dev, *power);
398 }
399
pcie_cap_update_power(PCIDevice * hotplug_dev)400 static void pcie_cap_update_power(PCIDevice *hotplug_dev)
401 {
402 uint8_t *exp_cap = hotplug_dev->config + hotplug_dev->exp.exp_cap;
403 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(hotplug_dev));
404 uint32_t sltcap = pci_get_long(exp_cap + PCI_EXP_SLTCAP);
405 uint16_t sltctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL);
406 bool power = true;
407
408 if (sltcap & PCI_EXP_SLTCAP_PCP) {
409 power = (sltctl & PCI_EXP_SLTCTL_PCC) == PCI_EXP_SLTCTL_PWR_ON;
410 /* Don't we need to check also (sltctl & PCI_EXP_SLTCTL_PIC) ? */
411 }
412
413 pci_for_each_device(sec_bus, pci_bus_num(sec_bus),
414 pcie_set_power_device, &power);
415 }
416
417 /*
418 * A PCI Express Hot-Plug Event has occurred, so update slot status register
419 * and notify OS of the event if necessary.
420 *
421 * 6.7.3 PCI Express Hot-Plug Events
422 * 6.7.3.4 Software Notification of Hot-Plug Events
423 */
pcie_cap_slot_event(PCIDevice * dev,PCIExpressHotPlugEvent event)424 static void pcie_cap_slot_event(PCIDevice *dev, PCIExpressHotPlugEvent event)
425 {
426 /* Minor optimization: if nothing changed - no event is needed. */
427 if (pci_word_test_and_set_mask(dev->config + dev->exp.exp_cap +
428 PCI_EXP_SLTSTA, event) == event) {
429 return;
430 }
431 hotplug_event_notify(dev);
432 }
433
pcie_cap_slot_plug_common(PCIDevice * hotplug_dev,DeviceState * dev,Error ** errp)434 static void pcie_cap_slot_plug_common(PCIDevice *hotplug_dev, DeviceState *dev,
435 Error **errp)
436 {
437 uint8_t *exp_cap = hotplug_dev->config + hotplug_dev->exp.exp_cap;
438 uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
439
440 PCIE_DEV_PRINTF(PCI_DEVICE(dev), "hotplug state: 0x%x\n", sltsta);
441 if (sltsta & PCI_EXP_SLTSTA_EIS) {
442 /* the slot is electromechanically locked.
443 * This error is propagated up to qdev and then to HMP/QMP.
444 */
445 error_setg_errno(errp, EBUSY, "slot is electromechanically locked");
446 }
447 }
448
pcie_cap_slot_pre_plug_cb(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)449 void pcie_cap_slot_pre_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
450 Error **errp)
451 {
452 PCIDevice *hotplug_pdev = PCI_DEVICE(hotplug_dev);
453 uint8_t *exp_cap = hotplug_pdev->config + hotplug_pdev->exp.exp_cap;
454 uint32_t sltcap = pci_get_word(exp_cap + PCI_EXP_SLTCAP);
455
456 /* Check if hot-plug is disabled on the slot */
457 if (dev->hotplugged && (sltcap & PCI_EXP_SLTCAP_HPC) == 0) {
458 error_setg(errp, "Hot-plug failed: unsupported by the port device '%s'",
459 DEVICE(hotplug_pdev)->id);
460 return;
461 }
462
463 pcie_cap_slot_plug_common(PCI_DEVICE(hotplug_dev), dev, errp);
464 }
465
pcie_cap_slot_plug_cb(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)466 void pcie_cap_slot_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
467 Error **errp)
468 {
469 PCIDevice *hotplug_pdev = PCI_DEVICE(hotplug_dev);
470 uint8_t *exp_cap = hotplug_pdev->config + hotplug_pdev->exp.exp_cap;
471 PCIDevice *pci_dev = PCI_DEVICE(dev);
472 uint32_t lnkcap = pci_get_long(exp_cap + PCI_EXP_LNKCAP);
473
474 if (pci_is_vf(pci_dev)) {
475 /* Virtual function cannot be physically disconnected */
476 return;
477 }
478
479 /* Don't send event when device is enabled during qemu machine creation:
480 * it is present on boot, no hotplug event is necessary. We do send an
481 * event when the device is disabled later. */
482 if (!dev->hotplugged) {
483 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA,
484 PCI_EXP_SLTSTA_PDS);
485 if (pci_dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA ||
486 (lnkcap & PCI_EXP_LNKCAP_DLLLARC)) {
487 pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA,
488 PCI_EXP_LNKSTA_DLLLA);
489 }
490 pcie_cap_update_power(hotplug_pdev);
491 return;
492 }
493
494 /* To enable multifunction hot-plug, we just ensure the function
495 * 0 added last. When function 0 is added, we set the sltsta and
496 * inform OS via event notification.
497 */
498 if (pci_get_function_0(pci_dev)) {
499 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA,
500 PCI_EXP_SLTSTA_PDS);
501 if (pci_dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA ||
502 (lnkcap & PCI_EXP_LNKCAP_DLLLARC)) {
503 pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA,
504 PCI_EXP_LNKSTA_DLLLA);
505 }
506 pcie_cap_slot_event(hotplug_pdev,
507 PCI_EXP_HP_EV_PDC | PCI_EXP_HP_EV_ABP);
508 pcie_cap_update_power(hotplug_pdev);
509 }
510 }
511
pcie_cap_slot_unplug_cb(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)512 void pcie_cap_slot_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
513 Error **errp)
514 {
515 qdev_unrealize(dev);
516 }
517
pcie_unplug_device(PCIBus * bus,PCIDevice * dev,void * opaque)518 static void pcie_unplug_device(PCIBus *bus, PCIDevice *dev, void *opaque)
519 {
520 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(DEVICE(dev));
521
522 if (dev->partially_hotplugged) {
523 dev->qdev.pending_deleted_event = false;
524 return;
525 }
526 hotplug_handler_unplug(hotplug_ctrl, DEVICE(dev), &error_abort);
527 object_unparent(OBJECT(dev));
528 }
529
pcie_cap_slot_do_unplug(PCIDevice * dev)530 static void pcie_cap_slot_do_unplug(PCIDevice *dev)
531 {
532 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev));
533 uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
534 uint32_t lnkcap = pci_get_long(exp_cap + PCI_EXP_LNKCAP);
535
536 pci_for_each_device_under_bus(sec_bus, pcie_unplug_device, NULL);
537
538 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA,
539 PCI_EXP_SLTSTA_PDS);
540 if (dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA ||
541 (lnkcap & PCI_EXP_LNKCAP_DLLLARC)) {
542 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_LNKSTA,
543 PCI_EXP_LNKSTA_DLLLA);
544 }
545 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA,
546 PCI_EXP_SLTSTA_PDC);
547 }
548
pcie_cap_slot_unplug_request_cb(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)549 void pcie_cap_slot_unplug_request_cb(HotplugHandler *hotplug_dev,
550 DeviceState *dev, Error **errp)
551 {
552 Error *local_err = NULL;
553 PCIDevice *pci_dev = PCI_DEVICE(dev);
554 PCIBus *bus = pci_get_bus(pci_dev);
555 PCIDevice *hotplug_pdev = PCI_DEVICE(hotplug_dev);
556 uint8_t *exp_cap = hotplug_pdev->config + hotplug_pdev->exp.exp_cap;
557 uint32_t sltcap = pci_get_word(exp_cap + PCI_EXP_SLTCAP);
558 uint16_t sltctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL);
559
560 /* Check if hot-unplug is disabled on the slot */
561 if ((sltcap & PCI_EXP_SLTCAP_HPC) == 0) {
562 error_setg(errp, "Hot-unplug failed: "
563 "unsupported by the port device '%s'",
564 DEVICE(hotplug_pdev)->id);
565 return;
566 }
567
568 pcie_cap_slot_plug_common(hotplug_pdev, dev, &local_err);
569 if (local_err) {
570 error_propagate(errp, local_err);
571 return;
572 }
573
574 if ((sltctl & PCI_EXP_SLTCTL_PIC) == PCI_EXP_SLTCTL_PWR_IND_BLINK) {
575 error_setg(errp, "Hot-unplug failed: "
576 "guest is busy (power indicator blinking)");
577 return;
578 }
579
580 dev->pending_deleted_event = true;
581 dev->pending_deleted_expires_ms =
582 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 5000; /* 5 secs */
583
584 /* In case user cancel the operation of multi-function hot-add,
585 * remove the function that is unexposed to guest individually,
586 * without interaction with guest.
587 */
588 if (pci_dev->devfn &&
589 !bus->devices[0]) {
590 pcie_unplug_device(bus, pci_dev, NULL);
591
592 return;
593 }
594
595 if (pcie_sltctl_powered_off(sltctl)) {
596 /* slot is powered off -> unplug without round-trip to the guest */
597 pcie_cap_slot_do_unplug(hotplug_pdev);
598 hotplug_event_notify(hotplug_pdev);
599 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA,
600 PCI_EXP_SLTSTA_ABP);
601 return;
602 }
603
604 pcie_cap_slot_push_attention_button(hotplug_pdev);
605 }
606
607 /* pci express slot for pci express root/downstream port
608 PCI express capability slot registers */
pcie_cap_slot_init(PCIDevice * dev,PCIESlot * s)609 void pcie_cap_slot_init(PCIDevice *dev, PCIESlot *s)
610 {
611 uint32_t pos = dev->exp.exp_cap;
612
613 pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_FLAGS,
614 PCI_EXP_FLAGS_SLOT);
615
616 pci_long_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCAP,
617 ~PCI_EXP_SLTCAP_PSN);
618 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP,
619 (s->slot << PCI_EXP_SLTCAP_PSN_SHIFT) |
620 PCI_EXP_SLTCAP_EIP |
621 PCI_EXP_SLTCAP_PIP |
622 PCI_EXP_SLTCAP_AIP |
623 PCI_EXP_SLTCAP_ABP);
624
625 /*
626 * Expose native hot-plug on all bridges if hot-plug is enabled on the slot.
627 * (unless broken 6.1 ABI is enforced for compat reasons)
628 */
629 if (s->hotplug &&
630 (!s->hide_native_hotplug_cap || DEVICE(dev)->hotplugged)) {
631 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP,
632 PCI_EXP_SLTCAP_HPS |
633 PCI_EXP_SLTCAP_HPC);
634 }
635
636 if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) {
637 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP,
638 PCI_EXP_SLTCAP_PCP);
639 pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL,
640 PCI_EXP_SLTCTL_PCC);
641 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL,
642 PCI_EXP_SLTCTL_PCC);
643 }
644
645 pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL,
646 PCI_EXP_SLTCTL_PIC |
647 PCI_EXP_SLTCTL_AIC);
648 pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCTL,
649 PCI_EXP_SLTCTL_PWR_IND_OFF |
650 PCI_EXP_SLTCTL_ATTN_IND_OFF);
651 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL,
652 PCI_EXP_SLTCTL_PIC |
653 PCI_EXP_SLTCTL_AIC |
654 PCI_EXP_SLTCTL_HPIE |
655 PCI_EXP_SLTCTL_CCIE |
656 PCI_EXP_SLTCTL_PDCE |
657 PCI_EXP_SLTCTL_ABPE);
658 /* Although reading PCI_EXP_SLTCTL_EIC returns always 0,
659 * make the bit writable here in order to detect 1b is written.
660 * pcie_cap_slot_write_config() test-and-clear the bit, so
661 * this bit always returns 0 to the guest.
662 */
663 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL,
664 PCI_EXP_SLTCTL_EIC);
665
666 pci_word_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_SLTSTA,
667 PCI_EXP_HP_EV_SUPPORTED);
668
669 /* Avoid migration abortion when this device hot-removed by guest */
670 pci_word_test_and_clear_mask(dev->cmask + pos + PCI_EXP_SLTSTA,
671 PCI_EXP_SLTSTA_PDS);
672
673 dev->exp.hpev_notified = false;
674
675 qbus_set_hotplug_handler(BUS(pci_bridge_get_sec_bus(PCI_BRIDGE(dev))),
676 OBJECT(dev));
677 }
678
pcie_cap_slot_reset(PCIDevice * dev)679 void pcie_cap_slot_reset(PCIDevice *dev)
680 {
681 uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
682 uint8_t port_type = pcie_cap_get_type(dev);
683
684 assert(port_type == PCI_EXP_TYPE_DOWNSTREAM ||
685 port_type == PCI_EXP_TYPE_ROOT_PORT);
686
687 PCIE_DEV_PRINTF(dev, "reset\n");
688
689 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,
690 PCI_EXP_SLTCTL_EIC |
691 PCI_EXP_SLTCTL_PIC |
692 PCI_EXP_SLTCTL_AIC |
693 PCI_EXP_SLTCTL_HPIE |
694 PCI_EXP_SLTCTL_CCIE |
695 PCI_EXP_SLTCTL_PDCE |
696 PCI_EXP_SLTCTL_ABPE);
697 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL,
698 PCI_EXP_SLTCTL_PWR_IND_OFF |
699 PCI_EXP_SLTCTL_ATTN_IND_OFF);
700
701 if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) {
702 /* Downstream ports enforce device number 0. */
703 bool populated = pci_bridge_get_sec_bus(PCI_BRIDGE(dev))->devices[0];
704 uint16_t pic;
705
706 if (populated) {
707 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,
708 PCI_EXP_SLTCTL_PCC);
709 } else {
710 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL,
711 PCI_EXP_SLTCTL_PCC);
712 }
713
714 pic = populated ?
715 PCI_EXP_SLTCTL_PWR_IND_ON : PCI_EXP_SLTCTL_PWR_IND_OFF;
716 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, pic);
717 }
718
719 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA,
720 PCI_EXP_SLTSTA_EIS |/* on reset,
721 the lock is released */
722 PCI_EXP_SLTSTA_CC |
723 PCI_EXP_SLTSTA_PDC |
724 PCI_EXP_SLTSTA_ABP);
725
726 pcie_cap_update_power(dev);
727 hotplug_event_update_event_status(dev);
728 }
729
pcie_cap_slot_get(PCIDevice * dev,uint16_t * slt_ctl,uint16_t * slt_sta)730 void pcie_cap_slot_get(PCIDevice *dev, uint16_t *slt_ctl, uint16_t *slt_sta)
731 {
732 uint32_t pos = dev->exp.exp_cap;
733 uint8_t *exp_cap = dev->config + pos;
734 *slt_ctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL);
735 *slt_sta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
736 }
737
pcie_cap_slot_write_config(PCIDevice * dev,uint16_t old_slt_ctl,uint16_t old_slt_sta,uint32_t addr,uint32_t val,int len)738 void pcie_cap_slot_write_config(PCIDevice *dev,
739 uint16_t old_slt_ctl, uint16_t old_slt_sta,
740 uint32_t addr, uint32_t val, int len)
741 {
742 uint32_t pos = dev->exp.exp_cap;
743 uint8_t *exp_cap = dev->config + pos;
744 uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
745
746 if (ranges_overlap(addr, len, pos + PCI_EXP_SLTSTA, 2)) {
747 /*
748 * Guests tend to clears all bits during init.
749 * If they clear bits that weren't set this is racy and will lose events:
750 * not a big problem for manual button presses, but a problem for us.
751 * As a work-around, detect this and revert status to what it was
752 * before the write.
753 *
754 * Note: in theory this can be detected as a duplicate button press
755 * which cancels the previous press. Does not seem to happen in
756 * practice as guests seem to only have this bug during init.
757 */
758 #define PCIE_SLOT_EVENTS (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | \
759 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC | \
760 PCI_EXP_SLTSTA_CC)
761
762 if (val & ~old_slt_sta & PCIE_SLOT_EVENTS) {
763 sltsta = (sltsta & ~PCIE_SLOT_EVENTS) | (old_slt_sta & PCIE_SLOT_EVENTS);
764 pci_set_word(exp_cap + PCI_EXP_SLTSTA, sltsta);
765 }
766 hotplug_event_clear(dev);
767 }
768
769 if (!ranges_overlap(addr, len, pos + PCI_EXP_SLTCTL, 2)) {
770 return;
771 }
772
773 if (pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,
774 PCI_EXP_SLTCTL_EIC)) {
775 sltsta ^= PCI_EXP_SLTSTA_EIS; /* toggle PCI_EXP_SLTSTA_EIS bit */
776 pci_set_word(exp_cap + PCI_EXP_SLTSTA, sltsta);
777 PCIE_DEV_PRINTF(dev, "PCI_EXP_SLTCTL_EIC: "
778 "sltsta -> 0x%02"PRIx16"\n",
779 sltsta);
780 }
781
782 /*
783 * If the slot is populated, power indicator is off and power
784 * controller is off, it is safe to detach the devices.
785 *
786 * Note: don't detach if condition was already true:
787 * this is a work around for guests that overwrite
788 * control of powered off slots before powering them on.
789 */
790 if ((sltsta & PCI_EXP_SLTSTA_PDS) && pcie_sltctl_powered_off(val) &&
791 !pcie_sltctl_powered_off(old_slt_ctl))
792 {
793 pcie_cap_slot_do_unplug(dev);
794 }
795 pcie_cap_update_power(dev);
796
797 hotplug_event_notify(dev);
798
799 /*
800 * 6.7.3.2 Command Completed Events
801 *
802 * Software issues a command to a hot-plug capable Downstream Port by
803 * issuing a write transaction that targets any portion of the Port’s Slot
804 * Control register. A single write to the Slot Control register is
805 * considered to be a single command, even if the write affects more than
806 * one field in the Slot Control register. In response to this transaction,
807 * the Port must carry out the requested actions and then set the
808 * associated status field for the command completed event. */
809
810 /* Real hardware might take a while to complete requested command because
811 * physical movement would be involved like locking the electromechanical
812 * lock. However in our case, command is completed instantaneously above,
813 * so send a command completion event right now.
814 */
815 pcie_cap_slot_event(dev, PCI_EXP_HP_EV_CCI);
816 }
817
pcie_cap_slot_post_load(void * opaque,int version_id)818 int pcie_cap_slot_post_load(void *opaque, int version_id)
819 {
820 PCIDevice *dev = opaque;
821 hotplug_event_update_event_status(dev);
822 pcie_cap_update_power(dev);
823 return 0;
824 }
825
pcie_cap_slot_push_attention_button(PCIDevice * dev)826 void pcie_cap_slot_push_attention_button(PCIDevice *dev)
827 {
828 pcie_cap_slot_event(dev, PCI_EXP_HP_EV_ABP);
829 }
830
831 /* root control/capabilities/status. PME isn't emulated for now */
pcie_cap_root_init(PCIDevice * dev)832 void pcie_cap_root_init(PCIDevice *dev)
833 {
834 pci_set_word(dev->wmask + dev->exp.exp_cap + PCI_EXP_RTCTL,
835 PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE |
836 PCI_EXP_RTCTL_SEFEE);
837 }
838
pcie_cap_root_reset(PCIDevice * dev)839 void pcie_cap_root_reset(PCIDevice *dev)
840 {
841 pci_set_word(dev->config + dev->exp.exp_cap + PCI_EXP_RTCTL, 0);
842 }
843
844 /* function level reset(FLR) */
pcie_cap_flr_init(PCIDevice * dev)845 void pcie_cap_flr_init(PCIDevice *dev)
846 {
847 pci_long_test_and_set_mask(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCAP,
848 PCI_EXP_DEVCAP_FLR);
849
850 /* Although reading BCR_FLR returns always 0,
851 * the bit is made writable here in order to detect the 1b is written
852 * pcie_cap_flr_write_config() test-and-clear the bit, so
853 * this bit always returns 0 to the guest.
854 */
855 pci_word_test_and_set_mask(dev->wmask + dev->exp.exp_cap + PCI_EXP_DEVCTL,
856 PCI_EXP_DEVCTL_BCR_FLR);
857 }
858
pcie_cap_flr_write_config(PCIDevice * dev,uint32_t addr,uint32_t val,int len)859 void pcie_cap_flr_write_config(PCIDevice *dev,
860 uint32_t addr, uint32_t val, int len)
861 {
862 uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL;
863 if (pci_get_word(devctl) & PCI_EXP_DEVCTL_BCR_FLR) {
864 /* Clear PCI_EXP_DEVCTL_BCR_FLR after invoking the reset handler
865 so the handler can detect FLR by looking at this bit. */
866 pci_device_reset(dev);
867 pci_word_test_and_clear_mask(devctl, PCI_EXP_DEVCTL_BCR_FLR);
868 }
869 }
870
871 /* Alternative Routing-ID Interpretation (ARI)
872 * forwarding support for root and downstream ports
873 */
pcie_cap_arifwd_init(PCIDevice * dev)874 void pcie_cap_arifwd_init(PCIDevice *dev)
875 {
876 uint32_t pos = dev->exp.exp_cap;
877 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP2,
878 PCI_EXP_DEVCAP2_ARI);
879 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL2,
880 PCI_EXP_DEVCTL2_ARI);
881 }
882
pcie_cap_arifwd_reset(PCIDevice * dev)883 void pcie_cap_arifwd_reset(PCIDevice *dev)
884 {
885 uint8_t *devctl2 = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2;
886 pci_long_test_and_clear_mask(devctl2, PCI_EXP_DEVCTL2_ARI);
887 }
888
pcie_cap_is_arifwd_enabled(const PCIDevice * dev)889 bool pcie_cap_is_arifwd_enabled(const PCIDevice *dev)
890 {
891 if (!pci_is_express(dev)) {
892 return false;
893 }
894 if (!dev->exp.exp_cap) {
895 return false;
896 }
897
898 return pci_get_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2) &
899 PCI_EXP_DEVCTL2_ARI;
900 }
901
902 /**************************************************************************
903 * pci express extended capability list management functions
904 * uint16_t ext_cap_id (16 bit)
905 * uint8_t cap_ver (4 bit)
906 * uint16_t cap_offset (12 bit)
907 * uint16_t ext_cap_size
908 */
909
910 /* Passing a cap_id value > 0xffff will return 0 and put end of list in prev */
pcie_find_capability_list(PCIDevice * dev,uint32_t cap_id,uint16_t * prev_p)911 static uint16_t pcie_find_capability_list(PCIDevice *dev, uint32_t cap_id,
912 uint16_t *prev_p)
913 {
914 uint16_t prev = 0;
915 uint16_t next;
916 uint32_t header = pci_get_long(dev->config + PCI_CONFIG_SPACE_SIZE);
917
918 if (!header) {
919 /* no extended capability */
920 next = 0;
921 goto out;
922 }
923 for (next = PCI_CONFIG_SPACE_SIZE; next;
924 prev = next, next = PCI_EXT_CAP_NEXT(header)) {
925
926 assert(next >= PCI_CONFIG_SPACE_SIZE);
927 assert(next <= PCIE_CONFIG_SPACE_SIZE - 8);
928
929 header = pci_get_long(dev->config + next);
930 if (PCI_EXT_CAP_ID(header) == cap_id) {
931 break;
932 }
933 }
934
935 out:
936 if (prev_p) {
937 *prev_p = prev;
938 }
939 return next;
940 }
941
pcie_find_capability(PCIDevice * dev,uint16_t cap_id)942 uint16_t pcie_find_capability(PCIDevice *dev, uint16_t cap_id)
943 {
944 return pcie_find_capability_list(dev, cap_id, NULL);
945 }
946
pcie_ext_cap_set_next(PCIDevice * dev,uint16_t pos,uint16_t next)947 static void pcie_ext_cap_set_next(PCIDevice *dev, uint16_t pos, uint16_t next)
948 {
949 uint32_t header = pci_get_long(dev->config + pos);
950 assert(!(next & (PCI_EXT_CAP_ALIGN - 1)));
951 header = (header & ~PCI_EXT_CAP_NEXT_MASK) |
952 ((next << PCI_EXT_CAP_NEXT_SHIFT) & PCI_EXT_CAP_NEXT_MASK);
953 pci_set_long(dev->config + pos, header);
954 }
955
956 /*
957 * Caller must supply valid (offset, size) such that the range wouldn't
958 * overlap with other capability or other registers.
959 * This function doesn't check it.
960 */
pcie_add_capability(PCIDevice * dev,uint16_t cap_id,uint8_t cap_ver,uint16_t offset,uint16_t size)961 void pcie_add_capability(PCIDevice *dev,
962 uint16_t cap_id, uint8_t cap_ver,
963 uint16_t offset, uint16_t size)
964 {
965 assert(offset >= PCI_CONFIG_SPACE_SIZE);
966 assert(offset < (uint16_t)(offset + size));
967 assert((uint16_t)(offset + size) <= PCIE_CONFIG_SPACE_SIZE);
968 assert(size >= 8);
969 assert(pci_is_express(dev));
970
971 if (offset != PCI_CONFIG_SPACE_SIZE) {
972 uint16_t prev;
973
974 /*
975 * 0xffffffff is not a valid cap id (it's a 16 bit field). use
976 * internally to find the last capability in the linked list.
977 */
978 pcie_find_capability_list(dev, 0xffffffff, &prev);
979 assert(prev >= PCI_CONFIG_SPACE_SIZE);
980 pcie_ext_cap_set_next(dev, prev, offset);
981 }
982 pci_set_long(dev->config + offset, PCI_EXT_CAP(cap_id, cap_ver, 0));
983
984 /* Make capability read-only by default */
985 memset(dev->wmask + offset, 0, size);
986 memset(dev->w1cmask + offset, 0, size);
987 /* Check capability by default */
988 memset(dev->cmask + offset, 0xFF, size);
989 }
990
991 /*
992 * Sync the PCIe Link Status negotiated speed and width of a bridge with the
993 * downstream device. If downstream device is not present, re-write with the
994 * Link Capability fields. If downstream device reports invalid width or
995 * speed, replace with minimum values (LnkSta fields are RsvdZ on VFs but such
996 * values interfere with PCIe native hotplug detecting new devices). Limit
997 * width and speed to bridge capabilities for compatibility. Use config_read
998 * to access the downstream device since it could be an assigned device with
999 * volatile link information.
1000 */
pcie_sync_bridge_lnk(PCIDevice * bridge_dev)1001 void pcie_sync_bridge_lnk(PCIDevice *bridge_dev)
1002 {
1003 PCIBridge *br = PCI_BRIDGE(bridge_dev);
1004 PCIBus *bus = pci_bridge_get_sec_bus(br);
1005 PCIDevice *target = bus->devices[0];
1006 uint8_t *exp_cap = bridge_dev->config + bridge_dev->exp.exp_cap;
1007 uint16_t lnksta, lnkcap = pci_get_word(exp_cap + PCI_EXP_LNKCAP);
1008
1009 if (!target || !target->exp.exp_cap) {
1010 lnksta = lnkcap;
1011 } else {
1012 lnksta = target->config_read(target,
1013 target->exp.exp_cap + PCI_EXP_LNKSTA,
1014 sizeof(lnksta));
1015
1016 if ((lnksta & PCI_EXP_LNKSTA_NLW) > (lnkcap & PCI_EXP_LNKCAP_MLW)) {
1017 lnksta &= ~PCI_EXP_LNKSTA_NLW;
1018 lnksta |= lnkcap & PCI_EXP_LNKCAP_MLW;
1019 } else if (!(lnksta & PCI_EXP_LNKSTA_NLW)) {
1020 lnksta |= QEMU_PCI_EXP_LNKSTA_NLW(QEMU_PCI_EXP_LNK_X1);
1021 }
1022
1023 if ((lnksta & PCI_EXP_LNKSTA_CLS) > (lnkcap & PCI_EXP_LNKCAP_SLS)) {
1024 lnksta &= ~PCI_EXP_LNKSTA_CLS;
1025 lnksta |= lnkcap & PCI_EXP_LNKCAP_SLS;
1026 } else if (!(lnksta & PCI_EXP_LNKSTA_CLS)) {
1027 lnksta |= QEMU_PCI_EXP_LNKSTA_CLS(QEMU_PCI_EXP_LNK_2_5GT);
1028 }
1029 }
1030
1031 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_LNKSTA,
1032 PCI_EXP_LNKSTA_CLS | PCI_EXP_LNKSTA_NLW);
1033 pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA, lnksta &
1034 (PCI_EXP_LNKSTA_CLS | PCI_EXP_LNKSTA_NLW));
1035 }
1036
1037 /**************************************************************************
1038 * pci express extended capability helper functions
1039 */
1040
1041 /* ARI */
pcie_ari_init(PCIDevice * dev,uint16_t offset)1042 void pcie_ari_init(PCIDevice *dev, uint16_t offset)
1043 {
1044 uint16_t nextfn = dev->cap_present & QEMU_PCIE_ARI_NEXTFN_1 ? 1 : 0;
1045
1046 pcie_add_capability(dev, PCI_EXT_CAP_ID_ARI, PCI_ARI_VER,
1047 offset, PCI_ARI_SIZEOF);
1048 pci_set_long(dev->config + offset + PCI_ARI_CAP, (nextfn & 0xff) << 8);
1049 }
1050
pcie_dev_ser_num_init(PCIDevice * dev,uint16_t offset,uint64_t ser_num)1051 void pcie_dev_ser_num_init(PCIDevice *dev, uint16_t offset, uint64_t ser_num)
1052 {
1053 static const int pci_dsn_ver = 1;
1054 static const int pci_dsn_cap = 4;
1055
1056 pcie_add_capability(dev, PCI_EXT_CAP_ID_DSN, pci_dsn_ver, offset,
1057 PCI_EXT_CAP_DSN_SIZEOF);
1058 pci_set_quad(dev->config + offset + pci_dsn_cap, ser_num);
1059 }
1060
pcie_ats_init(PCIDevice * dev,uint16_t offset,bool aligned)1061 void pcie_ats_init(PCIDevice *dev, uint16_t offset, bool aligned)
1062 {
1063 pcie_add_capability(dev, PCI_EXT_CAP_ID_ATS, 0x1,
1064 offset, PCI_EXT_CAP_ATS_SIZEOF);
1065
1066 dev->exp.ats_cap = offset;
1067
1068 /* Invalidate Queue Depth 0 */
1069 if (aligned) {
1070 pci_set_word(dev->config + offset + PCI_ATS_CAP,
1071 PCI_ATS_CAP_PAGE_ALIGNED);
1072 }
1073 /* STU 0, Disabled by default */
1074 pci_set_word(dev->config + offset + PCI_ATS_CTRL, 0);
1075
1076 pci_set_word(dev->wmask + dev->exp.ats_cap + PCI_ATS_CTRL, 0x800f);
1077 }
1078
1079 /* ACS (Access Control Services) */
pcie_acs_init(PCIDevice * dev,uint16_t offset)1080 void pcie_acs_init(PCIDevice *dev, uint16_t offset)
1081 {
1082 bool is_downstream = pci_is_express_downstream_port(dev);
1083 uint16_t cap_bits = 0;
1084
1085 /* For endpoints, only multifunction devs may have an ACS capability: */
1086 assert(is_downstream ||
1087 (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) ||
1088 PCI_FUNC(dev->devfn));
1089
1090 pcie_add_capability(dev, PCI_EXT_CAP_ID_ACS, PCI_ACS_VER, offset,
1091 PCI_ACS_SIZEOF);
1092 dev->exp.acs_cap = offset;
1093
1094 if (is_downstream) {
1095 /*
1096 * Downstream ports must implement SV, TB, RR, CR, UF, and DT (with
1097 * caveats on the latter four that we ignore for simplicity).
1098 * Endpoints may also implement a subset of ACS capabilities,
1099 * but these are optional if the endpoint does not support
1100 * peer-to-peer between functions and thus omitted here.
1101 */
1102 cap_bits = PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
1103 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT;
1104 }
1105
1106 pci_set_word(dev->config + offset + PCI_ACS_CAP, cap_bits);
1107 pci_set_word(dev->wmask + offset + PCI_ACS_CTRL, cap_bits);
1108 }
1109
pcie_acs_reset(PCIDevice * dev)1110 void pcie_acs_reset(PCIDevice *dev)
1111 {
1112 if (dev->exp.acs_cap) {
1113 pci_set_word(dev->config + dev->exp.acs_cap + PCI_ACS_CTRL, 0);
1114 }
1115 }
1116