1 // SPDX-License-Identifier: GPL-2.0+
2 #include <common.h>
3 #include <dm.h>
4 #include <reset.h>
5 #include <fdtdec.h>
6 #include <pci.h>
7 #include <asm/io.h>
8 #include <asm/arch/ahbc_aspeed.h>
9 #include "pcie_aspeed.h"
10
11 DECLARE_GLOBAL_DATA_PTR;
12
13 struct pcie_aspeed {
14 struct aspeed_h2x_reg *h2x_reg;
15 };
16
17 static u8 txTag;
18
aspeed_pcie_set_slot_power_limit(struct pcie_aspeed * pcie,int slot)19 void aspeed_pcie_set_slot_power_limit(struct pcie_aspeed *pcie, int slot)
20 {
21 u32 timeout = 0;
22 struct aspeed_h2x_reg *h2x_reg = pcie->h2x_reg;
23
24 //optional : set_slot_power_limit
25 switch (slot) {
26 case 0:
27 writel(BIT(4) | readl(&h2x_reg->h2x_rc_l_ctrl),
28 &h2x_reg->h2x_rc_l_ctrl);
29 break;
30 case 1:
31 writel(BIT(4) | readl(&h2x_reg->h2x_rc_h_ctrl),
32 &h2x_reg->h2x_rc_h_ctrl);
33 break;
34 }
35
36 txTag %= 0x7;
37
38 writel(0x74000001, &h2x_reg->h2x_tx_desc3);
39 switch (slot) {
40 case 0: //write for 0.8.0
41 writel(0x00400050 | (txTag << 8), &h2x_reg->h2x_tx_desc2);
42 break;
43 case 1: //write for 0.4.0
44 writel(0x00200050 | (txTag << 8), &h2x_reg->h2x_tx_desc2);
45 break;
46 }
47 writel(0x0, &h2x_reg->h2x_tx_desc1);
48 writel(0x0, &h2x_reg->h2x_tx_desc0);
49
50 writel(0x1a, &h2x_reg->h2x_tx_data);
51
52 //trigger tx
53 writel(PCIE_TRIGGER_TX, &h2x_reg->h2x_reg24);
54
55 //wait tx idle
56 while (!(readl(&h2x_reg->h2x_reg24) & BIT(31))) {
57 timeout++;
58 if (timeout > 1000)
59 goto out;
60 };
61
62 //write clr tx idle
63 writel(1, &h2x_reg->h2x_reg08);
64 timeout = 0;
65
66 switch (slot) {
67 case 0:
68 //check tx status and clr rx done int
69 while (!(readl(&h2x_reg->h2x_rc_l_isr) & PCIE_RC_RX_DONE_ISR)) {
70 timeout++;
71 if (timeout > 10)
72 break;
73 mdelay(1);
74 }
75 writel(PCIE_RC_RX_DONE_ISR, &h2x_reg->h2x_rc_l_isr);
76 break;
77 case 1:
78 //check tx status and clr rx done int
79 while (!(readl(&h2x_reg->h2x_rc_h_isr) & PCIE_RC_RX_DONE_ISR)) {
80 timeout++;
81 if (timeout > 10)
82 break;
83 mdelay(1);
84 }
85 writel(PCIE_RC_RX_DONE_ISR, &h2x_reg->h2x_rc_h_isr);
86 break;
87 }
88 out:
89 txTag++;
90 }
91
aspeed_pcie_cfg_read(struct pcie_aspeed * pcie,pci_dev_t bdf,uint offset,ulong * valuep)92 static void aspeed_pcie_cfg_read(struct pcie_aspeed *pcie, pci_dev_t bdf,
93 uint offset, ulong *valuep)
94 {
95 struct aspeed_h2x_reg *h2x_reg = pcie->h2x_reg;
96 u32 timeout = 0;
97 u32 bdf_offset;
98 u32 type = 0;
99 int rx_done_fail = 0;
100
101 //H2X80[4] (unlock) is write-only.
102 //Driver may set H2X80/H2XC0[4]=1 before triggering next TX config.
103 writel(BIT(4) | readl(&h2x_reg->h2x_rc_l_ctrl),
104 &h2x_reg->h2x_rc_l_ctrl);
105 writel(BIT(4) | readl(&h2x_reg->h2x_rc_h_ctrl),
106 &h2x_reg->h2x_rc_h_ctrl);
107
108 if (PCI_BUS(bdf) == 0)
109 type = 0;
110 else
111 type = 1;
112
113 bdf_offset = (PCI_BUS(bdf) << 24) |
114 (PCI_DEV(bdf) << 19) |
115 (PCI_FUNC(bdf) << 16) |
116 (offset & ~3);
117
118 txTag %= 0x7;
119
120 writel(0x04000001 | (type << 24), &h2x_reg->h2x_tx_desc3);
121 writel(0x0000200f | (txTag << 8), &h2x_reg->h2x_tx_desc2);
122 writel(bdf_offset, &h2x_reg->h2x_tx_desc1);
123 writel(0x00000000, &h2x_reg->h2x_tx_desc0);
124
125 //trigger tx
126 writel(PCIE_TRIGGER_TX, &h2x_reg->h2x_reg24);
127
128 //wait tx idle
129 while (!(readl(&h2x_reg->h2x_reg24) & PCIE_TX_IDLE)) {
130 timeout++;
131 if (timeout > 1000) {
132 *valuep = 0xffffffff;
133 goto out;
134 }
135 };
136
137 //write clr tx idle
138 writel(1, &h2x_reg->h2x_reg08);
139
140 timeout = 0;
141 //check tx status
142 switch (readl(&h2x_reg->h2x_reg24) & PCIE_STATUS_OF_TX) {
143 case PCIE_RC_L_TX_COMPLETE:
144 while (!(readl(&h2x_reg->h2x_rc_l_isr) & PCIE_RC_RX_DONE_ISR)) {
145 timeout++;
146 if (timeout > 10) {
147 rx_done_fail = 1;
148 *valuep = 0xffffffff;
149 break;
150 }
151 mdelay(1);
152 }
153 if (!rx_done_fail) {
154 if (readl(&h2x_reg->h2x_rc_l_rxdesc2) & BIT(13))
155 *valuep = 0xffffffff;
156 else
157 *valuep = readl(&h2x_reg->h2x_rc_l_rdata);
158 }
159 writel(BIT(4) | readl(&h2x_reg->h2x_rc_l_ctrl),
160 &h2x_reg->h2x_rc_l_ctrl);
161 writel(readl(&h2x_reg->h2x_rc_l_isr),
162 &h2x_reg->h2x_rc_l_isr);
163 break;
164 case PCIE_RC_H_TX_COMPLETE:
165 while (!(readl(&h2x_reg->h2x_rc_h_isr) & PCIE_RC_RX_DONE_ISR)) {
166 timeout++;
167 if (timeout > 10) {
168 rx_done_fail = 1;
169 *valuep = 0xffffffff;
170 break;
171 }
172 mdelay(1);
173 }
174 if (!rx_done_fail) {
175 if (readl(&h2x_reg->h2x_rc_h_rxdesc2) & BIT(13))
176 *valuep = 0xffffffff;
177 else
178 *valuep = readl(&h2x_reg->h2x_rc_h_rdata);
179 }
180 writel(BIT(4) | readl(&h2x_reg->h2x_rc_h_ctrl),
181 &h2x_reg->h2x_rc_h_ctrl);
182 writel(readl(&h2x_reg->h2x_rc_h_isr), &h2x_reg->h2x_rc_h_isr);
183 break;
184 default: //read rc data
185 *valuep = readl(&h2x_reg->h2x_rdata);
186 break;
187 }
188
189 out:
190 txTag++;
191 }
192
aspeed_pcie_cfg_write(struct pcie_aspeed * pcie,pci_dev_t bdf,uint offset,ulong value,enum pci_size_t size)193 static void aspeed_pcie_cfg_write(struct pcie_aspeed *pcie, pci_dev_t bdf,
194 uint offset, ulong value,
195 enum pci_size_t size)
196 {
197 struct aspeed_h2x_reg *h2x_reg = pcie->h2x_reg;
198 u32 timeout = 0;
199 u32 type = 0;
200 u32 bdf_offset;
201 u8 byte_en = 0;
202
203 writel(BIT(4) | readl(&h2x_reg->h2x_rc_l_ctrl),
204 &h2x_reg->h2x_rc_l_ctrl);
205 writel(BIT(4) | readl(&h2x_reg->h2x_rc_h_ctrl),
206 &h2x_reg->h2x_rc_h_ctrl);
207
208 switch (size) {
209 case PCI_SIZE_8:
210 switch (offset % 4) {
211 case 0:
212 byte_en = 0x1;
213 break;
214 case 1:
215 byte_en = 0x2;
216 break;
217 case 2:
218 byte_en = 0x4;
219 break;
220 case 3:
221 byte_en = 0x8;
222 break;
223 }
224 break;
225 case PCI_SIZE_16:
226 switch ((offset >> 1) % 2) {
227 case 0:
228 byte_en = 0x3;
229 break;
230 case 1:
231 byte_en = 0xc;
232 break;
233 }
234 break;
235 default:
236 byte_en = 0xf;
237 break;
238 }
239
240 if (PCI_BUS(bdf) == 0)
241 type = 0;
242 else
243 type = 1;
244
245 bdf_offset = (PCI_BUS(bdf) << 24) |
246 (PCI_DEV(bdf) << 19) |
247 (PCI_FUNC(bdf) << 16) |
248 (offset & ~3);
249
250 txTag %= 0x7;
251
252 writel(0x44000001 | (type << 24), &h2x_reg->h2x_tx_desc3);
253 writel(0x00002000 | (txTag << 8) | byte_en, &h2x_reg->h2x_tx_desc2);
254 writel(bdf_offset, &h2x_reg->h2x_tx_desc1);
255 writel(0x00000000, &h2x_reg->h2x_tx_desc0);
256
257 value = pci_conv_size_to_32(0x0, value, offset, size);
258
259 writel(value, &h2x_reg->h2x_tx_data);
260
261 //trigger tx
262 writel(1, &h2x_reg->h2x_reg24);
263
264 //wait tx idle
265 while (!(readl(&h2x_reg->h2x_reg24) & BIT(31))) {
266 timeout++;
267 if (timeout > 1000)
268 goto out;
269 };
270
271 //write clr tx idle
272 writel(1, &h2x_reg->h2x_reg08);
273
274 timeout = 0;
275 //check tx status and clr rx done int
276 switch (readl(&h2x_reg->h2x_reg24) & PCIE_STATUS_OF_TX) {
277 case PCIE_RC_L_TX_COMPLETE:
278 while (!(readl(&h2x_reg->h2x_rc_l_isr) & PCIE_RC_RX_DONE_ISR)) {
279 timeout++;
280 if (timeout > 10)
281 break;
282 mdelay(1);
283 }
284 writel(PCIE_RC_RX_DONE_ISR, &h2x_reg->h2x_rc_l_isr);
285 break;
286 case PCIE_RC_H_TX_COMPLETE:
287 while (!(readl(&h2x_reg->h2x_rc_h_isr) & PCIE_RC_RX_DONE_ISR)) {
288 timeout++;
289 if (timeout > 10)
290 break;
291 mdelay(1);
292 }
293 writel(PCIE_RC_RX_DONE_ISR, &h2x_reg->h2x_rc_h_isr);
294 break;
295 }
296
297 out:
298 txTag++;
299 }
300
pcie_aspeed_read_config(struct udevice * bus,pci_dev_t bdf,uint offset,ulong * valuep,enum pci_size_t size)301 static int pcie_aspeed_read_config(struct udevice *bus, pci_dev_t bdf,
302 uint offset, ulong *valuep,
303 enum pci_size_t size)
304 {
305 struct pcie_aspeed *pcie = dev_get_priv(bus);
306
307 debug("PCIE CFG read: (b,d,f)=(%2d,%2d,%2d)\n",
308 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
309
310 /* Only allow one other device besides the local one on the local bus */
311 if (PCI_BUS(bdf) == 1 && PCI_DEV(bdf) > 0) {
312 debug("- out of range\n");
313 /*
314 * If local dev is 0, the first other dev can
315 * only be 1
316 */
317 *valuep = pci_get_ff(size);
318 return 0;
319 }
320
321 if (PCI_BUS(bdf) == 2 && PCI_DEV(bdf) > 0) {
322 debug("- out of range\n");
323 /*
324 * If local dev is 0, the first other dev can
325 * only be 1
326 */
327 *valuep = pci_get_ff(size);
328 return 0;
329 }
330
331 aspeed_pcie_cfg_read(pcie, bdf, offset, valuep);
332
333 *valuep = pci_conv_32_to_size(*valuep, offset, size);
334 debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, *valuep);
335
336 return 0;
337 }
338
pcie_aspeed_write_config(struct udevice * bus,pci_dev_t bdf,uint offset,ulong value,enum pci_size_t size)339 static int pcie_aspeed_write_config(struct udevice *bus, pci_dev_t bdf,
340 uint offset, ulong value,
341 enum pci_size_t size)
342 {
343 struct pcie_aspeed *pcie = dev_get_priv(bus);
344
345 debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
346 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
347 debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
348
349 aspeed_pcie_cfg_write(pcie, bdf, offset, value, size);
350
351 return 0;
352 }
353
aspeed_pcie_rc_slot_enable(struct pcie_aspeed * pcie,int slot)354 void aspeed_pcie_rc_slot_enable(struct pcie_aspeed *pcie, int slot)
355
356 {
357 struct aspeed_h2x_reg *h2x_reg = pcie->h2x_reg;
358
359 switch (slot) {
360 case 0:
361 //rc_l
362 writel(PCIE_RX_LINEAR | PCIE_RX_MSI_EN |
363 PCIE_WAIT_RX_TLP_CLR |
364 PCIE_RC_RX_ENABLE | PCIE_RC_ENABLE,
365 &h2x_reg->h2x_rc_l_ctrl);
366 //assign debug tx tag
367 writel((u32)&h2x_reg->h2x_rc_l_ctrl, &h2x_reg->h2x_rc_l_tx_tag);
368 break;
369 case 1:
370 //rc_h
371 writel(PCIE_RX_LINEAR | PCIE_RX_MSI_EN |
372 PCIE_WAIT_RX_TLP_CLR |
373 PCIE_RC_RX_ENABLE | PCIE_RC_ENABLE,
374 &h2x_reg->h2x_rc_h_ctrl);
375 //assign debug tx tag
376 writel((u32)&h2x_reg->h2x_rc_h_ctrl, &h2x_reg->h2x_rc_h_tx_tag);
377 break;
378 }
379 }
380
pcie_aspeed_probe(struct udevice * dev)381 static int pcie_aspeed_probe(struct udevice *dev)
382 {
383 void *fdt = (void *)gd->fdt_blob;
384 struct reset_ctl reset_ctl, rc0_reset_ctl, rc1_reset_ctl;
385 struct pcie_aspeed *pcie = (struct pcie_aspeed *)dev_get_priv(dev);
386 struct aspeed_h2x_reg *h2x_reg = pcie->h2x_reg;
387 struct udevice *ahbc_dev, *slot0_dev, *slot1_dev;
388 int slot0_of_handle, slot1_of_handle;
389 int ret = 0;
390
391 txTag = 0;
392 ret = reset_get_by_index(dev, 0, &reset_ctl);
393 if (ret) {
394 printf("%s(): Failed to get pcie reset signal\n", __func__);
395 return ret;
396 }
397
398 reset_assert(&reset_ctl);
399 mdelay(1);
400 reset_deassert(&reset_ctl);
401
402 //workaround : Send vender define message for avoid when PCIE RESET send unknown message out
403 writel(0x34000000, &h2x_reg->h2x_tx_desc3);
404 writel(0x0000007f, &h2x_reg->h2x_tx_desc2);
405 writel(0x00001a03, &h2x_reg->h2x_tx_desc1);
406 writel(0x00000000, &h2x_reg->h2x_tx_desc0);
407
408 ret = uclass_get_device_by_driver
409 (UCLASS_MISC, DM_GET_DRIVER(aspeed_ahbc), &ahbc_dev);
410 if (ret) {
411 debug("ahbc device not defined\n");
412 return ret;
413 }
414 aspeed_ahbc_remap_enable(devfdt_get_addr_ptr(ahbc_dev));
415
416 //ahb to pcie rc
417 writel(0xe0006000, &h2x_reg->h2x_reg60);
418 writel(0x0, &h2x_reg->h2x_reg64);
419 writel(0xFFFFFFFF, &h2x_reg->h2x_reg68);
420
421 //PCIe Host Enable
422 writel(BIT(0), &h2x_reg->h2x_reg00);
423
424 slot0_of_handle =
425 fdtdec_lookup_phandle(fdt, dev_of_offset(dev), "slot0-handle");
426 if (slot0_of_handle) {
427 ret = reset_get_by_index(dev, 1, &rc0_reset_ctl);
428 if (ret) {
429 printf("%s(): Failed to get rc low reset signal\n", __func__);
430 return ret;
431 }
432 aspeed_pcie_rc_slot_enable(pcie, 0);
433 reset_deassert(&rc0_reset_ctl);
434 mdelay(50);
435 if (uclass_get_device_by_of_offset
436 (UCLASS_MISC, slot0_of_handle, &slot0_dev))
437 goto slot1;
438 if (aspeed_pcie_phy_link_status(slot0_dev))
439 aspeed_pcie_set_slot_power_limit(pcie, 0);
440 }
441
442 slot1:
443 slot1_of_handle =
444 fdtdec_lookup_phandle(fdt, dev_of_offset(dev), "slot1-handle");
445 if (slot1_of_handle) {
446 ret = reset_get_by_index(dev, 2, &rc1_reset_ctl);
447 if (ret) {
448 printf("%s(): Failed to get rc high reset signal\n", __func__);
449 return ret;
450 }
451 aspeed_pcie_rc_slot_enable(pcie, 1);
452 reset_deassert(&rc1_reset_ctl);
453 mdelay(50);
454 if (uclass_get_device_by_of_offset
455 (UCLASS_MISC, slot1_of_handle, &slot1_dev))
456 goto end;
457 if (aspeed_pcie_phy_link_status(slot1_dev))
458 aspeed_pcie_set_slot_power_limit(pcie, 1);
459 }
460 end:
461 return 0;
462 }
463
pcie_aspeed_ofdata_to_platdata(struct udevice * dev)464 static int pcie_aspeed_ofdata_to_platdata(struct udevice *dev)
465 {
466 struct pcie_aspeed *pcie = dev_get_priv(dev);
467
468 /* Get the controller base address */
469 pcie->h2x_reg = (void *)devfdt_get_addr_index(dev, 0);
470
471 return 0;
472 }
473
474 static const struct dm_pci_ops pcie_aspeed_ops = {
475 .read_config = pcie_aspeed_read_config,
476 .write_config = pcie_aspeed_write_config,
477 };
478
479 static const struct udevice_id pcie_aspeed_ids[] = {
480 { .compatible = "aspeed,ast2600-pcie" },
481 { }
482 };
483
484 U_BOOT_DRIVER(pcie_aspeed) = {
485 .name = "pcie_aspeed",
486 .id = UCLASS_PCI,
487 .of_match = pcie_aspeed_ids,
488 .ops = &pcie_aspeed_ops,
489 .ofdata_to_platdata = pcie_aspeed_ofdata_to_platdata,
490 .probe = pcie_aspeed_probe,
491 .priv_auto_alloc_size = sizeof(struct pcie_aspeed),
492 };
493