1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (C) 2016 Broadcom Corporation
3 *
4 * This file contains the Northstar2 IOMUX driver that supports group
5 * based PINMUX configuration. The PWM is functional only when the
6 * corresponding mfio pin group is selected as gpio.
7 */
8
9 #include <linux/err.h>
10 #include <linux/io.h>
11 #include <linux/of.h>
12 #include <linux/platform_device.h>
13 #include <linux/seq_file.h>
14 #include <linux/slab.h>
15
16 #include <linux/pinctrl/pinconf-generic.h>
17 #include <linux/pinctrl/pinconf.h>
18 #include <linux/pinctrl/pinctrl.h>
19 #include <linux/pinctrl/pinmux.h>
20
21 #include "../core.h"
22 #include "../pinctrl-utils.h"
23
24 #define NS2_NUM_IOMUX 19
25 #define NS2_NUM_PWM_MUX 4
26
27 #define NS2_PIN_MUX_BASE0 0x00
28 #define NS2_PIN_MUX_BASE1 0x01
29 #define NS2_PIN_CONF_BASE 0x02
30 #define NS2_MUX_PAD_FUNC1_OFFSET 0x04
31
32 #define NS2_PIN_SRC_MASK 0x01
33 #define NS2_PIN_PULL_MASK 0x03
34 #define NS2_PIN_DRIVE_STRENGTH_MASK 0x07
35
36 #define NS2_PIN_PULL_UP 0x01
37 #define NS2_PIN_PULL_DOWN 0x02
38
39 #define NS2_PIN_INPUT_EN_MASK 0x01
40
41 /*
42 * Northstar2 IOMUX register description
43 *
44 * @base: base address number
45 * @offset: register offset for mux configuration of a group
46 * @shift: bit shift for mux configuration of a group
47 * @mask: mask bits
48 * @alt: alternate function to set to
49 */
50 struct ns2_mux {
51 unsigned int base;
52 unsigned int offset;
53 unsigned int shift;
54 unsigned int mask;
55 unsigned int alt;
56 };
57
58 /*
59 * Keep track of Northstar2 IOMUX configuration and prevent double
60 * configuration
61 *
62 * @ns2_mux: Northstar2 IOMUX register description
63 * @is_configured: flag to indicate whether a mux setting has already
64 * been configured
65 */
66 struct ns2_mux_log {
67 struct ns2_mux mux;
68 bool is_configured;
69 };
70
71 /*
72 * Group based IOMUX configuration
73 *
74 * @name: name of the group
75 * @pins: array of pins used by this group
76 * @num_pins: total number of pins used by this group
77 * @mux: Northstar2 group based IOMUX configuration
78 */
79 struct ns2_pin_group {
80 const char *name;
81 const unsigned int *pins;
82 const unsigned int num_pins;
83 const struct ns2_mux mux;
84 };
85
86 /*
87 * Northstar2 mux function and supported pin groups
88 *
89 * @name: name of the function
90 * @groups: array of groups that can be supported by this function
91 * @num_groups: total number of groups that can be supported by function
92 */
93 struct ns2_pin_function {
94 const char *name;
95 const char * const *groups;
96 const unsigned int num_groups;
97 };
98
99 /*
100 * Northstar2 IOMUX pinctrl core
101 *
102 * @pctl: pointer to pinctrl_dev
103 * @dev: pointer to device
104 * @base0: first IOMUX register base
105 * @base1: second IOMUX register base
106 * @pinconf_base: configuration register base
107 * @groups: pointer to array of groups
108 * @num_groups: total number of groups
109 * @functions: pointer to array of functions
110 * @num_functions: total number of functions
111 * @mux_log: pointer to the array of mux logs
112 * @lock: lock to protect register access
113 */
114 struct ns2_pinctrl {
115 struct pinctrl_dev *pctl;
116 struct device *dev;
117 void __iomem *base0;
118 void __iomem *base1;
119 void __iomem *pinconf_base;
120
121 const struct ns2_pin_group *groups;
122 unsigned int num_groups;
123
124 const struct ns2_pin_function *functions;
125 unsigned int num_functions;
126
127 struct ns2_mux_log *mux_log;
128
129 spinlock_t lock;
130 };
131
132 /*
133 * Pin configuration info
134 *
135 * @base: base address number
136 * @offset: register offset from base
137 * @src_shift: slew rate control bit shift in the register
138 * @input_en: input enable control bit shift
139 * @pull_shift: pull-up/pull-down control bit shift in the register
140 * @drive_shift: drive strength control bit shift in the register
141 */
142 struct ns2_pinconf {
143 unsigned int base;
144 unsigned int offset;
145 unsigned int src_shift;
146 unsigned int input_en;
147 unsigned int pull_shift;
148 unsigned int drive_shift;
149 };
150
151 /*
152 * Description of a pin in Northstar2
153 *
154 * @pin: pin number
155 * @name: pin name
156 * @pin_conf: pin configuration structure
157 */
158 struct ns2_pin {
159 unsigned int pin;
160 char *name;
161 struct ns2_pinconf pin_conf;
162 };
163
164 #define NS2_PIN_DESC(p, n, b, o, s, i, pu, d) \
165 { \
166 .pin = p, \
167 .name = n, \
168 .pin_conf = { \
169 .base = b, \
170 .offset = o, \
171 .src_shift = s, \
172 .input_en = i, \
173 .pull_shift = pu, \
174 .drive_shift = d, \
175 } \
176 }
177
178 /*
179 * List of pins in Northstar2
180 */
181 static struct ns2_pin ns2_pins[] = {
182 NS2_PIN_DESC(0, "mfio_0", -1, 0, 0, 0, 0, 0),
183 NS2_PIN_DESC(1, "mfio_1", -1, 0, 0, 0, 0, 0),
184 NS2_PIN_DESC(2, "mfio_2", -1, 0, 0, 0, 0, 0),
185 NS2_PIN_DESC(3, "mfio_3", -1, 0, 0, 0, 0, 0),
186 NS2_PIN_DESC(4, "mfio_4", -1, 0, 0, 0, 0, 0),
187 NS2_PIN_DESC(5, "mfio_5", -1, 0, 0, 0, 0, 0),
188 NS2_PIN_DESC(6, "mfio_6", -1, 0, 0, 0, 0, 0),
189 NS2_PIN_DESC(7, "mfio_7", -1, 0, 0, 0, 0, 0),
190 NS2_PIN_DESC(8, "mfio_8", -1, 0, 0, 0, 0, 0),
191 NS2_PIN_DESC(9, "mfio_9", -1, 0, 0, 0, 0, 0),
192 NS2_PIN_DESC(10, "mfio_10", -1, 0, 0, 0, 0, 0),
193 NS2_PIN_DESC(11, "mfio_11", -1, 0, 0, 0, 0, 0),
194 NS2_PIN_DESC(12, "mfio_12", -1, 0, 0, 0, 0, 0),
195 NS2_PIN_DESC(13, "mfio_13", -1, 0, 0, 0, 0, 0),
196 NS2_PIN_DESC(14, "mfio_14", -1, 0, 0, 0, 0, 0),
197 NS2_PIN_DESC(15, "mfio_15", -1, 0, 0, 0, 0, 0),
198 NS2_PIN_DESC(16, "mfio_16", -1, 0, 0, 0, 0, 0),
199 NS2_PIN_DESC(17, "mfio_17", -1, 0, 0, 0, 0, 0),
200 NS2_PIN_DESC(18, "mfio_18", -1, 0, 0, 0, 0, 0),
201 NS2_PIN_DESC(19, "mfio_19", -1, 0, 0, 0, 0, 0),
202 NS2_PIN_DESC(20, "mfio_20", -1, 0, 0, 0, 0, 0),
203 NS2_PIN_DESC(21, "mfio_21", -1, 0, 0, 0, 0, 0),
204 NS2_PIN_DESC(22, "mfio_22", -1, 0, 0, 0, 0, 0),
205 NS2_PIN_DESC(23, "mfio_23", -1, 0, 0, 0, 0, 0),
206 NS2_PIN_DESC(24, "mfio_24", -1, 0, 0, 0, 0, 0),
207 NS2_PIN_DESC(25, "mfio_25", -1, 0, 0, 0, 0, 0),
208 NS2_PIN_DESC(26, "mfio_26", -1, 0, 0, 0, 0, 0),
209 NS2_PIN_DESC(27, "mfio_27", -1, 0, 0, 0, 0, 0),
210 NS2_PIN_DESC(28, "mfio_28", -1, 0, 0, 0, 0, 0),
211 NS2_PIN_DESC(29, "mfio_29", -1, 0, 0, 0, 0, 0),
212 NS2_PIN_DESC(30, "mfio_30", -1, 0, 0, 0, 0, 0),
213 NS2_PIN_DESC(31, "mfio_31", -1, 0, 0, 0, 0, 0),
214 NS2_PIN_DESC(32, "mfio_32", -1, 0, 0, 0, 0, 0),
215 NS2_PIN_DESC(33, "mfio_33", -1, 0, 0, 0, 0, 0),
216 NS2_PIN_DESC(34, "mfio_34", -1, 0, 0, 0, 0, 0),
217 NS2_PIN_DESC(35, "mfio_35", -1, 0, 0, 0, 0, 0),
218 NS2_PIN_DESC(36, "mfio_36", -1, 0, 0, 0, 0, 0),
219 NS2_PIN_DESC(37, "mfio_37", -1, 0, 0, 0, 0, 0),
220 NS2_PIN_DESC(38, "mfio_38", -1, 0, 0, 0, 0, 0),
221 NS2_PIN_DESC(39, "mfio_39", -1, 0, 0, 0, 0, 0),
222 NS2_PIN_DESC(40, "mfio_40", -1, 0, 0, 0, 0, 0),
223 NS2_PIN_DESC(41, "mfio_41", -1, 0, 0, 0, 0, 0),
224 NS2_PIN_DESC(42, "mfio_42", -1, 0, 0, 0, 0, 0),
225 NS2_PIN_DESC(43, "mfio_43", -1, 0, 0, 0, 0, 0),
226 NS2_PIN_DESC(44, "mfio_44", -1, 0, 0, 0, 0, 0),
227 NS2_PIN_DESC(45, "mfio_45", -1, 0, 0, 0, 0, 0),
228 NS2_PIN_DESC(46, "mfio_46", -1, 0, 0, 0, 0, 0),
229 NS2_PIN_DESC(47, "mfio_47", -1, 0, 0, 0, 0, 0),
230 NS2_PIN_DESC(48, "mfio_48", -1, 0, 0, 0, 0, 0),
231 NS2_PIN_DESC(49, "mfio_49", -1, 0, 0, 0, 0, 0),
232 NS2_PIN_DESC(50, "mfio_50", -1, 0, 0, 0, 0, 0),
233 NS2_PIN_DESC(51, "mfio_51", -1, 0, 0, 0, 0, 0),
234 NS2_PIN_DESC(52, "mfio_52", -1, 0, 0, 0, 0, 0),
235 NS2_PIN_DESC(53, "mfio_53", -1, 0, 0, 0, 0, 0),
236 NS2_PIN_DESC(54, "mfio_54", -1, 0, 0, 0, 0, 0),
237 NS2_PIN_DESC(55, "mfio_55", -1, 0, 0, 0, 0, 0),
238 NS2_PIN_DESC(56, "mfio_56", -1, 0, 0, 0, 0, 0),
239 NS2_PIN_DESC(57, "mfio_57", -1, 0, 0, 0, 0, 0),
240 NS2_PIN_DESC(58, "mfio_58", -1, 0, 0, 0, 0, 0),
241 NS2_PIN_DESC(59, "mfio_59", -1, 0, 0, 0, 0, 0),
242 NS2_PIN_DESC(60, "mfio_60", -1, 0, 0, 0, 0, 0),
243 NS2_PIN_DESC(61, "mfio_61", -1, 0, 0, 0, 0, 0),
244 NS2_PIN_DESC(62, "mfio_62", -1, 0, 0, 0, 0, 0),
245 NS2_PIN_DESC(63, "qspi_wp", 2, 0x0, 31, 30, 27, 24),
246 NS2_PIN_DESC(64, "qspi_hold", 2, 0x0, 23, 22, 19, 16),
247 NS2_PIN_DESC(65, "qspi_cs", 2, 0x0, 15, 14, 11, 8),
248 NS2_PIN_DESC(66, "qspi_sck", 2, 0x0, 7, 6, 3, 0),
249 NS2_PIN_DESC(67, "uart3_sin", 2, 0x04, 31, 30, 27, 24),
250 NS2_PIN_DESC(68, "uart3_sout", 2, 0x04, 23, 22, 19, 16),
251 NS2_PIN_DESC(69, "qspi_mosi", 2, 0x04, 15, 14, 11, 8),
252 NS2_PIN_DESC(70, "qspi_miso", 2, 0x04, 7, 6, 3, 0),
253 NS2_PIN_DESC(71, "spi0_fss", 2, 0x08, 31, 30, 27, 24),
254 NS2_PIN_DESC(72, "spi0_rxd", 2, 0x08, 23, 22, 19, 16),
255 NS2_PIN_DESC(73, "spi0_txd", 2, 0x08, 15, 14, 11, 8),
256 NS2_PIN_DESC(74, "spi0_sck", 2, 0x08, 7, 6, 3, 0),
257 NS2_PIN_DESC(75, "spi1_fss", 2, 0x0c, 31, 30, 27, 24),
258 NS2_PIN_DESC(76, "spi1_rxd", 2, 0x0c, 23, 22, 19, 16),
259 NS2_PIN_DESC(77, "spi1_txd", 2, 0x0c, 15, 14, 11, 8),
260 NS2_PIN_DESC(78, "spi1_sck", 2, 0x0c, 7, 6, 3, 0),
261 NS2_PIN_DESC(79, "sdio0_data7", 2, 0x10, 31, 30, 27, 24),
262 NS2_PIN_DESC(80, "sdio0_emmc_rst", 2, 0x10, 23, 22, 19, 16),
263 NS2_PIN_DESC(81, "sdio0_led_on", 2, 0x10, 15, 14, 11, 8),
264 NS2_PIN_DESC(82, "sdio0_wp", 2, 0x10, 7, 6, 3, 0),
265 NS2_PIN_DESC(83, "sdio0_data3", 2, 0x14, 31, 30, 27, 24),
266 NS2_PIN_DESC(84, "sdio0_data4", 2, 0x14, 23, 22, 19, 16),
267 NS2_PIN_DESC(85, "sdio0_data5", 2, 0x14, 15, 14, 11, 8),
268 NS2_PIN_DESC(86, "sdio0_data6", 2, 0x14, 7, 6, 3, 0),
269 NS2_PIN_DESC(87, "sdio0_cmd", 2, 0x18, 31, 30, 27, 24),
270 NS2_PIN_DESC(88, "sdio0_data0", 2, 0x18, 23, 22, 19, 16),
271 NS2_PIN_DESC(89, "sdio0_data1", 2, 0x18, 15, 14, 11, 8),
272 NS2_PIN_DESC(90, "sdio0_data2", 2, 0x18, 7, 6, 3, 0),
273 NS2_PIN_DESC(91, "sdio1_led_on", 2, 0x1c, 31, 30, 27, 24),
274 NS2_PIN_DESC(92, "sdio1_wp", 2, 0x1c, 23, 22, 19, 16),
275 NS2_PIN_DESC(93, "sdio0_cd_l", 2, 0x1c, 15, 14, 11, 8),
276 NS2_PIN_DESC(94, "sdio0_clk", 2, 0x1c, 7, 6, 3, 0),
277 NS2_PIN_DESC(95, "sdio1_data5", 2, 0x20, 31, 30, 27, 24),
278 NS2_PIN_DESC(96, "sdio1_data6", 2, 0x20, 23, 22, 19, 16),
279 NS2_PIN_DESC(97, "sdio1_data7", 2, 0x20, 15, 14, 11, 8),
280 NS2_PIN_DESC(98, "sdio1_emmc_rst", 2, 0x20, 7, 6, 3, 0),
281 NS2_PIN_DESC(99, "sdio1_data1", 2, 0x24, 31, 30, 27, 24),
282 NS2_PIN_DESC(100, "sdio1_data2", 2, 0x24, 23, 22, 19, 16),
283 NS2_PIN_DESC(101, "sdio1_data3", 2, 0x24, 15, 14, 11, 8),
284 NS2_PIN_DESC(102, "sdio1_data4", 2, 0x24, 7, 6, 3, 0),
285 NS2_PIN_DESC(103, "sdio1_cd_l", 2, 0x28, 31, 30, 27, 24),
286 NS2_PIN_DESC(104, "sdio1_clk", 2, 0x28, 23, 22, 19, 16),
287 NS2_PIN_DESC(105, "sdio1_cmd", 2, 0x28, 15, 14, 11, 8),
288 NS2_PIN_DESC(106, "sdio1_data0", 2, 0x28, 7, 6, 3, 0),
289 NS2_PIN_DESC(107, "ext_mdio_0", 2, 0x2c, 15, 14, 11, 8),
290 NS2_PIN_DESC(108, "ext_mdc_0", 2, 0x2c, 7, 6, 3, 0),
291 NS2_PIN_DESC(109, "usb3_p1_vbus_ppc", 2, 0x34, 31, 30, 27, 24),
292 NS2_PIN_DESC(110, "usb3_p1_overcurrent", 2, 0x34, 23, 22, 19, 16),
293 NS2_PIN_DESC(111, "usb3_p0_vbus_ppc", 2, 0x34, 15, 14, 11, 8),
294 NS2_PIN_DESC(112, "usb3_p0_overcurrent", 2, 0x34, 7, 6, 3, 0),
295 NS2_PIN_DESC(113, "usb2_presence_indication", 2, 0x38, 31, 30, 27, 24),
296 NS2_PIN_DESC(114, "usb2_vbus_present", 2, 0x38, 23, 22, 19, 16),
297 NS2_PIN_DESC(115, "usb2_vbus_ppc", 2, 0x38, 15, 14, 11, 8),
298 NS2_PIN_DESC(116, "usb2_overcurrent", 2, 0x38, 7, 6, 3, 0),
299 NS2_PIN_DESC(117, "sata_led1", 2, 0x3c, 15, 14, 11, 8),
300 NS2_PIN_DESC(118, "sata_led0", 2, 0x3c, 7, 6, 3, 0),
301 };
302
303 /*
304 * List of groups of pins
305 */
306
307 static const unsigned int nand_pins[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
308 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23};
309 static const unsigned int nor_data_pins[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
310 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25};
311
312 static const unsigned int gpio_0_1_pins[] = {24, 25};
313 static const unsigned int pwm_0_pins[] = {24};
314 static const unsigned int pwm_1_pins[] = {25};
315
316 static const unsigned int uart1_ext_clk_pins[] = {26};
317 static const unsigned int nor_adv_pins[] = {26};
318
319 static const unsigned int gpio_2_5_pins[] = {27, 28, 29, 30};
320 static const unsigned int pcie_ab1_clk_wak_pins[] = {27, 28, 29, 30};
321 static const unsigned int nor_addr_0_3_pins[] = {27, 28, 29, 30};
322 static const unsigned int pwm_2_pins[] = {27};
323 static const unsigned int pwm_3_pins[] = {28};
324
325 static const unsigned int gpio_6_7_pins[] = {31, 32};
326 static const unsigned int pcie_a3_clk_wak_pins[] = {31, 32};
327 static const unsigned int nor_addr_4_5_pins[] = {31, 32};
328
329 static const unsigned int gpio_8_9_pins[] = {33, 34};
330 static const unsigned int pcie_b3_clk_wak_pins[] = {33, 34};
331 static const unsigned int nor_addr_6_7_pins[] = {33, 34};
332
333 static const unsigned int gpio_10_11_pins[] = {35, 36};
334 static const unsigned int pcie_b2_clk_wak_pins[] = {35, 36};
335 static const unsigned int nor_addr_8_9_pins[] = {35, 36};
336
337 static const unsigned int gpio_12_13_pins[] = {37, 38};
338 static const unsigned int pcie_a2_clk_wak_pins[] = {37, 38};
339 static const unsigned int nor_addr_10_11_pins[] = {37, 38};
340
341 static const unsigned int gpio_14_17_pins[] = {39, 40, 41, 42};
342 static const unsigned int uart0_modem_pins[] = {39, 40, 41, 42};
343 static const unsigned int nor_addr_12_15_pins[] = {39, 40, 41, 42};
344
345 static const unsigned int gpio_18_19_pins[] = {43, 44};
346 static const unsigned int uart0_rts_cts_pins[] = {43, 44};
347
348 static const unsigned int gpio_20_21_pins[] = {45, 46};
349 static const unsigned int uart0_in_out_pins[] = {45, 46};
350
351 static const unsigned int gpio_22_23_pins[] = {47, 48};
352 static const unsigned int uart1_dcd_dsr_pins[] = {47, 48};
353
354 static const unsigned int gpio_24_25_pins[] = {49, 50};
355 static const unsigned int uart1_ri_dtr_pins[] = {49, 50};
356
357 static const unsigned int gpio_26_27_pins[] = {51, 52};
358 static const unsigned int uart1_rts_cts_pins[] = {51, 52};
359
360 static const unsigned int gpio_28_29_pins[] = {53, 54};
361 static const unsigned int uart1_in_out_pins[] = {53, 54};
362
363 static const unsigned int gpio_30_31_pins[] = {55, 56};
364 static const unsigned int uart2_rts_cts_pins[] = {55, 56};
365
366 #define NS2_PIN_GROUP(group_name, ba, off, sh, ma, al) \
367 { \
368 .name = __stringify(group_name) "_grp", \
369 .pins = group_name ## _pins, \
370 .num_pins = ARRAY_SIZE(group_name ## _pins), \
371 .mux = { \
372 .base = ba, \
373 .offset = off, \
374 .shift = sh, \
375 .mask = ma, \
376 .alt = al, \
377 } \
378 }
379
380 /*
381 * List of Northstar2 pin groups
382 */
383 static const struct ns2_pin_group ns2_pin_groups[] = {
384 NS2_PIN_GROUP(nand, 0, 0, 31, 1, 0),
385 NS2_PIN_GROUP(nor_data, 0, 0, 31, 1, 1),
386 NS2_PIN_GROUP(gpio_0_1, 0, 0, 31, 1, 0),
387
388 NS2_PIN_GROUP(uart1_ext_clk, 0, 4, 30, 3, 1),
389 NS2_PIN_GROUP(nor_adv, 0, 4, 30, 3, 2),
390
391 NS2_PIN_GROUP(gpio_2_5, 0, 4, 28, 3, 0),
392 NS2_PIN_GROUP(pcie_ab1_clk_wak, 0, 4, 28, 3, 1),
393 NS2_PIN_GROUP(nor_addr_0_3, 0, 4, 28, 3, 2),
394
395 NS2_PIN_GROUP(gpio_6_7, 0, 4, 26, 3, 0),
396 NS2_PIN_GROUP(pcie_a3_clk_wak, 0, 4, 26, 3, 1),
397 NS2_PIN_GROUP(nor_addr_4_5, 0, 4, 26, 3, 2),
398
399 NS2_PIN_GROUP(gpio_8_9, 0, 4, 24, 3, 0),
400 NS2_PIN_GROUP(pcie_b3_clk_wak, 0, 4, 24, 3, 1),
401 NS2_PIN_GROUP(nor_addr_6_7, 0, 4, 24, 3, 2),
402
403 NS2_PIN_GROUP(gpio_10_11, 0, 4, 22, 3, 0),
404 NS2_PIN_GROUP(pcie_b2_clk_wak, 0, 4, 22, 3, 1),
405 NS2_PIN_GROUP(nor_addr_8_9, 0, 4, 22, 3, 2),
406
407 NS2_PIN_GROUP(gpio_12_13, 0, 4, 20, 3, 0),
408 NS2_PIN_GROUP(pcie_a2_clk_wak, 0, 4, 20, 3, 1),
409 NS2_PIN_GROUP(nor_addr_10_11, 0, 4, 20, 3, 2),
410
411 NS2_PIN_GROUP(gpio_14_17, 0, 4, 18, 3, 0),
412 NS2_PIN_GROUP(uart0_modem, 0, 4, 18, 3, 1),
413 NS2_PIN_GROUP(nor_addr_12_15, 0, 4, 18, 3, 2),
414
415 NS2_PIN_GROUP(gpio_18_19, 0, 4, 16, 3, 0),
416 NS2_PIN_GROUP(uart0_rts_cts, 0, 4, 16, 3, 1),
417
418 NS2_PIN_GROUP(gpio_20_21, 0, 4, 14, 3, 0),
419 NS2_PIN_GROUP(uart0_in_out, 0, 4, 14, 3, 1),
420
421 NS2_PIN_GROUP(gpio_22_23, 0, 4, 12, 3, 0),
422 NS2_PIN_GROUP(uart1_dcd_dsr, 0, 4, 12, 3, 1),
423
424 NS2_PIN_GROUP(gpio_24_25, 0, 4, 10, 3, 0),
425 NS2_PIN_GROUP(uart1_ri_dtr, 0, 4, 10, 3, 1),
426
427 NS2_PIN_GROUP(gpio_26_27, 0, 4, 8, 3, 0),
428 NS2_PIN_GROUP(uart1_rts_cts, 0, 4, 8, 3, 1),
429
430 NS2_PIN_GROUP(gpio_28_29, 0, 4, 6, 3, 0),
431 NS2_PIN_GROUP(uart1_in_out, 0, 4, 6, 3, 1),
432
433 NS2_PIN_GROUP(gpio_30_31, 0, 4, 4, 3, 0),
434 NS2_PIN_GROUP(uart2_rts_cts, 0, 4, 4, 3, 1),
435
436 NS2_PIN_GROUP(pwm_0, 1, 0, 0, 1, 1),
437 NS2_PIN_GROUP(pwm_1, 1, 0, 1, 1, 1),
438 NS2_PIN_GROUP(pwm_2, 1, 0, 2, 1, 1),
439 NS2_PIN_GROUP(pwm_3, 1, 0, 3, 1, 1),
440 };
441
442 /*
443 * List of groups supported by functions
444 */
445
446 static const char * const nand_grps[] = {"nand_grp"};
447
448 static const char * const nor_grps[] = {"nor_data_grp", "nor_adv_grp",
449 "nor_addr_0_3_grp", "nor_addr_4_5_grp", "nor_addr_6_7_grp",
450 "nor_addr_8_9_grp", "nor_addr_10_11_grp", "nor_addr_12_15_grp"};
451
452 static const char * const gpio_grps[] = {"gpio_0_1_grp", "gpio_2_5_grp",
453 "gpio_6_7_grp", "gpio_8_9_grp", "gpio_10_11_grp", "gpio_12_13_grp",
454 "gpio_14_17_grp", "gpio_18_19_grp", "gpio_20_21_grp", "gpio_22_23_grp",
455 "gpio_24_25_grp", "gpio_26_27_grp", "gpio_28_29_grp",
456 "gpio_30_31_grp"};
457
458 static const char * const pcie_grps[] = {"pcie_ab1_clk_wak_grp",
459 "pcie_a3_clk_wak_grp", "pcie_b3_clk_wak_grp", "pcie_b2_clk_wak_grp",
460 "pcie_a2_clk_wak_grp"};
461
462 static const char * const uart0_grps[] = {"uart0_modem_grp",
463 "uart0_rts_cts_grp", "uart0_in_out_grp"};
464
465 static const char * const uart1_grps[] = {"uart1_ext_clk_grp",
466 "uart1_dcd_dsr_grp", "uart1_ri_dtr_grp", "uart1_rts_cts_grp",
467 "uart1_in_out_grp"};
468
469 static const char * const uart2_grps[] = {"uart2_rts_cts_grp"};
470
471 static const char * const pwm_grps[] = {"pwm_0_grp", "pwm_1_grp",
472 "pwm_2_grp", "pwm_3_grp"};
473
474 #define NS2_PIN_FUNCTION(func) \
475 { \
476 .name = #func, \
477 .groups = func ## _grps, \
478 .num_groups = ARRAY_SIZE(func ## _grps), \
479 }
480
481 /*
482 * List of supported functions
483 */
484 static const struct ns2_pin_function ns2_pin_functions[] = {
485 NS2_PIN_FUNCTION(nand),
486 NS2_PIN_FUNCTION(nor),
487 NS2_PIN_FUNCTION(gpio),
488 NS2_PIN_FUNCTION(pcie),
489 NS2_PIN_FUNCTION(uart0),
490 NS2_PIN_FUNCTION(uart1),
491 NS2_PIN_FUNCTION(uart2),
492 NS2_PIN_FUNCTION(pwm),
493 };
494
ns2_get_groups_count(struct pinctrl_dev * pctrl_dev)495 static int ns2_get_groups_count(struct pinctrl_dev *pctrl_dev)
496 {
497 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
498
499 return pinctrl->num_groups;
500 }
501
ns2_get_group_name(struct pinctrl_dev * pctrl_dev,unsigned int selector)502 static const char *ns2_get_group_name(struct pinctrl_dev *pctrl_dev,
503 unsigned int selector)
504 {
505 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
506
507 return pinctrl->groups[selector].name;
508 }
509
ns2_get_group_pins(struct pinctrl_dev * pctrl_dev,unsigned int selector,const unsigned int ** pins,unsigned int * num_pins)510 static int ns2_get_group_pins(struct pinctrl_dev *pctrl_dev,
511 unsigned int selector, const unsigned int **pins,
512 unsigned int *num_pins)
513 {
514 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
515
516 *pins = pinctrl->groups[selector].pins;
517 *num_pins = pinctrl->groups[selector].num_pins;
518
519 return 0;
520 }
521
ns2_pin_dbg_show(struct pinctrl_dev * pctrl_dev,struct seq_file * s,unsigned int offset)522 static void ns2_pin_dbg_show(struct pinctrl_dev *pctrl_dev,
523 struct seq_file *s, unsigned int offset)
524 {
525 seq_printf(s, " %s", dev_name(pctrl_dev->dev));
526 }
527
528 static const struct pinctrl_ops ns2_pinctrl_ops = {
529 .get_groups_count = ns2_get_groups_count,
530 .get_group_name = ns2_get_group_name,
531 .get_group_pins = ns2_get_group_pins,
532 .pin_dbg_show = ns2_pin_dbg_show,
533 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
534 .dt_free_map = pinctrl_utils_free_map,
535 };
536
ns2_get_functions_count(struct pinctrl_dev * pctrl_dev)537 static int ns2_get_functions_count(struct pinctrl_dev *pctrl_dev)
538 {
539 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
540
541 return pinctrl->num_functions;
542 }
543
ns2_get_function_name(struct pinctrl_dev * pctrl_dev,unsigned int selector)544 static const char *ns2_get_function_name(struct pinctrl_dev *pctrl_dev,
545 unsigned int selector)
546 {
547 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
548
549 return pinctrl->functions[selector].name;
550 }
551
ns2_get_function_groups(struct pinctrl_dev * pctrl_dev,unsigned int selector,const char * const ** groups,unsigned int * const num_groups)552 static int ns2_get_function_groups(struct pinctrl_dev *pctrl_dev,
553 unsigned int selector,
554 const char * const **groups,
555 unsigned int * const num_groups)
556 {
557 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
558
559 *groups = pinctrl->functions[selector].groups;
560 *num_groups = pinctrl->functions[selector].num_groups;
561
562 return 0;
563 }
564
ns2_pinmux_set(struct ns2_pinctrl * pinctrl,const struct ns2_pin_function * func,const struct ns2_pin_group * grp,struct ns2_mux_log * mux_log)565 static int ns2_pinmux_set(struct ns2_pinctrl *pinctrl,
566 const struct ns2_pin_function *func,
567 const struct ns2_pin_group *grp,
568 struct ns2_mux_log *mux_log)
569 {
570 const struct ns2_mux *mux = &grp->mux;
571 int i;
572 u32 val, mask;
573 unsigned long flags;
574 void __iomem *base_address;
575
576 for (i = 0; i < NS2_NUM_IOMUX; i++) {
577 if ((mux->shift != mux_log[i].mux.shift) ||
578 (mux->base != mux_log[i].mux.base) ||
579 (mux->offset != mux_log[i].mux.offset))
580 continue;
581
582 /* if this is a new configuration, just do it! */
583 if (!mux_log[i].is_configured)
584 break;
585
586 /*
587 * IOMUX has been configured previously and one is trying to
588 * configure it to a different function
589 */
590 if (mux_log[i].mux.alt != mux->alt) {
591 dev_err(pinctrl->dev,
592 "double configuration error detected!\n");
593 dev_err(pinctrl->dev, "func:%s grp:%s\n",
594 func->name, grp->name);
595 return -EINVAL;
596 }
597
598 return 0;
599 }
600 if (i == NS2_NUM_IOMUX)
601 return -EINVAL;
602
603 mask = mux->mask;
604 mux_log[i].mux.alt = mux->alt;
605 mux_log[i].is_configured = true;
606
607 switch (mux->base) {
608 case NS2_PIN_MUX_BASE0:
609 base_address = pinctrl->base0;
610 break;
611
612 case NS2_PIN_MUX_BASE1:
613 base_address = pinctrl->base1;
614 break;
615
616 default:
617 return -EINVAL;
618 }
619
620 spin_lock_irqsave(&pinctrl->lock, flags);
621 val = readl(base_address + grp->mux.offset);
622 val &= ~(mask << grp->mux.shift);
623 val |= grp->mux.alt << grp->mux.shift;
624 writel(val, (base_address + grp->mux.offset));
625 spin_unlock_irqrestore(&pinctrl->lock, flags);
626
627 return 0;
628 }
629
ns2_pinmux_enable(struct pinctrl_dev * pctrl_dev,unsigned int func_select,unsigned int grp_select)630 static int ns2_pinmux_enable(struct pinctrl_dev *pctrl_dev,
631 unsigned int func_select, unsigned int grp_select)
632 {
633 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
634 const struct ns2_pin_function *func;
635 const struct ns2_pin_group *grp;
636
637 if (grp_select >= pinctrl->num_groups ||
638 func_select >= pinctrl->num_functions)
639 return -EINVAL;
640
641 func = &pinctrl->functions[func_select];
642 grp = &pinctrl->groups[grp_select];
643
644 dev_dbg(pctrl_dev->dev, "func:%u name:%s grp:%u name:%s\n",
645 func_select, func->name, grp_select, grp->name);
646
647 dev_dbg(pctrl_dev->dev, "offset:0x%08x shift:%u alt:%u\n",
648 grp->mux.offset, grp->mux.shift, grp->mux.alt);
649
650 return ns2_pinmux_set(pinctrl, func, grp, pinctrl->mux_log);
651 }
652
ns2_pin_set_enable(struct pinctrl_dev * pctrldev,unsigned int pin,u16 enable)653 static int ns2_pin_set_enable(struct pinctrl_dev *pctrldev, unsigned int pin,
654 u16 enable)
655 {
656 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
657 struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
658 unsigned long flags;
659 u32 val;
660 void __iomem *base_address;
661
662 base_address = pinctrl->pinconf_base;
663 spin_lock_irqsave(&pinctrl->lock, flags);
664 val = readl(base_address + pin_data->pin_conf.offset);
665 val &= ~(NS2_PIN_SRC_MASK << pin_data->pin_conf.input_en);
666
667 if (!enable)
668 val |= NS2_PIN_INPUT_EN_MASK << pin_data->pin_conf.input_en;
669
670 writel(val, (base_address + pin_data->pin_conf.offset));
671 spin_unlock_irqrestore(&pinctrl->lock, flags);
672
673 dev_dbg(pctrldev->dev, "pin:%u set enable:%d\n", pin, enable);
674 return 0;
675 }
676
ns2_pin_get_enable(struct pinctrl_dev * pctrldev,unsigned int pin)677 static int ns2_pin_get_enable(struct pinctrl_dev *pctrldev, unsigned int pin)
678 {
679 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
680 struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
681 unsigned long flags;
682 int enable;
683
684 spin_lock_irqsave(&pinctrl->lock, flags);
685 enable = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset);
686 enable = (enable >> pin_data->pin_conf.input_en) &
687 NS2_PIN_INPUT_EN_MASK;
688 spin_unlock_irqrestore(&pinctrl->lock, flags);
689
690 if (!enable)
691 enable = NS2_PIN_INPUT_EN_MASK;
692 else
693 enable = 0;
694
695 dev_dbg(pctrldev->dev, "pin:%u get disable:%d\n", pin, enable);
696 return enable;
697 }
698
ns2_pin_set_slew(struct pinctrl_dev * pctrldev,unsigned int pin,u32 slew)699 static int ns2_pin_set_slew(struct pinctrl_dev *pctrldev, unsigned int pin,
700 u32 slew)
701 {
702 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
703 struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
704 unsigned long flags;
705 u32 val;
706 void __iomem *base_address;
707
708 base_address = pinctrl->pinconf_base;
709 spin_lock_irqsave(&pinctrl->lock, flags);
710 val = readl(base_address + pin_data->pin_conf.offset);
711 val &= ~(NS2_PIN_SRC_MASK << pin_data->pin_conf.src_shift);
712
713 if (slew)
714 val |= NS2_PIN_SRC_MASK << pin_data->pin_conf.src_shift;
715
716 writel(val, (base_address + pin_data->pin_conf.offset));
717 spin_unlock_irqrestore(&pinctrl->lock, flags);
718
719 dev_dbg(pctrldev->dev, "pin:%u set slew:%d\n", pin, slew);
720 return 0;
721 }
722
ns2_pin_get_slew(struct pinctrl_dev * pctrldev,unsigned int pin,u16 * slew)723 static int ns2_pin_get_slew(struct pinctrl_dev *pctrldev, unsigned int pin,
724 u16 *slew)
725 {
726 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
727 struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
728 unsigned long flags;
729 u32 val;
730
731 spin_lock_irqsave(&pinctrl->lock, flags);
732 val = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset);
733 *slew = (val >> pin_data->pin_conf.src_shift) & NS2_PIN_SRC_MASK;
734 spin_unlock_irqrestore(&pinctrl->lock, flags);
735
736 dev_dbg(pctrldev->dev, "pin:%u get slew:%d\n", pin, *slew);
737 return 0;
738 }
739
ns2_pin_set_pull(struct pinctrl_dev * pctrldev,unsigned int pin,bool pull_up,bool pull_down)740 static int ns2_pin_set_pull(struct pinctrl_dev *pctrldev, unsigned int pin,
741 bool pull_up, bool pull_down)
742 {
743 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
744 struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
745 unsigned long flags;
746 u32 val;
747 void __iomem *base_address;
748
749 base_address = pinctrl->pinconf_base;
750 spin_lock_irqsave(&pinctrl->lock, flags);
751 val = readl(base_address + pin_data->pin_conf.offset);
752 val &= ~(NS2_PIN_PULL_MASK << pin_data->pin_conf.pull_shift);
753
754 if (pull_up == true)
755 val |= NS2_PIN_PULL_UP << pin_data->pin_conf.pull_shift;
756 if (pull_down == true)
757 val |= NS2_PIN_PULL_DOWN << pin_data->pin_conf.pull_shift;
758 writel(val, (base_address + pin_data->pin_conf.offset));
759 spin_unlock_irqrestore(&pinctrl->lock, flags);
760
761 dev_dbg(pctrldev->dev, "pin:%u set pullup:%d pulldown: %d\n",
762 pin, pull_up, pull_down);
763 return 0;
764 }
765
ns2_pin_get_pull(struct pinctrl_dev * pctrldev,unsigned int pin,bool * pull_up,bool * pull_down)766 static void ns2_pin_get_pull(struct pinctrl_dev *pctrldev,
767 unsigned int pin, bool *pull_up,
768 bool *pull_down)
769 {
770 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
771 struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
772 unsigned long flags;
773 u32 val;
774
775 spin_lock_irqsave(&pinctrl->lock, flags);
776 val = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset);
777 val = (val >> pin_data->pin_conf.pull_shift) & NS2_PIN_PULL_MASK;
778 *pull_up = false;
779 *pull_down = false;
780
781 if (val == NS2_PIN_PULL_UP)
782 *pull_up = true;
783
784 if (val == NS2_PIN_PULL_DOWN)
785 *pull_down = true;
786 spin_unlock_irqrestore(&pinctrl->lock, flags);
787 }
788
ns2_pin_set_strength(struct pinctrl_dev * pctrldev,unsigned int pin,u32 strength)789 static int ns2_pin_set_strength(struct pinctrl_dev *pctrldev, unsigned int pin,
790 u32 strength)
791 {
792 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
793 struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
794 u32 val;
795 unsigned long flags;
796 void __iomem *base_address;
797
798 /* make sure drive strength is supported */
799 if (strength < 2 || strength > 16 || (strength % 2))
800 return -ENOTSUPP;
801
802 base_address = pinctrl->pinconf_base;
803 spin_lock_irqsave(&pinctrl->lock, flags);
804 val = readl(base_address + pin_data->pin_conf.offset);
805 val &= ~(NS2_PIN_DRIVE_STRENGTH_MASK << pin_data->pin_conf.drive_shift);
806 val |= ((strength / 2) - 1) << pin_data->pin_conf.drive_shift;
807 writel(val, (base_address + pin_data->pin_conf.offset));
808 spin_unlock_irqrestore(&pinctrl->lock, flags);
809
810 dev_dbg(pctrldev->dev, "pin:%u set drive strength:%d mA\n",
811 pin, strength);
812 return 0;
813 }
814
ns2_pin_get_strength(struct pinctrl_dev * pctrldev,unsigned int pin,u16 * strength)815 static int ns2_pin_get_strength(struct pinctrl_dev *pctrldev, unsigned int pin,
816 u16 *strength)
817 {
818 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
819 struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
820 u32 val;
821 unsigned long flags;
822
823 spin_lock_irqsave(&pinctrl->lock, flags);
824 val = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset);
825 *strength = (val >> pin_data->pin_conf.drive_shift) &
826 NS2_PIN_DRIVE_STRENGTH_MASK;
827 *strength = (*strength + 1) * 2;
828 spin_unlock_irqrestore(&pinctrl->lock, flags);
829
830 dev_dbg(pctrldev->dev, "pin:%u get drive strength:%d mA\n",
831 pin, *strength);
832 return 0;
833 }
834
ns2_pin_config_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)835 static int ns2_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
836 unsigned long *config)
837 {
838 struct ns2_pin *pin_data = pctldev->desc->pins[pin].drv_data;
839 enum pin_config_param param = pinconf_to_config_param(*config);
840 bool pull_up, pull_down;
841 u16 arg = 0;
842 int ret;
843
844 if (pin_data->pin_conf.base == -1)
845 return -ENOTSUPP;
846
847 switch (param) {
848 case PIN_CONFIG_BIAS_DISABLE:
849 ns2_pin_get_pull(pctldev, pin, &pull_up, &pull_down);
850 if (!pull_up && !pull_down)
851 return 0;
852 else
853 return -EINVAL;
854
855 case PIN_CONFIG_BIAS_PULL_UP:
856 ns2_pin_get_pull(pctldev, pin, &pull_up, &pull_down);
857 if (pull_up)
858 return 0;
859 else
860 return -EINVAL;
861
862 case PIN_CONFIG_BIAS_PULL_DOWN:
863 ns2_pin_get_pull(pctldev, pin, &pull_up, &pull_down);
864 if (pull_down)
865 return 0;
866 else
867 return -EINVAL;
868
869 case PIN_CONFIG_DRIVE_STRENGTH:
870 ret = ns2_pin_get_strength(pctldev, pin, &arg);
871 if (ret)
872 return ret;
873 *config = pinconf_to_config_packed(param, arg);
874 return 0;
875
876 case PIN_CONFIG_SLEW_RATE:
877 ret = ns2_pin_get_slew(pctldev, pin, &arg);
878 if (ret)
879 return ret;
880 *config = pinconf_to_config_packed(param, arg);
881 return 0;
882
883 case PIN_CONFIG_INPUT_ENABLE:
884 ret = ns2_pin_get_enable(pctldev, pin);
885 if (ret)
886 return 0;
887 else
888 return -EINVAL;
889
890 default:
891 return -ENOTSUPP;
892 }
893 }
894
ns2_pin_config_set(struct pinctrl_dev * pctrldev,unsigned int pin,unsigned long * configs,unsigned int num_configs)895 static int ns2_pin_config_set(struct pinctrl_dev *pctrldev, unsigned int pin,
896 unsigned long *configs, unsigned int num_configs)
897 {
898 struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
899 enum pin_config_param param;
900 unsigned int i;
901 u32 arg;
902 int ret = -ENOTSUPP;
903
904 if (pin_data->pin_conf.base == -1)
905 return -ENOTSUPP;
906
907 for (i = 0; i < num_configs; i++) {
908 param = pinconf_to_config_param(configs[i]);
909 arg = pinconf_to_config_argument(configs[i]);
910
911 switch (param) {
912 case PIN_CONFIG_BIAS_DISABLE:
913 ret = ns2_pin_set_pull(pctrldev, pin, false, false);
914 if (ret < 0)
915 goto out;
916 break;
917
918 case PIN_CONFIG_BIAS_PULL_UP:
919 ret = ns2_pin_set_pull(pctrldev, pin, true, false);
920 if (ret < 0)
921 goto out;
922 break;
923
924 case PIN_CONFIG_BIAS_PULL_DOWN:
925 ret = ns2_pin_set_pull(pctrldev, pin, false, true);
926 if (ret < 0)
927 goto out;
928 break;
929
930 case PIN_CONFIG_DRIVE_STRENGTH:
931 ret = ns2_pin_set_strength(pctrldev, pin, arg);
932 if (ret < 0)
933 goto out;
934 break;
935
936 case PIN_CONFIG_SLEW_RATE:
937 ret = ns2_pin_set_slew(pctrldev, pin, arg);
938 if (ret < 0)
939 goto out;
940 break;
941
942 case PIN_CONFIG_INPUT_ENABLE:
943 ret = ns2_pin_set_enable(pctrldev, pin, arg);
944 if (ret < 0)
945 goto out;
946 break;
947
948 default:
949 dev_err(pctrldev->dev, "invalid configuration\n");
950 return -ENOTSUPP;
951 }
952 }
953 out:
954 return ret;
955 }
956 static const struct pinmux_ops ns2_pinmux_ops = {
957 .get_functions_count = ns2_get_functions_count,
958 .get_function_name = ns2_get_function_name,
959 .get_function_groups = ns2_get_function_groups,
960 .set_mux = ns2_pinmux_enable,
961 };
962
963 static const struct pinconf_ops ns2_pinconf_ops = {
964 .is_generic = true,
965 .pin_config_get = ns2_pin_config_get,
966 .pin_config_set = ns2_pin_config_set,
967 };
968
969 static struct pinctrl_desc ns2_pinctrl_desc = {
970 .name = "ns2-pinmux",
971 .pctlops = &ns2_pinctrl_ops,
972 .pmxops = &ns2_pinmux_ops,
973 .confops = &ns2_pinconf_ops,
974 };
975
ns2_mux_log_init(struct ns2_pinctrl * pinctrl)976 static int ns2_mux_log_init(struct ns2_pinctrl *pinctrl)
977 {
978 struct ns2_mux_log *log;
979 unsigned int i;
980
981 pinctrl->mux_log = devm_kcalloc(pinctrl->dev, NS2_NUM_IOMUX,
982 sizeof(struct ns2_mux_log),
983 GFP_KERNEL);
984 if (!pinctrl->mux_log)
985 return -ENOMEM;
986
987 for (i = 0; i < NS2_NUM_IOMUX; i++)
988 pinctrl->mux_log[i].is_configured = false;
989 /* Group 0 uses bit 31 in the IOMUX_PAD_FUNCTION_0 register */
990 log = &pinctrl->mux_log[0];
991 log->mux.base = NS2_PIN_MUX_BASE0;
992 log->mux.offset = 0;
993 log->mux.shift = 31;
994 log->mux.alt = 0;
995
996 /*
997 * Groups 1 through 14 use two bits each in the
998 * IOMUX_PAD_FUNCTION_1 register starting with
999 * bit position 30.
1000 */
1001 for (i = 1; i < (NS2_NUM_IOMUX - NS2_NUM_PWM_MUX); i++) {
1002 log = &pinctrl->mux_log[i];
1003 log->mux.base = NS2_PIN_MUX_BASE0;
1004 log->mux.offset = NS2_MUX_PAD_FUNC1_OFFSET;
1005 log->mux.shift = 32 - (i * 2);
1006 log->mux.alt = 0;
1007 }
1008
1009 /*
1010 * Groups 15 through 18 use one bit each in the
1011 * AUX_SEL register.
1012 */
1013 for (i = 0; i < NS2_NUM_PWM_MUX; i++) {
1014 log = &pinctrl->mux_log[(NS2_NUM_IOMUX - NS2_NUM_PWM_MUX) + i];
1015 log->mux.base = NS2_PIN_MUX_BASE1;
1016 log->mux.offset = 0;
1017 log->mux.shift = i;
1018 log->mux.alt = 0;
1019 }
1020 return 0;
1021 }
1022
ns2_pinmux_probe(struct platform_device * pdev)1023 static int ns2_pinmux_probe(struct platform_device *pdev)
1024 {
1025 struct ns2_pinctrl *pinctrl;
1026 struct resource *res;
1027 int i, ret;
1028 struct pinctrl_pin_desc *pins;
1029 unsigned int num_pins = ARRAY_SIZE(ns2_pins);
1030
1031 pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL);
1032 if (!pinctrl)
1033 return -ENOMEM;
1034
1035 pinctrl->dev = &pdev->dev;
1036 platform_set_drvdata(pdev, pinctrl);
1037 spin_lock_init(&pinctrl->lock);
1038
1039 pinctrl->base0 = devm_platform_ioremap_resource(pdev, 0);
1040 if (IS_ERR(pinctrl->base0))
1041 return PTR_ERR(pinctrl->base0);
1042
1043 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1044 if (!res)
1045 return -EINVAL;
1046 pinctrl->base1 = devm_ioremap(&pdev->dev, res->start,
1047 resource_size(res));
1048 if (!pinctrl->base1) {
1049 dev_err(&pdev->dev, "unable to map I/O space\n");
1050 return -ENOMEM;
1051 }
1052
1053 pinctrl->pinconf_base = devm_platform_ioremap_resource(pdev, 2);
1054 if (IS_ERR(pinctrl->pinconf_base))
1055 return PTR_ERR(pinctrl->pinconf_base);
1056
1057 ret = ns2_mux_log_init(pinctrl);
1058 if (ret) {
1059 dev_err(&pdev->dev, "unable to initialize IOMUX log\n");
1060 return ret;
1061 }
1062
1063 pins = devm_kcalloc(&pdev->dev, num_pins, sizeof(*pins), GFP_KERNEL);
1064 if (!pins)
1065 return -ENOMEM;
1066
1067 for (i = 0; i < num_pins; i++) {
1068 pins[i].number = ns2_pins[i].pin;
1069 pins[i].name = ns2_pins[i].name;
1070 pins[i].drv_data = &ns2_pins[i];
1071 }
1072
1073 pinctrl->groups = ns2_pin_groups;
1074 pinctrl->num_groups = ARRAY_SIZE(ns2_pin_groups);
1075 pinctrl->functions = ns2_pin_functions;
1076 pinctrl->num_functions = ARRAY_SIZE(ns2_pin_functions);
1077 ns2_pinctrl_desc.pins = pins;
1078 ns2_pinctrl_desc.npins = num_pins;
1079
1080 pinctrl->pctl = pinctrl_register(&ns2_pinctrl_desc, &pdev->dev,
1081 pinctrl);
1082 if (IS_ERR(pinctrl->pctl)) {
1083 dev_err(&pdev->dev, "unable to register IOMUX pinctrl\n");
1084 return PTR_ERR(pinctrl->pctl);
1085 }
1086
1087 return 0;
1088 }
1089
1090 static const struct of_device_id ns2_pinmux_of_match[] = {
1091 {.compatible = "brcm,ns2-pinmux"},
1092 { }
1093 };
1094
1095 static struct platform_driver ns2_pinmux_driver = {
1096 .driver = {
1097 .name = "ns2-pinmux",
1098 .of_match_table = ns2_pinmux_of_match,
1099 },
1100 .probe = ns2_pinmux_probe,
1101 };
1102
ns2_pinmux_init(void)1103 static int __init ns2_pinmux_init(void)
1104 {
1105 return platform_driver_register(&ns2_pinmux_driver);
1106 }
1107 arch_initcall(ns2_pinmux_init);
1108