xref: /openbmc/linux/drivers/edac/edac_pci.h (revision fdaf0b35)
1 /*
2  * Defines, structures, APIs for edac_pci and edac_pci_sysfs
3  *
4  * (C) 2007 Linux Networx (http://lnxi.com)
5  * This file may be distributed under the terms of the
6  * GNU General Public License.
7  *
8  * Written by Thayne Harbaugh
9  * Based on work by Dan Hollis <goemon at anime dot net> and others.
10  *	http://www.anime.net/~goemon/linux-ecc/
11  *
12  * NMI handling support added by
13  *     Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>
14  *
15  * Refactored for multi-source files:
16  *	Doug Thompson <norsk5@xmission.com>
17  *
18  * Please look at Documentation/driver-api/edac.rst for more info about
19  * EDAC core structs and functions.
20  */
21 
22 #ifndef _EDAC_PCI_H_
23 #define _EDAC_PCI_H_
24 
25 #include <linux/completion.h>
26 #include <linux/device.h>
27 #include <linux/edac.h>
28 #include <linux/kobject.h>
29 #include <linux/list.h>
30 #include <linux/pci.h>
31 #include <linux/types.h>
32 #include <linux/workqueue.h>
33 
34 #ifdef CONFIG_PCI
35 
36 struct edac_pci_counter {
37 	atomic_t pe_count;
38 	atomic_t npe_count;
39 };
40 
41 /*
42  * Abstract edac_pci control info structure
43  *
44  */
45 struct edac_pci_ctl_info {
46 	/* for global list of edac_pci_ctl_info structs */
47 	struct list_head link;
48 
49 	int pci_idx;
50 
51 	struct bus_type *edac_subsys;	/* pointer to subsystem */
52 
53 	/* the internal state of this controller instance */
54 	int op_state;
55 	/* work struct for this instance */
56 	struct delayed_work work;
57 
58 	/* pointer to edac polling checking routine:
59 	 *      If NOT NULL: points to polling check routine
60 	 *      If NULL: Then assumes INTERRUPT operation, where
61 	 *              MC driver will receive events
62 	 */
63 	void (*edac_check) (struct edac_pci_ctl_info * edac_dev);
64 
65 	struct device *dev;	/* pointer to device structure */
66 
67 	const char *mod_name;	/* module name */
68 	const char *ctl_name;	/* edac controller  name */
69 	const char *dev_name;	/* pci/platform/etc... name */
70 
71 	void *pvt_info;		/* pointer to 'private driver' info */
72 
73 	unsigned long start_time;	/* edac_pci load start time (jiffies) */
74 
75 	struct completion complete;
76 
77 	/* sysfs top name under 'edac' directory
78 	 * and instance name:
79 	 *      cpu/cpu0/...
80 	 *      cpu/cpu1/...
81 	 *      cpu/cpu2/...
82 	 *      ...
83 	 */
84 	char name[EDAC_DEVICE_NAME_LEN + 1];
85 
86 	/* Event counters for the this whole EDAC Device */
87 	struct edac_pci_counter counters;
88 
89 	/* edac sysfs device control for the 'name'
90 	 * device this structure controls
91 	 */
92 	struct kobject kobj;
93 };
94 
95 #define to_edac_pci_ctl_work(w) \
96 		container_of(w, struct edac_pci_ctl_info,work)
97 
98 /* write all or some bits in a byte-register*/
pci_write_bits8(struct pci_dev * pdev,int offset,u8 value,u8 mask)99 static inline void pci_write_bits8(struct pci_dev *pdev, int offset, u8 value,
100 				   u8 mask)
101 {
102 	if (mask != 0xff) {
103 		u8 buf;
104 
105 		pci_read_config_byte(pdev, offset, &buf);
106 		value &= mask;
107 		buf &= ~mask;
108 		value |= buf;
109 	}
110 
111 	pci_write_config_byte(pdev, offset, value);
112 }
113 
114 /* write all or some bits in a word-register*/
pci_write_bits16(struct pci_dev * pdev,int offset,u16 value,u16 mask)115 static inline void pci_write_bits16(struct pci_dev *pdev, int offset,
116 				    u16 value, u16 mask)
117 {
118 	if (mask != 0xffff) {
119 		u16 buf;
120 
121 		pci_read_config_word(pdev, offset, &buf);
122 		value &= mask;
123 		buf &= ~mask;
124 		value |= buf;
125 	}
126 
127 	pci_write_config_word(pdev, offset, value);
128 }
129 
130 /*
131  * pci_write_bits32
132  *
133  * edac local routine to do pci_write_config_dword, but adds
134  * a mask parameter. If mask is all ones, ignore the mask.
135  * Otherwise utilize the mask to isolate specified bits
136  *
137  * write all or some bits in a dword-register
138  */
pci_write_bits32(struct pci_dev * pdev,int offset,u32 value,u32 mask)139 static inline void pci_write_bits32(struct pci_dev *pdev, int offset,
140 				    u32 value, u32 mask)
141 {
142 	if (mask != 0xffffffff) {
143 		u32 buf;
144 
145 		pci_read_config_dword(pdev, offset, &buf);
146 		value &= mask;
147 		buf &= ~mask;
148 		value |= buf;
149 	}
150 
151 	pci_write_config_dword(pdev, offset, value);
152 }
153 
154 #endif				/* CONFIG_PCI */
155 
156 /*
157  * edac_pci APIs
158  */
159 
160 /**
161  * edac_pci_alloc_ctl_info:
162  *	The alloc() function for the 'edac_pci' control info
163  *	structure.
164  *
165  * @sz_pvt: size of the private info at struct &edac_pci_ctl_info
166  * @edac_pci_name: name of the PCI device
167  *
168  * The chip driver will allocate one of these for each
169  * edac_pci it is going to control/register with the EDAC CORE.
170  *
171  * Returns: a pointer to struct &edac_pci_ctl_info on success; %NULL otherwise.
172  */
173 extern struct edac_pci_ctl_info *edac_pci_alloc_ctl_info(unsigned int sz_pvt,
174 				const char *edac_pci_name);
175 
176 /**
177  * edac_pci_free_ctl_info():
178  *	Last action on the pci control structure.
179  *
180  * @pci: pointer to struct &edac_pci_ctl_info
181  *
182  * Calls the remove sysfs information, which will unregister
183  * this control struct's kobj. When that kobj's ref count
184  * goes to zero, its release function will be call and then
185  * kfree() the memory.
186  */
187 extern void edac_pci_free_ctl_info(struct edac_pci_ctl_info *pci);
188 
189 /**
190  * edac_pci_alloc_index: Allocate a unique PCI index number
191  *
192  * Returns:
193  *      allocated index number
194  *
195  */
196 extern int edac_pci_alloc_index(void);
197 
198 /**
199  * edac_pci_add_device(): Insert the 'edac_dev' structure into the
200  *	edac_pci global list and create sysfs entries associated with
201  *	edac_pci structure.
202  *
203  * @pci: pointer to the edac_device structure to be added to the list
204  * @edac_idx: A unique numeric identifier to be assigned to the
205  *	'edac_pci' structure.
206  *
207  * Returns:
208  *	0 on Success, or an error code on failure
209  */
210 extern int edac_pci_add_device(struct edac_pci_ctl_info *pci, int edac_idx);
211 
212 /**
213  * edac_pci_del_device()
214  *	Remove sysfs entries for specified edac_pci structure and
215  *	then remove edac_pci structure from global list
216  *
217  * @dev:
218  *	Pointer to 'struct device' representing edac_pci structure
219  *	to remove
220  *
221  * Returns:
222  *	Pointer to removed edac_pci structure,
223  *	or %NULL if device not found
224  */
225 extern struct edac_pci_ctl_info *edac_pci_del_device(struct device *dev);
226 
227 /**
228  * edac_pci_create_generic_ctl()
229  *	A generic constructor for a PCI parity polling device
230  *	Some systems have more than one domain of PCI busses.
231  *	For systems with one domain, then this API will
232  *	provide for a generic poller.
233  *
234  * @dev: pointer to struct &device;
235  * @mod_name: name of the PCI device
236  *
237  * This routine calls the edac_pci_alloc_ctl_info() for
238  * the generic device, with default values
239  *
240  * Returns: Pointer to struct &edac_pci_ctl_info on success, %NULL on
241  *	failure.
242  */
243 extern struct edac_pci_ctl_info *edac_pci_create_generic_ctl(
244 				struct device *dev,
245 				const char *mod_name);
246 
247 /**
248  * edac_pci_release_generic_ctl
249  *	The release function of a generic EDAC PCI polling device
250  *
251  * @pci: pointer to struct &edac_pci_ctl_info
252  */
253 extern void edac_pci_release_generic_ctl(struct edac_pci_ctl_info *pci);
254 
255 /**
256  * edac_pci_create_sysfs
257  *	Create the controls/attributes for the specified EDAC PCI device
258  *
259  * @pci: pointer to struct &edac_pci_ctl_info
260  */
261 extern int edac_pci_create_sysfs(struct edac_pci_ctl_info *pci);
262 
263 /**
264  * edac_pci_remove_sysfs()
265  *	remove the controls and attributes for this EDAC PCI device
266  *
267  * @pci: pointer to struct &edac_pci_ctl_info
268  */
269 extern void edac_pci_remove_sysfs(struct edac_pci_ctl_info *pci);
270 
271 #endif
272