xref: /openbmc/linux/drivers/gpio/gpio-pca953x.c (revision 060f35a317ef09101b128f399dce7ed13d019461)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  *  PCA953x 4/8/16/24/40 bit I/O ports
4  *
5  *  Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com>
6  *  Copyright (C) 2007 Marvell International Ltd.
7  *
8  *  Derived from drivers/i2c/chips/pca9539.c
9  */
10 
11 #include <linux/acpi.h>
12 #include <linux/bitmap.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/gpio/driver.h>
15 #include <linux/i2c.h>
16 #include <linux/init.h>
17 #include <linux/interrupt.h>
18 #include <linux/module.h>
19 #include <linux/of_platform.h>
20 #include <linux/platform_data/pca953x.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/seq_file.h>
24 #include <linux/slab.h>
25 
26 #include <asm/unaligned.h>
27 
28 #define PCA953X_INPUT		0x00
29 #define PCA953X_OUTPUT		0x01
30 #define PCA953X_INVERT		0x02
31 #define PCA953X_DIRECTION	0x03
32 
33 #define REG_ADDR_MASK		GENMASK(5, 0)
34 #define REG_ADDR_EXT		BIT(6)
35 #define REG_ADDR_AI		BIT(7)
36 
37 #define PCA957X_IN		0x00
38 #define PCA957X_INVRT		0x01
39 #define PCA957X_BKEN		0x02
40 #define PCA957X_PUPD		0x03
41 #define PCA957X_CFG		0x04
42 #define PCA957X_OUT		0x05
43 #define PCA957X_MSK		0x06
44 #define PCA957X_INTS		0x07
45 
46 #define PCAL953X_OUT_STRENGTH	0x20
47 #define PCAL953X_IN_LATCH	0x22
48 #define PCAL953X_PULL_EN	0x23
49 #define PCAL953X_PULL_SEL	0x24
50 #define PCAL953X_INT_MASK	0x25
51 #define PCAL953X_INT_STAT	0x26
52 #define PCAL953X_OUT_CONF	0x27
53 
54 #define PCAL6524_INT_EDGE	0x28
55 #define PCAL6524_INT_CLR	0x2a
56 #define PCAL6524_IN_STATUS	0x2b
57 #define PCAL6524_OUT_INDCONF	0x2c
58 #define PCAL6524_DEBOUNCE	0x2d
59 
60 #define PCA_GPIO_MASK		GENMASK(7, 0)
61 
62 #define PCAL_GPIO_MASK		GENMASK(4, 0)
63 #define PCAL_PINCTRL_MASK	GENMASK(6, 5)
64 
65 #define PCA_INT			BIT(8)
66 #define PCA_PCAL		BIT(9)
67 #define PCA_LATCH_INT		(PCA_PCAL | PCA_INT)
68 #define PCA953X_TYPE		BIT(12)
69 #define PCA957X_TYPE		BIT(13)
70 #define PCAL653X_TYPE		BIT(14)
71 #define PCA_TYPE_MASK		GENMASK(15, 12)
72 
73 #define PCA_CHIP_TYPE(x)	((x) & PCA_TYPE_MASK)
74 
75 static const struct i2c_device_id pca953x_id[] = {
76 	{ "pca6408", 8  | PCA953X_TYPE | PCA_INT, },
77 	{ "pca6416", 16 | PCA953X_TYPE | PCA_INT, },
78 	{ "pca9505", 40 | PCA953X_TYPE | PCA_INT, },
79 	{ "pca9506", 40 | PCA953X_TYPE | PCA_INT, },
80 	{ "pca9534", 8  | PCA953X_TYPE | PCA_INT, },
81 	{ "pca9535", 16 | PCA953X_TYPE | PCA_INT, },
82 	{ "pca9536", 4  | PCA953X_TYPE, },
83 	{ "pca9537", 4  | PCA953X_TYPE | PCA_INT, },
84 	{ "pca9538", 8  | PCA953X_TYPE | PCA_INT, },
85 	{ "pca9539", 16 | PCA953X_TYPE | PCA_INT, },
86 	{ "pca9554", 8  | PCA953X_TYPE | PCA_INT, },
87 	{ "pca9555", 16 | PCA953X_TYPE | PCA_INT, },
88 	{ "pca9556", 8  | PCA953X_TYPE, },
89 	{ "pca9557", 8  | PCA953X_TYPE, },
90 	{ "pca9574", 8  | PCA957X_TYPE | PCA_INT, },
91 	{ "pca9575", 16 | PCA957X_TYPE | PCA_INT, },
92 	{ "pca9698", 40 | PCA953X_TYPE, },
93 
94 	{ "pcal6408", 8 | PCA953X_TYPE | PCA_LATCH_INT, },
95 	{ "pcal6416", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
96 	{ "pcal6524", 24 | PCA953X_TYPE | PCA_LATCH_INT, },
97 	{ "pcal6534", 34 | PCAL653X_TYPE | PCA_LATCH_INT, },
98 	{ "pcal9535", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
99 	{ "pcal9554b", 8  | PCA953X_TYPE | PCA_LATCH_INT, },
100 	{ "pcal9555a", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
101 
102 	{ "max7310", 8  | PCA953X_TYPE, },
103 	{ "max7312", 16 | PCA953X_TYPE | PCA_INT, },
104 	{ "max7313", 16 | PCA953X_TYPE | PCA_INT, },
105 	{ "max7315", 8  | PCA953X_TYPE | PCA_INT, },
106 	{ "max7318", 16 | PCA953X_TYPE | PCA_INT, },
107 	{ "pca6107", 8  | PCA953X_TYPE | PCA_INT, },
108 	{ "tca6408", 8  | PCA953X_TYPE | PCA_INT, },
109 	{ "tca6416", 16 | PCA953X_TYPE | PCA_INT, },
110 	{ "tca6424", 24 | PCA953X_TYPE | PCA_INT, },
111 	{ "tca9538", 8  | PCA953X_TYPE | PCA_INT, },
112 	{ "tca9539", 16 | PCA953X_TYPE | PCA_INT, },
113 	{ "tca9554", 8  | PCA953X_TYPE | PCA_INT, },
114 	{ "xra1202", 8  | PCA953X_TYPE },
115 	{ }
116 };
117 MODULE_DEVICE_TABLE(i2c, pca953x_id);
118 
119 #ifdef CONFIG_GPIO_PCA953X_IRQ
120 
121 #include <linux/dmi.h>
122 
123 static const struct acpi_gpio_params pca953x_irq_gpios = { 0, 0, true };
124 
125 static const struct acpi_gpio_mapping pca953x_acpi_irq_gpios[] = {
126 	{ "irq-gpios", &pca953x_irq_gpios, 1, ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER },
127 	{ }
128 };
129 
pca953x_acpi_get_irq(struct device * dev)130 static int pca953x_acpi_get_irq(struct device *dev)
131 {
132 	int ret;
133 
134 	ret = devm_acpi_dev_add_driver_gpios(dev, pca953x_acpi_irq_gpios);
135 	if (ret)
136 		dev_warn(dev, "can't add GPIO ACPI mapping\n");
137 
138 	ret = acpi_dev_gpio_irq_get_by(ACPI_COMPANION(dev), "irq-gpios", 0);
139 	if (ret < 0)
140 		return ret;
141 
142 	dev_info(dev, "ACPI interrupt quirk (IRQ %d)\n", ret);
143 	return ret;
144 }
145 
146 static const struct dmi_system_id pca953x_dmi_acpi_irq_info[] = {
147 	{
148 		/*
149 		 * On Intel Galileo Gen 2 board the IRQ pin of one of
150 		 * the I²C GPIO expanders, which has GpioInt() resource,
151 		 * is provided as an absolute number instead of being
152 		 * relative. Since first controller (gpio-sch.c) and
153 		 * second (gpio-dwapb.c) are at the fixed bases, we may
154 		 * safely refer to the number in the global space to get
155 		 * an IRQ out of it.
156 		 */
157 		.matches = {
158 			DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"),
159 		},
160 	},
161 	{}
162 };
163 #endif
164 
165 static const struct acpi_device_id pca953x_acpi_ids[] = {
166 	{ "INT3491", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
167 	{ }
168 };
169 MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids);
170 
171 #define MAX_BANK 5
172 #define BANK_SZ 8
173 #define MAX_LINE	(MAX_BANK * BANK_SZ)
174 
175 #define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ)
176 
177 struct pca953x_reg_config {
178 	int direction;
179 	int output;
180 	int input;
181 	int invert;
182 };
183 
184 static const struct pca953x_reg_config pca953x_regs = {
185 	.direction = PCA953X_DIRECTION,
186 	.output = PCA953X_OUTPUT,
187 	.input = PCA953X_INPUT,
188 	.invert = PCA953X_INVERT,
189 };
190 
191 static const struct pca953x_reg_config pca957x_regs = {
192 	.direction = PCA957X_CFG,
193 	.output = PCA957X_OUT,
194 	.input = PCA957X_IN,
195 	.invert = PCA957X_INVRT,
196 };
197 
198 struct pca953x_chip {
199 	unsigned gpio_start;
200 	struct mutex i2c_lock;
201 	struct regmap *regmap;
202 
203 #ifdef CONFIG_GPIO_PCA953X_IRQ
204 	struct mutex irq_lock;
205 	DECLARE_BITMAP(irq_mask, MAX_LINE);
206 	DECLARE_BITMAP(irq_stat, MAX_LINE);
207 	DECLARE_BITMAP(irq_trig_raise, MAX_LINE);
208 	DECLARE_BITMAP(irq_trig_fall, MAX_LINE);
209 #endif
210 	atomic_t wakeup_path;
211 
212 	struct i2c_client *client;
213 	struct gpio_chip gpio_chip;
214 	unsigned long driver_data;
215 	struct regulator *regulator;
216 
217 	const struct pca953x_reg_config *regs;
218 
219 	u8 (*recalc_addr)(struct pca953x_chip *chip, int reg, int off);
220 	bool (*check_reg)(struct pca953x_chip *chip, unsigned int reg,
221 			  u32 checkbank);
222 };
223 
pca953x_bank_shift(struct pca953x_chip * chip)224 static int pca953x_bank_shift(struct pca953x_chip *chip)
225 {
226 	return fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
227 }
228 
229 #define PCA953x_BANK_INPUT	BIT(0)
230 #define PCA953x_BANK_OUTPUT	BIT(1)
231 #define PCA953x_BANK_POLARITY	BIT(2)
232 #define PCA953x_BANK_CONFIG	BIT(3)
233 
234 #define PCA957x_BANK_INPUT	BIT(0)
235 #define PCA957x_BANK_POLARITY	BIT(1)
236 #define PCA957x_BANK_BUSHOLD	BIT(2)
237 #define PCA957x_BANK_CONFIG	BIT(4)
238 #define PCA957x_BANK_OUTPUT	BIT(5)
239 
240 #define PCAL9xxx_BANK_IN_LATCH	BIT(8 + 2)
241 #define PCAL9xxx_BANK_PULL_EN	BIT(8 + 3)
242 #define PCAL9xxx_BANK_PULL_SEL	BIT(8 + 4)
243 #define PCAL9xxx_BANK_IRQ_MASK	BIT(8 + 5)
244 #define PCAL9xxx_BANK_IRQ_STAT	BIT(8 + 6)
245 
246 /*
247  * We care about the following registers:
248  * - Standard set, below 0x40, each port can be replicated up to 8 times
249  *   - PCA953x standard
250  *     Input port			0x00 + 0 * bank_size	R
251  *     Output port			0x00 + 1 * bank_size	RW
252  *     Polarity Inversion port		0x00 + 2 * bank_size	RW
253  *     Configuration port		0x00 + 3 * bank_size	RW
254  *   - PCA957x with mixed up registers
255  *     Input port			0x00 + 0 * bank_size	R
256  *     Polarity Inversion port		0x00 + 1 * bank_size	RW
257  *     Bus hold port			0x00 + 2 * bank_size	RW
258  *     Configuration port		0x00 + 4 * bank_size	RW
259  *     Output port			0x00 + 5 * bank_size	RW
260  *
261  * - Extended set, above 0x40, often chip specific.
262  *   - PCAL6524/PCAL9555A with custom PCAL IRQ handling:
263  *     Input latch register		0x40 + 2 * bank_size	RW
264  *     Pull-up/pull-down enable reg	0x40 + 3 * bank_size    RW
265  *     Pull-up/pull-down select reg	0x40 + 4 * bank_size    RW
266  *     Interrupt mask register		0x40 + 5 * bank_size	RW
267  *     Interrupt status register	0x40 + 6 * bank_size	R
268  *
269  * - Registers with bit 0x80 set, the AI bit
270  *   The bit is cleared and the registers fall into one of the
271  *   categories above.
272  */
273 
pca953x_check_register(struct pca953x_chip * chip,unsigned int reg,u32 checkbank)274 static bool pca953x_check_register(struct pca953x_chip *chip, unsigned int reg,
275 				   u32 checkbank)
276 {
277 	int bank_shift = pca953x_bank_shift(chip);
278 	int bank = (reg & REG_ADDR_MASK) >> bank_shift;
279 	int offset = reg & (BIT(bank_shift) - 1);
280 
281 	/* Special PCAL extended register check. */
282 	if (reg & REG_ADDR_EXT) {
283 		if (!(chip->driver_data & PCA_PCAL))
284 			return false;
285 		bank += 8;
286 	}
287 
288 	/* Register is not in the matching bank. */
289 	if (!(BIT(bank) & checkbank))
290 		return false;
291 
292 	/* Register is not within allowed range of bank. */
293 	if (offset >= NBANK(chip))
294 		return false;
295 
296 	return true;
297 }
298 
299 /*
300  * Unfortunately, whilst the PCAL6534 chip (and compatibles) broadly follow the
301  * same register layout as the PCAL6524, the spacing of the registers has been
302  * fundamentally altered by compacting them and thus does not obey the same
303  * rules, including being able to use bit shifting to determine bank. These
304  * chips hence need special handling here.
305  */
pcal6534_check_register(struct pca953x_chip * chip,unsigned int reg,u32 checkbank)306 static bool pcal6534_check_register(struct pca953x_chip *chip, unsigned int reg,
307 				    u32 checkbank)
308 {
309 	int bank_shift;
310 	int bank;
311 	int offset;
312 
313 	if (reg >= 0x54) {
314 		/*
315 		 * Handle lack of reserved registers after output port
316 		 * configuration register to form a bank.
317 		 */
318 		reg -= 0x54;
319 		bank_shift = 16;
320 	} else if (reg >= 0x30) {
321 		/*
322 		 * Reserved block between 14h and 2Fh does not align on
323 		 * expected bank boundaries like other devices.
324 		 */
325 		reg -= 0x30;
326 		bank_shift = 8;
327 	} else {
328 		bank_shift = 0;
329 	}
330 
331 	bank = bank_shift + reg / NBANK(chip);
332 	offset = reg % NBANK(chip);
333 
334 	/* Register is not in the matching bank. */
335 	if (!(BIT(bank) & checkbank))
336 		return false;
337 
338 	/* Register is not within allowed range of bank. */
339 	if (offset >= NBANK(chip))
340 		return false;
341 
342 	return true;
343 }
344 
pca953x_readable_register(struct device * dev,unsigned int reg)345 static bool pca953x_readable_register(struct device *dev, unsigned int reg)
346 {
347 	struct pca953x_chip *chip = dev_get_drvdata(dev);
348 	u32 bank;
349 
350 	if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) {
351 		bank = PCA957x_BANK_INPUT | PCA957x_BANK_OUTPUT |
352 		       PCA957x_BANK_POLARITY | PCA957x_BANK_CONFIG |
353 		       PCA957x_BANK_BUSHOLD;
354 	} else {
355 		bank = PCA953x_BANK_INPUT | PCA953x_BANK_OUTPUT |
356 		       PCA953x_BANK_POLARITY | PCA953x_BANK_CONFIG;
357 	}
358 
359 	if (chip->driver_data & PCA_PCAL) {
360 		bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN |
361 			PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK |
362 			PCAL9xxx_BANK_IRQ_STAT;
363 	}
364 
365 	return chip->check_reg(chip, reg, bank);
366 }
367 
pca953x_writeable_register(struct device * dev,unsigned int reg)368 static bool pca953x_writeable_register(struct device *dev, unsigned int reg)
369 {
370 	struct pca953x_chip *chip = dev_get_drvdata(dev);
371 	u32 bank;
372 
373 	if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) {
374 		bank = PCA957x_BANK_OUTPUT | PCA957x_BANK_POLARITY |
375 			PCA957x_BANK_CONFIG | PCA957x_BANK_BUSHOLD;
376 	} else {
377 		bank = PCA953x_BANK_OUTPUT | PCA953x_BANK_POLARITY |
378 			PCA953x_BANK_CONFIG;
379 	}
380 
381 	if (chip->driver_data & PCA_PCAL)
382 		bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN |
383 			PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK;
384 
385 	return chip->check_reg(chip, reg, bank);
386 }
387 
pca953x_volatile_register(struct device * dev,unsigned int reg)388 static bool pca953x_volatile_register(struct device *dev, unsigned int reg)
389 {
390 	struct pca953x_chip *chip = dev_get_drvdata(dev);
391 	u32 bank;
392 
393 	if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE)
394 		bank = PCA957x_BANK_INPUT;
395 	else
396 		bank = PCA953x_BANK_INPUT;
397 
398 	if (chip->driver_data & PCA_PCAL)
399 		bank |= PCAL9xxx_BANK_IRQ_STAT;
400 
401 	return chip->check_reg(chip, reg, bank);
402 }
403 
404 static const struct regmap_config pca953x_i2c_regmap = {
405 	.reg_bits = 8,
406 	.val_bits = 8,
407 
408 	.use_single_read = true,
409 	.use_single_write = true,
410 
411 	.readable_reg = pca953x_readable_register,
412 	.writeable_reg = pca953x_writeable_register,
413 	.volatile_reg = pca953x_volatile_register,
414 
415 	.disable_locking = true,
416 	.cache_type = REGCACHE_RBTREE,
417 	.max_register = 0x7f,
418 };
419 
420 static const struct regmap_config pca953x_ai_i2c_regmap = {
421 	.reg_bits = 8,
422 	.val_bits = 8,
423 
424 	.read_flag_mask = REG_ADDR_AI,
425 	.write_flag_mask = REG_ADDR_AI,
426 
427 	.readable_reg = pca953x_readable_register,
428 	.writeable_reg = pca953x_writeable_register,
429 	.volatile_reg = pca953x_volatile_register,
430 
431 	.disable_locking = true,
432 	.cache_type = REGCACHE_RBTREE,
433 	.max_register = 0x7f,
434 };
435 
pca953x_recalc_addr(struct pca953x_chip * chip,int reg,int off)436 static u8 pca953x_recalc_addr(struct pca953x_chip *chip, int reg, int off)
437 {
438 	int bank_shift = pca953x_bank_shift(chip);
439 	int addr = (reg & PCAL_GPIO_MASK) << bank_shift;
440 	int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1;
441 	u8 regaddr = pinctrl | addr | (off / BANK_SZ);
442 
443 	return regaddr;
444 }
445 
446 /*
447  * The PCAL6534 and compatible chips have altered bank alignment that doesn't
448  * fit within the bit shifting scheme used for other devices.
449  */
pcal6534_recalc_addr(struct pca953x_chip * chip,int reg,int off)450 static u8 pcal6534_recalc_addr(struct pca953x_chip *chip, int reg, int off)
451 {
452 	int addr;
453 	int pinctrl;
454 
455 	addr = (reg & PCAL_GPIO_MASK) * NBANK(chip);
456 
457 	switch (reg) {
458 	case PCAL953X_OUT_STRENGTH:
459 	case PCAL953X_IN_LATCH:
460 	case PCAL953X_PULL_EN:
461 	case PCAL953X_PULL_SEL:
462 	case PCAL953X_INT_MASK:
463 	case PCAL953X_INT_STAT:
464 		pinctrl = ((reg & PCAL_PINCTRL_MASK) >> 1) + 0x20;
465 		break;
466 	case PCAL6524_INT_EDGE:
467 	case PCAL6524_INT_CLR:
468 	case PCAL6524_IN_STATUS:
469 	case PCAL6524_OUT_INDCONF:
470 	case PCAL6524_DEBOUNCE:
471 		pinctrl = ((reg & PCAL_PINCTRL_MASK) >> 1) + 0x1c;
472 		break;
473 	default:
474 		pinctrl = 0;
475 		break;
476 	}
477 
478 	return pinctrl + addr + (off / BANK_SZ);
479 }
480 
pca953x_write_regs(struct pca953x_chip * chip,int reg,unsigned long * val)481 static int pca953x_write_regs(struct pca953x_chip *chip, int reg, unsigned long *val)
482 {
483 	u8 regaddr = chip->recalc_addr(chip, reg, 0);
484 	u8 value[MAX_BANK];
485 	int i, ret;
486 
487 	for (i = 0; i < NBANK(chip); i++)
488 		value[i] = bitmap_get_value8(val, i * BANK_SZ);
489 
490 	ret = regmap_bulk_write(chip->regmap, regaddr, value, NBANK(chip));
491 	if (ret < 0) {
492 		dev_err(&chip->client->dev, "failed writing register\n");
493 		return ret;
494 	}
495 
496 	return 0;
497 }
498 
pca953x_read_regs(struct pca953x_chip * chip,int reg,unsigned long * val)499 static int pca953x_read_regs(struct pca953x_chip *chip, int reg, unsigned long *val)
500 {
501 	u8 regaddr = chip->recalc_addr(chip, reg, 0);
502 	u8 value[MAX_BANK];
503 	int i, ret;
504 
505 	ret = regmap_bulk_read(chip->regmap, regaddr, value, NBANK(chip));
506 	if (ret < 0) {
507 		dev_err(&chip->client->dev, "failed reading register\n");
508 		return ret;
509 	}
510 
511 	for (i = 0; i < NBANK(chip); i++)
512 		bitmap_set_value8(val, value[i], i * BANK_SZ);
513 
514 	return 0;
515 }
516 
pca953x_gpio_direction_input(struct gpio_chip * gc,unsigned off)517 static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
518 {
519 	struct pca953x_chip *chip = gpiochip_get_data(gc);
520 	u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off);
521 	u8 bit = BIT(off % BANK_SZ);
522 	int ret;
523 
524 	mutex_lock(&chip->i2c_lock);
525 	ret = regmap_write_bits(chip->regmap, dirreg, bit, bit);
526 	mutex_unlock(&chip->i2c_lock);
527 	return ret;
528 }
529 
pca953x_gpio_direction_output(struct gpio_chip * gc,unsigned off,int val)530 static int pca953x_gpio_direction_output(struct gpio_chip *gc,
531 		unsigned off, int val)
532 {
533 	struct pca953x_chip *chip = gpiochip_get_data(gc);
534 	u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off);
535 	u8 outreg = chip->recalc_addr(chip, chip->regs->output, off);
536 	u8 bit = BIT(off % BANK_SZ);
537 	int ret;
538 
539 	mutex_lock(&chip->i2c_lock);
540 	/* set output level */
541 	ret = regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);
542 	if (ret)
543 		goto exit;
544 
545 	/* then direction */
546 	ret = regmap_write_bits(chip->regmap, dirreg, bit, 0);
547 exit:
548 	mutex_unlock(&chip->i2c_lock);
549 	return ret;
550 }
551 
pca953x_gpio_get_value(struct gpio_chip * gc,unsigned off)552 static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
553 {
554 	struct pca953x_chip *chip = gpiochip_get_data(gc);
555 	u8 inreg = chip->recalc_addr(chip, chip->regs->input, off);
556 	u8 bit = BIT(off % BANK_SZ);
557 	u32 reg_val;
558 	int ret;
559 
560 	mutex_lock(&chip->i2c_lock);
561 	ret = regmap_read(chip->regmap, inreg, &reg_val);
562 	mutex_unlock(&chip->i2c_lock);
563 	if (ret < 0)
564 		return ret;
565 
566 	return !!(reg_val & bit);
567 }
568 
pca953x_gpio_set_value(struct gpio_chip * gc,unsigned off,int val)569 static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
570 {
571 	struct pca953x_chip *chip = gpiochip_get_data(gc);
572 	u8 outreg = chip->recalc_addr(chip, chip->regs->output, off);
573 	u8 bit = BIT(off % BANK_SZ);
574 
575 	mutex_lock(&chip->i2c_lock);
576 	regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);
577 	mutex_unlock(&chip->i2c_lock);
578 }
579 
pca953x_gpio_get_direction(struct gpio_chip * gc,unsigned off)580 static int pca953x_gpio_get_direction(struct gpio_chip *gc, unsigned off)
581 {
582 	struct pca953x_chip *chip = gpiochip_get_data(gc);
583 	u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off);
584 	u8 bit = BIT(off % BANK_SZ);
585 	u32 reg_val;
586 	int ret;
587 
588 	mutex_lock(&chip->i2c_lock);
589 	ret = regmap_read(chip->regmap, dirreg, &reg_val);
590 	mutex_unlock(&chip->i2c_lock);
591 	if (ret < 0)
592 		return ret;
593 
594 	if (reg_val & bit)
595 		return GPIO_LINE_DIRECTION_IN;
596 
597 	return GPIO_LINE_DIRECTION_OUT;
598 }
599 
pca953x_gpio_get_multiple(struct gpio_chip * gc,unsigned long * mask,unsigned long * bits)600 static int pca953x_gpio_get_multiple(struct gpio_chip *gc,
601 				     unsigned long *mask, unsigned long *bits)
602 {
603 	struct pca953x_chip *chip = gpiochip_get_data(gc);
604 	DECLARE_BITMAP(reg_val, MAX_LINE);
605 	int ret;
606 
607 	mutex_lock(&chip->i2c_lock);
608 	ret = pca953x_read_regs(chip, chip->regs->input, reg_val);
609 	mutex_unlock(&chip->i2c_lock);
610 	if (ret)
611 		return ret;
612 
613 	bitmap_replace(bits, bits, reg_val, mask, gc->ngpio);
614 	return 0;
615 }
616 
pca953x_gpio_set_multiple(struct gpio_chip * gc,unsigned long * mask,unsigned long * bits)617 static void pca953x_gpio_set_multiple(struct gpio_chip *gc,
618 				      unsigned long *mask, unsigned long *bits)
619 {
620 	struct pca953x_chip *chip = gpiochip_get_data(gc);
621 	DECLARE_BITMAP(reg_val, MAX_LINE);
622 	int ret;
623 
624 	mutex_lock(&chip->i2c_lock);
625 	ret = pca953x_read_regs(chip, chip->regs->output, reg_val);
626 	if (ret)
627 		goto exit;
628 
629 	bitmap_replace(reg_val, reg_val, bits, mask, gc->ngpio);
630 
631 	pca953x_write_regs(chip, chip->regs->output, reg_val);
632 exit:
633 	mutex_unlock(&chip->i2c_lock);
634 }
635 
pca953x_gpio_set_pull_up_down(struct pca953x_chip * chip,unsigned int offset,unsigned long config)636 static int pca953x_gpio_set_pull_up_down(struct pca953x_chip *chip,
637 					 unsigned int offset,
638 					 unsigned long config)
639 {
640 	enum pin_config_param param = pinconf_to_config_param(config);
641 
642 	u8 pull_en_reg = chip->recalc_addr(chip, PCAL953X_PULL_EN, offset);
643 	u8 pull_sel_reg = chip->recalc_addr(chip, PCAL953X_PULL_SEL, offset);
644 	u8 bit = BIT(offset % BANK_SZ);
645 	int ret;
646 
647 	/*
648 	 * pull-up/pull-down configuration requires PCAL extended
649 	 * registers
650 	 */
651 	if (!(chip->driver_data & PCA_PCAL))
652 		return -ENOTSUPP;
653 
654 	mutex_lock(&chip->i2c_lock);
655 
656 	/* Configure pull-up/pull-down */
657 	if (param == PIN_CONFIG_BIAS_PULL_UP)
658 		ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, bit);
659 	else if (param == PIN_CONFIG_BIAS_PULL_DOWN)
660 		ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, 0);
661 	else
662 		ret = 0;
663 	if (ret)
664 		goto exit;
665 
666 	/* Disable/Enable pull-up/pull-down */
667 	if (param == PIN_CONFIG_BIAS_DISABLE)
668 		ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, 0);
669 	else
670 		ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, bit);
671 
672 exit:
673 	mutex_unlock(&chip->i2c_lock);
674 	return ret;
675 }
676 
pca953x_gpio_set_config(struct gpio_chip * gc,unsigned int offset,unsigned long config)677 static int pca953x_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
678 				   unsigned long config)
679 {
680 	struct pca953x_chip *chip = gpiochip_get_data(gc);
681 
682 	switch (pinconf_to_config_param(config)) {
683 	case PIN_CONFIG_BIAS_PULL_UP:
684 	case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
685 	case PIN_CONFIG_BIAS_PULL_DOWN:
686 	case PIN_CONFIG_BIAS_DISABLE:
687 		return pca953x_gpio_set_pull_up_down(chip, offset, config);
688 	default:
689 		return -ENOTSUPP;
690 	}
691 }
692 
pca953x_setup_gpio(struct pca953x_chip * chip,int gpios)693 static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios)
694 {
695 	struct gpio_chip *gc;
696 
697 	gc = &chip->gpio_chip;
698 
699 	gc->direction_input  = pca953x_gpio_direction_input;
700 	gc->direction_output = pca953x_gpio_direction_output;
701 	gc->get = pca953x_gpio_get_value;
702 	gc->set = pca953x_gpio_set_value;
703 	gc->get_direction = pca953x_gpio_get_direction;
704 	gc->get_multiple = pca953x_gpio_get_multiple;
705 	gc->set_multiple = pca953x_gpio_set_multiple;
706 	gc->set_config = pca953x_gpio_set_config;
707 	gc->can_sleep = true;
708 
709 	gc->base = chip->gpio_start;
710 	gc->ngpio = gpios;
711 	gc->label = dev_name(&chip->client->dev);
712 	gc->parent = &chip->client->dev;
713 	gc->owner = THIS_MODULE;
714 }
715 
716 #ifdef CONFIG_GPIO_PCA953X_IRQ
pca953x_irq_mask(struct irq_data * d)717 static void pca953x_irq_mask(struct irq_data *d)
718 {
719 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
720 	struct pca953x_chip *chip = gpiochip_get_data(gc);
721 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
722 
723 	clear_bit(hwirq, chip->irq_mask);
724 	gpiochip_disable_irq(gc, hwirq);
725 }
726 
pca953x_irq_unmask(struct irq_data * d)727 static void pca953x_irq_unmask(struct irq_data *d)
728 {
729 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
730 	struct pca953x_chip *chip = gpiochip_get_data(gc);
731 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
732 
733 	gpiochip_enable_irq(gc, hwirq);
734 	set_bit(hwirq, chip->irq_mask);
735 }
736 
pca953x_irq_set_wake(struct irq_data * d,unsigned int on)737 static int pca953x_irq_set_wake(struct irq_data *d, unsigned int on)
738 {
739 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
740 	struct pca953x_chip *chip = gpiochip_get_data(gc);
741 
742 	if (on)
743 		atomic_inc(&chip->wakeup_path);
744 	else
745 		atomic_dec(&chip->wakeup_path);
746 
747 	return irq_set_irq_wake(chip->client->irq, on);
748 }
749 
pca953x_irq_bus_lock(struct irq_data * d)750 static void pca953x_irq_bus_lock(struct irq_data *d)
751 {
752 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
753 	struct pca953x_chip *chip = gpiochip_get_data(gc);
754 
755 	mutex_lock(&chip->irq_lock);
756 }
757 
pca953x_irq_bus_sync_unlock(struct irq_data * d)758 static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
759 {
760 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
761 	struct pca953x_chip *chip = gpiochip_get_data(gc);
762 	DECLARE_BITMAP(irq_mask, MAX_LINE);
763 	DECLARE_BITMAP(reg_direction, MAX_LINE);
764 	int level;
765 
766 	if (chip->driver_data & PCA_PCAL) {
767 		guard(mutex)(&chip->i2c_lock);
768 
769 		/* Enable latch on interrupt-enabled inputs */
770 		pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask);
771 
772 		bitmap_complement(irq_mask, chip->irq_mask, gc->ngpio);
773 
774 		/* Unmask enabled interrupts */
775 		pca953x_write_regs(chip, PCAL953X_INT_MASK, irq_mask);
776 	}
777 
778 	/* Switch direction to input if needed */
779 	pca953x_read_regs(chip, chip->regs->direction, reg_direction);
780 
781 	bitmap_or(irq_mask, chip->irq_trig_fall, chip->irq_trig_raise, gc->ngpio);
782 	bitmap_complement(reg_direction, reg_direction, gc->ngpio);
783 	bitmap_and(irq_mask, irq_mask, reg_direction, gc->ngpio);
784 
785 	/* Look for any newly setup interrupt */
786 	for_each_set_bit(level, irq_mask, gc->ngpio)
787 		pca953x_gpio_direction_input(&chip->gpio_chip, level);
788 
789 	mutex_unlock(&chip->irq_lock);
790 }
791 
pca953x_irq_set_type(struct irq_data * d,unsigned int type)792 static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)
793 {
794 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
795 	struct pca953x_chip *chip = gpiochip_get_data(gc);
796 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
797 
798 	if (!(type & IRQ_TYPE_EDGE_BOTH)) {
799 		dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
800 			d->irq, type);
801 		return -EINVAL;
802 	}
803 
804 	assign_bit(hwirq, chip->irq_trig_fall, type & IRQ_TYPE_EDGE_FALLING);
805 	assign_bit(hwirq, chip->irq_trig_raise, type & IRQ_TYPE_EDGE_RISING);
806 
807 	return 0;
808 }
809 
pca953x_irq_shutdown(struct irq_data * d)810 static void pca953x_irq_shutdown(struct irq_data *d)
811 {
812 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
813 	struct pca953x_chip *chip = gpiochip_get_data(gc);
814 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
815 
816 	clear_bit(hwirq, chip->irq_trig_raise);
817 	clear_bit(hwirq, chip->irq_trig_fall);
818 }
819 
pca953x_irq_print_chip(struct irq_data * data,struct seq_file * p)820 static void pca953x_irq_print_chip(struct irq_data *data, struct seq_file *p)
821 {
822 	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
823 
824 	seq_printf(p, dev_name(gc->parent));
825 }
826 
827 static const struct irq_chip pca953x_irq_chip = {
828 	.irq_mask		= pca953x_irq_mask,
829 	.irq_unmask		= pca953x_irq_unmask,
830 	.irq_set_wake		= pca953x_irq_set_wake,
831 	.irq_bus_lock		= pca953x_irq_bus_lock,
832 	.irq_bus_sync_unlock	= pca953x_irq_bus_sync_unlock,
833 	.irq_set_type		= pca953x_irq_set_type,
834 	.irq_shutdown		= pca953x_irq_shutdown,
835 	.irq_print_chip		= pca953x_irq_print_chip,
836 	.flags			= IRQCHIP_IMMUTABLE,
837 	GPIOCHIP_IRQ_RESOURCE_HELPERS,
838 };
839 
pca953x_irq_pending(struct pca953x_chip * chip,unsigned long * pending)840 static bool pca953x_irq_pending(struct pca953x_chip *chip, unsigned long *pending)
841 {
842 	struct gpio_chip *gc = &chip->gpio_chip;
843 	DECLARE_BITMAP(reg_direction, MAX_LINE);
844 	DECLARE_BITMAP(old_stat, MAX_LINE);
845 	DECLARE_BITMAP(cur_stat, MAX_LINE);
846 	DECLARE_BITMAP(new_stat, MAX_LINE);
847 	DECLARE_BITMAP(trigger, MAX_LINE);
848 	int ret;
849 
850 	if (chip->driver_data & PCA_PCAL) {
851 		/* Read the current interrupt status from the device */
852 		ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, trigger);
853 		if (ret)
854 			return false;
855 
856 		/* Check latched inputs and clear interrupt status */
857 		ret = pca953x_read_regs(chip, chip->regs->input, cur_stat);
858 		if (ret)
859 			return false;
860 
861 		/* Apply filter for rising/falling edge selection */
862 		bitmap_replace(new_stat, chip->irq_trig_fall, chip->irq_trig_raise, cur_stat, gc->ngpio);
863 
864 		bitmap_and(pending, new_stat, trigger, gc->ngpio);
865 
866 		return !bitmap_empty(pending, gc->ngpio);
867 	}
868 
869 	ret = pca953x_read_regs(chip, chip->regs->input, cur_stat);
870 	if (ret)
871 		return false;
872 
873 	/* Remove output pins from the equation */
874 	pca953x_read_regs(chip, chip->regs->direction, reg_direction);
875 
876 	bitmap_copy(old_stat, chip->irq_stat, gc->ngpio);
877 
878 	bitmap_and(new_stat, cur_stat, reg_direction, gc->ngpio);
879 	bitmap_xor(cur_stat, new_stat, old_stat, gc->ngpio);
880 	bitmap_and(trigger, cur_stat, chip->irq_mask, gc->ngpio);
881 
882 	bitmap_copy(chip->irq_stat, new_stat, gc->ngpio);
883 
884 	if (bitmap_empty(trigger, gc->ngpio))
885 		return false;
886 
887 	bitmap_and(cur_stat, chip->irq_trig_fall, old_stat, gc->ngpio);
888 	bitmap_and(old_stat, chip->irq_trig_raise, new_stat, gc->ngpio);
889 	bitmap_or(new_stat, old_stat, cur_stat, gc->ngpio);
890 	bitmap_and(pending, new_stat, trigger, gc->ngpio);
891 
892 	return !bitmap_empty(pending, gc->ngpio);
893 }
894 
pca953x_irq_handler(int irq,void * devid)895 static irqreturn_t pca953x_irq_handler(int irq, void *devid)
896 {
897 	struct pca953x_chip *chip = devid;
898 	struct gpio_chip *gc = &chip->gpio_chip;
899 	DECLARE_BITMAP(pending, MAX_LINE);
900 	int level;
901 	bool ret;
902 
903 	bitmap_zero(pending, MAX_LINE);
904 
905 	mutex_lock(&chip->i2c_lock);
906 	ret = pca953x_irq_pending(chip, pending);
907 	mutex_unlock(&chip->i2c_lock);
908 
909 	if (ret) {
910 		ret = 0;
911 
912 		for_each_set_bit(level, pending, gc->ngpio) {
913 			int nested_irq = irq_find_mapping(gc->irq.domain, level);
914 
915 			if (unlikely(nested_irq <= 0)) {
916 				dev_warn_ratelimited(gc->parent, "unmapped interrupt %d\n", level);
917 				continue;
918 			}
919 
920 			handle_nested_irq(nested_irq);
921 			ret = 1;
922 		}
923 	}
924 
925 	return IRQ_RETVAL(ret);
926 }
927 
pca953x_irq_setup(struct pca953x_chip * chip,int irq_base)928 static int pca953x_irq_setup(struct pca953x_chip *chip, int irq_base)
929 {
930 	struct i2c_client *client = chip->client;
931 	DECLARE_BITMAP(reg_direction, MAX_LINE);
932 	DECLARE_BITMAP(irq_stat, MAX_LINE);
933 	struct gpio_irq_chip *girq;
934 	int ret;
935 
936 	if (dmi_first_match(pca953x_dmi_acpi_irq_info)) {
937 		ret = pca953x_acpi_get_irq(&client->dev);
938 		if (ret > 0)
939 			client->irq = ret;
940 	}
941 
942 	if (!client->irq)
943 		return 0;
944 
945 	if (irq_base == -1)
946 		return 0;
947 
948 	if (!(chip->driver_data & PCA_INT))
949 		return 0;
950 
951 	ret = pca953x_read_regs(chip, chip->regs->input, irq_stat);
952 	if (ret)
953 		return ret;
954 
955 	/*
956 	 * There is no way to know which GPIO line generated the
957 	 * interrupt.  We have to rely on the previous read for
958 	 * this purpose.
959 	 */
960 	pca953x_read_regs(chip, chip->regs->direction, reg_direction);
961 	bitmap_and(chip->irq_stat, irq_stat, reg_direction, chip->gpio_chip.ngpio);
962 	mutex_init(&chip->irq_lock);
963 
964 	girq = &chip->gpio_chip.irq;
965 	gpio_irq_chip_set_chip(girq, &pca953x_irq_chip);
966 	/* This will let us handle the parent IRQ in the driver */
967 	girq->parent_handler = NULL;
968 	girq->num_parents = 0;
969 	girq->parents = NULL;
970 	girq->default_type = IRQ_TYPE_NONE;
971 	girq->handler = handle_simple_irq;
972 	girq->threaded = true;
973 	girq->first = irq_base; /* FIXME: get rid of this */
974 
975 	ret = devm_request_threaded_irq(&client->dev, client->irq,
976 					NULL, pca953x_irq_handler,
977 					IRQF_ONESHOT | IRQF_SHARED,
978 					dev_name(&client->dev), chip);
979 	if (ret) {
980 		dev_err(&client->dev, "failed to request irq %d\n",
981 			client->irq);
982 		return ret;
983 	}
984 
985 	return 0;
986 }
987 
988 #else /* CONFIG_GPIO_PCA953X_IRQ */
pca953x_irq_setup(struct pca953x_chip * chip,int irq_base)989 static int pca953x_irq_setup(struct pca953x_chip *chip,
990 			     int irq_base)
991 {
992 	struct i2c_client *client = chip->client;
993 
994 	if (client->irq && irq_base != -1 && (chip->driver_data & PCA_INT))
995 		dev_warn(&client->dev, "interrupt support not compiled in\n");
996 
997 	return 0;
998 }
999 #endif
1000 
device_pca95xx_init(struct pca953x_chip * chip)1001 static int device_pca95xx_init(struct pca953x_chip *chip)
1002 {
1003 	DECLARE_BITMAP(val, MAX_LINE);
1004 	u8 regaddr;
1005 	int ret;
1006 
1007 	regaddr = chip->recalc_addr(chip, chip->regs->output, 0);
1008 	ret = regcache_sync_region(chip->regmap, regaddr,
1009 				   regaddr + NBANK(chip) - 1);
1010 	if (ret)
1011 		goto out;
1012 
1013 	regaddr = chip->recalc_addr(chip, chip->regs->direction, 0);
1014 	ret = regcache_sync_region(chip->regmap, regaddr,
1015 				   regaddr + NBANK(chip) - 1);
1016 	if (ret)
1017 		goto out;
1018 
1019 	/* clear polarity inversion */
1020 	bitmap_zero(val, MAX_LINE);
1021 
1022 	ret = pca953x_write_regs(chip, chip->regs->invert, val);
1023 out:
1024 	return ret;
1025 }
1026 
device_pca957x_init(struct pca953x_chip * chip)1027 static int device_pca957x_init(struct pca953x_chip *chip)
1028 {
1029 	DECLARE_BITMAP(val, MAX_LINE);
1030 	unsigned int i;
1031 	int ret;
1032 
1033 	ret = device_pca95xx_init(chip);
1034 	if (ret)
1035 		goto out;
1036 
1037 	/* To enable register 6, 7 to control pull up and pull down */
1038 	for (i = 0; i < NBANK(chip); i++)
1039 		bitmap_set_value8(val, 0x02, i * BANK_SZ);
1040 
1041 	ret = pca953x_write_regs(chip, PCA957X_BKEN, val);
1042 	if (ret)
1043 		goto out;
1044 
1045 	return 0;
1046 out:
1047 	return ret;
1048 }
1049 
pca953x_disable_regulator(void * reg)1050 static void pca953x_disable_regulator(void *reg)
1051 {
1052 	regulator_disable(reg);
1053 }
1054 
pca953x_get_and_enable_regulator(struct pca953x_chip * chip)1055 static int pca953x_get_and_enable_regulator(struct pca953x_chip *chip)
1056 {
1057 	struct device *dev = &chip->client->dev;
1058 	struct regulator *reg = chip->regulator;
1059 	int ret;
1060 
1061 	reg = devm_regulator_get(dev, "vcc");
1062 	if (IS_ERR(reg))
1063 		return dev_err_probe(dev, PTR_ERR(reg), "reg get err\n");
1064 
1065 	ret = regulator_enable(reg);
1066 	if (ret)
1067 	        return dev_err_probe(dev, ret, "reg en err\n");
1068 
1069 	ret = devm_add_action_or_reset(dev, pca953x_disable_regulator, reg);
1070 	if (ret)
1071 		return ret;
1072 
1073 	chip->regulator = reg;
1074 	return 0;
1075 }
1076 
pca953x_probe(struct i2c_client * client)1077 static int pca953x_probe(struct i2c_client *client)
1078 {
1079 	struct device *dev = &client->dev;
1080 	struct pca953x_platform_data *pdata;
1081 	struct pca953x_chip *chip;
1082 	int irq_base;
1083 	int ret;
1084 	const struct regmap_config *regmap_config;
1085 
1086 	chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
1087 	if (chip == NULL)
1088 		return -ENOMEM;
1089 
1090 	pdata = dev_get_platdata(&client->dev);
1091 	if (pdata) {
1092 		irq_base = pdata->irq_base;
1093 		chip->gpio_start = pdata->gpio_base;
1094 	} else {
1095 		struct gpio_desc *reset_gpio;
1096 
1097 		chip->gpio_start = -1;
1098 		irq_base = 0;
1099 
1100 		/*
1101 		 * See if we need to de-assert a reset pin.
1102 		 *
1103 		 * There is no known ACPI-enabled platforms that are
1104 		 * using "reset" GPIO. Otherwise any of those platform
1105 		 * must use _DSD method with corresponding property.
1106 		 */
1107 		reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
1108 						     GPIOD_OUT_LOW);
1109 		if (IS_ERR(reset_gpio))
1110 			return dev_err_probe(dev, PTR_ERR(reset_gpio),
1111 					     "Failed to get reset gpio\n");
1112 	}
1113 
1114 	chip->client = client;
1115 	chip->driver_data = (uintptr_t)i2c_get_match_data(client);
1116 	if (!chip->driver_data)
1117 		return -ENODEV;
1118 
1119 	ret = pca953x_get_and_enable_regulator(chip);
1120 	if (ret)
1121 		return ret;
1122 
1123 	i2c_set_clientdata(client, chip);
1124 
1125 	pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK);
1126 
1127 	if (NBANK(chip) > 2 || PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) {
1128 		dev_info(&client->dev, "using AI\n");
1129 		regmap_config = &pca953x_ai_i2c_regmap;
1130 	} else {
1131 		dev_info(&client->dev, "using no AI\n");
1132 		regmap_config = &pca953x_i2c_regmap;
1133 	}
1134 
1135 	if (PCA_CHIP_TYPE(chip->driver_data) == PCAL653X_TYPE) {
1136 		chip->recalc_addr = pcal6534_recalc_addr;
1137 		chip->check_reg = pcal6534_check_register;
1138 	} else {
1139 		chip->recalc_addr = pca953x_recalc_addr;
1140 		chip->check_reg = pca953x_check_register;
1141 	}
1142 
1143 	chip->regmap = devm_regmap_init_i2c(client, regmap_config);
1144 	if (IS_ERR(chip->regmap))
1145 		return PTR_ERR(chip->regmap);
1146 
1147 	regcache_mark_dirty(chip->regmap);
1148 
1149 	mutex_init(&chip->i2c_lock);
1150 	/*
1151 	 * In case we have an i2c-mux controlled by a GPIO provided by an
1152 	 * expander using the same driver higher on the device tree, read the
1153 	 * i2c adapter nesting depth and use the retrieved value as lockdep
1154 	 * subclass for chip->i2c_lock.
1155 	 *
1156 	 * REVISIT: This solution is not complete. It protects us from lockdep
1157 	 * false positives when the expander controlling the i2c-mux is on
1158 	 * a different level on the device tree, but not when it's on the same
1159 	 * level on a different branch (in which case the subclass number
1160 	 * would be the same).
1161 	 *
1162 	 * TODO: Once a correct solution is developed, a similar fix should be
1163 	 * applied to all other i2c-controlled GPIO expanders (and potentially
1164 	 * regmap-i2c).
1165 	 */
1166 	lockdep_set_subclass(&chip->i2c_lock,
1167 			     i2c_adapter_depth(client->adapter));
1168 
1169 	/* initialize cached registers from their original values.
1170 	 * we can't share this chip with another i2c master.
1171 	 */
1172 	if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) {
1173 		chip->regs = &pca957x_regs;
1174 		ret = device_pca957x_init(chip);
1175 	} else {
1176 		chip->regs = &pca953x_regs;
1177 		ret = device_pca95xx_init(chip);
1178 	}
1179 	if (ret)
1180 		return ret;
1181 
1182 	ret = pca953x_irq_setup(chip, irq_base);
1183 	if (ret)
1184 		return ret;
1185 
1186 	return devm_gpiochip_add_data(dev, &chip->gpio_chip, chip);
1187 }
1188 
1189 #ifdef CONFIG_PM_SLEEP
pca953x_regcache_sync(struct device * dev)1190 static int pca953x_regcache_sync(struct device *dev)
1191 {
1192 	struct pca953x_chip *chip = dev_get_drvdata(dev);
1193 	int ret;
1194 	u8 regaddr;
1195 
1196 	/*
1197 	 * The ordering between direction and output is important,
1198 	 * sync these registers first and only then sync the rest.
1199 	 */
1200 	regaddr = chip->recalc_addr(chip, chip->regs->direction, 0);
1201 	ret = regcache_sync_region(chip->regmap, regaddr, regaddr + NBANK(chip) - 1);
1202 	if (ret) {
1203 		dev_err(dev, "Failed to sync GPIO dir registers: %d\n", ret);
1204 		return ret;
1205 	}
1206 
1207 	regaddr = chip->recalc_addr(chip, chip->regs->output, 0);
1208 	ret = regcache_sync_region(chip->regmap, regaddr, regaddr + NBANK(chip) - 1);
1209 	if (ret) {
1210 		dev_err(dev, "Failed to sync GPIO out registers: %d\n", ret);
1211 		return ret;
1212 	}
1213 
1214 #ifdef CONFIG_GPIO_PCA953X_IRQ
1215 	if (chip->driver_data & PCA_PCAL) {
1216 		regaddr = chip->recalc_addr(chip, PCAL953X_IN_LATCH, 0);
1217 		ret = regcache_sync_region(chip->regmap, regaddr,
1218 					   regaddr + NBANK(chip) - 1);
1219 		if (ret) {
1220 			dev_err(dev, "Failed to sync INT latch registers: %d\n",
1221 				ret);
1222 			return ret;
1223 		}
1224 
1225 		regaddr = chip->recalc_addr(chip, PCAL953X_INT_MASK, 0);
1226 		ret = regcache_sync_region(chip->regmap, regaddr,
1227 					   regaddr + NBANK(chip) - 1);
1228 		if (ret) {
1229 			dev_err(dev, "Failed to sync INT mask registers: %d\n",
1230 				ret);
1231 			return ret;
1232 		}
1233 	}
1234 #endif
1235 
1236 	return 0;
1237 }
1238 
pca953x_suspend(struct device * dev)1239 static int pca953x_suspend(struct device *dev)
1240 {
1241 	struct pca953x_chip *chip = dev_get_drvdata(dev);
1242 
1243 	mutex_lock(&chip->i2c_lock);
1244 	regcache_cache_only(chip->regmap, true);
1245 	mutex_unlock(&chip->i2c_lock);
1246 
1247 	if (atomic_read(&chip->wakeup_path))
1248 		device_set_wakeup_path(dev);
1249 	else
1250 		regulator_disable(chip->regulator);
1251 
1252 	return 0;
1253 }
1254 
pca953x_resume(struct device * dev)1255 static int pca953x_resume(struct device *dev)
1256 {
1257 	struct pca953x_chip *chip = dev_get_drvdata(dev);
1258 	int ret;
1259 
1260 	if (!atomic_read(&chip->wakeup_path)) {
1261 		ret = regulator_enable(chip->regulator);
1262 		if (ret) {
1263 			dev_err(dev, "Failed to enable regulator: %d\n", ret);
1264 			return 0;
1265 		}
1266 	}
1267 
1268 	mutex_lock(&chip->i2c_lock);
1269 	regcache_cache_only(chip->regmap, false);
1270 	regcache_mark_dirty(chip->regmap);
1271 	ret = pca953x_regcache_sync(dev);
1272 	if (ret) {
1273 		mutex_unlock(&chip->i2c_lock);
1274 		return ret;
1275 	}
1276 
1277 	ret = regcache_sync(chip->regmap);
1278 	mutex_unlock(&chip->i2c_lock);
1279 	if (ret) {
1280 		dev_err(dev, "Failed to restore register map: %d\n", ret);
1281 		return ret;
1282 	}
1283 
1284 	return 0;
1285 }
1286 #endif
1287 
1288 /* convenience to stop overlong match-table lines */
1289 #define OF_653X(__nrgpio, __int) ((void *)(__nrgpio | PCAL653X_TYPE | __int))
1290 #define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int)
1291 #define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int)
1292 
1293 static const struct of_device_id pca953x_dt_ids[] = {
1294 	{ .compatible = "nxp,pca6408", .data = OF_953X(8, PCA_INT), },
1295 	{ .compatible = "nxp,pca6416", .data = OF_953X(16, PCA_INT), },
1296 	{ .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), },
1297 	{ .compatible = "nxp,pca9506", .data = OF_953X(40, PCA_INT), },
1298 	{ .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), },
1299 	{ .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), },
1300 	{ .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), },
1301 	{ .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), },
1302 	{ .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), },
1303 	{ .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), },
1304 	{ .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), },
1305 	{ .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), },
1306 	{ .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), },
1307 	{ .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), },
1308 	{ .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), },
1309 	{ .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },
1310 	{ .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },
1311 
1312 	{ .compatible = "nxp,pcal6408", .data = OF_953X(8, PCA_LATCH_INT), },
1313 	{ .compatible = "nxp,pcal6416", .data = OF_953X(16, PCA_LATCH_INT), },
1314 	{ .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), },
1315 	{ .compatible = "nxp,pcal6534", .data = OF_653X(34, PCA_LATCH_INT), },
1316 	{ .compatible = "nxp,pcal9535", .data = OF_953X(16, PCA_LATCH_INT), },
1317 	{ .compatible = "nxp,pcal9554b", .data = OF_953X( 8, PCA_LATCH_INT), },
1318 	{ .compatible = "nxp,pcal9555a", .data = OF_953X(16, PCA_LATCH_INT), },
1319 
1320 	{ .compatible = "maxim,max7310", .data = OF_953X( 8, 0), },
1321 	{ .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), },
1322 	{ .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), },
1323 	{ .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), },
1324 	{ .compatible = "maxim,max7318", .data = OF_953X(16, PCA_INT), },
1325 
1326 	{ .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), },
1327 	{ .compatible = "ti,pca9536", .data = OF_953X( 4, 0), },
1328 	{ .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), },
1329 	{ .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), },
1330 	{ .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), },
1331 	{ .compatible = "ti,tca9538", .data = OF_953X( 8, PCA_INT), },
1332 	{ .compatible = "ti,tca9539", .data = OF_953X(16, PCA_INT), },
1333 
1334 	{ .compatible = "onnn,cat9554", .data = OF_953X( 8, PCA_INT), },
1335 	{ .compatible = "onnn,pca9654", .data = OF_953X( 8, PCA_INT), },
1336 	{ .compatible = "onnn,pca9655", .data = OF_953X(16, PCA_INT), },
1337 
1338 	{ .compatible = "exar,xra1202", .data = OF_953X( 8, 0), },
1339 	{ }
1340 };
1341 
1342 MODULE_DEVICE_TABLE(of, pca953x_dt_ids);
1343 
1344 static SIMPLE_DEV_PM_OPS(pca953x_pm_ops, pca953x_suspend, pca953x_resume);
1345 
1346 static struct i2c_driver pca953x_driver = {
1347 	.driver = {
1348 		.name	= "pca953x",
1349 		.pm	= &pca953x_pm_ops,
1350 		.of_match_table = pca953x_dt_ids,
1351 		.acpi_match_table = pca953x_acpi_ids,
1352 	},
1353 	.probe		= pca953x_probe,
1354 	.id_table	= pca953x_id,
1355 };
1356 
pca953x_init(void)1357 static int __init pca953x_init(void)
1358 {
1359 	return i2c_add_driver(&pca953x_driver);
1360 }
1361 /* register after i2c postcore initcall and before
1362  * subsys initcalls that may rely on these GPIOs
1363  */
1364 subsys_initcall(pca953x_init);
1365 
pca953x_exit(void)1366 static void __exit pca953x_exit(void)
1367 {
1368 	i2c_del_driver(&pca953x_driver);
1369 }
1370 module_exit(pca953x_exit);
1371 
1372 MODULE_AUTHOR("eric miao <eric.miao@marvell.com>");
1373 MODULE_DESCRIPTION("GPIO expander driver for PCA953x");
1374 MODULE_LICENSE("GPL");
1375