1 /*
2 * QEMU PC System Emulator
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "exec/target_page.h"
28 #include "hw/i386/pc.h"
29 #include "hw/char/serial-isa.h"
30 #include "hw/char/parallel.h"
31 #include "hw/hyperv/hv-balloon.h"
32 #include "hw/i386/fw_cfg.h"
33 #include "hw/i386/vmport.h"
34 #include "system/cpus.h"
35 #include "hw/ide/ide-bus.h"
36 #include "hw/timer/hpet.h"
37 #include "hw/loader.h"
38 #include "hw/rtc/mc146818rtc.h"
39 #include "hw/intc/i8259.h"
40 #include "hw/timer/i8254.h"
41 #include "hw/input/i8042.h"
42 #include "hw/audio/pcspk.h"
43 #include "system/system.h"
44 #include "system/xen.h"
45 #include "system/reset.h"
46 #include "kvm/kvm_i386.h"
47 #include "kvm/tdx.h"
48 #include "hw/xen/xen.h"
49 #include "qobject/qlist.h"
50 #include "qemu/error-report.h"
51 #include "hw/acpi/cpu_hotplug.h"
52 #include "acpi-build.h"
53 #include "hw/mem/nvdimm.h"
54 #include "hw/cxl/cxl_host.h"
55 #include "hw/usb.h"
56 #include "hw/i386/intel_iommu.h"
57 #include "hw/net/ne2000-isa.h"
58 #include "hw/virtio/virtio-iommu.h"
59 #include "hw/virtio/virtio-md-pci.h"
60 #include "hw/i386/kvm/xen_overlay.h"
61 #include "hw/i386/kvm/xen_evtchn.h"
62 #include "hw/i386/kvm/xen_gnttab.h"
63 #include "hw/i386/kvm/xen_xenstore.h"
64 #include "hw/mem/memory-device.h"
65 #include "e820_memory_layout.h"
66 #include "trace.h"
67 #include "sev.h"
68 #include CONFIG_DEVICES
69
70 #ifdef CONFIG_XEN_EMU
71 #include "hw/xen/xen-legacy-backend.h"
72 #include "hw/xen/xen-bus.h"
73 #endif
74
75 /*
76 * Helper for setting model-id for CPU models that changed model-id
77 * depending on QEMU versions up to QEMU 2.4.
78 */
79 #define PC_CPU_MODEL_IDS(v) \
80 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
81 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
82 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },
83
84 GlobalProperty pc_compat_10_0[] = {
85 { TYPE_X86_CPU, "x-consistent-cache", "false" },
86 { TYPE_X86_CPU, "x-vendor-cpuid-only-v2", "false" },
87 { TYPE_X86_CPU, "x-arch-cap-always-on", "true" },
88 { TYPE_X86_CPU, "x-pdcm-on-even-without-pmu", "true" },
89 };
90 const size_t pc_compat_10_0_len = G_N_ELEMENTS(pc_compat_10_0);
91
92 GlobalProperty pc_compat_9_2[] = {};
93 const size_t pc_compat_9_2_len = G_N_ELEMENTS(pc_compat_9_2);
94
95 GlobalProperty pc_compat_9_1[] = {
96 { "ICH9-LPC", "x-smi-swsmi-timer", "off" },
97 { "ICH9-LPC", "x-smi-periodic-timer", "off" },
98 { TYPE_INTEL_IOMMU_DEVICE, "stale-tm", "on" },
99 { TYPE_INTEL_IOMMU_DEVICE, "aw-bits", "39" },
100 };
101 const size_t pc_compat_9_1_len = G_N_ELEMENTS(pc_compat_9_1);
102
103 GlobalProperty pc_compat_9_0[] = {
104 { TYPE_X86_CPU, "x-amd-topoext-features-only", "false" },
105 { TYPE_X86_CPU, "x-l1-cache-per-thread", "false" },
106 { TYPE_X86_CPU, "guest-phys-bits", "0" },
107 { "sev-guest", "legacy-vm-type", "on" },
108 { TYPE_X86_CPU, "legacy-multi-node", "on" },
109 };
110 const size_t pc_compat_9_0_len = G_N_ELEMENTS(pc_compat_9_0);
111
112 GlobalProperty pc_compat_8_2[] = {};
113 const size_t pc_compat_8_2_len = G_N_ELEMENTS(pc_compat_8_2);
114
115 GlobalProperty pc_compat_8_1[] = {};
116 const size_t pc_compat_8_1_len = G_N_ELEMENTS(pc_compat_8_1);
117
118 GlobalProperty pc_compat_8_0[] = {
119 { "virtio-mem", "unplugged-inaccessible", "auto" },
120 };
121 const size_t pc_compat_8_0_len = G_N_ELEMENTS(pc_compat_8_0);
122
123 GlobalProperty pc_compat_7_2[] = {
124 { "ICH9-LPC", "noreboot", "true" },
125 };
126 const size_t pc_compat_7_2_len = G_N_ELEMENTS(pc_compat_7_2);
127
128 GlobalProperty pc_compat_7_1[] = {};
129 const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1);
130
131 GlobalProperty pc_compat_7_0[] = {};
132 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0);
133
134 GlobalProperty pc_compat_6_2[] = {
135 { "virtio-mem", "unplugged-inaccessible", "off" },
136 };
137 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2);
138
139 GlobalProperty pc_compat_6_1[] = {
140 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" },
141 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" },
142 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" },
143 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" },
144 };
145 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1);
146
147 GlobalProperty pc_compat_6_0[] = {
148 { "qemu64" "-" TYPE_X86_CPU, "family", "6" },
149 { "qemu64" "-" TYPE_X86_CPU, "model", "6" },
150 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" },
151 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" },
152 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" },
153 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" },
154 };
155 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0);
156
157 GlobalProperty pc_compat_5_2[] = {
158 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" },
159 };
160 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2);
161
162 GlobalProperty pc_compat_5_1[] = {
163 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" },
164 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" },
165 };
166 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1);
167
168 GlobalProperty pc_compat_5_0[] = {
169 };
170 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0);
171
172 GlobalProperty pc_compat_4_2[] = {
173 { "mch", "smbase-smram", "off" },
174 };
175 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2);
176
177 GlobalProperty pc_compat_4_1[] = {};
178 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1);
179
180 GlobalProperty pc_compat_4_0[] = {};
181 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0);
182
183 GlobalProperty pc_compat_3_1[] = {
184 { "intel-iommu", "dma-drain", "off" },
185 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" },
186 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" },
187 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" },
188 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" },
189 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" },
190 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" },
191 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" },
192 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" },
193 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" },
194 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" },
195 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" },
196 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
197 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
198 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
199 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
200 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
201 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
202 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
203 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
204 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" },
205 };
206 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
207
208 GlobalProperty pc_compat_3_0[] = {
209 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" },
210 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" },
211 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" },
212 };
213 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0);
214
215 GlobalProperty pc_compat_2_12[] = {
216 { TYPE_X86_CPU, "legacy-cache", "on" },
217 { TYPE_X86_CPU, "topoext", "off" },
218 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
219 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
220 };
221 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
222
223 GlobalProperty pc_compat_2_11[] = {
224 { TYPE_X86_CPU, "x-migrate-smi-count", "off" },
225 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" },
226 };
227 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11);
228
229 GlobalProperty pc_compat_2_10[] = {
230 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" },
231 { "i440FX-pcihost", "x-pci-hole64-fix", "off" },
232 { "q35-pcihost", "x-pci-hole64-fix", "off" },
233 };
234 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10);
235
236 GlobalProperty pc_compat_2_9[] = {
237 { "mch", "extended-tseg-mbytes", "0" },
238 };
239 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9);
240
241 GlobalProperty pc_compat_2_8[] = {
242 { TYPE_X86_CPU, "tcg-cpuid", "off" },
243 { "kvmclock", "x-mach-use-reliable-get-clock", "off" },
244 { "ICH9-LPC", "x-smi-broadcast", "off" },
245 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" },
246 { "Haswell-" TYPE_X86_CPU, "stepping", "1" },
247 };
248 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8);
249
250 GlobalProperty pc_compat_2_7[] = {
251 { TYPE_X86_CPU, "l3-cache", "off" },
252 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" },
253 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" },
254 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" },
255 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" },
256 { "isa-pcspk", "migrate", "off" },
257 };
258 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7);
259
260 GlobalProperty pc_compat_2_6[] = {
261 { TYPE_X86_CPU, "cpuid-0xb", "off" },
262 { "vmxnet3", "romfile", "" },
263 { TYPE_X86_CPU, "fill-mtrr-mask", "off" },
264 { "apic-common", "legacy-instance-id", "on", }
265 };
266 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
267
268 /*
269 * @PC_FW_DATA:
270 * Size of the chunk of memory at the top of RAM for the BIOS ACPI tables
271 * and other BIOS datastructures.
272 *
273 * BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K
274 * reported to be used at the moment, 32K should be enough for a while.
275 */
276 #define PC_FW_DATA (0x20000 + 0x8000)
277
pc_gsi_create(qemu_irq ** irqs,bool pci_enabled)278 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
279 {
280 GSIState *s;
281
282 s = g_new0(GSIState, 1);
283 if (kvm_ioapic_in_kernel()) {
284 kvm_pc_setup_irq_routing(pci_enabled);
285 }
286 *irqs = qemu_allocate_irqs(gsi_handler, s, IOAPIC_NUM_PINS);
287
288 return s;
289 }
290
ioport80_write(void * opaque,hwaddr addr,uint64_t data,unsigned size)291 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
292 unsigned size)
293 {
294 }
295
ioport80_read(void * opaque,hwaddr addr,unsigned size)296 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
297 {
298 return 0xffffffffffffffffULL;
299 }
300
301 /* MS-DOS compatibility mode FPU exception support */
ioportF0_write(void * opaque,hwaddr addr,uint64_t data,unsigned size)302 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
303 unsigned size)
304 {
305 if (tcg_enabled()) {
306 cpu_set_ignne();
307 }
308 }
309
ioportF0_read(void * opaque,hwaddr addr,unsigned size)310 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
311 {
312 return 0xffffffffffffffffULL;
313 }
314
315 /* PC cmos mappings */
316
317 #define REG_EQUIPMENT_BYTE 0x14
318
cmos_init_hd(MC146818RtcState * s,int type_ofs,int info_ofs,int16_t cylinders,int8_t heads,int8_t sectors)319 static void cmos_init_hd(MC146818RtcState *s, int type_ofs, int info_ofs,
320 int16_t cylinders, int8_t heads, int8_t sectors)
321 {
322 mc146818rtc_set_cmos_data(s, type_ofs, 47);
323 mc146818rtc_set_cmos_data(s, info_ofs, cylinders);
324 mc146818rtc_set_cmos_data(s, info_ofs + 1, cylinders >> 8);
325 mc146818rtc_set_cmos_data(s, info_ofs + 2, heads);
326 mc146818rtc_set_cmos_data(s, info_ofs + 3, 0xff);
327 mc146818rtc_set_cmos_data(s, info_ofs + 4, 0xff);
328 mc146818rtc_set_cmos_data(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
329 mc146818rtc_set_cmos_data(s, info_ofs + 6, cylinders);
330 mc146818rtc_set_cmos_data(s, info_ofs + 7, cylinders >> 8);
331 mc146818rtc_set_cmos_data(s, info_ofs + 8, sectors);
332 }
333
334 /* convert boot_device letter to something recognizable by the bios */
boot_device2nibble(char boot_device)335 static int boot_device2nibble(char boot_device)
336 {
337 switch(boot_device) {
338 case 'a':
339 case 'b':
340 return 0x01; /* floppy boot */
341 case 'c':
342 return 0x02; /* hard drive boot */
343 case 'd':
344 return 0x03; /* CD-ROM boot */
345 case 'n':
346 return 0x04; /* Network boot */
347 }
348 return 0;
349 }
350
set_boot_dev(PCMachineState * pcms,MC146818RtcState * s,const char * boot_device,Error ** errp)351 static void set_boot_dev(PCMachineState *pcms, MC146818RtcState *s,
352 const char *boot_device, Error **errp)
353 {
354 #define PC_MAX_BOOT_DEVICES 3
355 int nbds, bds[3] = { 0, };
356 int i;
357
358 nbds = strlen(boot_device);
359 if (nbds > PC_MAX_BOOT_DEVICES) {
360 error_setg(errp, "Too many boot devices for PC");
361 return;
362 }
363 for (i = 0; i < nbds; i++) {
364 bds[i] = boot_device2nibble(boot_device[i]);
365 if (bds[i] == 0) {
366 error_setg(errp, "Invalid boot device for PC: '%c'",
367 boot_device[i]);
368 return;
369 }
370 }
371 mc146818rtc_set_cmos_data(s, 0x3d, (bds[1] << 4) | bds[0]);
372 mc146818rtc_set_cmos_data(s, 0x38, (bds[2] << 4) | !pcms->fd_bootchk);
373 }
374
pc_boot_set(void * opaque,const char * boot_device,Error ** errp)375 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
376 {
377 PCMachineState *pcms = opaque;
378 X86MachineState *x86ms = X86_MACHINE(pcms);
379
380 set_boot_dev(pcms, MC146818_RTC(x86ms->rtc), boot_device, errp);
381 }
382
pc_cmos_init_floppy(MC146818RtcState * rtc_state,ISADevice * floppy)383 static void pc_cmos_init_floppy(MC146818RtcState *rtc_state, ISADevice *floppy)
384 {
385 int val, nb;
386 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
387 FLOPPY_DRIVE_TYPE_NONE };
388
389 #ifdef CONFIG_FDC_ISA
390 /* floppy type */
391 if (floppy) {
392 for (int i = 0; i < 2; i++) {
393 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
394 }
395 }
396 #endif
397
398 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
399 cmos_get_fd_drive_type(fd_type[1]);
400 mc146818rtc_set_cmos_data(rtc_state, 0x10, val);
401
402 val = mc146818rtc_get_cmos_data(rtc_state, REG_EQUIPMENT_BYTE);
403 nb = 0;
404 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
405 nb++;
406 }
407 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
408 nb++;
409 }
410 switch (nb) {
411 case 0:
412 break;
413 case 1:
414 val |= 0x01; /* 1 drive, ready for boot */
415 break;
416 case 2:
417 val |= 0x41; /* 2 drives, ready for boot */
418 break;
419 }
420 mc146818rtc_set_cmos_data(rtc_state, REG_EQUIPMENT_BYTE, val);
421 }
422
423 typedef struct check_fdc_state {
424 ISADevice *floppy;
425 bool multiple;
426 } CheckFdcState;
427
check_fdc(Object * obj,void * opaque)428 static int check_fdc(Object *obj, void *opaque)
429 {
430 CheckFdcState *state = opaque;
431 Object *fdc;
432 uint32_t iobase;
433 Error *local_err = NULL;
434
435 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
436 if (!fdc) {
437 return 0;
438 }
439
440 iobase = object_property_get_uint(obj, "iobase", &local_err);
441 if (local_err || iobase != 0x3f0) {
442 error_free(local_err);
443 return 0;
444 }
445
446 if (state->floppy) {
447 state->multiple = true;
448 } else {
449 state->floppy = ISA_DEVICE(obj);
450 }
451 return 0;
452 }
453
454 static const char * const fdc_container_path[] = {
455 "unattached", "peripheral", "peripheral-anon"
456 };
457
458 /*
459 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
460 * and ACPI objects.
461 */
pc_find_fdc0(void)462 static ISADevice *pc_find_fdc0(void)
463 {
464 int i;
465 Object *container;
466 CheckFdcState state = { 0 };
467
468 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
469 container = machine_get_container(fdc_container_path[i]);
470 object_child_foreach(container, check_fdc, &state);
471 }
472
473 if (state.multiple) {
474 warn_report("multiple floppy disk controllers with "
475 "iobase=0x3f0 have been found");
476 error_printf("the one being picked for CMOS setup might not reflect "
477 "your intent");
478 }
479
480 return state.floppy;
481 }
482
pc_cmos_init_late(PCMachineState * pcms)483 static void pc_cmos_init_late(PCMachineState *pcms)
484 {
485 X86MachineState *x86ms = X86_MACHINE(pcms);
486 MC146818RtcState *s = MC146818_RTC(x86ms->rtc);
487 int16_t cylinders;
488 int8_t heads, sectors;
489 int val;
490 int i, trans;
491
492 val = 0;
493 if (pcms->idebus[0] &&
494 ide_get_geometry(pcms->idebus[0], 0,
495 &cylinders, &heads, §ors) >= 0) {
496 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
497 val |= 0xf0;
498 }
499 if (pcms->idebus[0] &&
500 ide_get_geometry(pcms->idebus[0], 1,
501 &cylinders, &heads, §ors) >= 0) {
502 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
503 val |= 0x0f;
504 }
505 mc146818rtc_set_cmos_data(s, 0x12, val);
506
507 val = 0;
508 for (i = 0; i < 4; i++) {
509 /* NOTE: ide_get_geometry() returns the physical
510 geometry. It is always such that: 1 <= sects <= 63, 1
511 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
512 geometry can be different if a translation is done. */
513 BusState *idebus = pcms->idebus[i / 2];
514 if (idebus &&
515 ide_get_geometry(idebus, i % 2,
516 &cylinders, &heads, §ors) >= 0) {
517 trans = ide_get_bios_chs_trans(idebus, i % 2) - 1;
518 assert((trans & ~3) == 0);
519 val |= trans << (i * 2);
520 }
521 }
522 mc146818rtc_set_cmos_data(s, 0x39, val);
523
524 pc_cmos_init_floppy(s, pc_find_fdc0());
525
526 /* various important CMOS locations needed by PC/Bochs bios */
527
528 /* memory size */
529 /* base memory (first MiB) */
530 val = MIN(x86ms->below_4g_mem_size / KiB, 640);
531 mc146818rtc_set_cmos_data(s, 0x15, val);
532 mc146818rtc_set_cmos_data(s, 0x16, val >> 8);
533 /* extended memory (next 64MiB) */
534 if (x86ms->below_4g_mem_size > 1 * MiB) {
535 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB;
536 } else {
537 val = 0;
538 }
539 if (val > 65535)
540 val = 65535;
541 mc146818rtc_set_cmos_data(s, 0x17, val);
542 mc146818rtc_set_cmos_data(s, 0x18, val >> 8);
543 mc146818rtc_set_cmos_data(s, 0x30, val);
544 mc146818rtc_set_cmos_data(s, 0x31, val >> 8);
545 /* memory between 16MiB and 4GiB */
546 if (x86ms->below_4g_mem_size > 16 * MiB) {
547 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
548 } else {
549 val = 0;
550 }
551 if (val > 65535)
552 val = 65535;
553 mc146818rtc_set_cmos_data(s, 0x34, val);
554 mc146818rtc_set_cmos_data(s, 0x35, val >> 8);
555 /* memory above 4GiB */
556 val = x86ms->above_4g_mem_size / 65536;
557 mc146818rtc_set_cmos_data(s, 0x5b, val);
558 mc146818rtc_set_cmos_data(s, 0x5c, val >> 8);
559 mc146818rtc_set_cmos_data(s, 0x5d, val >> 16);
560
561 val = 0;
562 val |= 0x02; /* FPU is there */
563 val |= 0x04; /* PS/2 mouse installed */
564 mc146818rtc_set_cmos_data(s, REG_EQUIPMENT_BYTE, val);
565 }
566
handle_a20_line_change(void * opaque,int irq,int level)567 static void handle_a20_line_change(void *opaque, int irq, int level)
568 {
569 X86CPU *cpu = opaque;
570
571 /* XXX: send to all CPUs ? */
572 /* XXX: add logic to handle multiple A20 line sources */
573 x86_cpu_set_a20(cpu, level);
574 }
575
576 #define NE2000_NB_MAX 6
577
578 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
579 0x280, 0x380 };
580 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
581
pc_init_ne2k_isa(ISABus * bus,NICInfo * nd,Error ** errp)582 static gboolean pc_init_ne2k_isa(ISABus *bus, NICInfo *nd, Error **errp)
583 {
584 static int nb_ne2k = 0;
585
586 if (nb_ne2k == NE2000_NB_MAX) {
587 error_setg(errp,
588 "maximum number of ISA NE2000 devices exceeded");
589 return false;
590 }
591 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
592 ne2000_irq[nb_ne2k], nd);
593 nb_ne2k++;
594 return true;
595 }
596
pc_acpi_smi_interrupt(void * opaque,int irq,int level)597 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
598 {
599 X86CPU *cpu = opaque;
600
601 if (level) {
602 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
603 }
604 }
605
606 static
pc_machine_done(Notifier * notifier,void * data)607 void pc_machine_done(Notifier *notifier, void *data)
608 {
609 PCMachineState *pcms = container_of(notifier,
610 PCMachineState, machine_done);
611 X86MachineState *x86ms = X86_MACHINE(pcms);
612
613 cxl_hook_up_pxb_registers(pcms->pcibus, &pcms->cxl_devices_state,
614 &error_fatal);
615
616 if (pcms->cxl_devices_state.is_enabled) {
617 cxl_fmws_link_targets(&error_fatal);
618 }
619
620 /* set the number of CPUs */
621 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
622
623 pci_bus_add_fw_cfg_extra_pci_roots(x86ms->fw_cfg, pcms->pcibus,
624 &error_abort);
625
626 acpi_setup();
627 if (x86ms->fw_cfg) {
628 fw_cfg_build_smbios(pcms, x86ms->fw_cfg, pcms->smbios_entry_point_type);
629 fw_cfg_add_e820(x86ms->fw_cfg);
630 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg);
631 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
632 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
633 }
634
635 pc_cmos_init_late(pcms);
636 }
637
638 /* setup pci memory address space mapping into system address space */
pc_pci_as_mapping_init(MemoryRegion * system_memory,MemoryRegion * pci_address_space)639 void pc_pci_as_mapping_init(MemoryRegion *system_memory,
640 MemoryRegion *pci_address_space)
641 {
642 /* Set to lower priority than RAM */
643 memory_region_add_subregion_overlap(system_memory, 0x0,
644 pci_address_space, -1);
645 }
646
xen_load_linux(PCMachineState * pcms)647 void xen_load_linux(PCMachineState *pcms)
648 {
649 int i;
650 FWCfgState *fw_cfg;
651 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
652 X86MachineState *x86ms = X86_MACHINE(pcms);
653
654 assert(MACHINE(pcms)->kernel_filename != NULL);
655
656 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4,
657 &address_space_memory);
658 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
659 rom_set_fw(fw_cfg);
660
661 x86_load_linux(x86ms, fw_cfg, PC_FW_DATA, pcmc->pvh_enabled);
662 for (i = 0; i < nb_option_roms; i++) {
663 assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
664 !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
665 !strcmp(option_rom[i].name, "pvh.bin") ||
666 !strcmp(option_rom[i].name, "multiboot.bin") ||
667 !strcmp(option_rom[i].name, "multiboot_dma.bin"));
668 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
669 }
670 x86ms->fw_cfg = fw_cfg;
671 }
672
673 #define PC_ROM_MIN_VGA 0xc0000
674 #define PC_ROM_MIN_OPTION 0xc8000
675 #define PC_ROM_MAX 0xe0000
676 #define PC_ROM_ALIGN 0x800
677 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA)
678
pc_above_4g_end(PCMachineState * pcms)679 static hwaddr pc_above_4g_end(PCMachineState *pcms)
680 {
681 X86MachineState *x86ms = X86_MACHINE(pcms);
682
683 if (pcms->sgx_epc.size != 0) {
684 return sgx_epc_above_4g_end(&pcms->sgx_epc);
685 }
686
687 return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size;
688 }
689
pc_get_device_memory_range(PCMachineState * pcms,hwaddr * base,ram_addr_t * device_mem_size)690 static void pc_get_device_memory_range(PCMachineState *pcms,
691 hwaddr *base,
692 ram_addr_t *device_mem_size)
693 {
694 MachineState *machine = MACHINE(pcms);
695 ram_addr_t size;
696 hwaddr addr;
697
698 size = machine->maxram_size - machine->ram_size;
699 addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB);
700
701 /* size device region assuming 1G page max alignment per slot */
702 size += (1 * GiB) * machine->ram_slots;
703
704 *base = addr;
705 *device_mem_size = size;
706 }
707
pc_get_cxl_range_start(PCMachineState * pcms)708 static uint64_t pc_get_cxl_range_start(PCMachineState *pcms)
709 {
710 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
711 MachineState *ms = MACHINE(pcms);
712 hwaddr cxl_base;
713 ram_addr_t size;
714
715 if (pcmc->has_reserved_memory &&
716 (ms->ram_size < ms->maxram_size)) {
717 pc_get_device_memory_range(pcms, &cxl_base, &size);
718 cxl_base += size;
719 } else {
720 cxl_base = pc_above_4g_end(pcms);
721 }
722
723 return cxl_base;
724 }
725
cxl_get_fmw_end(Object * obj,void * opaque)726 static int cxl_get_fmw_end(Object *obj, void *opaque)
727 {
728 struct CXLFixedWindow *fw;
729 uint64_t *start = opaque;
730
731 if (!object_dynamic_cast(obj, TYPE_CXL_FMW)) {
732 return 0;
733 }
734 fw = CXL_FMW(obj);
735
736 *start += fw->size;
737
738 return 0;
739 }
740
pc_get_cxl_range_end(PCMachineState * pcms)741 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms)
742 {
743 uint64_t start = pc_get_cxl_range_start(pcms) + MiB;
744
745 /* Ordering doesn't matter so no need to build a sorted list */
746 object_child_foreach_recursive(object_get_root(), cxl_get_fmw_end,
747 &start);
748 return start;
749 }
750
pc_max_used_gpa(PCMachineState * pcms,uint64_t pci_hole64_size)751 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size)
752 {
753 X86CPU *cpu = X86_CPU(first_cpu);
754 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
755 MachineState *ms = MACHINE(pcms);
756
757 if (cpu->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
758 /* 64-bit systems */
759 return pc_pci_hole64_start() + pci_hole64_size - 1;
760 }
761
762 /* 32-bit systems */
763 if (pcmc->broken_32bit_mem_addr_check) {
764 /* old value for compatibility reasons */
765 return ((hwaddr)1 << cpu->phys_bits) - 1;
766 }
767
768 /*
769 * 32-bit systems don't have hole64 but they might have a region for
770 * memory devices. Even if additional hotplugged memory devices might
771 * not be usable by most guest OSes, we need to still consider them for
772 * calculating the highest possible GPA so that we can properly report
773 * if someone configures them on a CPU that cannot possibly address them.
774 */
775 if (pcmc->has_reserved_memory &&
776 (ms->ram_size < ms->maxram_size)) {
777 hwaddr devmem_start;
778 ram_addr_t devmem_size;
779
780 pc_get_device_memory_range(pcms, &devmem_start, &devmem_size);
781 devmem_start += devmem_size;
782 return devmem_start - 1;
783 }
784
785 /* configuration without any memory hotplug */
786 return pc_above_4g_end(pcms) - 1;
787 }
788
789 /*
790 * AMD systems with an IOMMU have an additional hole close to the
791 * 1Tb, which are special GPAs that cannot be DMA mapped. Depending
792 * on kernel version, VFIO may or may not let you DMA map those ranges.
793 * Starting Linux v5.4 we validate it, and can't create guests on AMD machines
794 * with certain memory sizes. It's also wrong to use those IOVA ranges
795 * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse.
796 * The ranges reserved for Hyper-Transport are:
797 *
798 * FD_0000_0000h - FF_FFFF_FFFFh
799 *
800 * The ranges represent the following:
801 *
802 * Base Address Top Address Use
803 *
804 * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space
805 * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl
806 * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK
807 * FD_F910_0000h FD_F91F_FFFFh System Management
808 * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables
809 * FD_FB00_0000h FD_FBFF_FFFFh Address Translation
810 * FD_FC00_0000h FD_FDFF_FFFFh I/O Space
811 * FD_FE00_0000h FD_FFFF_FFFFh Configuration
812 * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages
813 * FE_2000_0000h FF_FFFF_FFFFh Reserved
814 *
815 * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology",
816 * Table 3: Special Address Controls (GPA) for more information.
817 */
818 #define AMD_HT_START 0xfd00000000UL
819 #define AMD_HT_END 0xffffffffffUL
820 #define AMD_ABOVE_1TB_START (AMD_HT_END + 1)
821 #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START)
822
pc_memory_init(PCMachineState * pcms,MemoryRegion * system_memory,MemoryRegion * rom_memory,uint64_t pci_hole64_size)823 void pc_memory_init(PCMachineState *pcms,
824 MemoryRegion *system_memory,
825 MemoryRegion *rom_memory,
826 uint64_t pci_hole64_size)
827 {
828 int linux_boot, i;
829 MemoryRegion *option_rom_mr;
830 MemoryRegion *ram_below_4g, *ram_above_4g;
831 FWCfgState *fw_cfg;
832 MachineState *machine = MACHINE(pcms);
833 MachineClass *mc = MACHINE_GET_CLASS(machine);
834 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
835 X86MachineState *x86ms = X86_MACHINE(pcms);
836 hwaddr maxphysaddr, maxusedaddr;
837 hwaddr cxl_base, cxl_resv_end = 0;
838 X86CPU *cpu = X86_CPU(first_cpu);
839 uint64_t res_mem_end;
840
841 assert(machine->ram_size == x86ms->below_4g_mem_size +
842 x86ms->above_4g_mem_size);
843
844 linux_boot = (machine->kernel_filename != NULL);
845
846 /*
847 * The HyperTransport range close to the 1T boundary is unique to AMD
848 * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation
849 * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in
850 * older machine types (<= 7.0) for compatibility purposes.
851 */
852 if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) {
853 /* Bail out if max possible address does not cross HT range */
854 if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) {
855 x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START;
856 }
857
858 /*
859 * Advertise the HT region if address space covers the reserved
860 * region or if we relocate.
861 */
862 if (cpu->phys_bits >= 40) {
863 e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED);
864 }
865 }
866
867 /*
868 * phys-bits is required to be appropriately configured
869 * to make sure max used GPA is reachable.
870 */
871 maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size);
872 maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1;
873 if (maxphysaddr < maxusedaddr) {
874 error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64
875 " phys-bits too low (%u)",
876 maxphysaddr, maxusedaddr, cpu->phys_bits);
877 exit(EXIT_FAILURE);
878 }
879
880 /*
881 * Split single memory region and use aliases to address portions of it,
882 * done for backwards compatibility with older qemus.
883 */
884 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
885 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram,
886 0, x86ms->below_4g_mem_size);
887 memory_region_add_subregion(system_memory, 0, ram_below_4g);
888 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM);
889 if (x86ms->above_4g_mem_size > 0) {
890 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
891 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g",
892 machine->ram,
893 x86ms->below_4g_mem_size,
894 x86ms->above_4g_mem_size);
895 memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start,
896 ram_above_4g);
897 e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size,
898 E820_RAM);
899 }
900
901 if (pcms->sgx_epc.size != 0) {
902 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED);
903 }
904
905 if (!pcmc->has_reserved_memory &&
906 (machine->ram_slots ||
907 (machine->maxram_size > machine->ram_size))) {
908
909 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
910 mc->name);
911 exit(EXIT_FAILURE);
912 }
913
914 /* initialize device memory address space */
915 if (pcmc->has_reserved_memory &&
916 (machine->ram_size < machine->maxram_size)) {
917 ram_addr_t device_mem_size;
918 hwaddr device_mem_base;
919
920 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
921 error_report("unsupported amount of memory slots: %"PRIu64,
922 machine->ram_slots);
923 exit(EXIT_FAILURE);
924 }
925
926 if (QEMU_ALIGN_UP(machine->maxram_size,
927 TARGET_PAGE_SIZE) != machine->maxram_size) {
928 error_report("maximum memory size must by aligned to multiple of "
929 "%d bytes", TARGET_PAGE_SIZE);
930 exit(EXIT_FAILURE);
931 }
932
933 pc_get_device_memory_range(pcms, &device_mem_base, &device_mem_size);
934
935 if (device_mem_base + device_mem_size < device_mem_size) {
936 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
937 machine->maxram_size);
938 exit(EXIT_FAILURE);
939 }
940 machine_memory_devices_init(machine, device_mem_base, device_mem_size);
941 }
942
943 if (pcms->cxl_devices_state.is_enabled) {
944 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr;
945 hwaddr cxl_size = MiB;
946
947 cxl_base = pc_get_cxl_range_start(pcms);
948 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size);
949 memory_region_add_subregion(system_memory, cxl_base, mr);
950 cxl_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB);
951 cxl_resv_end = cxl_fmws_set_memmap(cxl_base, maxphysaddr);
952 cxl_fmws_update_mmio();
953 }
954
955 /* Initialize PC system firmware */
956 pc_system_firmware_init(pcms, rom_memory);
957
958 if (!is_tdx_vm()) {
959 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
960 if (machine_require_guest_memfd(machine)) {
961 memory_region_init_ram_guest_memfd(option_rom_mr, NULL, "pc.rom",
962 PC_ROM_SIZE, &error_fatal);
963 } else {
964 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
965 &error_fatal);
966 if (pcmc->pci_enabled) {
967 memory_region_set_readonly(option_rom_mr, true);
968 }
969 }
970 memory_region_add_subregion_overlap(rom_memory,
971 PC_ROM_MIN_VGA,
972 option_rom_mr,
973 1);
974 }
975
976 fw_cfg = fw_cfg_arch_create(machine,
977 x86ms->boot_cpus, x86ms->apic_id_limit);
978
979 rom_set_fw(fw_cfg);
980
981 if (pcms->cxl_devices_state.is_enabled) {
982 res_mem_end = cxl_resv_end;
983 } else if (machine->device_memory) {
984 res_mem_end = machine->device_memory->base
985 + memory_region_size(&machine->device_memory->mr);
986 } else {
987 res_mem_end = 0;
988 }
989
990 if (res_mem_end) {
991 uint64_t *val = g_malloc(sizeof(*val));
992 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
993 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
994 }
995
996 if (linux_boot) {
997 x86_load_linux(x86ms, fw_cfg, PC_FW_DATA, pcmc->pvh_enabled);
998 }
999
1000 for (i = 0; i < nb_option_roms; i++) {
1001 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1002 }
1003 x86ms->fw_cfg = fw_cfg;
1004
1005 /* Init default IOAPIC address space */
1006 x86ms->ioapic_as = &address_space_memory;
1007
1008 /* Init ACPI memory hotplug IO base address */
1009 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
1010 }
1011
1012 /*
1013 * The 64bit pci hole starts after "above 4G RAM" and
1014 * potentially the space reserved for memory hotplug.
1015 */
pc_pci_hole64_start(void)1016 uint64_t pc_pci_hole64_start(void)
1017 {
1018 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1019 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1020 MachineState *ms = MACHINE(pcms);
1021 uint64_t hole64_start = 0;
1022 ram_addr_t size = 0;
1023
1024 if (pcms->cxl_devices_state.is_enabled) {
1025 hole64_start = pc_get_cxl_range_end(pcms);
1026 } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) {
1027 pc_get_device_memory_range(pcms, &hole64_start, &size);
1028 hole64_start += size;
1029 } else {
1030 hole64_start = pc_above_4g_end(pcms);
1031 }
1032
1033 return ROUND_UP(hole64_start, 1 * GiB);
1034 }
1035
pc_vga_init(ISABus * isa_bus,PCIBus * pci_bus)1036 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1037 {
1038 DeviceState *dev = NULL;
1039
1040 if (pci_bus) {
1041 PCIDevice *pcidev = pci_vga_init(pci_bus);
1042 dev = pcidev ? &pcidev->qdev : NULL;
1043 } else if (isa_bus) {
1044 ISADevice *isadev = isa_vga_init(isa_bus);
1045 dev = isadev ? DEVICE(isadev) : NULL;
1046 }
1047
1048 return dev;
1049 }
1050
1051 static const MemoryRegionOps ioport80_io_ops = {
1052 .write = ioport80_write,
1053 .read = ioport80_read,
1054 .endianness = DEVICE_LITTLE_ENDIAN,
1055 .impl = {
1056 .min_access_size = 1,
1057 .max_access_size = 1,
1058 },
1059 };
1060
1061 static const MemoryRegionOps ioportF0_io_ops = {
1062 .write = ioportF0_write,
1063 .read = ioportF0_read,
1064 .endianness = DEVICE_LITTLE_ENDIAN,
1065 .impl = {
1066 .min_access_size = 1,
1067 .max_access_size = 1,
1068 },
1069 };
1070
pc_superio_init(ISABus * isa_bus,bool create_fdctrl,bool create_i8042,bool no_vmport,Error ** errp)1071 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl,
1072 bool create_i8042, bool no_vmport, Error **errp)
1073 {
1074 int i;
1075 DriveInfo *fd[MAX_FD];
1076 qemu_irq *a20_line;
1077 ISADevice *i8042, *port92, *vmmouse;
1078
1079 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
1080 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1081
1082 for (i = 0; i < MAX_FD; i++) {
1083 fd[i] = drive_get(IF_FLOPPY, 0, i);
1084 create_fdctrl |= !!fd[i];
1085 }
1086 if (create_fdctrl) {
1087 #ifdef CONFIG_FDC_ISA
1088 ISADevice *fdc = isa_new(TYPE_ISA_FDC);
1089 if (fdc) {
1090 isa_realize_and_unref(fdc, isa_bus, &error_fatal);
1091 isa_fdc_init_drives(fdc, fd);
1092 }
1093 #endif
1094 }
1095
1096 if (!create_i8042) {
1097 if (!no_vmport) {
1098 error_setg(errp,
1099 "vmport requires the i8042 controller to be enabled");
1100 }
1101 return;
1102 }
1103
1104 i8042 = isa_create_simple(isa_bus, TYPE_I8042);
1105 if (!no_vmport) {
1106 isa_create_simple(isa_bus, TYPE_VMPORT);
1107 vmmouse = isa_try_new("vmmouse");
1108 } else {
1109 vmmouse = NULL;
1110 }
1111 if (vmmouse) {
1112 object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042),
1113 &error_abort);
1114 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal);
1115 }
1116 port92 = isa_create_simple(isa_bus, TYPE_PORT92);
1117
1118 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1119 qdev_connect_gpio_out_named(DEVICE(i8042),
1120 I8042_A20_LINE, 0, a20_line[0]);
1121 qdev_connect_gpio_out_named(DEVICE(port92),
1122 PORT92_A20_LINE, 0, a20_line[1]);
1123 g_free(a20_line);
1124 }
1125
pc_basic_device_init(struct PCMachineState * pcms,ISABus * isa_bus,qemu_irq * gsi,ISADevice * rtc_state,bool create_fdctrl,uint32_t hpet_irqs)1126 void pc_basic_device_init(struct PCMachineState *pcms,
1127 ISABus *isa_bus, qemu_irq *gsi,
1128 ISADevice *rtc_state,
1129 bool create_fdctrl,
1130 uint32_t hpet_irqs)
1131 {
1132 int i;
1133 DeviceState *hpet = NULL;
1134 int pit_isa_irq = 0;
1135 qemu_irq pit_alt_irq = NULL;
1136 ISADevice *pit = NULL;
1137 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1138 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1139 X86MachineState *x86ms = X86_MACHINE(pcms);
1140
1141 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1142 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1143
1144 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1145 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1146
1147 /*
1148 * Check if an HPET shall be created.
1149 */
1150 if (pcms->hpet_enabled) {
1151 qemu_irq rtc_irq;
1152
1153 hpet = qdev_try_new(TYPE_HPET);
1154 if (!hpet) {
1155 error_report("couldn't create HPET device");
1156 exit(1);
1157 }
1158 /*
1159 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-*,
1160 * use IRQ16~23, IRQ8 and IRQ2. If the user has already set
1161 * the property, use whatever mask they specified.
1162 */
1163 uint8_t compat = object_property_get_uint(OBJECT(hpet),
1164 HPET_INTCAP, NULL);
1165 if (!compat) {
1166 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1167 }
1168 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal);
1169 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1170
1171 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1172 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1173 }
1174 pit_isa_irq = -1;
1175 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1176 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1177
1178 /* overwrite connection created by south bridge */
1179 qdev_connect_gpio_out(DEVICE(rtc_state), 0, rtc_irq);
1180 }
1181
1182 object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(rtc_state),
1183 "date");
1184
1185 #ifdef CONFIG_XEN_EMU
1186 if (xen_mode == XEN_EMULATE) {
1187 xen_overlay_create();
1188 xen_evtchn_create(IOAPIC_NUM_PINS, gsi);
1189 xen_gnttab_create();
1190 xen_xenstore_create();
1191 if (pcms->pcibus) {
1192 pci_create_simple(pcms->pcibus, -1, "xen-platform");
1193 }
1194 xen_bus_init();
1195 }
1196 #endif
1197
1198 qemu_register_boot_set(pc_boot_set, pcms);
1199 set_boot_dev(pcms, MC146818_RTC(rtc_state),
1200 MACHINE(pcms)->boot_config.order, &error_fatal);
1201
1202 if (!xen_enabled() &&
1203 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) {
1204 if (kvm_pit_in_kernel()) {
1205 pit = kvm_pit_init(isa_bus, 0x40);
1206 } else {
1207 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1208 }
1209 if (hpet) {
1210 /* connect PIT to output control line of the HPET */
1211 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1212 }
1213 object_property_set_link(OBJECT(pcms->pcspk), "pit",
1214 OBJECT(pit), &error_fatal);
1215 isa_realize_and_unref(pcms->pcspk, isa_bus, &error_fatal);
1216 }
1217
1218 if (pcms->vmport == ON_OFF_AUTO_AUTO) {
1219 pcms->vmport = (xen_enabled() || !pcms->i8042_enabled)
1220 ? ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON;
1221 }
1222
1223 /* Super I/O */
1224 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled,
1225 pcms->vmport != ON_OFF_AUTO_ON, &error_fatal);
1226
1227 pcms->machine_done.notify = pc_machine_done;
1228 qemu_add_machine_init_done_notifier(&pcms->machine_done);
1229 }
1230
pc_nic_init(PCMachineClass * pcmc,ISABus * isa_bus,PCIBus * pci_bus)1231 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
1232 {
1233 MachineClass *mc = MACHINE_CLASS(pcmc);
1234 bool default_is_ne2k = g_str_equal(mc->default_nic, TYPE_ISA_NE2000);
1235 NICInfo *nd;
1236
1237 while ((nd = qemu_find_nic_info(TYPE_ISA_NE2000, default_is_ne2k, NULL))) {
1238 pc_init_ne2k_isa(isa_bus, nd, &error_fatal);
1239 }
1240
1241 /* Anything remaining should be a PCI NIC */
1242 if (pci_bus) {
1243 pci_init_nic_devices(pci_bus, mc->default_nic);
1244 }
1245 }
1246
pc_i8259_create(ISABus * isa_bus,qemu_irq * i8259_irqs)1247 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs)
1248 {
1249 qemu_irq *i8259;
1250
1251 if (kvm_pic_in_kernel()) {
1252 i8259 = kvm_i8259_init(isa_bus);
1253 } else if (xen_enabled()) {
1254 i8259 = xen_interrupt_controller_init();
1255 } else {
1256 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq());
1257 }
1258
1259 for (size_t i = 0; i < ISA_NUM_IRQS; i++) {
1260 i8259_irqs[i] = i8259[i];
1261 }
1262
1263 g_free(i8259);
1264 }
1265
pc_memory_pre_plug(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)1266 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
1267 Error **errp)
1268 {
1269 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1270 const MachineState *ms = MACHINE(hotplug_dev);
1271 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1272 Error *local_err = NULL;
1273
1274 /*
1275 * When "acpi=off" is used with the Q35 machine type, no ACPI is built,
1276 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1277 * addition to cover this case.
1278 */
1279 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
1280 error_setg(errp,
1281 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1282 return;
1283 }
1284
1285 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
1286 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1287 return;
1288 }
1289
1290 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err);
1291 if (local_err) {
1292 error_propagate(errp, local_err);
1293 return;
1294 }
1295
1296 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), errp);
1297 }
1298
pc_memory_plug(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)1299 static void pc_memory_plug(HotplugHandler *hotplug_dev,
1300 DeviceState *dev, Error **errp)
1301 {
1302 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1303 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1304 MachineState *ms = MACHINE(hotplug_dev);
1305 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1306
1307 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms));
1308
1309 if (is_nvdimm) {
1310 nvdimm_plug(ms->nvdimms_state);
1311 }
1312
1313 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort);
1314 }
1315
pc_memory_unplug_request(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)1316 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
1317 DeviceState *dev, Error **errp)
1318 {
1319 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1320
1321 /*
1322 * When "acpi=off" is used with the Q35 machine type, no ACPI is built,
1323 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1324 * addition to cover this case.
1325 */
1326 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
1327 error_setg(errp,
1328 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1329 return;
1330 }
1331
1332 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
1333 error_setg(errp, "nvdimm device hot unplug is not supported yet.");
1334 return;
1335 }
1336
1337 hotplug_handler_unplug_request(x86ms->acpi_dev, dev,
1338 errp);
1339 }
1340
pc_memory_unplug(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)1341 static void pc_memory_unplug(HotplugHandler *hotplug_dev,
1342 DeviceState *dev, Error **errp)
1343 {
1344 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1345 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1346 Error *local_err = NULL;
1347
1348 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err);
1349 if (local_err) {
1350 goto out;
1351 }
1352
1353 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
1354 qdev_unrealize(dev);
1355 out:
1356 error_propagate(errp, local_err);
1357 }
1358
pc_hv_balloon_pre_plug(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)1359 static void pc_hv_balloon_pre_plug(HotplugHandler *hotplug_dev,
1360 DeviceState *dev, Error **errp)
1361 {
1362 /* The vmbus handler has no hotplug handler; we should never end up here. */
1363 g_assert(!dev->hotplugged);
1364 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), errp);
1365 }
1366
pc_hv_balloon_plug(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)1367 static void pc_hv_balloon_plug(HotplugHandler *hotplug_dev,
1368 DeviceState *dev, Error **errp)
1369 {
1370 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1371 }
1372
pc_machine_device_pre_plug_cb(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)1373 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
1374 DeviceState *dev, Error **errp)
1375 {
1376 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1377 pc_memory_pre_plug(hotplug_dev, dev, errp);
1378 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1379 x86_cpu_pre_plug(hotplug_dev, dev, errp);
1380 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
1381 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
1382 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1383 /* Declare the APIC range as the reserved MSI region */
1384 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d",
1385 VIRTIO_IOMMU_RESV_MEM_T_MSI);
1386 QList *reserved_regions = qlist_new();
1387
1388 qlist_append_str(reserved_regions, resv_prop_str);
1389 qdev_prop_set_array(dev, "reserved-regions", reserved_regions);
1390
1391 g_free(resv_prop_str);
1392 }
1393
1394 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) ||
1395 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1396 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1397
1398 if (pcms->iommu) {
1399 error_setg(errp, "QEMU does not support multiple vIOMMUs "
1400 "for x86 yet.");
1401 return;
1402 }
1403 pcms->iommu = dev;
1404 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) {
1405 pc_hv_balloon_pre_plug(hotplug_dev, dev, errp);
1406 }
1407 }
1408
pc_machine_device_plug_cb(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)1409 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1410 DeviceState *dev, Error **errp)
1411 {
1412 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1413 pc_memory_plug(hotplug_dev, dev, errp);
1414 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1415 x86_cpu_plug(hotplug_dev, dev, errp);
1416 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
1417 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
1418 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) {
1419 pc_hv_balloon_plug(hotplug_dev, dev, errp);
1420 }
1421 }
1422
pc_machine_device_unplug_request_cb(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)1423 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
1424 DeviceState *dev, Error **errp)
1425 {
1426 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1427 pc_memory_unplug_request(hotplug_dev, dev, errp);
1428 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1429 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp);
1430 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
1431 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev),
1432 errp);
1433 } else {
1434 error_setg(errp, "acpi: device unplug request for not supported device"
1435 " type: %s", object_get_typename(OBJECT(dev)));
1436 }
1437 }
1438
pc_machine_device_unplug_cb(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)1439 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
1440 DeviceState *dev, Error **errp)
1441 {
1442 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1443 pc_memory_unplug(hotplug_dev, dev, errp);
1444 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1445 x86_cpu_unplug_cb(hotplug_dev, dev, errp);
1446 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
1447 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
1448 } else {
1449 error_setg(errp, "acpi: device unplug for not supported device"
1450 " type: %s", object_get_typename(OBJECT(dev)));
1451 }
1452 }
1453
pc_get_hotplug_handler(MachineState * machine,DeviceState * dev)1454 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine,
1455 DeviceState *dev)
1456 {
1457 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
1458 object_dynamic_cast(OBJECT(dev), TYPE_CPU) ||
1459 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) ||
1460 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) ||
1461 object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON) ||
1462 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) {
1463 return HOTPLUG_HANDLER(machine);
1464 }
1465
1466 return NULL;
1467 }
1468
pc_machine_get_vmport(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)1469 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
1470 void *opaque, Error **errp)
1471 {
1472 PCMachineState *pcms = PC_MACHINE(obj);
1473 OnOffAuto vmport = pcms->vmport;
1474
1475 visit_type_OnOffAuto(v, name, &vmport, errp);
1476 }
1477
pc_machine_set_vmport(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)1478 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
1479 void *opaque, Error **errp)
1480 {
1481 PCMachineState *pcms = PC_MACHINE(obj);
1482
1483 visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
1484 }
1485
pc_machine_get_fd_bootchk(Object * obj,Error ** errp)1486 static bool pc_machine_get_fd_bootchk(Object *obj, Error **errp)
1487 {
1488 PCMachineState *pcms = PC_MACHINE(obj);
1489
1490 return pcms->fd_bootchk;
1491 }
1492
pc_machine_set_fd_bootchk(Object * obj,bool value,Error ** errp)1493 static void pc_machine_set_fd_bootchk(Object *obj, bool value, Error **errp)
1494 {
1495 PCMachineState *pcms = PC_MACHINE(obj);
1496
1497 pcms->fd_bootchk = value;
1498 }
1499
pc_machine_get_smbus(Object * obj,Error ** errp)1500 static bool pc_machine_get_smbus(Object *obj, Error **errp)
1501 {
1502 PCMachineState *pcms = PC_MACHINE(obj);
1503
1504 return pcms->smbus_enabled;
1505 }
1506
pc_machine_set_smbus(Object * obj,bool value,Error ** errp)1507 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
1508 {
1509 PCMachineState *pcms = PC_MACHINE(obj);
1510
1511 pcms->smbus_enabled = value;
1512 }
1513
pc_machine_get_sata(Object * obj,Error ** errp)1514 static bool pc_machine_get_sata(Object *obj, Error **errp)
1515 {
1516 PCMachineState *pcms = PC_MACHINE(obj);
1517
1518 return pcms->sata_enabled;
1519 }
1520
pc_machine_set_sata(Object * obj,bool value,Error ** errp)1521 static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
1522 {
1523 PCMachineState *pcms = PC_MACHINE(obj);
1524
1525 pcms->sata_enabled = value;
1526 }
1527
pc_machine_get_hpet(Object * obj,Error ** errp)1528 static bool pc_machine_get_hpet(Object *obj, Error **errp)
1529 {
1530 PCMachineState *pcms = PC_MACHINE(obj);
1531
1532 return pcms->hpet_enabled;
1533 }
1534
pc_machine_set_hpet(Object * obj,bool value,Error ** errp)1535 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp)
1536 {
1537 PCMachineState *pcms = PC_MACHINE(obj);
1538
1539 pcms->hpet_enabled = value;
1540 }
1541
pc_machine_get_i8042(Object * obj,Error ** errp)1542 static bool pc_machine_get_i8042(Object *obj, Error **errp)
1543 {
1544 PCMachineState *pcms = PC_MACHINE(obj);
1545
1546 return pcms->i8042_enabled;
1547 }
1548
pc_machine_set_i8042(Object * obj,bool value,Error ** errp)1549 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp)
1550 {
1551 PCMachineState *pcms = PC_MACHINE(obj);
1552
1553 pcms->i8042_enabled = value;
1554 }
1555
pc_machine_get_default_bus_bypass_iommu(Object * obj,Error ** errp)1556 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp)
1557 {
1558 PCMachineState *pcms = PC_MACHINE(obj);
1559
1560 return pcms->default_bus_bypass_iommu;
1561 }
1562
pc_machine_set_default_bus_bypass_iommu(Object * obj,bool value,Error ** errp)1563 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value,
1564 Error **errp)
1565 {
1566 PCMachineState *pcms = PC_MACHINE(obj);
1567
1568 pcms->default_bus_bypass_iommu = value;
1569 }
1570
pc_machine_get_smbios_ep(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)1571 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name,
1572 void *opaque, Error **errp)
1573 {
1574 PCMachineState *pcms = PC_MACHINE(obj);
1575 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type;
1576
1577 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp);
1578 }
1579
pc_machine_set_smbios_ep(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)1580 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name,
1581 void *opaque, Error **errp)
1582 {
1583 PCMachineState *pcms = PC_MACHINE(obj);
1584
1585 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp);
1586 }
1587
pc_machine_get_max_ram_below_4g(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)1588 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
1589 const char *name, void *opaque,
1590 Error **errp)
1591 {
1592 PCMachineState *pcms = PC_MACHINE(obj);
1593 uint64_t value = pcms->max_ram_below_4g;
1594
1595 visit_type_size(v, name, &value, errp);
1596 }
1597
pc_machine_set_max_ram_below_4g(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)1598 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
1599 const char *name, void *opaque,
1600 Error **errp)
1601 {
1602 PCMachineState *pcms = PC_MACHINE(obj);
1603 uint64_t value;
1604
1605 if (!visit_type_size(v, name, &value, errp)) {
1606 return;
1607 }
1608 if (value > 4 * GiB) {
1609 error_setg(errp,
1610 "Machine option 'max-ram-below-4g=%"PRIu64
1611 "' expects size less than or equal to 4G", value);
1612 return;
1613 }
1614
1615 if (value < 1 * MiB) {
1616 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
1617 "BIOS may not work with less than 1MiB", value);
1618 }
1619
1620 pcms->max_ram_below_4g = value;
1621 }
1622
pc_machine_get_max_fw_size(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)1623 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v,
1624 const char *name, void *opaque,
1625 Error **errp)
1626 {
1627 PCMachineState *pcms = PC_MACHINE(obj);
1628 uint64_t value = pcms->max_fw_size;
1629
1630 visit_type_size(v, name, &value, errp);
1631 }
1632
pc_machine_set_max_fw_size(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)1633 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v,
1634 const char *name, void *opaque,
1635 Error **errp)
1636 {
1637 PCMachineState *pcms = PC_MACHINE(obj);
1638 uint64_t value;
1639
1640 if (!visit_type_size(v, name, &value, errp)) {
1641 return;
1642 }
1643
1644 /*
1645 * We don't have a theoretically justifiable exact lower bound on the base
1646 * address of any flash mapping. In practice, the IO-APIC MMIO range is
1647 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free
1648 * only 18MiB-4KiB below 4GiB. For now, restrict the cumulative mapping to
1649 * 16MiB in size.
1650 */
1651 if (value > 16 * MiB) {
1652 error_setg(errp,
1653 "User specified max allowed firmware size %" PRIu64 " is "
1654 "greater than 16MiB. If combined firmware size exceeds "
1655 "16MiB the system may not boot, or experience intermittent"
1656 "stability issues.",
1657 value);
1658 return;
1659 }
1660
1661 pcms->max_fw_size = value;
1662 }
1663
1664
pc_machine_initfn(Object * obj)1665 static void pc_machine_initfn(Object *obj)
1666 {
1667 PCMachineState *pcms = PC_MACHINE(obj);
1668 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1669
1670 #ifdef CONFIG_VMPORT
1671 pcms->vmport = ON_OFF_AUTO_AUTO;
1672 #else
1673 pcms->vmport = ON_OFF_AUTO_OFF;
1674 #endif /* CONFIG_VMPORT */
1675 pcms->max_ram_below_4g = 0; /* use default */
1676 pcms->smbios_entry_point_type = pcmc->default_smbios_ep_type;
1677 pcms->south_bridge = pcmc->default_south_bridge;
1678
1679 /* acpi build is enabled by default if machine supports it */
1680 pcms->acpi_build_enabled = pcmc->has_acpi_build;
1681 pcms->smbus_enabled = true;
1682 pcms->sata_enabled = true;
1683 pcms->i8042_enabled = true;
1684 pcms->max_fw_size = 8 * MiB;
1685 #if defined(CONFIG_HPET)
1686 pcms->hpet_enabled = true;
1687 #endif
1688 pcms->fd_bootchk = true;
1689 pcms->default_bus_bypass_iommu = false;
1690
1691 pc_system_flash_create(pcms);
1692 pcms->pcspk = isa_new(TYPE_PC_SPEAKER);
1693 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev",
1694 OBJECT(pcms->pcspk), "audiodev");
1695 if (pcmc->pci_enabled) {
1696 cxl_machine_init(obj, &pcms->cxl_devices_state);
1697 }
1698 }
1699
pc_machine_reset(MachineState * machine,ResetType type)1700 static void pc_machine_reset(MachineState *machine, ResetType type)
1701 {
1702 CPUState *cs;
1703 X86CPU *cpu;
1704
1705 qemu_devices_reset(type);
1706
1707 /* Reset APIC after devices have been reset to cancel
1708 * any changes that qemu_devices_reset() might have done.
1709 */
1710 CPU_FOREACH(cs) {
1711 cpu = X86_CPU(cs);
1712
1713 x86_cpu_after_reset(cpu);
1714 }
1715 }
1716
pc_machine_wakeup(MachineState * machine)1717 static void pc_machine_wakeup(MachineState *machine)
1718 {
1719 cpu_synchronize_all_states();
1720 pc_machine_reset(machine, RESET_TYPE_WAKEUP);
1721 cpu_synchronize_all_post_reset();
1722 }
1723
pc_hotplug_allowed(MachineState * ms,DeviceState * dev,Error ** errp)1724 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp)
1725 {
1726 X86IOMMUState *iommu = x86_iommu_get_default();
1727 IntelIOMMUState *intel_iommu;
1728
1729 if (iommu &&
1730 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) &&
1731 object_dynamic_cast((Object *)dev, "vfio-pci")) {
1732 intel_iommu = INTEL_IOMMU_DEVICE(iommu);
1733 if (!intel_iommu->caching_mode) {
1734 error_setg(errp, "Device assignment is not allowed without "
1735 "enabling caching-mode=on for Intel IOMMU.");
1736 return false;
1737 }
1738 }
1739
1740 return true;
1741 }
1742
pc_machine_class_init(ObjectClass * oc,const void * data)1743 static void pc_machine_class_init(ObjectClass *oc, const void *data)
1744 {
1745 MachineClass *mc = MACHINE_CLASS(oc);
1746 X86MachineClass *x86mc = X86_MACHINE_CLASS(oc);
1747 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
1748 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1749
1750 pcmc->pci_enabled = true;
1751 pcmc->has_acpi_build = true;
1752 pcmc->smbios_defaults = true;
1753 pcmc->gigabyte_align = true;
1754 pcmc->has_reserved_memory = true;
1755 pcmc->enforce_amd_1tb_hole = true;
1756 pcmc->isa_bios_alias = true;
1757 pcmc->pvh_enabled = true;
1758 pcmc->kvmclock_create_always = true;
1759 x86mc->apic_xrupt_override = true;
1760 assert(!mc->get_hotplug_handler);
1761 mc->get_hotplug_handler = pc_get_hotplug_handler;
1762 mc->hotplug_allowed = pc_hotplug_allowed;
1763 mc->auto_enable_numa_with_memhp = true;
1764 mc->auto_enable_numa_with_memdev = true;
1765 mc->has_hotpluggable_cpus = true;
1766 mc->default_boot_order = "cad";
1767 mc->block_default_type = IF_IDE;
1768 mc->max_cpus = 255;
1769 mc->reset = pc_machine_reset;
1770 mc->wakeup = pc_machine_wakeup;
1771 hc->pre_plug = pc_machine_device_pre_plug_cb;
1772 hc->plug = pc_machine_device_plug_cb;
1773 hc->unplug_request = pc_machine_device_unplug_request_cb;
1774 hc->unplug = pc_machine_device_unplug_cb;
1775 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
1776 mc->nvdimm_supported = true;
1777 mc->smp_props.dies_supported = true;
1778 mc->smp_props.modules_supported = true;
1779 mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1D] = true;
1780 mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1I] = true;
1781 mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L2] = true;
1782 mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L3] = true;
1783 mc->default_ram_id = "pc.ram";
1784 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_AUTO;
1785
1786 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
1787 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g,
1788 NULL, NULL);
1789 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G,
1790 "Maximum ram below the 4G boundary (32bit boundary)");
1791
1792 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
1793 pc_machine_get_vmport, pc_machine_set_vmport,
1794 NULL, NULL);
1795 object_class_property_set_description(oc, PC_MACHINE_VMPORT,
1796 "Enable vmport (pc & q35)");
1797
1798 object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
1799 pc_machine_get_smbus, pc_machine_set_smbus);
1800 object_class_property_set_description(oc, PC_MACHINE_SMBUS,
1801 "Enable/disable system management bus");
1802
1803 object_class_property_add_bool(oc, PC_MACHINE_SATA,
1804 pc_machine_get_sata, pc_machine_set_sata);
1805 object_class_property_set_description(oc, PC_MACHINE_SATA,
1806 "Enable/disable Serial ATA bus");
1807
1808 object_class_property_add_bool(oc, "hpet",
1809 pc_machine_get_hpet, pc_machine_set_hpet);
1810 object_class_property_set_description(oc, "hpet",
1811 "Enable/disable high precision event timer emulation");
1812
1813 object_class_property_add_bool(oc, PC_MACHINE_I8042,
1814 pc_machine_get_i8042, pc_machine_set_i8042);
1815 object_class_property_set_description(oc, PC_MACHINE_I8042,
1816 "Enable/disable Intel 8042 PS/2 controller emulation");
1817
1818 object_class_property_add_bool(oc, "default-bus-bypass-iommu",
1819 pc_machine_get_default_bus_bypass_iommu,
1820 pc_machine_set_default_bus_bypass_iommu);
1821
1822 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size",
1823 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size,
1824 NULL, NULL);
1825 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE,
1826 "Maximum combined firmware size");
1827
1828 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str",
1829 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep,
1830 NULL, NULL);
1831 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP,
1832 "SMBIOS Entry Point type [32, 64]");
1833
1834 object_class_property_add_bool(oc, "fd-bootchk",
1835 pc_machine_get_fd_bootchk,
1836 pc_machine_set_fd_bootchk);
1837
1838 #if defined(CONFIG_IGVM)
1839 object_class_property_add_link(oc, "igvm-cfg",
1840 TYPE_IGVM_CFG,
1841 offsetof(X86MachineState, igvm),
1842 object_property_allow_set_link,
1843 OBJ_PROP_LINK_STRONG);
1844 object_class_property_set_description(oc, "igvm-cfg",
1845 "Set IGVM configuration");
1846 #endif
1847
1848
1849 }
1850
1851 static const TypeInfo pc_machine_info = {
1852 .name = TYPE_PC_MACHINE,
1853 .parent = TYPE_X86_MACHINE,
1854 .abstract = true,
1855 .instance_size = sizeof(PCMachineState),
1856 .instance_init = pc_machine_initfn,
1857 .class_size = sizeof(PCMachineClass),
1858 .class_init = pc_machine_class_init,
1859 .interfaces = (const InterfaceInfo[]) {
1860 { TYPE_HOTPLUG_HANDLER },
1861 { }
1862 },
1863 };
1864
pc_machine_register_types(void)1865 static void pc_machine_register_types(void)
1866 {
1867 type_register_static(&pc_machine_info);
1868 }
1869
1870 type_init(pc_machine_register_types)
1871