1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/module.h>
7 #include <linux/of.h>
8 #include <linux/platform_device.h>
9
10 #include "pinctrl-msm.h"
11
12 #define REG_SIZE 0x1000
13
14 #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
15 { \
16 .grp = PINCTRL_PINGROUP("gpio" #id, \
17 gpio##id##_pins, \
18 ARRAY_SIZE(gpio##id##_pins)), \
19 .funcs = (int[]){ \
20 msm_mux_gpio, /* gpio mode */ \
21 msm_mux_##f1, \
22 msm_mux_##f2, \
23 msm_mux_##f3, \
24 msm_mux_##f4, \
25 msm_mux_##f5, \
26 msm_mux_##f6, \
27 msm_mux_##f7, \
28 msm_mux_##f8, \
29 msm_mux_##f9 \
30 }, \
31 .nfuncs = 10, \
32 .ctl_reg = REG_SIZE * id, \
33 .io_reg = 0x4 + REG_SIZE * id, \
34 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
35 .intr_status_reg = 0xc + REG_SIZE * id, \
36 .intr_target_reg = 0x8 + REG_SIZE * id, \
37 .mux_bit = 2, \
38 .pull_bit = 0, \
39 .drv_bit = 6, \
40 .oe_bit = 9, \
41 .in_bit = 0, \
42 .out_bit = 1, \
43 .intr_enable_bit = 0, \
44 .intr_status_bit = 0, \
45 .intr_target_bit = 5, \
46 .intr_target_kpss_val = 3, \
47 .intr_raw_status_bit = 4, \
48 .intr_polarity_bit = 1, \
49 .intr_detection_bit = 2, \
50 .intr_detection_width = 2, \
51 }
52
53 #define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
54 { \
55 .grp = PINCTRL_PINGROUP(#pg_name, \
56 pg_name##_pins, \
57 ARRAY_SIZE(pg_name##_pins)), \
58 .ctl_reg = ctl, \
59 .io_reg = 0, \
60 .intr_cfg_reg = 0, \
61 .intr_status_reg = 0, \
62 .intr_target_reg = 0, \
63 .mux_bit = -1, \
64 .pull_bit = pull, \
65 .drv_bit = drv, \
66 .oe_bit = -1, \
67 .in_bit = -1, \
68 .out_bit = -1, \
69 .intr_enable_bit = -1, \
70 .intr_status_bit = -1, \
71 .intr_target_bit = -1, \
72 .intr_raw_status_bit = -1, \
73 .intr_polarity_bit = -1, \
74 .intr_detection_bit = -1, \
75 .intr_detection_width = -1, \
76 }
77
78 #define UFS_RESET(pg_name, offset) \
79 { \
80 .grp = PINCTRL_PINGROUP(#pg_name, \
81 pg_name##_pins, \
82 ARRAY_SIZE(pg_name##_pins)), \
83 .ctl_reg = offset, \
84 .io_reg = offset + 0x4, \
85 .intr_cfg_reg = 0, \
86 .intr_status_reg = 0, \
87 .intr_target_reg = 0, \
88 .mux_bit = -1, \
89 .pull_bit = 3, \
90 .drv_bit = 0, \
91 .oe_bit = -1, \
92 .in_bit = -1, \
93 .out_bit = 0, \
94 .intr_enable_bit = -1, \
95 .intr_status_bit = -1, \
96 .intr_target_bit = -1, \
97 .intr_raw_status_bit = -1, \
98 .intr_polarity_bit = -1, \
99 .intr_detection_bit = -1, \
100 .intr_detection_width = -1, \
101 }
102 static const struct pinctrl_pin_desc qcm2290_pins[] = {
103 PINCTRL_PIN(0, "GPIO_0"),
104 PINCTRL_PIN(1, "GPIO_1"),
105 PINCTRL_PIN(2, "GPIO_2"),
106 PINCTRL_PIN(3, "GPIO_3"),
107 PINCTRL_PIN(4, "GPIO_4"),
108 PINCTRL_PIN(5, "GPIO_5"),
109 PINCTRL_PIN(6, "GPIO_6"),
110 PINCTRL_PIN(7, "GPIO_7"),
111 PINCTRL_PIN(8, "GPIO_8"),
112 PINCTRL_PIN(9, "GPIO_9"),
113 PINCTRL_PIN(10, "GPIO_10"),
114 PINCTRL_PIN(11, "GPIO_11"),
115 PINCTRL_PIN(12, "GPIO_12"),
116 PINCTRL_PIN(13, "GPIO_13"),
117 PINCTRL_PIN(14, "GPIO_14"),
118 PINCTRL_PIN(15, "GPIO_15"),
119 PINCTRL_PIN(16, "GPIO_16"),
120 PINCTRL_PIN(17, "GPIO_17"),
121 PINCTRL_PIN(18, "GPIO_18"),
122 PINCTRL_PIN(19, "GPIO_19"),
123 PINCTRL_PIN(20, "GPIO_20"),
124 PINCTRL_PIN(21, "GPIO_21"),
125 PINCTRL_PIN(22, "GPIO_22"),
126 PINCTRL_PIN(23, "GPIO_23"),
127 PINCTRL_PIN(24, "GPIO_24"),
128 PINCTRL_PIN(25, "GPIO_25"),
129 PINCTRL_PIN(26, "GPIO_26"),
130 PINCTRL_PIN(27, "GPIO_27"),
131 PINCTRL_PIN(28, "GPIO_28"),
132 PINCTRL_PIN(29, "GPIO_29"),
133 PINCTRL_PIN(30, "GPIO_30"),
134 PINCTRL_PIN(31, "GPIO_31"),
135 PINCTRL_PIN(32, "GPIO_32"),
136 PINCTRL_PIN(33, "GPIO_33"),
137 PINCTRL_PIN(34, "GPIO_34"),
138 PINCTRL_PIN(35, "GPIO_35"),
139 PINCTRL_PIN(36, "GPIO_36"),
140 PINCTRL_PIN(37, "GPIO_37"),
141 PINCTRL_PIN(38, "GPIO_38"),
142 PINCTRL_PIN(39, "GPIO_39"),
143 PINCTRL_PIN(40, "GPIO_40"),
144 PINCTRL_PIN(41, "GPIO_41"),
145 PINCTRL_PIN(42, "GPIO_42"),
146 PINCTRL_PIN(43, "GPIO_43"),
147 PINCTRL_PIN(44, "GPIO_44"),
148 PINCTRL_PIN(45, "GPIO_45"),
149 PINCTRL_PIN(46, "GPIO_46"),
150 PINCTRL_PIN(47, "GPIO_47"),
151 PINCTRL_PIN(48, "GPIO_48"),
152 PINCTRL_PIN(49, "GPIO_49"),
153 PINCTRL_PIN(50, "GPIO_50"),
154 PINCTRL_PIN(51, "GPIO_51"),
155 PINCTRL_PIN(52, "GPIO_52"),
156 PINCTRL_PIN(53, "GPIO_53"),
157 PINCTRL_PIN(54, "GPIO_54"),
158 PINCTRL_PIN(55, "GPIO_55"),
159 PINCTRL_PIN(56, "GPIO_56"),
160 PINCTRL_PIN(57, "GPIO_57"),
161 PINCTRL_PIN(58, "GPIO_58"),
162 PINCTRL_PIN(59, "GPIO_59"),
163 PINCTRL_PIN(60, "GPIO_60"),
164 PINCTRL_PIN(61, "GPIO_61"),
165 PINCTRL_PIN(62, "GPIO_62"),
166 PINCTRL_PIN(63, "GPIO_63"),
167 PINCTRL_PIN(64, "GPIO_64"),
168 PINCTRL_PIN(69, "GPIO_69"),
169 PINCTRL_PIN(70, "GPIO_70"),
170 PINCTRL_PIN(71, "GPIO_71"),
171 PINCTRL_PIN(72, "GPIO_72"),
172 PINCTRL_PIN(73, "GPIO_73"),
173 PINCTRL_PIN(74, "GPIO_74"),
174 PINCTRL_PIN(75, "GPIO_75"),
175 PINCTRL_PIN(76, "GPIO_76"),
176 PINCTRL_PIN(77, "GPIO_77"),
177 PINCTRL_PIN(78, "GPIO_78"),
178 PINCTRL_PIN(79, "GPIO_79"),
179 PINCTRL_PIN(80, "GPIO_80"),
180 PINCTRL_PIN(81, "GPIO_81"),
181 PINCTRL_PIN(82, "GPIO_82"),
182 PINCTRL_PIN(86, "GPIO_86"),
183 PINCTRL_PIN(87, "GPIO_87"),
184 PINCTRL_PIN(88, "GPIO_88"),
185 PINCTRL_PIN(89, "GPIO_89"),
186 PINCTRL_PIN(90, "GPIO_90"),
187 PINCTRL_PIN(91, "GPIO_91"),
188 PINCTRL_PIN(94, "GPIO_94"),
189 PINCTRL_PIN(95, "GPIO_95"),
190 PINCTRL_PIN(96, "GPIO_96"),
191 PINCTRL_PIN(97, "GPIO_97"),
192 PINCTRL_PIN(98, "GPIO_98"),
193 PINCTRL_PIN(99, "GPIO_99"),
194 PINCTRL_PIN(100, "GPIO_100"),
195 PINCTRL_PIN(101, "GPIO_101"),
196 PINCTRL_PIN(102, "GPIO_102"),
197 PINCTRL_PIN(103, "GPIO_103"),
198 PINCTRL_PIN(104, "GPIO_104"),
199 PINCTRL_PIN(105, "GPIO_105"),
200 PINCTRL_PIN(106, "GPIO_106"),
201 PINCTRL_PIN(107, "GPIO_107"),
202 PINCTRL_PIN(108, "GPIO_108"),
203 PINCTRL_PIN(109, "GPIO_109"),
204 PINCTRL_PIN(110, "GPIO_110"),
205 PINCTRL_PIN(111, "GPIO_111"),
206 PINCTRL_PIN(112, "GPIO_112"),
207 PINCTRL_PIN(113, "GPIO_113"),
208 PINCTRL_PIN(114, "GPIO_114"),
209 PINCTRL_PIN(115, "GPIO_115"),
210 PINCTRL_PIN(116, "GPIO_116"),
211 PINCTRL_PIN(117, "GPIO_117"),
212 PINCTRL_PIN(118, "GPIO_118"),
213 PINCTRL_PIN(119, "GPIO_119"),
214 PINCTRL_PIN(120, "GPIO_120"),
215 PINCTRL_PIN(121, "GPIO_121"),
216 PINCTRL_PIN(122, "GPIO_122"),
217 PINCTRL_PIN(123, "GPIO_123"),
218 PINCTRL_PIN(124, "GPIO_124"),
219 PINCTRL_PIN(125, "GPIO_125"),
220 PINCTRL_PIN(126, "GPIO_126"),
221 PINCTRL_PIN(127, "SDC1_RCLK"),
222 PINCTRL_PIN(128, "SDC1_CLK"),
223 PINCTRL_PIN(129, "SDC1_CMD"),
224 PINCTRL_PIN(130, "SDC1_DATA"),
225 PINCTRL_PIN(131, "SDC2_CLK"),
226 PINCTRL_PIN(132, "SDC2_CMD"),
227 PINCTRL_PIN(133, "SDC2_DATA"),
228 };
229
230 #define DECLARE_MSM_GPIO_PINS(pin) \
231 static const unsigned int gpio##pin##_pins[] = { pin }
232 DECLARE_MSM_GPIO_PINS(0);
233 DECLARE_MSM_GPIO_PINS(1);
234 DECLARE_MSM_GPIO_PINS(2);
235 DECLARE_MSM_GPIO_PINS(3);
236 DECLARE_MSM_GPIO_PINS(4);
237 DECLARE_MSM_GPIO_PINS(5);
238 DECLARE_MSM_GPIO_PINS(6);
239 DECLARE_MSM_GPIO_PINS(7);
240 DECLARE_MSM_GPIO_PINS(8);
241 DECLARE_MSM_GPIO_PINS(9);
242 DECLARE_MSM_GPIO_PINS(10);
243 DECLARE_MSM_GPIO_PINS(11);
244 DECLARE_MSM_GPIO_PINS(12);
245 DECLARE_MSM_GPIO_PINS(13);
246 DECLARE_MSM_GPIO_PINS(14);
247 DECLARE_MSM_GPIO_PINS(15);
248 DECLARE_MSM_GPIO_PINS(16);
249 DECLARE_MSM_GPIO_PINS(17);
250 DECLARE_MSM_GPIO_PINS(18);
251 DECLARE_MSM_GPIO_PINS(19);
252 DECLARE_MSM_GPIO_PINS(20);
253 DECLARE_MSM_GPIO_PINS(21);
254 DECLARE_MSM_GPIO_PINS(22);
255 DECLARE_MSM_GPIO_PINS(23);
256 DECLARE_MSM_GPIO_PINS(24);
257 DECLARE_MSM_GPIO_PINS(25);
258 DECLARE_MSM_GPIO_PINS(26);
259 DECLARE_MSM_GPIO_PINS(27);
260 DECLARE_MSM_GPIO_PINS(28);
261 DECLARE_MSM_GPIO_PINS(29);
262 DECLARE_MSM_GPIO_PINS(30);
263 DECLARE_MSM_GPIO_PINS(31);
264 DECLARE_MSM_GPIO_PINS(32);
265 DECLARE_MSM_GPIO_PINS(33);
266 DECLARE_MSM_GPIO_PINS(34);
267 DECLARE_MSM_GPIO_PINS(35);
268 DECLARE_MSM_GPIO_PINS(36);
269 DECLARE_MSM_GPIO_PINS(37);
270 DECLARE_MSM_GPIO_PINS(38);
271 DECLARE_MSM_GPIO_PINS(39);
272 DECLARE_MSM_GPIO_PINS(40);
273 DECLARE_MSM_GPIO_PINS(41);
274 DECLARE_MSM_GPIO_PINS(42);
275 DECLARE_MSM_GPIO_PINS(43);
276 DECLARE_MSM_GPIO_PINS(44);
277 DECLARE_MSM_GPIO_PINS(45);
278 DECLARE_MSM_GPIO_PINS(46);
279 DECLARE_MSM_GPIO_PINS(47);
280 DECLARE_MSM_GPIO_PINS(48);
281 DECLARE_MSM_GPIO_PINS(49);
282 DECLARE_MSM_GPIO_PINS(50);
283 DECLARE_MSM_GPIO_PINS(51);
284 DECLARE_MSM_GPIO_PINS(52);
285 DECLARE_MSM_GPIO_PINS(53);
286 DECLARE_MSM_GPIO_PINS(54);
287 DECLARE_MSM_GPIO_PINS(55);
288 DECLARE_MSM_GPIO_PINS(56);
289 DECLARE_MSM_GPIO_PINS(57);
290 DECLARE_MSM_GPIO_PINS(58);
291 DECLARE_MSM_GPIO_PINS(59);
292 DECLARE_MSM_GPIO_PINS(60);
293 DECLARE_MSM_GPIO_PINS(61);
294 DECLARE_MSM_GPIO_PINS(62);
295 DECLARE_MSM_GPIO_PINS(63);
296 DECLARE_MSM_GPIO_PINS(64);
297 DECLARE_MSM_GPIO_PINS(65);
298 DECLARE_MSM_GPIO_PINS(66);
299 DECLARE_MSM_GPIO_PINS(67);
300 DECLARE_MSM_GPIO_PINS(68);
301 DECLARE_MSM_GPIO_PINS(69);
302 DECLARE_MSM_GPIO_PINS(70);
303 DECLARE_MSM_GPIO_PINS(71);
304 DECLARE_MSM_GPIO_PINS(72);
305 DECLARE_MSM_GPIO_PINS(73);
306 DECLARE_MSM_GPIO_PINS(74);
307 DECLARE_MSM_GPIO_PINS(75);
308 DECLARE_MSM_GPIO_PINS(76);
309 DECLARE_MSM_GPIO_PINS(77);
310 DECLARE_MSM_GPIO_PINS(78);
311 DECLARE_MSM_GPIO_PINS(79);
312 DECLARE_MSM_GPIO_PINS(80);
313 DECLARE_MSM_GPIO_PINS(81);
314 DECLARE_MSM_GPIO_PINS(82);
315 DECLARE_MSM_GPIO_PINS(83);
316 DECLARE_MSM_GPIO_PINS(84);
317 DECLARE_MSM_GPIO_PINS(85);
318 DECLARE_MSM_GPIO_PINS(86);
319 DECLARE_MSM_GPIO_PINS(87);
320 DECLARE_MSM_GPIO_PINS(88);
321 DECLARE_MSM_GPIO_PINS(89);
322 DECLARE_MSM_GPIO_PINS(90);
323 DECLARE_MSM_GPIO_PINS(91);
324 DECLARE_MSM_GPIO_PINS(92);
325 DECLARE_MSM_GPIO_PINS(93);
326 DECLARE_MSM_GPIO_PINS(94);
327 DECLARE_MSM_GPIO_PINS(95);
328 DECLARE_MSM_GPIO_PINS(96);
329 DECLARE_MSM_GPIO_PINS(97);
330 DECLARE_MSM_GPIO_PINS(98);
331 DECLARE_MSM_GPIO_PINS(99);
332 DECLARE_MSM_GPIO_PINS(100);
333 DECLARE_MSM_GPIO_PINS(101);
334 DECLARE_MSM_GPIO_PINS(102);
335 DECLARE_MSM_GPIO_PINS(103);
336 DECLARE_MSM_GPIO_PINS(104);
337 DECLARE_MSM_GPIO_PINS(105);
338 DECLARE_MSM_GPIO_PINS(106);
339 DECLARE_MSM_GPIO_PINS(107);
340 DECLARE_MSM_GPIO_PINS(108);
341 DECLARE_MSM_GPIO_PINS(109);
342 DECLARE_MSM_GPIO_PINS(110);
343 DECLARE_MSM_GPIO_PINS(111);
344 DECLARE_MSM_GPIO_PINS(112);
345 DECLARE_MSM_GPIO_PINS(113);
346 DECLARE_MSM_GPIO_PINS(114);
347 DECLARE_MSM_GPIO_PINS(115);
348 DECLARE_MSM_GPIO_PINS(116);
349 DECLARE_MSM_GPIO_PINS(117);
350 DECLARE_MSM_GPIO_PINS(118);
351 DECLARE_MSM_GPIO_PINS(119);
352 DECLARE_MSM_GPIO_PINS(120);
353 DECLARE_MSM_GPIO_PINS(121);
354 DECLARE_MSM_GPIO_PINS(122);
355 DECLARE_MSM_GPIO_PINS(123);
356 DECLARE_MSM_GPIO_PINS(124);
357 DECLARE_MSM_GPIO_PINS(125);
358 DECLARE_MSM_GPIO_PINS(126);
359
360 static const unsigned int sdc1_rclk_pins[] = { 127 };
361 static const unsigned int sdc1_clk_pins[] = { 128 };
362 static const unsigned int sdc1_cmd_pins[] = { 129 };
363 static const unsigned int sdc1_data_pins[] = { 130 };
364 static const unsigned int sdc2_clk_pins[] = { 131 };
365 static const unsigned int sdc2_cmd_pins[] = { 132 };
366 static const unsigned int sdc2_data_pins[] = { 133 };
367
368 enum qcm2290_functions {
369 msm_mux_adsp_ext,
370 msm_mux_agera_pll,
371 msm_mux_atest,
372 msm_mux_cam_mclk,
373 msm_mux_cci_async,
374 msm_mux_cci_i2c,
375 msm_mux_cci_timer0,
376 msm_mux_cci_timer1,
377 msm_mux_cci_timer2,
378 msm_mux_cci_timer3,
379 msm_mux_char_exec,
380 msm_mux_cri_trng,
381 msm_mux_cri_trng0,
382 msm_mux_cri_trng1,
383 msm_mux_dac_calib,
384 msm_mux_dbg_out,
385 msm_mux_ddr_bist,
386 msm_mux_ddr_pxi0,
387 msm_mux_ddr_pxi1,
388 msm_mux_ddr_pxi2,
389 msm_mux_ddr_pxi3,
390 msm_mux_gcc_gp1,
391 msm_mux_gcc_gp2,
392 msm_mux_gcc_gp3,
393 msm_mux_gpio,
394 msm_mux_gp_pdm0,
395 msm_mux_gp_pdm1,
396 msm_mux_gp_pdm2,
397 msm_mux_gsm0_tx,
398 msm_mux_gsm1_tx,
399 msm_mux_jitter_bist,
400 msm_mux_mdp_vsync,
401 msm_mux_mdp_vsync_out_0,
402 msm_mux_mdp_vsync_out_1,
403 msm_mux_mpm_pwr,
404 msm_mux_mss_lte,
405 msm_mux_m_voc,
406 msm_mux_nav_gpio,
407 msm_mux_pa_indicator,
408 msm_mux_pbs0,
409 msm_mux_pbs1,
410 msm_mux_pbs2,
411 msm_mux_pbs3,
412 msm_mux_pbs4,
413 msm_mux_pbs5,
414 msm_mux_pbs6,
415 msm_mux_pbs7,
416 msm_mux_pbs8,
417 msm_mux_pbs9,
418 msm_mux_pbs10,
419 msm_mux_pbs11,
420 msm_mux_pbs12,
421 msm_mux_pbs13,
422 msm_mux_pbs14,
423 msm_mux_pbs15,
424 msm_mux_pbs_out,
425 msm_mux_phase_flag,
426 msm_mux_pll_bist,
427 msm_mux_pll_bypassnl,
428 msm_mux_pll_reset,
429 msm_mux_prng_rosc,
430 msm_mux_pwm_0,
431 msm_mux_pwm_1,
432 msm_mux_pwm_2,
433 msm_mux_pwm_3,
434 msm_mux_pwm_4,
435 msm_mux_pwm_5,
436 msm_mux_pwm_6,
437 msm_mux_pwm_7,
438 msm_mux_pwm_8,
439 msm_mux_pwm_9,
440 msm_mux_qdss_cti,
441 msm_mux_qdss_gpio,
442 msm_mux_qup0,
443 msm_mux_qup1,
444 msm_mux_qup2,
445 msm_mux_qup3,
446 msm_mux_qup4,
447 msm_mux_qup5,
448 msm_mux_sdc1_tb,
449 msm_mux_sdc2_tb,
450 msm_mux_sd_write,
451 msm_mux_ssbi_wtr1,
452 msm_mux_tgu_ch0,
453 msm_mux_tgu_ch1,
454 msm_mux_tgu_ch2,
455 msm_mux_tgu_ch3,
456 msm_mux_tsense_pwm,
457 msm_mux_uim1_clk,
458 msm_mux_uim1_data,
459 msm_mux_uim1_present,
460 msm_mux_uim1_reset,
461 msm_mux_uim2_clk,
462 msm_mux_uim2_data,
463 msm_mux_uim2_present,
464 msm_mux_uim2_reset,
465 msm_mux_usb_phy,
466 msm_mux_vfr_1,
467 msm_mux_vsense_trigger,
468 msm_mux_wlan1_adc0,
469 msm_mux_wlan1_adc1,
470 msm_mux__,
471 };
472
473 static const char * const qup0_groups[] = {
474 "gpio0", "gpio1", "gpio2", "gpio3", "gpio82", "gpio86",
475 };
476 static const char * const gpio_groups[] = {
477 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
478 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
479 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
480 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
481 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
482 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
483 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
484 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
485 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
486 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
487 "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
488 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
489 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
490 "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
491 "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
492 "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
493 "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
494 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
495 "gpio123", "gpio124", "gpio125", "gpio126",
496 };
497 static const char * const ddr_bist_groups[] = {
498 "gpio0", "gpio1", "gpio2", "gpio3",
499 };
500 static const char * const phase_flag_groups[] = {
501 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6",
502 "gpio14", "gpio15", "gpio16", "gpio17", "gpio22", "gpio23", "gpio24",
503 "gpio25", "gpio26", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33",
504 "gpio35", "gpio36", "gpio43", "gpio44", "gpio45", "gpio63", "gpio64",
505 "gpio102", "gpio103", "gpio104", "gpio105",
506 };
507 static const char * const qdss_gpio_groups[] = {
508 "gpio0", "gpio1", "gpio2", "gpio3", "gpio8", "gpio9", "gpio10",
509 "gpio11", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19",
510 "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26",
511 "gpio47", "gpio48", "gpio69", "gpio70", "gpio87", "gpio90", "gpio91",
512 "gpio94", "gpio95", "gpio104", "gpio105", "gpio106", "gpio107",
513 "gpio109", "gpio110",
514 };
515 static const char * const atest_groups[] = {
516 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6",
517 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio29", "gpio30",
518 "gpio31", "gpio32", "gpio33", "gpio86", "gpio89", "gpio100", "gpio101",
519 };
520 static const char * const mpm_pwr_groups[] = {
521 "gpio1",
522 };
523 static const char * const m_voc_groups[] = {
524 "gpio0",
525 };
526 static const char * const dac_calib_groups[] = {
527 "gpio2",
528 "gpio3",
529 "gpio4",
530 "gpio5",
531 "gpio6",
532 "gpio14",
533 "gpio15",
534 "gpio16",
535 "gpio17",
536 "gpio22",
537 "gpio23",
538 "gpio24",
539 "gpio25",
540 "gpio26",
541 "gpio29",
542 "gpio30",
543 "gpio31",
544 "gpio32",
545 "gpio33",
546 "gpio80",
547 "gpio81",
548 "gpio82",
549 "gpio102",
550 "gpio103",
551 "gpio104",
552 "gpio105",
553 };
554 static const char * const qup1_groups[] = {
555 "gpio4", "gpio5", "gpio69", "gpio70",
556 };
557 static const char * const cri_trng0_groups[] = {
558 "gpio4",
559 };
560 static const char * const cri_trng1_groups[] = {
561 "gpio5",
562 };
563 static const char * const qup2_groups[] = {
564 "gpio6", "gpio7", "gpio71", "gpio80",
565 };
566 static const char * const qup3_groups[] = {
567 "gpio8", "gpio9", "gpio10", "gpio11",
568 };
569 static const char * const pbs_out_groups[] = {
570 "gpio8", "gpio9", "gpio52",
571 };
572 static const char * const pll_bist_groups[] = {
573 "gpio8", "gpio9",
574 };
575 static const char * const tsense_pwm_groups[] = {
576 "gpio8",
577 };
578 static const char * const agera_pll_groups[] = {
579 "gpio10", "gpio11",
580 };
581 static const char * const pbs0_groups[] = {
582 "gpio10",
583 };
584 static const char * const pbs1_groups[] = {
585 "gpio11",
586 };
587 static const char * const qup4_groups[] = {
588 "gpio12", "gpio13", "gpio96", "gpio97",
589 };
590 static const char * const tgu_ch0_groups[] = {
591 "gpio12",
592 };
593 static const char * const tgu_ch1_groups[] = {
594 "gpio13",
595 };
596 static const char * const qup5_groups[] = {
597 "gpio14", "gpio15", "gpio16", "gpio17",
598 };
599 static const char * const tgu_ch2_groups[] = {
600 "gpio14",
601 };
602 static const char * const tgu_ch3_groups[] = {
603 "gpio15",
604 };
605 static const char * const sdc2_tb_groups[] = {
606 "gpio18",
607 };
608 static const char * const cri_trng_groups[] = {
609 "gpio18",
610 };
611 static const char * const pbs2_groups[] = {
612 "gpio18",
613 };
614 static const char * const pwm_0_groups[] = {
615 "gpio18",
616 };
617 static const char * const sdc1_tb_groups[] = {
618 "gpio19",
619 };
620 static const char * const pbs3_groups[] = {
621 "gpio19",
622 };
623 static const char * const cam_mclk_groups[] = {
624 "gpio20", "gpio21", "gpio27", "gpio28",
625 };
626 static const char * const pbs4_groups[] = {
627 "gpio20",
628 };
629 static const char * const adsp_ext_groups[] = {
630 "gpio21",
631 };
632 static const char * const pbs5_groups[] = {
633 "gpio21",
634 };
635 static const char * const cci_i2c_groups[] = {
636 "gpio22", "gpio23", "gpio29", "gpio30",
637 };
638 static const char * const prng_rosc_groups[] = {
639 "gpio22", "gpio23",
640 };
641 static const char * const pbs6_groups[] = {
642 "gpio22",
643 };
644 static const char * const pbs7_groups[] = {
645 "gpio23",
646 };
647 static const char * const cci_timer1_groups[] = {
648 "gpio24",
649 };
650 static const char * const gcc_gp1_groups[] = {
651 "gpio24", "gpio86",
652 };
653 static const char * const pbs8_groups[] = {
654 "gpio24",
655 };
656 static const char * const cci_async_groups[] = {
657 "gpio25",
658 };
659 static const char * const cci_timer0_groups[] = {
660 "gpio25",
661 };
662 static const char * const pbs9_groups[] = {
663 "gpio25",
664 };
665 static const char * const pbs10_groups[] = {
666 "gpio26",
667 };
668 static const char * const vsense_trigger_groups[] = {
669 "gpio26",
670 };
671 static const char * const qdss_cti_groups[] = {
672 "gpio27", "gpio28", "gpio72", "gpio73", "gpio96", "gpio97",
673 };
674 static const char * const cci_timer2_groups[] = {
675 "gpio28",
676 };
677 static const char * const pwm_1_groups[] = {
678 "gpio28",
679 };
680 static const char * const gp_pdm0_groups[] = {
681 "gpio31", "gpio95",
682 };
683 static const char * const cci_timer3_groups[] = {
684 "gpio32",
685 };
686 static const char * const gp_pdm1_groups[] = {
687 "gpio32", "gpio96",
688 };
689 static const char * const gp_pdm2_groups[] = {
690 "gpio33", "gpio97",
691 };
692 static const char * const char_exec_groups[] = {
693 "gpio37", "gpio38",
694 };
695 static const char * const nav_gpio_groups[] = {
696 "gpio42", "gpio47", "gpio52", "gpio95", "gpio96", "gpio97", "gpio106",
697 "gpio107", "gpio108",
698 };
699 static const char * const pbs14_groups[] = {
700 "gpio47",
701 };
702 static const char * const vfr_1_groups[] = {
703 "gpio48",
704 };
705 static const char * const pbs15_groups[] = {
706 "gpio48",
707 };
708 static const char * const pa_indicator_groups[] = {
709 "gpio49",
710 };
711 static const char * const pwm_2_groups[] = {
712 "gpio51",
713 };
714 static const char * const gsm1_tx_groups[] = {
715 "gpio53",
716 };
717 static const char * const ssbi_wtr1_groups[] = {
718 "gpio59", "gpio60",
719 };
720 static const char * const pll_bypassnl_groups[] = {
721 "gpio62",
722 };
723 static const char * const pll_reset_groups[] = {
724 "gpio63",
725 };
726 static const char * const ddr_pxi0_groups[] = {
727 "gpio63", "gpio64",
728 };
729 static const char * const gsm0_tx_groups[] = {
730 "gpio64",
731 };
732 static const char * const gcc_gp2_groups[] = {
733 "gpio69", "gpio107",
734 };
735 static const char * const ddr_pxi1_groups[] = {
736 "gpio69", "gpio70",
737 };
738 static const char * const gcc_gp3_groups[] = {
739 "gpio70", "gpio106",
740 };
741 static const char * const dbg_out_groups[] = {
742 "gpio71",
743 };
744 static const char * const uim2_data_groups[] = {
745 "gpio72",
746 };
747 static const char * const pwm_3_groups[] = {
748 "gpio72",
749 };
750 static const char * const uim2_clk_groups[] = {
751 "gpio73",
752 };
753 static const char * const uim2_reset_groups[] = {
754 "gpio74",
755 };
756 static const char * const pwm_4_groups[] = {
757 "gpio74",
758 };
759 static const char * const uim2_present_groups[] = {
760 "gpio75",
761 };
762 static const char * const pwm_5_groups[] = {
763 "gpio75",
764 };
765 static const char * const uim1_data_groups[] = {
766 "gpio76",
767 };
768 static const char * const uim1_clk_groups[] = {
769 "gpio77",
770 };
771 static const char * const uim1_reset_groups[] = {
772 "gpio78",
773 };
774 static const char * const uim1_present_groups[] = {
775 "gpio79",
776 };
777 static const char * const mdp_vsync_groups[] = {
778 "gpio81", "gpio96", "gpio97",
779 };
780 static const char * const mdp_vsync_out_0_groups[] = {
781 "gpio81",
782 };
783 static const char * const mdp_vsync_out_1_groups[] = {
784 "gpio81",
785 };
786 static const char * const pwm_6_groups[] = {
787 "gpio82",
788 };
789 static const char * const pbs11_groups[] = {
790 "gpio87",
791 };
792 static const char * const usb_phy_groups[] = {
793 "gpio89",
794 };
795 static const char * const pwm_7_groups[] = {
796 "gpio89",
797 };
798 static const char * const mss_lte_groups[] = {
799 "gpio90", "gpio91",
800 };
801 static const char * const pbs12_groups[] = {
802 "gpio90",
803 };
804 static const char * const pbs13_groups[] = {
805 "gpio91",
806 };
807 static const char * const wlan1_adc0_groups[] = {
808 "gpio94",
809 };
810 static const char * const wlan1_adc1_groups[] = {
811 "gpio95",
812 };
813 static const char * const sd_write_groups[] = {
814 "gpio96",
815 };
816 static const char * const jitter_bist_groups[] = {
817 "gpio96", "gpio97",
818 };
819 static const char * const ddr_pxi2_groups[] = {
820 "gpio102", "gpio103",
821 };
822 static const char * const ddr_pxi3_groups[] = {
823 "gpio104", "gpio105",
824 };
825 static const char * const pwm_8_groups[] = {
826 "gpio104",
827 };
828 static const char * const pwm_9_groups[] = {
829 "gpio115",
830 };
831
832 static const struct pinfunction qcm2290_functions[] = {
833 MSM_PIN_FUNCTION(adsp_ext),
834 MSM_PIN_FUNCTION(agera_pll),
835 MSM_PIN_FUNCTION(atest),
836 MSM_PIN_FUNCTION(cam_mclk),
837 MSM_PIN_FUNCTION(cci_async),
838 MSM_PIN_FUNCTION(cci_i2c),
839 MSM_PIN_FUNCTION(cci_timer0),
840 MSM_PIN_FUNCTION(cci_timer1),
841 MSM_PIN_FUNCTION(cci_timer2),
842 MSM_PIN_FUNCTION(cci_timer3),
843 MSM_PIN_FUNCTION(char_exec),
844 MSM_PIN_FUNCTION(cri_trng),
845 MSM_PIN_FUNCTION(cri_trng0),
846 MSM_PIN_FUNCTION(cri_trng1),
847 MSM_PIN_FUNCTION(dac_calib),
848 MSM_PIN_FUNCTION(dbg_out),
849 MSM_PIN_FUNCTION(ddr_bist),
850 MSM_PIN_FUNCTION(ddr_pxi0),
851 MSM_PIN_FUNCTION(ddr_pxi1),
852 MSM_PIN_FUNCTION(ddr_pxi2),
853 MSM_PIN_FUNCTION(ddr_pxi3),
854 MSM_PIN_FUNCTION(gcc_gp1),
855 MSM_PIN_FUNCTION(gcc_gp2),
856 MSM_PIN_FUNCTION(gcc_gp3),
857 MSM_PIN_FUNCTION(gpio),
858 MSM_PIN_FUNCTION(gp_pdm0),
859 MSM_PIN_FUNCTION(gp_pdm1),
860 MSM_PIN_FUNCTION(gp_pdm2),
861 MSM_PIN_FUNCTION(gsm0_tx),
862 MSM_PIN_FUNCTION(gsm1_tx),
863 MSM_PIN_FUNCTION(jitter_bist),
864 MSM_PIN_FUNCTION(mdp_vsync),
865 MSM_PIN_FUNCTION(mdp_vsync_out_0),
866 MSM_PIN_FUNCTION(mdp_vsync_out_1),
867 MSM_PIN_FUNCTION(mpm_pwr),
868 MSM_PIN_FUNCTION(mss_lte),
869 MSM_PIN_FUNCTION(m_voc),
870 MSM_PIN_FUNCTION(nav_gpio),
871 MSM_PIN_FUNCTION(pa_indicator),
872 MSM_PIN_FUNCTION(pbs0),
873 MSM_PIN_FUNCTION(pbs1),
874 MSM_PIN_FUNCTION(pbs2),
875 MSM_PIN_FUNCTION(pbs3),
876 MSM_PIN_FUNCTION(pbs4),
877 MSM_PIN_FUNCTION(pbs5),
878 MSM_PIN_FUNCTION(pbs6),
879 MSM_PIN_FUNCTION(pbs7),
880 MSM_PIN_FUNCTION(pbs8),
881 MSM_PIN_FUNCTION(pbs9),
882 MSM_PIN_FUNCTION(pbs10),
883 MSM_PIN_FUNCTION(pbs11),
884 MSM_PIN_FUNCTION(pbs12),
885 MSM_PIN_FUNCTION(pbs13),
886 MSM_PIN_FUNCTION(pbs14),
887 MSM_PIN_FUNCTION(pbs15),
888 MSM_PIN_FUNCTION(pbs_out),
889 MSM_PIN_FUNCTION(phase_flag),
890 MSM_PIN_FUNCTION(pll_bist),
891 MSM_PIN_FUNCTION(pll_bypassnl),
892 MSM_PIN_FUNCTION(pll_reset),
893 MSM_PIN_FUNCTION(prng_rosc),
894 MSM_PIN_FUNCTION(pwm_0),
895 MSM_PIN_FUNCTION(pwm_1),
896 MSM_PIN_FUNCTION(pwm_2),
897 MSM_PIN_FUNCTION(pwm_3),
898 MSM_PIN_FUNCTION(pwm_4),
899 MSM_PIN_FUNCTION(pwm_5),
900 MSM_PIN_FUNCTION(pwm_6),
901 MSM_PIN_FUNCTION(pwm_7),
902 MSM_PIN_FUNCTION(pwm_8),
903 MSM_PIN_FUNCTION(pwm_9),
904 MSM_PIN_FUNCTION(qdss_cti),
905 MSM_PIN_FUNCTION(qdss_gpio),
906 MSM_PIN_FUNCTION(qup0),
907 MSM_PIN_FUNCTION(qup1),
908 MSM_PIN_FUNCTION(qup2),
909 MSM_PIN_FUNCTION(qup3),
910 MSM_PIN_FUNCTION(qup4),
911 MSM_PIN_FUNCTION(qup5),
912 MSM_PIN_FUNCTION(sdc1_tb),
913 MSM_PIN_FUNCTION(sdc2_tb),
914 MSM_PIN_FUNCTION(sd_write),
915 MSM_PIN_FUNCTION(ssbi_wtr1),
916 MSM_PIN_FUNCTION(tgu_ch0),
917 MSM_PIN_FUNCTION(tgu_ch1),
918 MSM_PIN_FUNCTION(tgu_ch2),
919 MSM_PIN_FUNCTION(tgu_ch3),
920 MSM_PIN_FUNCTION(tsense_pwm),
921 MSM_PIN_FUNCTION(uim1_clk),
922 MSM_PIN_FUNCTION(uim1_data),
923 MSM_PIN_FUNCTION(uim1_present),
924 MSM_PIN_FUNCTION(uim1_reset),
925 MSM_PIN_FUNCTION(uim2_clk),
926 MSM_PIN_FUNCTION(uim2_data),
927 MSM_PIN_FUNCTION(uim2_present),
928 MSM_PIN_FUNCTION(uim2_reset),
929 MSM_PIN_FUNCTION(usb_phy),
930 MSM_PIN_FUNCTION(vfr_1),
931 MSM_PIN_FUNCTION(vsense_trigger),
932 MSM_PIN_FUNCTION(wlan1_adc0),
933 MSM_PIN_FUNCTION(wlan1_adc1),
934 };
935
936 /* Every pin is maintained as a single group, and missing or non-existing pin
937 * would be maintained as dummy group to synchronize pin group index with
938 * pin descriptor registered with pinctrl core.
939 * Clients would not be able to request these dummy pin groups.
940 */
941 static const struct msm_pingroup qcm2290_groups[] = {
942 [0] = PINGROUP(0, qup0, m_voc, ddr_bist, _, phase_flag, qdss_gpio, atest, _, _),
943 [1] = PINGROUP(1, qup0, mpm_pwr, ddr_bist, _, phase_flag, qdss_gpio, atest, _, _),
944 [2] = PINGROUP(2, qup0, ddr_bist, _, phase_flag, qdss_gpio, dac_calib, atest, _, _),
945 [3] = PINGROUP(3, qup0, ddr_bist, _, phase_flag, qdss_gpio, dac_calib, atest, _, _),
946 [4] = PINGROUP(4, qup1, cri_trng0, _, phase_flag, dac_calib, atest, _, _, _),
947 [5] = PINGROUP(5, qup1, cri_trng1, _, phase_flag, dac_calib, atest, _, _, _),
948 [6] = PINGROUP(6, qup2, _, phase_flag, dac_calib, atest, _, _, _, _),
949 [7] = PINGROUP(7, qup2, _, _, _, _, _, _, _, _),
950 [8] = PINGROUP(8, qup3, pbs_out, pll_bist, _, qdss_gpio, _, tsense_pwm, _, _),
951 [9] = PINGROUP(9, qup3, pbs_out, pll_bist, _, qdss_gpio, _, _, _, _),
952 [10] = PINGROUP(10, qup3, agera_pll, _, pbs0, qdss_gpio, _, _, _, _),
953 [11] = PINGROUP(11, qup3, agera_pll, _, pbs1, qdss_gpio, _, _, _, _),
954 [12] = PINGROUP(12, qup4, tgu_ch0, _, _, _, _, _, _, _),
955 [13] = PINGROUP(13, qup4, tgu_ch1, _, _, _, _, _, _, _),
956 [14] = PINGROUP(14, qup5, tgu_ch2, _, phase_flag, qdss_gpio, dac_calib, _, _, _),
957 [15] = PINGROUP(15, qup5, tgu_ch3, _, phase_flag, qdss_gpio, dac_calib, _, _, _),
958 [16] = PINGROUP(16, qup5, _, phase_flag, qdss_gpio, dac_calib, _, _, _, _),
959 [17] = PINGROUP(17, qup5, _, phase_flag, qdss_gpio, dac_calib, _, _, _, _),
960 [18] = PINGROUP(18, sdc2_tb, cri_trng, pbs2, qdss_gpio, _, pwm_0, _, _, _),
961 [19] = PINGROUP(19, sdc1_tb, pbs3, qdss_gpio, _, _, _, _, _, _),
962 [20] = PINGROUP(20, cam_mclk, pbs4, qdss_gpio, _, _, _, _, _, _),
963 [21] = PINGROUP(21, cam_mclk, adsp_ext, pbs5, qdss_gpio, _, _, _, _, _),
964 [22] = PINGROUP(22, cci_i2c, prng_rosc, _, pbs6, phase_flag, qdss_gpio, dac_calib, atest, _),
965 [23] = PINGROUP(23, cci_i2c, prng_rosc, _, pbs7, phase_flag, qdss_gpio, dac_calib, atest, _),
966 [24] = PINGROUP(24, cci_timer1, gcc_gp1, _, pbs8, phase_flag, qdss_gpio, dac_calib, atest, _),
967 [25] = PINGROUP(25, cci_async, cci_timer0, _, pbs9, phase_flag, qdss_gpio, dac_calib, atest, _),
968 [26] = PINGROUP(26, _, pbs10, phase_flag, qdss_gpio, dac_calib, atest, vsense_trigger, _, _),
969 [27] = PINGROUP(27, cam_mclk, qdss_cti, _, _, _, _, _, _, _),
970 [28] = PINGROUP(28, cam_mclk, cci_timer2, qdss_cti, _, pwm_1, _, _, _, _),
971 [29] = PINGROUP(29, cci_i2c, _, phase_flag, dac_calib, atest, _, _, _, _),
972 [30] = PINGROUP(30, cci_i2c, _, phase_flag, dac_calib, atest, _, _, _, _),
973 [31] = PINGROUP(31, gp_pdm0, _, phase_flag, dac_calib, atest, _, _, _, _),
974 [32] = PINGROUP(32, cci_timer3, gp_pdm1, _, phase_flag, dac_calib, atest, _, _, _),
975 [33] = PINGROUP(33, gp_pdm2, _, phase_flag, dac_calib, atest, _, _, _, _),
976 [34] = PINGROUP(34, _, _, _, _, _, _, _, _, _),
977 [35] = PINGROUP(35, _, phase_flag, _, _, _, _, _, _, _),
978 [36] = PINGROUP(36, _, phase_flag, _, _, _, _, _, _, _),
979 [37] = PINGROUP(37, _, _, char_exec, _, _, _, _, _, _),
980 [38] = PINGROUP(38, _, _, _, char_exec, _, _, _, _, _),
981 [39] = PINGROUP(39, _, _, _, _, _, _, _, _, _),
982 [40] = PINGROUP(40, _, _, _, _, _, _, _, _, _),
983 [41] = PINGROUP(41, _, _, _, _, _, _, _, _, _),
984 [42] = PINGROUP(42, _, nav_gpio, _, _, _, _, _, _, _),
985 [43] = PINGROUP(43, _, _, phase_flag, _, _, _, _, _, _),
986 [44] = PINGROUP(44, _, _, phase_flag, _, _, _, _, _, _),
987 [45] = PINGROUP(45, _, _, phase_flag, _, _, _, _, _, _),
988 [46] = PINGROUP(46, _, _, _, _, _, _, _, _, _),
989 [47] = PINGROUP(47, _, nav_gpio, pbs14, qdss_gpio, _, _, _, _, _),
990 [48] = PINGROUP(48, _, vfr_1, _, pbs15, qdss_gpio, _, _, _, _),
991 [49] = PINGROUP(49, _, pa_indicator, _, _, _, _, _, _, _),
992 [50] = PINGROUP(50, _, _, _, _, _, _, _, _, _),
993 [51] = PINGROUP(51, _, _, _, pwm_2, _, _, _, _, _),
994 [52] = PINGROUP(52, _, nav_gpio, pbs_out, _, _, _, _, _, _),
995 [53] = PINGROUP(53, _, gsm1_tx, _, _, _, _, _, _, _),
996 [54] = PINGROUP(54, _, _, _, _, _, _, _, _, _),
997 [55] = PINGROUP(55, _, _, _, _, _, _, _, _, _),
998 [56] = PINGROUP(56, _, _, _, _, _, _, _, _, _),
999 [57] = PINGROUP(57, _, _, _, _, _, _, _, _, _),
1000 [58] = PINGROUP(58, _, _, _, _, _, _, _, _, _),
1001 [59] = PINGROUP(59, _, ssbi_wtr1, _, _, _, _, _, _, _),
1002 [60] = PINGROUP(60, _, ssbi_wtr1, _, _, _, _, _, _, _),
1003 [61] = PINGROUP(61, _, _, _, _, _, _, _, _, _),
1004 [62] = PINGROUP(62, _, pll_bypassnl, _, _, _, _, _, _, _),
1005 [63] = PINGROUP(63, pll_reset, _, phase_flag, ddr_pxi0, _, _, _, _, _),
1006 [64] = PINGROUP(64, gsm0_tx, _, phase_flag, ddr_pxi0, _, _, _, _, _),
1007 [65] = PINGROUP(65, _, _, _, _, _, _, _, _, _),
1008 [66] = PINGROUP(66, _, _, _, _, _, _, _, _, _),
1009 [67] = PINGROUP(67, _, _, _, _, _, _, _, _, _),
1010 [68] = PINGROUP(68, _, _, _, _, _, _, _, _, _),
1011 [69] = PINGROUP(69, qup1, gcc_gp2, qdss_gpio, ddr_pxi1, _, _, _, _, _),
1012 [70] = PINGROUP(70, qup1, gcc_gp3, qdss_gpio, ddr_pxi1, _, _, _, _, _),
1013 [71] = PINGROUP(71, qup2, dbg_out, _, _, _, _, _, _, _),
1014 [72] = PINGROUP(72, uim2_data, qdss_cti, _, pwm_3, _, _, _, _, _),
1015 [73] = PINGROUP(73, uim2_clk, _, qdss_cti, _, _, _, _, _, _),
1016 [74] = PINGROUP(74, uim2_reset, _, _, pwm_4, _, _, _, _, _),
1017 [75] = PINGROUP(75, uim2_present, _, _, pwm_5, _, _, _, _, _),
1018 [76] = PINGROUP(76, uim1_data, _, _, _, _, _, _, _, _),
1019 [77] = PINGROUP(77, uim1_clk, _, _, _, _, _, _, _, _),
1020 [78] = PINGROUP(78, uim1_reset, _, _, _, _, _, _, _, _),
1021 [79] = PINGROUP(79, uim1_present, _, _, _, _, _, _, _, _),
1022 [80] = PINGROUP(80, qup2, dac_calib, _, _, _, _, _, _, _),
1023 [81] = PINGROUP(81, mdp_vsync_out_0, mdp_vsync_out_1, mdp_vsync, dac_calib, _, _, _, _, _),
1024 [82] = PINGROUP(82, qup0, dac_calib, _, pwm_6, _, _, _, _, _),
1025 [83] = PINGROUP(83, _, _, _, _, _, _, _, _, _),
1026 [84] = PINGROUP(84, _, _, _, _, _, _, _, _, _),
1027 [85] = PINGROUP(85, _, _, _, _, _, _, _, _, _),
1028 [86] = PINGROUP(86, qup0, gcc_gp1, atest, _, _, _, _, _, _),
1029 [87] = PINGROUP(87, pbs11, qdss_gpio, _, _, _, _, _, _, _),
1030 [88] = PINGROUP(88, _, _, _, _, _, _, _, _, _),
1031 [89] = PINGROUP(89, usb_phy, atest, _, pwm_7, _, _, _, _, _),
1032 [90] = PINGROUP(90, mss_lte, pbs12, qdss_gpio, _, _, _, _, _, _),
1033 [91] = PINGROUP(91, mss_lte, pbs13, qdss_gpio, _, _, _, _, _, _),
1034 [92] = PINGROUP(92, _, _, _, _, _, _, _, _, _),
1035 [93] = PINGROUP(93, _, _, _, _, _, _, _, _, _),
1036 [94] = PINGROUP(94, _, qdss_gpio, wlan1_adc0, _, _, _, _, _, _),
1037 [95] = PINGROUP(95, nav_gpio, gp_pdm0, qdss_gpio, wlan1_adc1, _, _, _, _, _),
1038 [96] = PINGROUP(96, qup4, nav_gpio, mdp_vsync, gp_pdm1, sd_write, jitter_bist, qdss_cti, qdss_cti, _),
1039 [97] = PINGROUP(97, qup4, nav_gpio, mdp_vsync, gp_pdm2, jitter_bist, qdss_cti, qdss_cti, _, _),
1040 [98] = PINGROUP(98, _, _, _, _, _, _, _, _, _),
1041 [99] = PINGROUP(99, _, _, _, _, _, _, _, _, _),
1042 [100] = PINGROUP(100, atest, _, _, _, _, _, _, _, _),
1043 [101] = PINGROUP(101, atest, _, _, _, _, _, _, _, _),
1044 [102] = PINGROUP(102, _, phase_flag, dac_calib, ddr_pxi2, _, _, _, _, _),
1045 [103] = PINGROUP(103, _, phase_flag, dac_calib, ddr_pxi2, _, _, _, _, _),
1046 [104] = PINGROUP(104, _, phase_flag, qdss_gpio, dac_calib, ddr_pxi3, _, pwm_8, _, _),
1047 [105] = PINGROUP(105, _, phase_flag, qdss_gpio, dac_calib, ddr_pxi3, _, _, _, _),
1048 [106] = PINGROUP(106, nav_gpio, gcc_gp3, qdss_gpio, _, _, _, _, _, _),
1049 [107] = PINGROUP(107, nav_gpio, gcc_gp2, qdss_gpio, _, _, _, _, _, _),
1050 [108] = PINGROUP(108, nav_gpio, _, _, _, _, _, _, _, _),
1051 [109] = PINGROUP(109, _, qdss_gpio, _, _, _, _, _, _, _),
1052 [110] = PINGROUP(110, _, qdss_gpio, _, _, _, _, _, _, _),
1053 [111] = PINGROUP(111, _, _, _, _, _, _, _, _, _),
1054 [112] = PINGROUP(112, _, _, _, _, _, _, _, _, _),
1055 [113] = PINGROUP(113, _, _, _, _, _, _, _, _, _),
1056 [114] = PINGROUP(114, _, _, _, _, _, _, _, _, _),
1057 [115] = PINGROUP(115, _, pwm_9, _, _, _, _, _, _, _),
1058 [116] = PINGROUP(116, _, _, _, _, _, _, _, _, _),
1059 [117] = PINGROUP(117, _, _, _, _, _, _, _, _, _),
1060 [118] = PINGROUP(118, _, _, _, _, _, _, _, _, _),
1061 [119] = PINGROUP(119, _, _, _, _, _, _, _, _, _),
1062 [120] = PINGROUP(120, _, _, _, _, _, _, _, _, _),
1063 [121] = PINGROUP(121, _, _, _, _, _, _, _, _, _),
1064 [122] = PINGROUP(122, _, _, _, _, _, _, _, _, _),
1065 [123] = PINGROUP(123, _, _, _, _, _, _, _, _, _),
1066 [124] = PINGROUP(124, _, _, _, _, _, _, _, _, _),
1067 [125] = PINGROUP(125, _, _, _, _, _, _, _, _, _),
1068 [126] = PINGROUP(126, _, _, _, _, _, _, _, _, _),
1069 [127] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x84004, 0, 0),
1070 [128] = SDC_QDSD_PINGROUP(sdc1_clk, 0x84000, 13, 6),
1071 [129] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x84000, 11, 3),
1072 [130] = SDC_QDSD_PINGROUP(sdc1_data, 0x84000, 9, 0),
1073 [131] = SDC_QDSD_PINGROUP(sdc2_clk, 0x86000, 14, 6),
1074 [132] = SDC_QDSD_PINGROUP(sdc2_cmd, 0x86000, 11, 3),
1075 [133] = SDC_QDSD_PINGROUP(sdc2_data, 0x86000, 9, 0),
1076 };
1077
1078 static const struct msm_gpio_wakeirq_map qcm2290_mpm_map[] = {
1079 { 0, 84 }, { 3, 75 }, { 4, 16 }, { 6, 59 }, { 8, 63 }, { 11, 17 },
1080 { 13, 18 }, { 14, 51 }, { 17, 20 }, { 18, 52 }, { 19, 53 }, { 24, 6 },
1081 { 25, 71 }, { 27, 73 }, { 28, 41 }, { 31, 27 }, { 32, 54 }, { 33, 55 },
1082 { 34, 56 }, { 35, 57 }, { 36, 58 }, { 39, 28 }, { 46, 29 }, { 62, 60 },
1083 { 63, 61 }, { 64, 62 }, { 69, 33 }, { 70, 34 }, { 72, 72 }, { 75, 35 },
1084 { 79, 36 }, { 80, 21 }, { 81, 38 }, { 86, 19 }, { 87, 42 }, { 88, 43 },
1085 { 89, 45 }, { 91, 74 }, { 94, 47 }, { 95, 48 }, { 96, 49 }, { 97, 50 },
1086 };
1087
1088 static const struct msm_pinctrl_soc_data qcm2290_pinctrl = {
1089 .pins = qcm2290_pins,
1090 .npins = ARRAY_SIZE(qcm2290_pins),
1091 .functions = qcm2290_functions,
1092 .nfunctions = ARRAY_SIZE(qcm2290_functions),
1093 .groups = qcm2290_groups,
1094 .ngroups = ARRAY_SIZE(qcm2290_groups),
1095 .ngpios = 127,
1096 .wakeirq_map = qcm2290_mpm_map,
1097 .nwakeirq_map = ARRAY_SIZE(qcm2290_mpm_map),
1098 };
1099
qcm2290_pinctrl_probe(struct platform_device * pdev)1100 static int qcm2290_pinctrl_probe(struct platform_device *pdev)
1101 {
1102 return msm_pinctrl_probe(pdev, &qcm2290_pinctrl);
1103 }
1104
1105 static const struct of_device_id qcm2290_pinctrl_of_match[] = {
1106 { .compatible = "qcom,qcm2290-tlmm", },
1107 { },
1108 };
1109
1110 static struct platform_driver qcm2290_pinctrl_driver = {
1111 .driver = {
1112 .name = "qcm2290-pinctrl",
1113 .of_match_table = qcm2290_pinctrl_of_match,
1114 },
1115 .probe = qcm2290_pinctrl_probe,
1116 .remove = msm_pinctrl_remove,
1117 };
1118
qcm2290_pinctrl_init(void)1119 static int __init qcm2290_pinctrl_init(void)
1120 {
1121 return platform_driver_register(&qcm2290_pinctrl_driver);
1122 }
1123 arch_initcall(qcm2290_pinctrl_init);
1124
qcm2290_pinctrl_exit(void)1125 static void __exit qcm2290_pinctrl_exit(void)
1126 {
1127 platform_driver_unregister(&qcm2290_pinctrl_driver);
1128 }
1129 module_exit(qcm2290_pinctrl_exit);
1130
1131 MODULE_DESCRIPTION("QTI QCM2290 pinctrl driver");
1132 MODULE_LICENSE("GPL v2");
1133 MODULE_DEVICE_TABLE(of, qcm2290_pinctrl_of_match);
1134