1 /*
2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <linux/delay.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/i2c.h>
27 #include <linux/media-bus-format.h>
28 #include <linux/module.h>
29 #include <linux/of_platform.h>
30 #include <linux/platform_device.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/regulator/consumer.h>
33
34 #include <video/display_timing.h>
35 #include <video/of_display_timing.h>
36 #include <video/videomode.h>
37
38 #include <drm/drm_crtc.h>
39 #include <drm/drm_device.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_mipi_dsi.h>
42 #include <drm/drm_panel.h>
43
44 /**
45 * struct panel_desc - Describes a simple panel.
46 */
47 struct panel_desc {
48 /**
49 * @modes: Pointer to array of fixed modes appropriate for this panel.
50 *
51 * If only one mode then this can just be the address of the mode.
52 * NOTE: cannot be used with "timings" and also if this is specified
53 * then you cannot override the mode in the device tree.
54 */
55 const struct drm_display_mode *modes;
56
57 /** @num_modes: Number of elements in modes array. */
58 unsigned int num_modes;
59
60 /**
61 * @timings: Pointer to array of display timings
62 *
63 * NOTE: cannot be used with "modes" and also these will be used to
64 * validate a device tree override if one is present.
65 */
66 const struct display_timing *timings;
67
68 /** @num_timings: Number of elements in timings array. */
69 unsigned int num_timings;
70
71 /** @bpc: Bits per color. */
72 unsigned int bpc;
73
74 /** @size: Structure containing the physical size of this panel. */
75 struct {
76 /**
77 * @size.width: Width (in mm) of the active display area.
78 */
79 unsigned int width;
80
81 /**
82 * @size.height: Height (in mm) of the active display area.
83 */
84 unsigned int height;
85 } size;
86
87 /** @delay: Structure containing various delay values for this panel. */
88 struct {
89 /**
90 * @delay.prepare: Time for the panel to become ready.
91 *
92 * The time (in milliseconds) that it takes for the panel to
93 * become ready and start receiving video data
94 */
95 unsigned int prepare;
96
97 /**
98 * @delay.enable: Time for the panel to display a valid frame.
99 *
100 * The time (in milliseconds) that it takes for the panel to
101 * display the first valid frame after starting to receive
102 * video data.
103 */
104 unsigned int enable;
105
106 /**
107 * @delay.disable: Time for the panel to turn the display off.
108 *
109 * The time (in milliseconds) that it takes for the panel to
110 * turn the display off (no content is visible).
111 */
112 unsigned int disable;
113
114 /**
115 * @delay.unprepare: Time to power down completely.
116 *
117 * The time (in milliseconds) that it takes for the panel
118 * to power itself down completely.
119 *
120 * This time is used to prevent a future "prepare" from
121 * starting until at least this many milliseconds has passed.
122 * If at prepare time less time has passed since unprepare
123 * finished, the driver waits for the remaining time.
124 */
125 unsigned int unprepare;
126 } delay;
127
128 /** @bus_format: See MEDIA_BUS_FMT_... defines. */
129 u32 bus_format;
130
131 /** @bus_flags: See DRM_BUS_FLAG_... defines. */
132 u32 bus_flags;
133
134 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */
135 int connector_type;
136 };
137
138 struct panel_simple {
139 struct drm_panel base;
140 bool enabled;
141
142 bool prepared;
143
144 ktime_t unprepared_time;
145
146 const struct panel_desc *desc;
147
148 struct regulator *supply;
149 struct i2c_adapter *ddc;
150
151 struct gpio_desc *enable_gpio;
152
153 struct edid *edid;
154
155 struct drm_display_mode override_mode;
156
157 enum drm_panel_orientation orientation;
158 };
159
to_panel_simple(struct drm_panel * panel)160 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
161 {
162 return container_of(panel, struct panel_simple, base);
163 }
164
panel_simple_get_timings_modes(struct panel_simple * panel,struct drm_connector * connector)165 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel,
166 struct drm_connector *connector)
167 {
168 struct drm_display_mode *mode;
169 unsigned int i, num = 0;
170
171 for (i = 0; i < panel->desc->num_timings; i++) {
172 const struct display_timing *dt = &panel->desc->timings[i];
173 struct videomode vm;
174
175 videomode_from_timing(dt, &vm);
176 mode = drm_mode_create(connector->dev);
177 if (!mode) {
178 dev_err(panel->base.dev, "failed to add mode %ux%u\n",
179 dt->hactive.typ, dt->vactive.typ);
180 continue;
181 }
182
183 drm_display_mode_from_videomode(&vm, mode);
184
185 mode->type |= DRM_MODE_TYPE_DRIVER;
186
187 if (panel->desc->num_timings == 1)
188 mode->type |= DRM_MODE_TYPE_PREFERRED;
189
190 drm_mode_probed_add(connector, mode);
191 num++;
192 }
193
194 return num;
195 }
196
panel_simple_get_display_modes(struct panel_simple * panel,struct drm_connector * connector)197 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel,
198 struct drm_connector *connector)
199 {
200 struct drm_display_mode *mode;
201 unsigned int i, num = 0;
202
203 for (i = 0; i < panel->desc->num_modes; i++) {
204 const struct drm_display_mode *m = &panel->desc->modes[i];
205
206 mode = drm_mode_duplicate(connector->dev, m);
207 if (!mode) {
208 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n",
209 m->hdisplay, m->vdisplay,
210 drm_mode_vrefresh(m));
211 continue;
212 }
213
214 mode->type |= DRM_MODE_TYPE_DRIVER;
215
216 if (panel->desc->num_modes == 1)
217 mode->type |= DRM_MODE_TYPE_PREFERRED;
218
219 drm_mode_set_name(mode);
220
221 drm_mode_probed_add(connector, mode);
222 num++;
223 }
224
225 return num;
226 }
227
panel_simple_get_non_edid_modes(struct panel_simple * panel,struct drm_connector * connector)228 static int panel_simple_get_non_edid_modes(struct panel_simple *panel,
229 struct drm_connector *connector)
230 {
231 struct drm_display_mode *mode;
232 bool has_override = panel->override_mode.type;
233 unsigned int num = 0;
234
235 if (!panel->desc)
236 return 0;
237
238 if (has_override) {
239 mode = drm_mode_duplicate(connector->dev,
240 &panel->override_mode);
241 if (mode) {
242 drm_mode_probed_add(connector, mode);
243 num = 1;
244 } else {
245 dev_err(panel->base.dev, "failed to add override mode\n");
246 }
247 }
248
249 /* Only add timings if override was not there or failed to validate */
250 if (num == 0 && panel->desc->num_timings)
251 num = panel_simple_get_timings_modes(panel, connector);
252
253 /*
254 * Only add fixed modes if timings/override added no mode.
255 *
256 * We should only ever have either the display timings specified
257 * or a fixed mode. Anything else is rather bogus.
258 */
259 WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
260 if (num == 0)
261 num = panel_simple_get_display_modes(panel, connector);
262
263 connector->display_info.bpc = panel->desc->bpc;
264 connector->display_info.width_mm = panel->desc->size.width;
265 connector->display_info.height_mm = panel->desc->size.height;
266 if (panel->desc->bus_format)
267 drm_display_info_set_bus_formats(&connector->display_info,
268 &panel->desc->bus_format, 1);
269 connector->display_info.bus_flags = panel->desc->bus_flags;
270
271 return num;
272 }
273
panel_simple_wait(ktime_t start_ktime,unsigned int min_ms)274 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms)
275 {
276 ktime_t now_ktime, min_ktime;
277
278 if (!min_ms)
279 return;
280
281 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms));
282 now_ktime = ktime_get_boottime();
283
284 if (ktime_before(now_ktime, min_ktime))
285 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1);
286 }
287
panel_simple_disable(struct drm_panel * panel)288 static int panel_simple_disable(struct drm_panel *panel)
289 {
290 struct panel_simple *p = to_panel_simple(panel);
291
292 if (!p->enabled)
293 return 0;
294
295 if (p->desc->delay.disable)
296 msleep(p->desc->delay.disable);
297
298 p->enabled = false;
299
300 return 0;
301 }
302
panel_simple_suspend(struct device * dev)303 static int panel_simple_suspend(struct device *dev)
304 {
305 struct panel_simple *p = dev_get_drvdata(dev);
306
307 gpiod_set_value_cansleep(p->enable_gpio, 0);
308 regulator_disable(p->supply);
309 p->unprepared_time = ktime_get_boottime();
310
311 kfree(p->edid);
312 p->edid = NULL;
313
314 return 0;
315 }
316
panel_simple_unprepare(struct drm_panel * panel)317 static int panel_simple_unprepare(struct drm_panel *panel)
318 {
319 struct panel_simple *p = to_panel_simple(panel);
320 int ret;
321
322 /* Unpreparing when already unprepared is a no-op */
323 if (!p->prepared)
324 return 0;
325
326 pm_runtime_mark_last_busy(panel->dev);
327 ret = pm_runtime_put_autosuspend(panel->dev);
328 if (ret < 0)
329 return ret;
330 p->prepared = false;
331
332 return 0;
333 }
334
panel_simple_resume(struct device * dev)335 static int panel_simple_resume(struct device *dev)
336 {
337 struct panel_simple *p = dev_get_drvdata(dev);
338 int err;
339
340 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare);
341
342 err = regulator_enable(p->supply);
343 if (err < 0) {
344 dev_err(dev, "failed to enable supply: %d\n", err);
345 return err;
346 }
347
348 gpiod_set_value_cansleep(p->enable_gpio, 1);
349
350 if (p->desc->delay.prepare)
351 msleep(p->desc->delay.prepare);
352
353 return 0;
354 }
355
panel_simple_prepare(struct drm_panel * panel)356 static int panel_simple_prepare(struct drm_panel *panel)
357 {
358 struct panel_simple *p = to_panel_simple(panel);
359 int ret;
360
361 /* Preparing when already prepared is a no-op */
362 if (p->prepared)
363 return 0;
364
365 ret = pm_runtime_get_sync(panel->dev);
366 if (ret < 0) {
367 pm_runtime_put_autosuspend(panel->dev);
368 return ret;
369 }
370
371 p->prepared = true;
372
373 return 0;
374 }
375
panel_simple_enable(struct drm_panel * panel)376 static int panel_simple_enable(struct drm_panel *panel)
377 {
378 struct panel_simple *p = to_panel_simple(panel);
379
380 if (p->enabled)
381 return 0;
382
383 if (p->desc->delay.enable)
384 msleep(p->desc->delay.enable);
385
386 p->enabled = true;
387
388 return 0;
389 }
390
panel_simple_get_modes(struct drm_panel * panel,struct drm_connector * connector)391 static int panel_simple_get_modes(struct drm_panel *panel,
392 struct drm_connector *connector)
393 {
394 struct panel_simple *p = to_panel_simple(panel);
395 int num = 0;
396
397 /* probe EDID if a DDC bus is available */
398 if (p->ddc) {
399 pm_runtime_get_sync(panel->dev);
400
401 if (!p->edid)
402 p->edid = drm_get_edid(connector, p->ddc);
403
404 if (p->edid)
405 num += drm_add_edid_modes(connector, p->edid);
406
407 pm_runtime_mark_last_busy(panel->dev);
408 pm_runtime_put_autosuspend(panel->dev);
409 }
410
411 /* add hard-coded panel modes */
412 num += panel_simple_get_non_edid_modes(p, connector);
413
414 /*
415 * TODO: Remove once all drm drivers call
416 * drm_connector_set_orientation_from_panel()
417 */
418 drm_connector_set_panel_orientation(connector, p->orientation);
419
420 return num;
421 }
422
panel_simple_get_timings(struct drm_panel * panel,unsigned int num_timings,struct display_timing * timings)423 static int panel_simple_get_timings(struct drm_panel *panel,
424 unsigned int num_timings,
425 struct display_timing *timings)
426 {
427 struct panel_simple *p = to_panel_simple(panel);
428 unsigned int i;
429
430 if (p->desc->num_timings < num_timings)
431 num_timings = p->desc->num_timings;
432
433 if (timings)
434 for (i = 0; i < num_timings; i++)
435 timings[i] = p->desc->timings[i];
436
437 return p->desc->num_timings;
438 }
439
panel_simple_get_orientation(struct drm_panel * panel)440 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel)
441 {
442 struct panel_simple *p = to_panel_simple(panel);
443
444 return p->orientation;
445 }
446
447 static const struct drm_panel_funcs panel_simple_funcs = {
448 .disable = panel_simple_disable,
449 .unprepare = panel_simple_unprepare,
450 .prepare = panel_simple_prepare,
451 .enable = panel_simple_enable,
452 .get_modes = panel_simple_get_modes,
453 .get_orientation = panel_simple_get_orientation,
454 .get_timings = panel_simple_get_timings,
455 };
456
457 static struct panel_desc panel_dpi;
458
panel_dpi_probe(struct device * dev,struct panel_simple * panel)459 static int panel_dpi_probe(struct device *dev,
460 struct panel_simple *panel)
461 {
462 struct display_timing *timing;
463 const struct device_node *np;
464 struct panel_desc *desc;
465 unsigned int bus_flags;
466 struct videomode vm;
467 int ret;
468
469 np = dev->of_node;
470 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
471 if (!desc)
472 return -ENOMEM;
473
474 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
475 if (!timing)
476 return -ENOMEM;
477
478 ret = of_get_display_timing(np, "panel-timing", timing);
479 if (ret < 0) {
480 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n",
481 np);
482 return ret;
483 }
484
485 desc->timings = timing;
486 desc->num_timings = 1;
487
488 of_property_read_u32(np, "width-mm", &desc->size.width);
489 of_property_read_u32(np, "height-mm", &desc->size.height);
490
491 /* Extract bus_flags from display_timing */
492 bus_flags = 0;
493 vm.flags = timing->flags;
494 drm_bus_flags_from_videomode(&vm, &bus_flags);
495 desc->bus_flags = bus_flags;
496
497 /* We do not know the connector for the DT node, so guess it */
498 desc->connector_type = DRM_MODE_CONNECTOR_DPI;
499
500 panel->desc = desc;
501
502 return 0;
503 }
504
505 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
506 (to_check->field.typ >= bounds->field.min && \
507 to_check->field.typ <= bounds->field.max)
panel_simple_parse_panel_timing_node(struct device * dev,struct panel_simple * panel,const struct display_timing * ot)508 static void panel_simple_parse_panel_timing_node(struct device *dev,
509 struct panel_simple *panel,
510 const struct display_timing *ot)
511 {
512 const struct panel_desc *desc = panel->desc;
513 struct videomode vm;
514 unsigned int i;
515
516 if (WARN_ON(desc->num_modes)) {
517 dev_err(dev, "Reject override mode: panel has a fixed mode\n");
518 return;
519 }
520 if (WARN_ON(!desc->num_timings)) {
521 dev_err(dev, "Reject override mode: no timings specified\n");
522 return;
523 }
524
525 for (i = 0; i < panel->desc->num_timings; i++) {
526 const struct display_timing *dt = &panel->desc->timings[i];
527
528 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
529 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
530 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
531 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
532 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
533 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
534 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
535 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
536 continue;
537
538 if (ot->flags != dt->flags)
539 continue;
540
541 videomode_from_timing(ot, &vm);
542 drm_display_mode_from_videomode(&vm, &panel->override_mode);
543 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
544 DRM_MODE_TYPE_PREFERRED;
545 break;
546 }
547
548 if (WARN_ON(!panel->override_mode.type))
549 dev_err(dev, "Reject override mode: No display_timing found\n");
550 }
551
panel_simple_probe(struct device * dev,const struct panel_desc * desc)552 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
553 {
554 struct panel_simple *panel;
555 struct display_timing dt;
556 struct device_node *ddc;
557 int connector_type;
558 u32 bus_flags;
559 int err;
560
561 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
562 if (!panel)
563 return -ENOMEM;
564
565 panel->enabled = false;
566 panel->desc = desc;
567
568 panel->supply = devm_regulator_get(dev, "power");
569 if (IS_ERR(panel->supply))
570 return PTR_ERR(panel->supply);
571
572 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
573 GPIOD_OUT_LOW);
574 if (IS_ERR(panel->enable_gpio))
575 return dev_err_probe(dev, PTR_ERR(panel->enable_gpio),
576 "failed to request GPIO\n");
577
578 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation);
579 if (err) {
580 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
581 return err;
582 }
583
584 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
585 if (ddc) {
586 panel->ddc = of_find_i2c_adapter_by_node(ddc);
587 of_node_put(ddc);
588
589 if (!panel->ddc)
590 return -EPROBE_DEFER;
591 }
592
593 if (desc == &panel_dpi) {
594 /* Handle the generic panel-dpi binding */
595 err = panel_dpi_probe(dev, panel);
596 if (err)
597 goto free_ddc;
598 desc = panel->desc;
599 } else {
600 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
601 panel_simple_parse_panel_timing_node(dev, panel, &dt);
602 }
603
604 connector_type = desc->connector_type;
605 /* Catch common mistakes for panels. */
606 switch (connector_type) {
607 case 0:
608 dev_warn(dev, "Specify missing connector_type\n");
609 connector_type = DRM_MODE_CONNECTOR_DPI;
610 break;
611 case DRM_MODE_CONNECTOR_LVDS:
612 WARN_ON(desc->bus_flags &
613 ~(DRM_BUS_FLAG_DE_LOW |
614 DRM_BUS_FLAG_DE_HIGH |
615 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
616 DRM_BUS_FLAG_DATA_LSB_TO_MSB));
617 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
618 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG &&
619 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA);
620 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
621 desc->bpc != 6);
622 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG ||
623 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) &&
624 desc->bpc != 8);
625 break;
626 case DRM_MODE_CONNECTOR_eDP:
627 dev_warn(dev, "eDP panels moved to panel-edp\n");
628 err = -EINVAL;
629 goto free_ddc;
630 case DRM_MODE_CONNECTOR_DSI:
631 if (desc->bpc != 6 && desc->bpc != 8)
632 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
633 break;
634 case DRM_MODE_CONNECTOR_DPI:
635 bus_flags = DRM_BUS_FLAG_DE_LOW |
636 DRM_BUS_FLAG_DE_HIGH |
637 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE |
638 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
639 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
640 DRM_BUS_FLAG_DATA_LSB_TO_MSB |
641 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE |
642 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE;
643 if (desc->bus_flags & ~bus_flags)
644 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags);
645 if (!(desc->bus_flags & bus_flags))
646 dev_warn(dev, "Specify missing bus_flags\n");
647 if (desc->bus_format == 0)
648 dev_warn(dev, "Specify missing bus_format\n");
649 if (desc->bpc != 6 && desc->bpc != 8)
650 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
651 break;
652 default:
653 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type);
654 connector_type = DRM_MODE_CONNECTOR_DPI;
655 break;
656 }
657
658 dev_set_drvdata(dev, panel);
659
660 /*
661 * We use runtime PM for prepare / unprepare since those power the panel
662 * on and off and those can be very slow operations. This is important
663 * to optimize powering the panel on briefly to read the EDID before
664 * fully enabling the panel.
665 */
666 pm_runtime_enable(dev);
667 pm_runtime_set_autosuspend_delay(dev, 1000);
668 pm_runtime_use_autosuspend(dev);
669
670 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type);
671
672 err = drm_panel_of_backlight(&panel->base);
673 if (err) {
674 dev_err_probe(dev, err, "Could not find backlight\n");
675 goto disable_pm_runtime;
676 }
677
678 drm_panel_add(&panel->base);
679
680 return 0;
681
682 disable_pm_runtime:
683 pm_runtime_dont_use_autosuspend(dev);
684 pm_runtime_disable(dev);
685 free_ddc:
686 if (panel->ddc)
687 put_device(&panel->ddc->dev);
688
689 return err;
690 }
691
panel_simple_remove(struct device * dev)692 static void panel_simple_remove(struct device *dev)
693 {
694 struct panel_simple *panel = dev_get_drvdata(dev);
695
696 drm_panel_remove(&panel->base);
697 drm_panel_disable(&panel->base);
698 drm_panel_unprepare(&panel->base);
699
700 pm_runtime_dont_use_autosuspend(dev);
701 pm_runtime_disable(dev);
702 if (panel->ddc)
703 put_device(&panel->ddc->dev);
704 }
705
panel_simple_shutdown(struct device * dev)706 static void panel_simple_shutdown(struct device *dev)
707 {
708 struct panel_simple *panel = dev_get_drvdata(dev);
709
710 drm_panel_disable(&panel->base);
711 drm_panel_unprepare(&panel->base);
712 }
713
714 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = {
715 .clock = 71100,
716 .hdisplay = 1280,
717 .hsync_start = 1280 + 40,
718 .hsync_end = 1280 + 40 + 80,
719 .htotal = 1280 + 40 + 80 + 40,
720 .vdisplay = 800,
721 .vsync_start = 800 + 3,
722 .vsync_end = 800 + 3 + 10,
723 .vtotal = 800 + 3 + 10 + 10,
724 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
725 };
726
727 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = {
728 .modes = &ire_am_1280800n3tzqw_t00h_mode,
729 .num_modes = 1,
730 .bpc = 8,
731 .size = {
732 .width = 217,
733 .height = 136,
734 },
735 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
736 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
737 .connector_type = DRM_MODE_CONNECTOR_LVDS,
738 };
739
740 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
741 .clock = 9000,
742 .hdisplay = 480,
743 .hsync_start = 480 + 2,
744 .hsync_end = 480 + 2 + 41,
745 .htotal = 480 + 2 + 41 + 2,
746 .vdisplay = 272,
747 .vsync_start = 272 + 2,
748 .vsync_end = 272 + 2 + 10,
749 .vtotal = 272 + 2 + 10 + 2,
750 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
751 };
752
753 static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
754 .modes = &ire_am_480272h3tmqw_t01h_mode,
755 .num_modes = 1,
756 .bpc = 8,
757 .size = {
758 .width = 99,
759 .height = 58,
760 },
761 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
762 };
763
764 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
765 .clock = 33333,
766 .hdisplay = 800,
767 .hsync_start = 800 + 0,
768 .hsync_end = 800 + 0 + 255,
769 .htotal = 800 + 0 + 255 + 0,
770 .vdisplay = 480,
771 .vsync_start = 480 + 2,
772 .vsync_end = 480 + 2 + 45,
773 .vtotal = 480 + 2 + 45 + 0,
774 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
775 };
776
777 static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = {
778 .pixelclock = { 29930000, 33260000, 36590000 },
779 .hactive = { 800, 800, 800 },
780 .hfront_porch = { 1, 40, 168 },
781 .hback_porch = { 88, 88, 88 },
782 .hsync_len = { 1, 128, 128 },
783 .vactive = { 480, 480, 480 },
784 .vfront_porch = { 1, 35, 37 },
785 .vback_porch = { 8, 8, 8 },
786 .vsync_len = { 1, 2, 2 },
787 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
788 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
789 DISPLAY_FLAGS_SYNC_POSEDGE,
790 };
791
792 static const struct panel_desc ampire_am_800480l1tmqw_t00h = {
793 .timings = &ire_am_800480l1tmqw_t00h_timing,
794 .num_timings = 1,
795 .bpc = 8,
796 .size = {
797 .width = 111,
798 .height = 67,
799 },
800 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
801 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
802 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
803 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
804 .connector_type = DRM_MODE_CONNECTOR_DPI,
805 };
806
807 static const struct panel_desc ampire_am800480r3tmqwa1h = {
808 .modes = &ire_am800480r3tmqwa1h_mode,
809 .num_modes = 1,
810 .bpc = 6,
811 .size = {
812 .width = 152,
813 .height = 91,
814 },
815 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
816 };
817
818 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = {
819 .pixelclock = { 34500000, 39600000, 50400000 },
820 .hactive = { 800, 800, 800 },
821 .hfront_porch = { 12, 112, 312 },
822 .hback_porch = { 87, 87, 48 },
823 .hsync_len = { 1, 1, 40 },
824 .vactive = { 600, 600, 600 },
825 .vfront_porch = { 1, 21, 61 },
826 .vback_porch = { 38, 38, 19 },
827 .vsync_len = { 1, 1, 20 },
828 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
829 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
830 DISPLAY_FLAGS_SYNC_POSEDGE,
831 };
832
833 static const struct panel_desc ampire_am800600p5tmqwtb8h = {
834 .timings = &ire_am800600p5tmqw_tb8h_timing,
835 .num_timings = 1,
836 .bpc = 6,
837 .size = {
838 .width = 162,
839 .height = 122,
840 },
841 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
842 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
843 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
844 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
845 .connector_type = DRM_MODE_CONNECTOR_DPI,
846 };
847
848 static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
849 .pixelclock = { 26400000, 33300000, 46800000 },
850 .hactive = { 800, 800, 800 },
851 .hfront_porch = { 16, 210, 354 },
852 .hback_porch = { 45, 36, 6 },
853 .hsync_len = { 1, 10, 40 },
854 .vactive = { 480, 480, 480 },
855 .vfront_porch = { 7, 22, 147 },
856 .vback_porch = { 22, 13, 3 },
857 .vsync_len = { 1, 10, 20 },
858 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
859 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
860 };
861
862 static const struct panel_desc armadeus_st0700_adapt = {
863 .timings = &santek_st0700i5y_rbslw_f_timing,
864 .num_timings = 1,
865 .bpc = 6,
866 .size = {
867 .width = 154,
868 .height = 86,
869 },
870 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
871 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
872 };
873
874 static const struct drm_display_mode auo_b101aw03_mode = {
875 .clock = 51450,
876 .hdisplay = 1024,
877 .hsync_start = 1024 + 156,
878 .hsync_end = 1024 + 156 + 8,
879 .htotal = 1024 + 156 + 8 + 156,
880 .vdisplay = 600,
881 .vsync_start = 600 + 16,
882 .vsync_end = 600 + 16 + 6,
883 .vtotal = 600 + 16 + 6 + 16,
884 };
885
886 static const struct panel_desc auo_b101aw03 = {
887 .modes = &auo_b101aw03_mode,
888 .num_modes = 1,
889 .bpc = 6,
890 .size = {
891 .width = 223,
892 .height = 125,
893 },
894 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
895 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
896 .connector_type = DRM_MODE_CONNECTOR_LVDS,
897 };
898
899 static const struct drm_display_mode auo_b101xtn01_mode = {
900 .clock = 72000,
901 .hdisplay = 1366,
902 .hsync_start = 1366 + 20,
903 .hsync_end = 1366 + 20 + 70,
904 .htotal = 1366 + 20 + 70,
905 .vdisplay = 768,
906 .vsync_start = 768 + 14,
907 .vsync_end = 768 + 14 + 42,
908 .vtotal = 768 + 14 + 42,
909 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
910 };
911
912 static const struct panel_desc auo_b101xtn01 = {
913 .modes = &auo_b101xtn01_mode,
914 .num_modes = 1,
915 .bpc = 6,
916 .size = {
917 .width = 223,
918 .height = 125,
919 },
920 };
921
922 static const struct drm_display_mode auo_b116xw03_mode = {
923 .clock = 70589,
924 .hdisplay = 1366,
925 .hsync_start = 1366 + 40,
926 .hsync_end = 1366 + 40 + 40,
927 .htotal = 1366 + 40 + 40 + 32,
928 .vdisplay = 768,
929 .vsync_start = 768 + 10,
930 .vsync_end = 768 + 10 + 12,
931 .vtotal = 768 + 10 + 12 + 6,
932 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
933 };
934
935 static const struct panel_desc auo_b116xw03 = {
936 .modes = &auo_b116xw03_mode,
937 .num_modes = 1,
938 .bpc = 6,
939 .size = {
940 .width = 256,
941 .height = 144,
942 },
943 .delay = {
944 .prepare = 1,
945 .enable = 200,
946 .disable = 200,
947 .unprepare = 500,
948 },
949 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
950 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
951 .connector_type = DRM_MODE_CONNECTOR_LVDS,
952 };
953
954 static const struct display_timing auo_g070vvn01_timings = {
955 .pixelclock = { 33300000, 34209000, 45000000 },
956 .hactive = { 800, 800, 800 },
957 .hfront_porch = { 20, 40, 200 },
958 .hback_porch = { 87, 40, 1 },
959 .hsync_len = { 1, 48, 87 },
960 .vactive = { 480, 480, 480 },
961 .vfront_porch = { 5, 13, 200 },
962 .vback_porch = { 31, 31, 29 },
963 .vsync_len = { 1, 1, 3 },
964 };
965
966 static const struct panel_desc auo_g070vvn01 = {
967 .timings = &auo_g070vvn01_timings,
968 .num_timings = 1,
969 .bpc = 8,
970 .size = {
971 .width = 152,
972 .height = 91,
973 },
974 .delay = {
975 .prepare = 200,
976 .enable = 50,
977 .disable = 50,
978 .unprepare = 1000,
979 },
980 };
981
982 static const struct display_timing auo_g101evn010_timing = {
983 .pixelclock = { 64000000, 68930000, 85000000 },
984 .hactive = { 1280, 1280, 1280 },
985 .hfront_porch = { 8, 64, 256 },
986 .hback_porch = { 8, 64, 256 },
987 .hsync_len = { 40, 168, 767 },
988 .vactive = { 800, 800, 800 },
989 .vfront_porch = { 4, 8, 100 },
990 .vback_porch = { 4, 8, 100 },
991 .vsync_len = { 8, 16, 223 },
992 };
993
994 static const struct panel_desc auo_g101evn010 = {
995 .timings = &auo_g101evn010_timing,
996 .num_timings = 1,
997 .bpc = 6,
998 .size = {
999 .width = 216,
1000 .height = 135,
1001 },
1002 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1003 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1004 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1005 };
1006
1007 static const struct drm_display_mode auo_g104sn02_mode = {
1008 .clock = 40000,
1009 .hdisplay = 800,
1010 .hsync_start = 800 + 40,
1011 .hsync_end = 800 + 40 + 216,
1012 .htotal = 800 + 40 + 216 + 128,
1013 .vdisplay = 600,
1014 .vsync_start = 600 + 10,
1015 .vsync_end = 600 + 10 + 35,
1016 .vtotal = 600 + 10 + 35 + 2,
1017 };
1018
1019 static const struct panel_desc auo_g104sn02 = {
1020 .modes = &auo_g104sn02_mode,
1021 .num_modes = 1,
1022 .bpc = 8,
1023 .size = {
1024 .width = 211,
1025 .height = 158,
1026 },
1027 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1028 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1029 };
1030
1031 static const struct display_timing auo_g121ean01_timing = {
1032 .pixelclock = { 60000000, 74400000, 90000000 },
1033 .hactive = { 1280, 1280, 1280 },
1034 .hfront_porch = { 20, 50, 100 },
1035 .hback_porch = { 20, 50, 100 },
1036 .hsync_len = { 30, 100, 200 },
1037 .vactive = { 800, 800, 800 },
1038 .vfront_porch = { 2, 10, 25 },
1039 .vback_porch = { 2, 10, 25 },
1040 .vsync_len = { 4, 18, 50 },
1041 };
1042
1043 static const struct panel_desc auo_g121ean01 = {
1044 .timings = &auo_g121ean01_timing,
1045 .num_timings = 1,
1046 .bpc = 8,
1047 .size = {
1048 .width = 261,
1049 .height = 163,
1050 },
1051 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1052 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1053 };
1054
1055 static const struct display_timing auo_g133han01_timings = {
1056 .pixelclock = { 134000000, 141200000, 149000000 },
1057 .hactive = { 1920, 1920, 1920 },
1058 .hfront_porch = { 39, 58, 77 },
1059 .hback_porch = { 59, 88, 117 },
1060 .hsync_len = { 28, 42, 56 },
1061 .vactive = { 1080, 1080, 1080 },
1062 .vfront_porch = { 3, 8, 11 },
1063 .vback_porch = { 5, 14, 19 },
1064 .vsync_len = { 4, 14, 19 },
1065 };
1066
1067 static const struct panel_desc auo_g133han01 = {
1068 .timings = &auo_g133han01_timings,
1069 .num_timings = 1,
1070 .bpc = 8,
1071 .size = {
1072 .width = 293,
1073 .height = 165,
1074 },
1075 .delay = {
1076 .prepare = 200,
1077 .enable = 50,
1078 .disable = 50,
1079 .unprepare = 1000,
1080 },
1081 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1082 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1083 };
1084
1085 static const struct drm_display_mode auo_g156xtn01_mode = {
1086 .clock = 76000,
1087 .hdisplay = 1366,
1088 .hsync_start = 1366 + 33,
1089 .hsync_end = 1366 + 33 + 67,
1090 .htotal = 1560,
1091 .vdisplay = 768,
1092 .vsync_start = 768 + 4,
1093 .vsync_end = 768 + 4 + 4,
1094 .vtotal = 806,
1095 };
1096
1097 static const struct panel_desc auo_g156xtn01 = {
1098 .modes = &auo_g156xtn01_mode,
1099 .num_modes = 1,
1100 .bpc = 8,
1101 .size = {
1102 .width = 344,
1103 .height = 194,
1104 },
1105 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1106 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1107 };
1108
1109 static const struct display_timing auo_g185han01_timings = {
1110 .pixelclock = { 120000000, 144000000, 175000000 },
1111 .hactive = { 1920, 1920, 1920 },
1112 .hfront_porch = { 36, 120, 148 },
1113 .hback_porch = { 24, 88, 108 },
1114 .hsync_len = { 20, 48, 64 },
1115 .vactive = { 1080, 1080, 1080 },
1116 .vfront_porch = { 6, 10, 40 },
1117 .vback_porch = { 2, 5, 20 },
1118 .vsync_len = { 2, 5, 20 },
1119 };
1120
1121 static const struct panel_desc auo_g185han01 = {
1122 .timings = &auo_g185han01_timings,
1123 .num_timings = 1,
1124 .bpc = 8,
1125 .size = {
1126 .width = 409,
1127 .height = 230,
1128 },
1129 .delay = {
1130 .prepare = 50,
1131 .enable = 200,
1132 .disable = 110,
1133 .unprepare = 1000,
1134 },
1135 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1136 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1137 };
1138
1139 static const struct display_timing auo_g190ean01_timings = {
1140 .pixelclock = { 90000000, 108000000, 135000000 },
1141 .hactive = { 1280, 1280, 1280 },
1142 .hfront_porch = { 126, 184, 1266 },
1143 .hback_porch = { 84, 122, 844 },
1144 .hsync_len = { 70, 102, 704 },
1145 .vactive = { 1024, 1024, 1024 },
1146 .vfront_porch = { 4, 26, 76 },
1147 .vback_porch = { 2, 8, 25 },
1148 .vsync_len = { 2, 8, 25 },
1149 };
1150
1151 static const struct panel_desc auo_g190ean01 = {
1152 .timings = &auo_g190ean01_timings,
1153 .num_timings = 1,
1154 .bpc = 8,
1155 .size = {
1156 .width = 376,
1157 .height = 301,
1158 },
1159 .delay = {
1160 .prepare = 50,
1161 .enable = 200,
1162 .disable = 110,
1163 .unprepare = 1000,
1164 },
1165 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1166 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1167 };
1168
1169 static const struct display_timing auo_p320hvn03_timings = {
1170 .pixelclock = { 106000000, 148500000, 164000000 },
1171 .hactive = { 1920, 1920, 1920 },
1172 .hfront_porch = { 25, 50, 130 },
1173 .hback_porch = { 25, 50, 130 },
1174 .hsync_len = { 20, 40, 105 },
1175 .vactive = { 1080, 1080, 1080 },
1176 .vfront_porch = { 8, 17, 150 },
1177 .vback_porch = { 8, 17, 150 },
1178 .vsync_len = { 4, 11, 100 },
1179 };
1180
1181 static const struct panel_desc auo_p320hvn03 = {
1182 .timings = &auo_p320hvn03_timings,
1183 .num_timings = 1,
1184 .bpc = 8,
1185 .size = {
1186 .width = 698,
1187 .height = 393,
1188 },
1189 .delay = {
1190 .prepare = 1,
1191 .enable = 450,
1192 .unprepare = 500,
1193 },
1194 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1195 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1196 };
1197
1198 static const struct drm_display_mode auo_t215hvn01_mode = {
1199 .clock = 148800,
1200 .hdisplay = 1920,
1201 .hsync_start = 1920 + 88,
1202 .hsync_end = 1920 + 88 + 44,
1203 .htotal = 1920 + 88 + 44 + 148,
1204 .vdisplay = 1080,
1205 .vsync_start = 1080 + 4,
1206 .vsync_end = 1080 + 4 + 5,
1207 .vtotal = 1080 + 4 + 5 + 36,
1208 };
1209
1210 static const struct panel_desc auo_t215hvn01 = {
1211 .modes = &auo_t215hvn01_mode,
1212 .num_modes = 1,
1213 .bpc = 8,
1214 .size = {
1215 .width = 430,
1216 .height = 270,
1217 },
1218 .delay = {
1219 .disable = 5,
1220 .unprepare = 1000,
1221 },
1222 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1223 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1224 };
1225
1226 static const struct drm_display_mode avic_tm070ddh03_mode = {
1227 .clock = 51200,
1228 .hdisplay = 1024,
1229 .hsync_start = 1024 + 160,
1230 .hsync_end = 1024 + 160 + 4,
1231 .htotal = 1024 + 160 + 4 + 156,
1232 .vdisplay = 600,
1233 .vsync_start = 600 + 17,
1234 .vsync_end = 600 + 17 + 1,
1235 .vtotal = 600 + 17 + 1 + 17,
1236 };
1237
1238 static const struct panel_desc avic_tm070ddh03 = {
1239 .modes = &avic_tm070ddh03_mode,
1240 .num_modes = 1,
1241 .bpc = 8,
1242 .size = {
1243 .width = 154,
1244 .height = 90,
1245 },
1246 .delay = {
1247 .prepare = 20,
1248 .enable = 200,
1249 .disable = 200,
1250 },
1251 };
1252
1253 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
1254 .clock = 30000,
1255 .hdisplay = 800,
1256 .hsync_start = 800 + 40,
1257 .hsync_end = 800 + 40 + 48,
1258 .htotal = 800 + 40 + 48 + 40,
1259 .vdisplay = 480,
1260 .vsync_start = 480 + 13,
1261 .vsync_end = 480 + 13 + 3,
1262 .vtotal = 480 + 13 + 3 + 29,
1263 };
1264
1265 static const struct panel_desc bananapi_s070wv20_ct16 = {
1266 .modes = &bananapi_s070wv20_ct16_mode,
1267 .num_modes = 1,
1268 .bpc = 6,
1269 .size = {
1270 .width = 154,
1271 .height = 86,
1272 },
1273 };
1274
1275 static const struct display_timing boe_ev121wxm_n10_1850_timing = {
1276 .pixelclock = { 69922000, 71000000, 72293000 },
1277 .hactive = { 1280, 1280, 1280 },
1278 .hfront_porch = { 48, 48, 48 },
1279 .hback_porch = { 80, 80, 80 },
1280 .hsync_len = { 32, 32, 32 },
1281 .vactive = { 800, 800, 800 },
1282 .vfront_porch = { 3, 3, 3 },
1283 .vback_porch = { 14, 14, 14 },
1284 .vsync_len = { 6, 6, 6 },
1285 };
1286
1287 static const struct panel_desc boe_ev121wxm_n10_1850 = {
1288 .timings = &boe_ev121wxm_n10_1850_timing,
1289 .num_timings = 1,
1290 .bpc = 8,
1291 .size = {
1292 .width = 261,
1293 .height = 163,
1294 },
1295 .delay = {
1296 .prepare = 9,
1297 .enable = 300,
1298 .unprepare = 300,
1299 .disable = 560,
1300 },
1301 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1302 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1303 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1304 };
1305
1306 static const struct drm_display_mode boe_hv070wsa_mode = {
1307 .clock = 42105,
1308 .hdisplay = 1024,
1309 .hsync_start = 1024 + 30,
1310 .hsync_end = 1024 + 30 + 30,
1311 .htotal = 1024 + 30 + 30 + 30,
1312 .vdisplay = 600,
1313 .vsync_start = 600 + 10,
1314 .vsync_end = 600 + 10 + 10,
1315 .vtotal = 600 + 10 + 10 + 10,
1316 };
1317
1318 static const struct panel_desc boe_hv070wsa = {
1319 .modes = &boe_hv070wsa_mode,
1320 .num_modes = 1,
1321 .bpc = 8,
1322 .size = {
1323 .width = 154,
1324 .height = 90,
1325 },
1326 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1327 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1328 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1329 };
1330
1331 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1332 .clock = 9000,
1333 .hdisplay = 480,
1334 .hsync_start = 480 + 5,
1335 .hsync_end = 480 + 5 + 5,
1336 .htotal = 480 + 5 + 5 + 40,
1337 .vdisplay = 272,
1338 .vsync_start = 272 + 8,
1339 .vsync_end = 272 + 8 + 8,
1340 .vtotal = 272 + 8 + 8 + 8,
1341 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1342 };
1343
1344 static const struct panel_desc cdtech_s043wq26h_ct7 = {
1345 .modes = &cdtech_s043wq26h_ct7_mode,
1346 .num_modes = 1,
1347 .bpc = 8,
1348 .size = {
1349 .width = 95,
1350 .height = 54,
1351 },
1352 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1353 };
1354
1355 /* S070PWS19HP-FC21 2017/04/22 */
1356 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = {
1357 .clock = 51200,
1358 .hdisplay = 1024,
1359 .hsync_start = 1024 + 160,
1360 .hsync_end = 1024 + 160 + 20,
1361 .htotal = 1024 + 160 + 20 + 140,
1362 .vdisplay = 600,
1363 .vsync_start = 600 + 12,
1364 .vsync_end = 600 + 12 + 3,
1365 .vtotal = 600 + 12 + 3 + 20,
1366 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1367 };
1368
1369 static const struct panel_desc cdtech_s070pws19hp_fc21 = {
1370 .modes = &cdtech_s070pws19hp_fc21_mode,
1371 .num_modes = 1,
1372 .bpc = 6,
1373 .size = {
1374 .width = 154,
1375 .height = 86,
1376 },
1377 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1378 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1379 .connector_type = DRM_MODE_CONNECTOR_DPI,
1380 };
1381
1382 /* S070SWV29HG-DC44 2017/09/21 */
1383 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = {
1384 .clock = 33300,
1385 .hdisplay = 800,
1386 .hsync_start = 800 + 210,
1387 .hsync_end = 800 + 210 + 2,
1388 .htotal = 800 + 210 + 2 + 44,
1389 .vdisplay = 480,
1390 .vsync_start = 480 + 22,
1391 .vsync_end = 480 + 22 + 2,
1392 .vtotal = 480 + 22 + 2 + 21,
1393 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1394 };
1395
1396 static const struct panel_desc cdtech_s070swv29hg_dc44 = {
1397 .modes = &cdtech_s070swv29hg_dc44_mode,
1398 .num_modes = 1,
1399 .bpc = 6,
1400 .size = {
1401 .width = 154,
1402 .height = 86,
1403 },
1404 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1405 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1406 .connector_type = DRM_MODE_CONNECTOR_DPI,
1407 };
1408
1409 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1410 .clock = 35000,
1411 .hdisplay = 800,
1412 .hsync_start = 800 + 40,
1413 .hsync_end = 800 + 40 + 40,
1414 .htotal = 800 + 40 + 40 + 48,
1415 .vdisplay = 480,
1416 .vsync_start = 480 + 29,
1417 .vsync_end = 480 + 29 + 13,
1418 .vtotal = 480 + 29 + 13 + 3,
1419 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1420 };
1421
1422 static const struct panel_desc cdtech_s070wv95_ct16 = {
1423 .modes = &cdtech_s070wv95_ct16_mode,
1424 .num_modes = 1,
1425 .bpc = 8,
1426 .size = {
1427 .width = 154,
1428 .height = 85,
1429 },
1430 };
1431
1432 static const struct display_timing chefree_ch101olhlwh_002_timing = {
1433 .pixelclock = { 68900000, 71100000, 73400000 },
1434 .hactive = { 1280, 1280, 1280 },
1435 .hfront_porch = { 65, 80, 95 },
1436 .hback_porch = { 64, 79, 94 },
1437 .hsync_len = { 1, 1, 1 },
1438 .vactive = { 800, 800, 800 },
1439 .vfront_porch = { 7, 11, 14 },
1440 .vback_porch = { 7, 11, 14 },
1441 .vsync_len = { 1, 1, 1 },
1442 .flags = DISPLAY_FLAGS_DE_HIGH,
1443 };
1444
1445 static const struct panel_desc chefree_ch101olhlwh_002 = {
1446 .timings = &chefree_ch101olhlwh_002_timing,
1447 .num_timings = 1,
1448 .bpc = 8,
1449 .size = {
1450 .width = 217,
1451 .height = 135,
1452 },
1453 .delay = {
1454 .enable = 200,
1455 .disable = 200,
1456 },
1457 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1458 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1459 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1460 };
1461
1462 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1463 .clock = 66770,
1464 .hdisplay = 800,
1465 .hsync_start = 800 + 49,
1466 .hsync_end = 800 + 49 + 33,
1467 .htotal = 800 + 49 + 33 + 17,
1468 .vdisplay = 1280,
1469 .vsync_start = 1280 + 1,
1470 .vsync_end = 1280 + 1 + 7,
1471 .vtotal = 1280 + 1 + 7 + 15,
1472 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1473 };
1474
1475 static const struct panel_desc chunghwa_claa070wp03xg = {
1476 .modes = &chunghwa_claa070wp03xg_mode,
1477 .num_modes = 1,
1478 .bpc = 6,
1479 .size = {
1480 .width = 94,
1481 .height = 150,
1482 },
1483 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1484 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1485 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1486 };
1487
1488 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1489 .clock = 72070,
1490 .hdisplay = 1366,
1491 .hsync_start = 1366 + 58,
1492 .hsync_end = 1366 + 58 + 58,
1493 .htotal = 1366 + 58 + 58 + 58,
1494 .vdisplay = 768,
1495 .vsync_start = 768 + 4,
1496 .vsync_end = 768 + 4 + 4,
1497 .vtotal = 768 + 4 + 4 + 4,
1498 };
1499
1500 static const struct panel_desc chunghwa_claa101wa01a = {
1501 .modes = &chunghwa_claa101wa01a_mode,
1502 .num_modes = 1,
1503 .bpc = 6,
1504 .size = {
1505 .width = 220,
1506 .height = 120,
1507 },
1508 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1509 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1510 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1511 };
1512
1513 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1514 .clock = 69300,
1515 .hdisplay = 1366,
1516 .hsync_start = 1366 + 48,
1517 .hsync_end = 1366 + 48 + 32,
1518 .htotal = 1366 + 48 + 32 + 20,
1519 .vdisplay = 768,
1520 .vsync_start = 768 + 16,
1521 .vsync_end = 768 + 16 + 8,
1522 .vtotal = 768 + 16 + 8 + 16,
1523 };
1524
1525 static const struct panel_desc chunghwa_claa101wb01 = {
1526 .modes = &chunghwa_claa101wb01_mode,
1527 .num_modes = 1,
1528 .bpc = 6,
1529 .size = {
1530 .width = 223,
1531 .height = 125,
1532 },
1533 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1534 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1535 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1536 };
1537
1538 static const struct display_timing dataimage_fg040346dsswbg04_timing = {
1539 .pixelclock = { 5000000, 9000000, 12000000 },
1540 .hactive = { 480, 480, 480 },
1541 .hfront_porch = { 12, 12, 12 },
1542 .hback_porch = { 12, 12, 12 },
1543 .hsync_len = { 21, 21, 21 },
1544 .vactive = { 272, 272, 272 },
1545 .vfront_porch = { 4, 4, 4 },
1546 .vback_porch = { 4, 4, 4 },
1547 .vsync_len = { 8, 8, 8 },
1548 };
1549
1550 static const struct panel_desc dataimage_fg040346dsswbg04 = {
1551 .timings = &dataimage_fg040346dsswbg04_timing,
1552 .num_timings = 1,
1553 .bpc = 8,
1554 .size = {
1555 .width = 95,
1556 .height = 54,
1557 },
1558 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1559 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1560 .connector_type = DRM_MODE_CONNECTOR_DPI,
1561 };
1562
1563 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = {
1564 .pixelclock = { 68900000, 71110000, 73400000 },
1565 .hactive = { 1280, 1280, 1280 },
1566 .vactive = { 800, 800, 800 },
1567 .hback_porch = { 100, 100, 100 },
1568 .hfront_porch = { 100, 100, 100 },
1569 .vback_porch = { 5, 5, 5 },
1570 .vfront_porch = { 5, 5, 5 },
1571 .hsync_len = { 24, 24, 24 },
1572 .vsync_len = { 3, 3, 3 },
1573 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
1574 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1575 };
1576
1577 static const struct panel_desc dataimage_fg1001l0dsswmg01 = {
1578 .timings = &dataimage_fg1001l0dsswmg01_timing,
1579 .num_timings = 1,
1580 .bpc = 8,
1581 .size = {
1582 .width = 217,
1583 .height = 136,
1584 },
1585 };
1586
1587 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1588 .clock = 33260,
1589 .hdisplay = 800,
1590 .hsync_start = 800 + 40,
1591 .hsync_end = 800 + 40 + 128,
1592 .htotal = 800 + 40 + 128 + 88,
1593 .vdisplay = 480,
1594 .vsync_start = 480 + 10,
1595 .vsync_end = 480 + 10 + 2,
1596 .vtotal = 480 + 10 + 2 + 33,
1597 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1598 };
1599
1600 static const struct panel_desc dataimage_scf0700c48ggu18 = {
1601 .modes = &dataimage_scf0700c48ggu18_mode,
1602 .num_modes = 1,
1603 .bpc = 8,
1604 .size = {
1605 .width = 152,
1606 .height = 91,
1607 },
1608 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1609 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1610 };
1611
1612 static const struct display_timing dlc_dlc0700yzg_1_timing = {
1613 .pixelclock = { 45000000, 51200000, 57000000 },
1614 .hactive = { 1024, 1024, 1024 },
1615 .hfront_porch = { 100, 106, 113 },
1616 .hback_porch = { 100, 106, 113 },
1617 .hsync_len = { 100, 108, 114 },
1618 .vactive = { 600, 600, 600 },
1619 .vfront_porch = { 8, 11, 15 },
1620 .vback_porch = { 8, 11, 15 },
1621 .vsync_len = { 9, 13, 15 },
1622 .flags = DISPLAY_FLAGS_DE_HIGH,
1623 };
1624
1625 static const struct panel_desc dlc_dlc0700yzg_1 = {
1626 .timings = &dlc_dlc0700yzg_1_timing,
1627 .num_timings = 1,
1628 .bpc = 6,
1629 .size = {
1630 .width = 154,
1631 .height = 86,
1632 },
1633 .delay = {
1634 .prepare = 30,
1635 .enable = 200,
1636 .disable = 200,
1637 },
1638 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1639 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1640 };
1641
1642 static const struct display_timing dlc_dlc1010gig_timing = {
1643 .pixelclock = { 68900000, 71100000, 73400000 },
1644 .hactive = { 1280, 1280, 1280 },
1645 .hfront_porch = { 43, 53, 63 },
1646 .hback_porch = { 43, 53, 63 },
1647 .hsync_len = { 44, 54, 64 },
1648 .vactive = { 800, 800, 800 },
1649 .vfront_porch = { 5, 8, 11 },
1650 .vback_porch = { 5, 8, 11 },
1651 .vsync_len = { 5, 7, 11 },
1652 .flags = DISPLAY_FLAGS_DE_HIGH,
1653 };
1654
1655 static const struct panel_desc dlc_dlc1010gig = {
1656 .timings = &dlc_dlc1010gig_timing,
1657 .num_timings = 1,
1658 .bpc = 8,
1659 .size = {
1660 .width = 216,
1661 .height = 135,
1662 },
1663 .delay = {
1664 .prepare = 60,
1665 .enable = 150,
1666 .disable = 100,
1667 .unprepare = 60,
1668 },
1669 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1670 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1671 };
1672
1673 static const struct drm_display_mode edt_et035012dm6_mode = {
1674 .clock = 6500,
1675 .hdisplay = 320,
1676 .hsync_start = 320 + 20,
1677 .hsync_end = 320 + 20 + 30,
1678 .htotal = 320 + 20 + 68,
1679 .vdisplay = 240,
1680 .vsync_start = 240 + 4,
1681 .vsync_end = 240 + 4 + 4,
1682 .vtotal = 240 + 4 + 4 + 14,
1683 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1684 };
1685
1686 static const struct panel_desc edt_et035012dm6 = {
1687 .modes = &edt_et035012dm6_mode,
1688 .num_modes = 1,
1689 .bpc = 8,
1690 .size = {
1691 .width = 70,
1692 .height = 52,
1693 },
1694 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1695 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1696 };
1697
1698 static const struct drm_display_mode edt_etm0350g0dh6_mode = {
1699 .clock = 6520,
1700 .hdisplay = 320,
1701 .hsync_start = 320 + 20,
1702 .hsync_end = 320 + 20 + 68,
1703 .htotal = 320 + 20 + 68,
1704 .vdisplay = 240,
1705 .vsync_start = 240 + 4,
1706 .vsync_end = 240 + 4 + 18,
1707 .vtotal = 240 + 4 + 18,
1708 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1709 };
1710
1711 static const struct panel_desc edt_etm0350g0dh6 = {
1712 .modes = &edt_etm0350g0dh6_mode,
1713 .num_modes = 1,
1714 .bpc = 6,
1715 .size = {
1716 .width = 70,
1717 .height = 53,
1718 },
1719 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1720 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1721 .connector_type = DRM_MODE_CONNECTOR_DPI,
1722 };
1723
1724 static const struct drm_display_mode edt_etm043080dh6gp_mode = {
1725 .clock = 10870,
1726 .hdisplay = 480,
1727 .hsync_start = 480 + 8,
1728 .hsync_end = 480 + 8 + 4,
1729 .htotal = 480 + 8 + 4 + 41,
1730
1731 /*
1732 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while
1733 * fb_align
1734 */
1735
1736 .vdisplay = 288,
1737 .vsync_start = 288 + 2,
1738 .vsync_end = 288 + 2 + 4,
1739 .vtotal = 288 + 2 + 4 + 10,
1740 };
1741
1742 static const struct panel_desc edt_etm043080dh6gp = {
1743 .modes = &edt_etm043080dh6gp_mode,
1744 .num_modes = 1,
1745 .bpc = 8,
1746 .size = {
1747 .width = 100,
1748 .height = 65,
1749 },
1750 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1751 .connector_type = DRM_MODE_CONNECTOR_DPI,
1752 };
1753
1754 static const struct drm_display_mode edt_etm0430g0dh6_mode = {
1755 .clock = 9000,
1756 .hdisplay = 480,
1757 .hsync_start = 480 + 2,
1758 .hsync_end = 480 + 2 + 41,
1759 .htotal = 480 + 2 + 41 + 2,
1760 .vdisplay = 272,
1761 .vsync_start = 272 + 2,
1762 .vsync_end = 272 + 2 + 10,
1763 .vtotal = 272 + 2 + 10 + 2,
1764 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1765 };
1766
1767 static const struct panel_desc edt_etm0430g0dh6 = {
1768 .modes = &edt_etm0430g0dh6_mode,
1769 .num_modes = 1,
1770 .bpc = 6,
1771 .size = {
1772 .width = 95,
1773 .height = 54,
1774 },
1775 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1776 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1777 .connector_type = DRM_MODE_CONNECTOR_DPI,
1778 };
1779
1780 static const struct drm_display_mode edt_et057090dhu_mode = {
1781 .clock = 25175,
1782 .hdisplay = 640,
1783 .hsync_start = 640 + 16,
1784 .hsync_end = 640 + 16 + 30,
1785 .htotal = 640 + 16 + 30 + 114,
1786 .vdisplay = 480,
1787 .vsync_start = 480 + 10,
1788 .vsync_end = 480 + 10 + 3,
1789 .vtotal = 480 + 10 + 3 + 32,
1790 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1791 };
1792
1793 static const struct panel_desc edt_et057090dhu = {
1794 .modes = &edt_et057090dhu_mode,
1795 .num_modes = 1,
1796 .bpc = 6,
1797 .size = {
1798 .width = 115,
1799 .height = 86,
1800 },
1801 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1802 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1803 .connector_type = DRM_MODE_CONNECTOR_DPI,
1804 };
1805
1806 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1807 .clock = 33260,
1808 .hdisplay = 800,
1809 .hsync_start = 800 + 40,
1810 .hsync_end = 800 + 40 + 128,
1811 .htotal = 800 + 40 + 128 + 88,
1812 .vdisplay = 480,
1813 .vsync_start = 480 + 10,
1814 .vsync_end = 480 + 10 + 2,
1815 .vtotal = 480 + 10 + 2 + 33,
1816 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1817 };
1818
1819 static const struct panel_desc edt_etm0700g0dh6 = {
1820 .modes = &edt_etm0700g0dh6_mode,
1821 .num_modes = 1,
1822 .bpc = 6,
1823 .size = {
1824 .width = 152,
1825 .height = 91,
1826 },
1827 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1828 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1829 .connector_type = DRM_MODE_CONNECTOR_DPI,
1830 };
1831
1832 static const struct panel_desc edt_etm0700g0bdh6 = {
1833 .modes = &edt_etm0700g0dh6_mode,
1834 .num_modes = 1,
1835 .bpc = 6,
1836 .size = {
1837 .width = 152,
1838 .height = 91,
1839 },
1840 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1841 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1842 .connector_type = DRM_MODE_CONNECTOR_DPI,
1843 };
1844
1845 static const struct display_timing edt_etml0700y5dha_timing = {
1846 .pixelclock = { 40800000, 51200000, 67200000 },
1847 .hactive = { 1024, 1024, 1024 },
1848 .hfront_porch = { 30, 106, 125 },
1849 .hback_porch = { 30, 106, 125 },
1850 .hsync_len = { 30, 108, 126 },
1851 .vactive = { 600, 600, 600 },
1852 .vfront_porch = { 3, 12, 67},
1853 .vback_porch = { 3, 12, 67 },
1854 .vsync_len = { 4, 11, 66 },
1855 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
1856 DISPLAY_FLAGS_DE_HIGH,
1857 };
1858
1859 static const struct panel_desc edt_etml0700y5dha = {
1860 .timings = &edt_etml0700y5dha_timing,
1861 .num_timings = 1,
1862 .bpc = 8,
1863 .size = {
1864 .width = 155,
1865 .height = 86,
1866 },
1867 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1868 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1869 };
1870
1871 static const struct drm_display_mode edt_etmv570g2dhu_mode = {
1872 .clock = 25175,
1873 .hdisplay = 640,
1874 .hsync_start = 640,
1875 .hsync_end = 640 + 16,
1876 .htotal = 640 + 16 + 30 + 114,
1877 .vdisplay = 480,
1878 .vsync_start = 480 + 10,
1879 .vsync_end = 480 + 10 + 3,
1880 .vtotal = 480 + 10 + 3 + 35,
1881 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC,
1882 };
1883
1884 static const struct panel_desc edt_etmv570g2dhu = {
1885 .modes = &edt_etmv570g2dhu_mode,
1886 .num_modes = 1,
1887 .bpc = 6,
1888 .size = {
1889 .width = 115,
1890 .height = 86,
1891 },
1892 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1893 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1894 .connector_type = DRM_MODE_CONNECTOR_DPI,
1895 };
1896
1897 static const struct display_timing eink_vb3300_kca_timing = {
1898 .pixelclock = { 40000000, 40000000, 40000000 },
1899 .hactive = { 334, 334, 334 },
1900 .hfront_porch = { 1, 1, 1 },
1901 .hback_porch = { 1, 1, 1 },
1902 .hsync_len = { 1, 1, 1 },
1903 .vactive = { 1405, 1405, 1405 },
1904 .vfront_porch = { 1, 1, 1 },
1905 .vback_porch = { 1, 1, 1 },
1906 .vsync_len = { 1, 1, 1 },
1907 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
1908 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
1909 };
1910
1911 static const struct panel_desc eink_vb3300_kca = {
1912 .timings = &eink_vb3300_kca_timing,
1913 .num_timings = 1,
1914 .bpc = 6,
1915 .size = {
1916 .width = 157,
1917 .height = 209,
1918 },
1919 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1920 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1921 .connector_type = DRM_MODE_CONNECTOR_DPI,
1922 };
1923
1924 static const struct display_timing evervision_vgg804821_timing = {
1925 .pixelclock = { 27600000, 33300000, 50000000 },
1926 .hactive = { 800, 800, 800 },
1927 .hfront_porch = { 40, 66, 70 },
1928 .hback_porch = { 40, 67, 70 },
1929 .hsync_len = { 40, 67, 70 },
1930 .vactive = { 480, 480, 480 },
1931 .vfront_porch = { 6, 10, 10 },
1932 .vback_porch = { 7, 11, 11 },
1933 .vsync_len = { 7, 11, 11 },
1934 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
1935 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1936 DISPLAY_FLAGS_SYNC_NEGEDGE,
1937 };
1938
1939 static const struct panel_desc evervision_vgg804821 = {
1940 .timings = &evervision_vgg804821_timing,
1941 .num_timings = 1,
1942 .bpc = 8,
1943 .size = {
1944 .width = 108,
1945 .height = 64,
1946 },
1947 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1948 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1949 };
1950
1951 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1952 .clock = 32260,
1953 .hdisplay = 800,
1954 .hsync_start = 800 + 168,
1955 .hsync_end = 800 + 168 + 64,
1956 .htotal = 800 + 168 + 64 + 88,
1957 .vdisplay = 480,
1958 .vsync_start = 480 + 37,
1959 .vsync_end = 480 + 37 + 2,
1960 .vtotal = 480 + 37 + 2 + 8,
1961 };
1962
1963 static const struct panel_desc foxlink_fl500wvr00_a0t = {
1964 .modes = &foxlink_fl500wvr00_a0t_mode,
1965 .num_modes = 1,
1966 .bpc = 8,
1967 .size = {
1968 .width = 108,
1969 .height = 65,
1970 },
1971 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1972 };
1973
1974 static const struct drm_display_mode frida_frd350h54004_modes[] = {
1975 { /* 60 Hz */
1976 .clock = 6000,
1977 .hdisplay = 320,
1978 .hsync_start = 320 + 44,
1979 .hsync_end = 320 + 44 + 16,
1980 .htotal = 320 + 44 + 16 + 20,
1981 .vdisplay = 240,
1982 .vsync_start = 240 + 2,
1983 .vsync_end = 240 + 2 + 6,
1984 .vtotal = 240 + 2 + 6 + 2,
1985 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1986 },
1987 { /* 50 Hz */
1988 .clock = 5400,
1989 .hdisplay = 320,
1990 .hsync_start = 320 + 56,
1991 .hsync_end = 320 + 56 + 16,
1992 .htotal = 320 + 56 + 16 + 40,
1993 .vdisplay = 240,
1994 .vsync_start = 240 + 2,
1995 .vsync_end = 240 + 2 + 6,
1996 .vtotal = 240 + 2 + 6 + 2,
1997 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1998 },
1999 };
2000
2001 static const struct panel_desc frida_frd350h54004 = {
2002 .modes = frida_frd350h54004_modes,
2003 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes),
2004 .bpc = 8,
2005 .size = {
2006 .width = 77,
2007 .height = 64,
2008 },
2009 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2010 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2011 .connector_type = DRM_MODE_CONNECTOR_DPI,
2012 };
2013
2014 static const struct drm_display_mode friendlyarm_hd702e_mode = {
2015 .clock = 67185,
2016 .hdisplay = 800,
2017 .hsync_start = 800 + 20,
2018 .hsync_end = 800 + 20 + 24,
2019 .htotal = 800 + 20 + 24 + 20,
2020 .vdisplay = 1280,
2021 .vsync_start = 1280 + 4,
2022 .vsync_end = 1280 + 4 + 8,
2023 .vtotal = 1280 + 4 + 8 + 4,
2024 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2025 };
2026
2027 static const struct panel_desc friendlyarm_hd702e = {
2028 .modes = &friendlyarm_hd702e_mode,
2029 .num_modes = 1,
2030 .size = {
2031 .width = 94,
2032 .height = 151,
2033 },
2034 };
2035
2036 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
2037 .clock = 9000,
2038 .hdisplay = 480,
2039 .hsync_start = 480 + 5,
2040 .hsync_end = 480 + 5 + 1,
2041 .htotal = 480 + 5 + 1 + 40,
2042 .vdisplay = 272,
2043 .vsync_start = 272 + 8,
2044 .vsync_end = 272 + 8 + 1,
2045 .vtotal = 272 + 8 + 1 + 8,
2046 };
2047
2048 static const struct panel_desc giantplus_gpg482739qs5 = {
2049 .modes = &giantplus_gpg482739qs5_mode,
2050 .num_modes = 1,
2051 .bpc = 8,
2052 .size = {
2053 .width = 95,
2054 .height = 54,
2055 },
2056 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2057 };
2058
2059 static const struct display_timing giantplus_gpm940b0_timing = {
2060 .pixelclock = { 13500000, 27000000, 27500000 },
2061 .hactive = { 320, 320, 320 },
2062 .hfront_porch = { 14, 686, 718 },
2063 .hback_porch = { 50, 70, 255 },
2064 .hsync_len = { 1, 1, 1 },
2065 .vactive = { 240, 240, 240 },
2066 .vfront_porch = { 1, 1, 179 },
2067 .vback_porch = { 1, 21, 31 },
2068 .vsync_len = { 1, 1, 6 },
2069 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
2070 };
2071
2072 static const struct panel_desc giantplus_gpm940b0 = {
2073 .timings = &giantplus_gpm940b0_timing,
2074 .num_timings = 1,
2075 .bpc = 8,
2076 .size = {
2077 .width = 60,
2078 .height = 45,
2079 },
2080 .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
2081 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
2082 };
2083
2084 static const struct display_timing hannstar_hsd070pww1_timing = {
2085 .pixelclock = { 64300000, 71100000, 82000000 },
2086 .hactive = { 1280, 1280, 1280 },
2087 .hfront_porch = { 1, 1, 10 },
2088 .hback_porch = { 1, 1, 10 },
2089 /*
2090 * According to the data sheet, the minimum horizontal blanking interval
2091 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
2092 * minimum working horizontal blanking interval to be 60 clocks.
2093 */
2094 .hsync_len = { 58, 158, 661 },
2095 .vactive = { 800, 800, 800 },
2096 .vfront_porch = { 1, 1, 10 },
2097 .vback_porch = { 1, 1, 10 },
2098 .vsync_len = { 1, 21, 203 },
2099 .flags = DISPLAY_FLAGS_DE_HIGH,
2100 };
2101
2102 static const struct panel_desc hannstar_hsd070pww1 = {
2103 .timings = &hannstar_hsd070pww1_timing,
2104 .num_timings = 1,
2105 .bpc = 6,
2106 .size = {
2107 .width = 151,
2108 .height = 94,
2109 },
2110 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2111 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2112 };
2113
2114 static const struct display_timing hannstar_hsd100pxn1_timing = {
2115 .pixelclock = { 55000000, 65000000, 75000000 },
2116 .hactive = { 1024, 1024, 1024 },
2117 .hfront_porch = { 40, 40, 40 },
2118 .hback_porch = { 220, 220, 220 },
2119 .hsync_len = { 20, 60, 100 },
2120 .vactive = { 768, 768, 768 },
2121 .vfront_porch = { 7, 7, 7 },
2122 .vback_porch = { 21, 21, 21 },
2123 .vsync_len = { 10, 10, 10 },
2124 .flags = DISPLAY_FLAGS_DE_HIGH,
2125 };
2126
2127 static const struct panel_desc hannstar_hsd100pxn1 = {
2128 .timings = &hannstar_hsd100pxn1_timing,
2129 .num_timings = 1,
2130 .bpc = 6,
2131 .size = {
2132 .width = 203,
2133 .height = 152,
2134 },
2135 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2136 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2137 };
2138
2139 static const struct display_timing hannstar_hsd101pww2_timing = {
2140 .pixelclock = { 64300000, 71100000, 82000000 },
2141 .hactive = { 1280, 1280, 1280 },
2142 .hfront_porch = { 1, 1, 10 },
2143 .hback_porch = { 1, 1, 10 },
2144 .hsync_len = { 58, 158, 661 },
2145 .vactive = { 800, 800, 800 },
2146 .vfront_porch = { 1, 1, 10 },
2147 .vback_porch = { 1, 1, 10 },
2148 .vsync_len = { 1, 21, 203 },
2149 .flags = DISPLAY_FLAGS_DE_HIGH,
2150 };
2151
2152 static const struct panel_desc hannstar_hsd101pww2 = {
2153 .timings = &hannstar_hsd101pww2_timing,
2154 .num_timings = 1,
2155 .bpc = 8,
2156 .size = {
2157 .width = 217,
2158 .height = 136,
2159 },
2160 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2161 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2162 };
2163
2164 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
2165 .clock = 33333,
2166 .hdisplay = 800,
2167 .hsync_start = 800 + 85,
2168 .hsync_end = 800 + 85 + 86,
2169 .htotal = 800 + 85 + 86 + 85,
2170 .vdisplay = 480,
2171 .vsync_start = 480 + 16,
2172 .vsync_end = 480 + 16 + 13,
2173 .vtotal = 480 + 16 + 13 + 16,
2174 };
2175
2176 static const struct panel_desc hitachi_tx23d38vm0caa = {
2177 .modes = &hitachi_tx23d38vm0caa_mode,
2178 .num_modes = 1,
2179 .bpc = 6,
2180 .size = {
2181 .width = 195,
2182 .height = 117,
2183 },
2184 .delay = {
2185 .enable = 160,
2186 .disable = 160,
2187 },
2188 };
2189
2190 static const struct drm_display_mode innolux_at043tn24_mode = {
2191 .clock = 9000,
2192 .hdisplay = 480,
2193 .hsync_start = 480 + 2,
2194 .hsync_end = 480 + 2 + 41,
2195 .htotal = 480 + 2 + 41 + 2,
2196 .vdisplay = 272,
2197 .vsync_start = 272 + 2,
2198 .vsync_end = 272 + 2 + 10,
2199 .vtotal = 272 + 2 + 10 + 2,
2200 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2201 };
2202
2203 static const struct panel_desc innolux_at043tn24 = {
2204 .modes = &innolux_at043tn24_mode,
2205 .num_modes = 1,
2206 .bpc = 8,
2207 .size = {
2208 .width = 95,
2209 .height = 54,
2210 },
2211 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2212 .connector_type = DRM_MODE_CONNECTOR_DPI,
2213 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2214 };
2215
2216 static const struct drm_display_mode innolux_at070tn92_mode = {
2217 .clock = 33333,
2218 .hdisplay = 800,
2219 .hsync_start = 800 + 210,
2220 .hsync_end = 800 + 210 + 20,
2221 .htotal = 800 + 210 + 20 + 46,
2222 .vdisplay = 480,
2223 .vsync_start = 480 + 22,
2224 .vsync_end = 480 + 22 + 10,
2225 .vtotal = 480 + 22 + 23 + 10,
2226 };
2227
2228 static const struct panel_desc innolux_at070tn92 = {
2229 .modes = &innolux_at070tn92_mode,
2230 .num_modes = 1,
2231 .size = {
2232 .width = 154,
2233 .height = 86,
2234 },
2235 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2236 };
2237
2238 static const struct display_timing innolux_g070ace_l01_timing = {
2239 .pixelclock = { 25200000, 35000000, 35700000 },
2240 .hactive = { 800, 800, 800 },
2241 .hfront_porch = { 30, 32, 87 },
2242 .hback_porch = { 30, 32, 87 },
2243 .hsync_len = { 1, 1, 1 },
2244 .vactive = { 480, 480, 480 },
2245 .vfront_porch = { 3, 3, 3 },
2246 .vback_porch = { 13, 13, 13 },
2247 .vsync_len = { 1, 1, 4 },
2248 .flags = DISPLAY_FLAGS_DE_HIGH,
2249 };
2250
2251 static const struct panel_desc innolux_g070ace_l01 = {
2252 .timings = &innolux_g070ace_l01_timing,
2253 .num_timings = 1,
2254 .bpc = 8,
2255 .size = {
2256 .width = 152,
2257 .height = 91,
2258 },
2259 .delay = {
2260 .prepare = 10,
2261 .enable = 50,
2262 .disable = 50,
2263 .unprepare = 500,
2264 },
2265 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2266 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2267 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2268 };
2269
2270 static const struct display_timing innolux_g070y2_l01_timing = {
2271 .pixelclock = { 28000000, 29500000, 32000000 },
2272 .hactive = { 800, 800, 800 },
2273 .hfront_porch = { 61, 91, 141 },
2274 .hback_porch = { 60, 90, 140 },
2275 .hsync_len = { 12, 12, 12 },
2276 .vactive = { 480, 480, 480 },
2277 .vfront_porch = { 4, 9, 30 },
2278 .vback_porch = { 4, 8, 28 },
2279 .vsync_len = { 2, 2, 2 },
2280 .flags = DISPLAY_FLAGS_DE_HIGH,
2281 };
2282
2283 static const struct panel_desc innolux_g070y2_l01 = {
2284 .timings = &innolux_g070y2_l01_timing,
2285 .num_timings = 1,
2286 .bpc = 8,
2287 .size = {
2288 .width = 152,
2289 .height = 91,
2290 },
2291 .delay = {
2292 .prepare = 10,
2293 .enable = 100,
2294 .disable = 100,
2295 .unprepare = 800,
2296 },
2297 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2298 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2299 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2300 };
2301
2302 static const struct drm_display_mode innolux_g070y2_t02_mode = {
2303 .clock = 33333,
2304 .hdisplay = 800,
2305 .hsync_start = 800 + 210,
2306 .hsync_end = 800 + 210 + 20,
2307 .htotal = 800 + 210 + 20 + 46,
2308 .vdisplay = 480,
2309 .vsync_start = 480 + 22,
2310 .vsync_end = 480 + 22 + 10,
2311 .vtotal = 480 + 22 + 23 + 10,
2312 };
2313
2314 static const struct panel_desc innolux_g070y2_t02 = {
2315 .modes = &innolux_g070y2_t02_mode,
2316 .num_modes = 1,
2317 .bpc = 8,
2318 .size = {
2319 .width = 152,
2320 .height = 92,
2321 },
2322 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2323 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2324 .connector_type = DRM_MODE_CONNECTOR_DPI,
2325 };
2326
2327 static const struct display_timing innolux_g101ice_l01_timing = {
2328 .pixelclock = { 60400000, 71100000, 74700000 },
2329 .hactive = { 1280, 1280, 1280 },
2330 .hfront_porch = { 30, 60, 70 },
2331 .hback_porch = { 30, 60, 70 },
2332 .hsync_len = { 22, 40, 60 },
2333 .vactive = { 800, 800, 800 },
2334 .vfront_porch = { 3, 8, 14 },
2335 .vback_porch = { 3, 8, 14 },
2336 .vsync_len = { 4, 7, 12 },
2337 .flags = DISPLAY_FLAGS_DE_HIGH,
2338 };
2339
2340 static const struct panel_desc innolux_g101ice_l01 = {
2341 .timings = &innolux_g101ice_l01_timing,
2342 .num_timings = 1,
2343 .bpc = 8,
2344 .size = {
2345 .width = 217,
2346 .height = 135,
2347 },
2348 .delay = {
2349 .enable = 200,
2350 .disable = 200,
2351 },
2352 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2353 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2354 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2355 };
2356
2357 static const struct display_timing innolux_g121i1_l01_timing = {
2358 .pixelclock = { 67450000, 71000000, 74550000 },
2359 .hactive = { 1280, 1280, 1280 },
2360 .hfront_porch = { 40, 80, 160 },
2361 .hback_porch = { 39, 79, 159 },
2362 .hsync_len = { 1, 1, 1 },
2363 .vactive = { 800, 800, 800 },
2364 .vfront_porch = { 5, 11, 100 },
2365 .vback_porch = { 4, 11, 99 },
2366 .vsync_len = { 1, 1, 1 },
2367 };
2368
2369 static const struct panel_desc innolux_g121i1_l01 = {
2370 .timings = &innolux_g121i1_l01_timing,
2371 .num_timings = 1,
2372 .bpc = 6,
2373 .size = {
2374 .width = 261,
2375 .height = 163,
2376 },
2377 .delay = {
2378 .enable = 200,
2379 .disable = 20,
2380 },
2381 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2382 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2383 };
2384
2385 static const struct drm_display_mode innolux_g121x1_l03_mode = {
2386 .clock = 65000,
2387 .hdisplay = 1024,
2388 .hsync_start = 1024 + 0,
2389 .hsync_end = 1024 + 1,
2390 .htotal = 1024 + 0 + 1 + 320,
2391 .vdisplay = 768,
2392 .vsync_start = 768 + 38,
2393 .vsync_end = 768 + 38 + 1,
2394 .vtotal = 768 + 38 + 1 + 0,
2395 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2396 };
2397
2398 static const struct panel_desc innolux_g121x1_l03 = {
2399 .modes = &innolux_g121x1_l03_mode,
2400 .num_modes = 1,
2401 .bpc = 6,
2402 .size = {
2403 .width = 246,
2404 .height = 185,
2405 },
2406 .delay = {
2407 .enable = 200,
2408 .unprepare = 200,
2409 .disable = 400,
2410 },
2411 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2412 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2413 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2414 };
2415
2416 static const struct display_timing innolux_g156hce_l01_timings = {
2417 .pixelclock = { 120000000, 141860000, 150000000 },
2418 .hactive = { 1920, 1920, 1920 },
2419 .hfront_porch = { 80, 90, 100 },
2420 .hback_porch = { 80, 90, 100 },
2421 .hsync_len = { 20, 30, 30 },
2422 .vactive = { 1080, 1080, 1080 },
2423 .vfront_porch = { 3, 10, 20 },
2424 .vback_porch = { 3, 10, 20 },
2425 .vsync_len = { 4, 10, 10 },
2426 };
2427
2428 static const struct panel_desc innolux_g156hce_l01 = {
2429 .timings = &innolux_g156hce_l01_timings,
2430 .num_timings = 1,
2431 .bpc = 8,
2432 .size = {
2433 .width = 344,
2434 .height = 194,
2435 },
2436 .delay = {
2437 .prepare = 1, /* T1+T2 */
2438 .enable = 450, /* T5 */
2439 .disable = 200, /* T6 */
2440 .unprepare = 10, /* T3+T7 */
2441 },
2442 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2443 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2444 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2445 };
2446
2447 static const struct drm_display_mode innolux_n156bge_l21_mode = {
2448 .clock = 69300,
2449 .hdisplay = 1366,
2450 .hsync_start = 1366 + 16,
2451 .hsync_end = 1366 + 16 + 34,
2452 .htotal = 1366 + 16 + 34 + 50,
2453 .vdisplay = 768,
2454 .vsync_start = 768 + 2,
2455 .vsync_end = 768 + 2 + 6,
2456 .vtotal = 768 + 2 + 6 + 12,
2457 };
2458
2459 static const struct panel_desc innolux_n156bge_l21 = {
2460 .modes = &innolux_n156bge_l21_mode,
2461 .num_modes = 1,
2462 .bpc = 6,
2463 .size = {
2464 .width = 344,
2465 .height = 193,
2466 },
2467 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2468 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2469 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2470 };
2471
2472 static const struct drm_display_mode innolux_zj070na_01p_mode = {
2473 .clock = 51501,
2474 .hdisplay = 1024,
2475 .hsync_start = 1024 + 128,
2476 .hsync_end = 1024 + 128 + 64,
2477 .htotal = 1024 + 128 + 64 + 128,
2478 .vdisplay = 600,
2479 .vsync_start = 600 + 16,
2480 .vsync_end = 600 + 16 + 4,
2481 .vtotal = 600 + 16 + 4 + 16,
2482 };
2483
2484 static const struct panel_desc innolux_zj070na_01p = {
2485 .modes = &innolux_zj070na_01p_mode,
2486 .num_modes = 1,
2487 .bpc = 6,
2488 .size = {
2489 .width = 154,
2490 .height = 90,
2491 },
2492 };
2493
2494 static const struct display_timing koe_tx14d24vm1bpa_timing = {
2495 .pixelclock = { 5580000, 5850000, 6200000 },
2496 .hactive = { 320, 320, 320 },
2497 .hfront_porch = { 30, 30, 30 },
2498 .hback_porch = { 30, 30, 30 },
2499 .hsync_len = { 1, 5, 17 },
2500 .vactive = { 240, 240, 240 },
2501 .vfront_porch = { 6, 6, 6 },
2502 .vback_porch = { 5, 5, 5 },
2503 .vsync_len = { 1, 2, 11 },
2504 .flags = DISPLAY_FLAGS_DE_HIGH,
2505 };
2506
2507 static const struct panel_desc koe_tx14d24vm1bpa = {
2508 .timings = &koe_tx14d24vm1bpa_timing,
2509 .num_timings = 1,
2510 .bpc = 6,
2511 .size = {
2512 .width = 115,
2513 .height = 86,
2514 },
2515 };
2516
2517 static const struct display_timing koe_tx26d202vm0bwa_timing = {
2518 .pixelclock = { 151820000, 156720000, 159780000 },
2519 .hactive = { 1920, 1920, 1920 },
2520 .hfront_porch = { 105, 130, 142 },
2521 .hback_porch = { 45, 70, 82 },
2522 .hsync_len = { 30, 30, 30 },
2523 .vactive = { 1200, 1200, 1200},
2524 .vfront_porch = { 3, 5, 10 },
2525 .vback_porch = { 2, 5, 10 },
2526 .vsync_len = { 5, 5, 5 },
2527 .flags = DISPLAY_FLAGS_DE_HIGH,
2528 };
2529
2530 static const struct panel_desc koe_tx26d202vm0bwa = {
2531 .timings = &koe_tx26d202vm0bwa_timing,
2532 .num_timings = 1,
2533 .bpc = 8,
2534 .size = {
2535 .width = 217,
2536 .height = 136,
2537 },
2538 .delay = {
2539 .prepare = 1000,
2540 .enable = 1000,
2541 .unprepare = 1000,
2542 .disable = 1000,
2543 },
2544 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2545 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2546 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2547 };
2548
2549 static const struct display_timing koe_tx31d200vm0baa_timing = {
2550 .pixelclock = { 39600000, 43200000, 48000000 },
2551 .hactive = { 1280, 1280, 1280 },
2552 .hfront_porch = { 16, 36, 56 },
2553 .hback_porch = { 16, 36, 56 },
2554 .hsync_len = { 8, 8, 8 },
2555 .vactive = { 480, 480, 480 },
2556 .vfront_porch = { 6, 21, 33 },
2557 .vback_porch = { 6, 21, 33 },
2558 .vsync_len = { 8, 8, 8 },
2559 .flags = DISPLAY_FLAGS_DE_HIGH,
2560 };
2561
2562 static const struct panel_desc koe_tx31d200vm0baa = {
2563 .timings = &koe_tx31d200vm0baa_timing,
2564 .num_timings = 1,
2565 .bpc = 6,
2566 .size = {
2567 .width = 292,
2568 .height = 109,
2569 },
2570 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2571 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2572 };
2573
2574 static const struct display_timing kyo_tcg121xglp_timing = {
2575 .pixelclock = { 52000000, 65000000, 71000000 },
2576 .hactive = { 1024, 1024, 1024 },
2577 .hfront_porch = { 2, 2, 2 },
2578 .hback_porch = { 2, 2, 2 },
2579 .hsync_len = { 86, 124, 244 },
2580 .vactive = { 768, 768, 768 },
2581 .vfront_porch = { 2, 2, 2 },
2582 .vback_porch = { 2, 2, 2 },
2583 .vsync_len = { 6, 34, 73 },
2584 .flags = DISPLAY_FLAGS_DE_HIGH,
2585 };
2586
2587 static const struct panel_desc kyo_tcg121xglp = {
2588 .timings = &kyo_tcg121xglp_timing,
2589 .num_timings = 1,
2590 .bpc = 8,
2591 .size = {
2592 .width = 246,
2593 .height = 184,
2594 },
2595 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2596 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2597 };
2598
2599 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
2600 .clock = 7000,
2601 .hdisplay = 320,
2602 .hsync_start = 320 + 20,
2603 .hsync_end = 320 + 20 + 30,
2604 .htotal = 320 + 20 + 30 + 38,
2605 .vdisplay = 240,
2606 .vsync_start = 240 + 4,
2607 .vsync_end = 240 + 4 + 3,
2608 .vtotal = 240 + 4 + 3 + 15,
2609 };
2610
2611 static const struct panel_desc lemaker_bl035_rgb_002 = {
2612 .modes = &lemaker_bl035_rgb_002_mode,
2613 .num_modes = 1,
2614 .size = {
2615 .width = 70,
2616 .height = 52,
2617 },
2618 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2619 .bus_flags = DRM_BUS_FLAG_DE_LOW,
2620 };
2621
2622 static const struct drm_display_mode lg_lb070wv8_mode = {
2623 .clock = 33246,
2624 .hdisplay = 800,
2625 .hsync_start = 800 + 88,
2626 .hsync_end = 800 + 88 + 80,
2627 .htotal = 800 + 88 + 80 + 88,
2628 .vdisplay = 480,
2629 .vsync_start = 480 + 10,
2630 .vsync_end = 480 + 10 + 25,
2631 .vtotal = 480 + 10 + 25 + 10,
2632 };
2633
2634 static const struct panel_desc lg_lb070wv8 = {
2635 .modes = &lg_lb070wv8_mode,
2636 .num_modes = 1,
2637 .bpc = 8,
2638 .size = {
2639 .width = 151,
2640 .height = 91,
2641 },
2642 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2643 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2644 };
2645
2646 static const struct display_timing logictechno_lt161010_2nh_timing = {
2647 .pixelclock = { 26400000, 33300000, 46800000 },
2648 .hactive = { 800, 800, 800 },
2649 .hfront_porch = { 16, 210, 354 },
2650 .hback_porch = { 46, 46, 46 },
2651 .hsync_len = { 1, 20, 40 },
2652 .vactive = { 480, 480, 480 },
2653 .vfront_porch = { 7, 22, 147 },
2654 .vback_porch = { 23, 23, 23 },
2655 .vsync_len = { 1, 10, 20 },
2656 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2657 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2658 DISPLAY_FLAGS_SYNC_POSEDGE,
2659 };
2660
2661 static const struct panel_desc logictechno_lt161010_2nh = {
2662 .timings = &logictechno_lt161010_2nh_timing,
2663 .num_timings = 1,
2664 .bpc = 6,
2665 .size = {
2666 .width = 154,
2667 .height = 86,
2668 },
2669 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2670 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
2671 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2672 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2673 .connector_type = DRM_MODE_CONNECTOR_DPI,
2674 };
2675
2676 static const struct display_timing logictechno_lt170410_2whc_timing = {
2677 .pixelclock = { 68900000, 71100000, 73400000 },
2678 .hactive = { 1280, 1280, 1280 },
2679 .hfront_porch = { 23, 60, 71 },
2680 .hback_porch = { 23, 60, 71 },
2681 .hsync_len = { 15, 40, 47 },
2682 .vactive = { 800, 800, 800 },
2683 .vfront_porch = { 5, 7, 10 },
2684 .vback_porch = { 5, 7, 10 },
2685 .vsync_len = { 6, 9, 12 },
2686 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2687 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2688 DISPLAY_FLAGS_SYNC_POSEDGE,
2689 };
2690
2691 static const struct panel_desc logictechno_lt170410_2whc = {
2692 .timings = &logictechno_lt170410_2whc_timing,
2693 .num_timings = 1,
2694 .bpc = 8,
2695 .size = {
2696 .width = 217,
2697 .height = 136,
2698 },
2699 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2700 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2701 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2702 };
2703
2704 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = {
2705 .clock = 33000,
2706 .hdisplay = 800,
2707 .hsync_start = 800 + 112,
2708 .hsync_end = 800 + 112 + 3,
2709 .htotal = 800 + 112 + 3 + 85,
2710 .vdisplay = 480,
2711 .vsync_start = 480 + 38,
2712 .vsync_end = 480 + 38 + 3,
2713 .vtotal = 480 + 38 + 3 + 29,
2714 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2715 };
2716
2717 static const struct panel_desc logictechno_lttd800480070_l2rt = {
2718 .modes = &logictechno_lttd800480070_l2rt_mode,
2719 .num_modes = 1,
2720 .bpc = 8,
2721 .size = {
2722 .width = 154,
2723 .height = 86,
2724 },
2725 .delay = {
2726 .prepare = 45,
2727 .enable = 100,
2728 .disable = 100,
2729 .unprepare = 45
2730 },
2731 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2732 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2733 .connector_type = DRM_MODE_CONNECTOR_DPI,
2734 };
2735
2736 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = {
2737 .clock = 33000,
2738 .hdisplay = 800,
2739 .hsync_start = 800 + 154,
2740 .hsync_end = 800 + 154 + 3,
2741 .htotal = 800 + 154 + 3 + 43,
2742 .vdisplay = 480,
2743 .vsync_start = 480 + 47,
2744 .vsync_end = 480 + 47 + 3,
2745 .vtotal = 480 + 47 + 3 + 20,
2746 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2747 };
2748
2749 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = {
2750 .modes = &logictechno_lttd800480070_l6wh_rt_mode,
2751 .num_modes = 1,
2752 .bpc = 8,
2753 .size = {
2754 .width = 154,
2755 .height = 86,
2756 },
2757 .delay = {
2758 .prepare = 45,
2759 .enable = 100,
2760 .disable = 100,
2761 .unprepare = 45
2762 },
2763 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2764 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2765 .connector_type = DRM_MODE_CONNECTOR_DPI,
2766 };
2767
2768 static const struct drm_display_mode logicpd_type_28_mode = {
2769 .clock = 9107,
2770 .hdisplay = 480,
2771 .hsync_start = 480 + 3,
2772 .hsync_end = 480 + 3 + 42,
2773 .htotal = 480 + 3 + 42 + 2,
2774
2775 .vdisplay = 272,
2776 .vsync_start = 272 + 2,
2777 .vsync_end = 272 + 2 + 11,
2778 .vtotal = 272 + 2 + 11 + 3,
2779 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2780 };
2781
2782 static const struct panel_desc logicpd_type_28 = {
2783 .modes = &logicpd_type_28_mode,
2784 .num_modes = 1,
2785 .bpc = 8,
2786 .size = {
2787 .width = 105,
2788 .height = 67,
2789 },
2790 .delay = {
2791 .prepare = 200,
2792 .enable = 200,
2793 .unprepare = 200,
2794 .disable = 200,
2795 },
2796 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2797 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2798 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
2799 .connector_type = DRM_MODE_CONNECTOR_DPI,
2800 };
2801
2802 static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
2803 .clock = 30400,
2804 .hdisplay = 800,
2805 .hsync_start = 800 + 0,
2806 .hsync_end = 800 + 1,
2807 .htotal = 800 + 0 + 1 + 160,
2808 .vdisplay = 480,
2809 .vsync_start = 480 + 0,
2810 .vsync_end = 480 + 48 + 1,
2811 .vtotal = 480 + 48 + 1 + 0,
2812 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2813 };
2814
2815 static const struct panel_desc mitsubishi_aa070mc01 = {
2816 .modes = &mitsubishi_aa070mc01_mode,
2817 .num_modes = 1,
2818 .bpc = 8,
2819 .size = {
2820 .width = 152,
2821 .height = 91,
2822 },
2823
2824 .delay = {
2825 .enable = 200,
2826 .unprepare = 200,
2827 .disable = 400,
2828 },
2829 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2830 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2831 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2832 };
2833
2834 static const struct display_timing multi_inno_mi0700s4t_6_timing = {
2835 .pixelclock = { 29000000, 33000000, 38000000 },
2836 .hactive = { 800, 800, 800 },
2837 .hfront_porch = { 180, 210, 240 },
2838 .hback_porch = { 16, 16, 16 },
2839 .hsync_len = { 30, 30, 30 },
2840 .vactive = { 480, 480, 480 },
2841 .vfront_porch = { 12, 22, 32 },
2842 .vback_porch = { 10, 10, 10 },
2843 .vsync_len = { 13, 13, 13 },
2844 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2845 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2846 DISPLAY_FLAGS_SYNC_POSEDGE,
2847 };
2848
2849 static const struct panel_desc multi_inno_mi0700s4t_6 = {
2850 .timings = &multi_inno_mi0700s4t_6_timing,
2851 .num_timings = 1,
2852 .bpc = 8,
2853 .size = {
2854 .width = 154,
2855 .height = 86,
2856 },
2857 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2858 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
2859 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2860 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2861 .connector_type = DRM_MODE_CONNECTOR_DPI,
2862 };
2863
2864 static const struct display_timing multi_inno_mi0800ft_9_timing = {
2865 .pixelclock = { 32000000, 40000000, 50000000 },
2866 .hactive = { 800, 800, 800 },
2867 .hfront_porch = { 16, 210, 354 },
2868 .hback_porch = { 6, 26, 45 },
2869 .hsync_len = { 1, 20, 40 },
2870 .vactive = { 600, 600, 600 },
2871 .vfront_porch = { 1, 12, 77 },
2872 .vback_porch = { 3, 13, 22 },
2873 .vsync_len = { 1, 10, 20 },
2874 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2875 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2876 DISPLAY_FLAGS_SYNC_POSEDGE,
2877 };
2878
2879 static const struct panel_desc multi_inno_mi0800ft_9 = {
2880 .timings = &multi_inno_mi0800ft_9_timing,
2881 .num_timings = 1,
2882 .bpc = 8,
2883 .size = {
2884 .width = 162,
2885 .height = 122,
2886 },
2887 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2888 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
2889 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2890 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2891 .connector_type = DRM_MODE_CONNECTOR_DPI,
2892 };
2893
2894 static const struct display_timing multi_inno_mi1010ait_1cp_timing = {
2895 .pixelclock = { 68900000, 70000000, 73400000 },
2896 .hactive = { 1280, 1280, 1280 },
2897 .hfront_porch = { 30, 60, 71 },
2898 .hback_porch = { 30, 60, 71 },
2899 .hsync_len = { 10, 10, 48 },
2900 .vactive = { 800, 800, 800 },
2901 .vfront_porch = { 5, 10, 10 },
2902 .vback_porch = { 5, 10, 10 },
2903 .vsync_len = { 5, 6, 13 },
2904 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2905 DISPLAY_FLAGS_DE_HIGH,
2906 };
2907
2908 static const struct panel_desc multi_inno_mi1010ait_1cp = {
2909 .timings = &multi_inno_mi1010ait_1cp_timing,
2910 .num_timings = 1,
2911 .bpc = 8,
2912 .size = {
2913 .width = 217,
2914 .height = 136,
2915 },
2916 .delay = {
2917 .enable = 50,
2918 .disable = 50,
2919 },
2920 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2921 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2922 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2923 };
2924
2925 static const struct display_timing nec_nl12880bc20_05_timing = {
2926 .pixelclock = { 67000000, 71000000, 75000000 },
2927 .hactive = { 1280, 1280, 1280 },
2928 .hfront_porch = { 2, 30, 30 },
2929 .hback_porch = { 6, 100, 100 },
2930 .hsync_len = { 2, 30, 30 },
2931 .vactive = { 800, 800, 800 },
2932 .vfront_porch = { 5, 5, 5 },
2933 .vback_porch = { 11, 11, 11 },
2934 .vsync_len = { 7, 7, 7 },
2935 };
2936
2937 static const struct panel_desc nec_nl12880bc20_05 = {
2938 .timings = &nec_nl12880bc20_05_timing,
2939 .num_timings = 1,
2940 .bpc = 8,
2941 .size = {
2942 .width = 261,
2943 .height = 163,
2944 },
2945 .delay = {
2946 .enable = 50,
2947 .disable = 50,
2948 },
2949 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2950 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2951 };
2952
2953 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
2954 .clock = 10870,
2955 .hdisplay = 480,
2956 .hsync_start = 480 + 2,
2957 .hsync_end = 480 + 2 + 41,
2958 .htotal = 480 + 2 + 41 + 2,
2959 .vdisplay = 272,
2960 .vsync_start = 272 + 2,
2961 .vsync_end = 272 + 2 + 4,
2962 .vtotal = 272 + 2 + 4 + 2,
2963 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2964 };
2965
2966 static const struct panel_desc nec_nl4827hc19_05b = {
2967 .modes = &nec_nl4827hc19_05b_mode,
2968 .num_modes = 1,
2969 .bpc = 8,
2970 .size = {
2971 .width = 95,
2972 .height = 54,
2973 },
2974 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2975 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2976 };
2977
2978 static const struct drm_display_mode netron_dy_e231732_mode = {
2979 .clock = 66000,
2980 .hdisplay = 1024,
2981 .hsync_start = 1024 + 160,
2982 .hsync_end = 1024 + 160 + 70,
2983 .htotal = 1024 + 160 + 70 + 90,
2984 .vdisplay = 600,
2985 .vsync_start = 600 + 127,
2986 .vsync_end = 600 + 127 + 20,
2987 .vtotal = 600 + 127 + 20 + 3,
2988 };
2989
2990 static const struct panel_desc netron_dy_e231732 = {
2991 .modes = &netron_dy_e231732_mode,
2992 .num_modes = 1,
2993 .size = {
2994 .width = 154,
2995 .height = 87,
2996 },
2997 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2998 };
2999
3000 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
3001 .clock = 9000,
3002 .hdisplay = 480,
3003 .hsync_start = 480 + 2,
3004 .hsync_end = 480 + 2 + 41,
3005 .htotal = 480 + 2 + 41 + 2,
3006 .vdisplay = 272,
3007 .vsync_start = 272 + 2,
3008 .vsync_end = 272 + 2 + 10,
3009 .vtotal = 272 + 2 + 10 + 2,
3010 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3011 };
3012
3013 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
3014 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
3015 .num_modes = 1,
3016 .bpc = 8,
3017 .size = {
3018 .width = 95,
3019 .height = 54,
3020 },
3021 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3022 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3023 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3024 .connector_type = DRM_MODE_CONNECTOR_DPI,
3025 };
3026
3027 static const struct display_timing nlt_nl192108ac18_02d_timing = {
3028 .pixelclock = { 130000000, 148350000, 163000000 },
3029 .hactive = { 1920, 1920, 1920 },
3030 .hfront_porch = { 80, 100, 100 },
3031 .hback_porch = { 100, 120, 120 },
3032 .hsync_len = { 50, 60, 60 },
3033 .vactive = { 1080, 1080, 1080 },
3034 .vfront_porch = { 12, 30, 30 },
3035 .vback_porch = { 4, 10, 10 },
3036 .vsync_len = { 4, 5, 5 },
3037 };
3038
3039 static const struct panel_desc nlt_nl192108ac18_02d = {
3040 .timings = &nlt_nl192108ac18_02d_timing,
3041 .num_timings = 1,
3042 .bpc = 8,
3043 .size = {
3044 .width = 344,
3045 .height = 194,
3046 },
3047 .delay = {
3048 .unprepare = 500,
3049 },
3050 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3051 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3052 };
3053
3054 static const struct drm_display_mode nvd_9128_mode = {
3055 .clock = 29500,
3056 .hdisplay = 800,
3057 .hsync_start = 800 + 130,
3058 .hsync_end = 800 + 130 + 98,
3059 .htotal = 800 + 0 + 130 + 98,
3060 .vdisplay = 480,
3061 .vsync_start = 480 + 10,
3062 .vsync_end = 480 + 10 + 50,
3063 .vtotal = 480 + 0 + 10 + 50,
3064 };
3065
3066 static const struct panel_desc nvd_9128 = {
3067 .modes = &nvd_9128_mode,
3068 .num_modes = 1,
3069 .bpc = 8,
3070 .size = {
3071 .width = 156,
3072 .height = 88,
3073 },
3074 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3075 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3076 };
3077
3078 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
3079 .pixelclock = { 30000000, 30000000, 40000000 },
3080 .hactive = { 800, 800, 800 },
3081 .hfront_porch = { 40, 40, 40 },
3082 .hback_porch = { 40, 40, 40 },
3083 .hsync_len = { 1, 48, 48 },
3084 .vactive = { 480, 480, 480 },
3085 .vfront_porch = { 13, 13, 13 },
3086 .vback_porch = { 29, 29, 29 },
3087 .vsync_len = { 3, 3, 3 },
3088 .flags = DISPLAY_FLAGS_DE_HIGH,
3089 };
3090
3091 static const struct panel_desc okaya_rs800480t_7x0gp = {
3092 .timings = &okaya_rs800480t_7x0gp_timing,
3093 .num_timings = 1,
3094 .bpc = 6,
3095 .size = {
3096 .width = 154,
3097 .height = 87,
3098 },
3099 .delay = {
3100 .prepare = 41,
3101 .enable = 50,
3102 .unprepare = 41,
3103 .disable = 50,
3104 },
3105 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3106 };
3107
3108 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
3109 .clock = 9000,
3110 .hdisplay = 480,
3111 .hsync_start = 480 + 5,
3112 .hsync_end = 480 + 5 + 30,
3113 .htotal = 480 + 5 + 30 + 10,
3114 .vdisplay = 272,
3115 .vsync_start = 272 + 8,
3116 .vsync_end = 272 + 8 + 5,
3117 .vtotal = 272 + 8 + 5 + 3,
3118 };
3119
3120 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
3121 .modes = &olimex_lcd_olinuxino_43ts_mode,
3122 .num_modes = 1,
3123 .size = {
3124 .width = 95,
3125 .height = 54,
3126 },
3127 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3128 };
3129
3130 /*
3131 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
3132 * pixel clocks, but this is the timing that was being used in the Adafruit
3133 * installation instructions.
3134 */
3135 static const struct drm_display_mode ontat_yx700wv03_mode = {
3136 .clock = 29500,
3137 .hdisplay = 800,
3138 .hsync_start = 824,
3139 .hsync_end = 896,
3140 .htotal = 992,
3141 .vdisplay = 480,
3142 .vsync_start = 483,
3143 .vsync_end = 493,
3144 .vtotal = 500,
3145 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3146 };
3147
3148 /*
3149 * Specification at:
3150 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
3151 */
3152 static const struct panel_desc ontat_yx700wv03 = {
3153 .modes = &ontat_yx700wv03_mode,
3154 .num_modes = 1,
3155 .bpc = 8,
3156 .size = {
3157 .width = 154,
3158 .height = 83,
3159 },
3160 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3161 };
3162
3163 static const struct drm_display_mode ortustech_com37h3m_mode = {
3164 .clock = 22230,
3165 .hdisplay = 480,
3166 .hsync_start = 480 + 40,
3167 .hsync_end = 480 + 40 + 10,
3168 .htotal = 480 + 40 + 10 + 40,
3169 .vdisplay = 640,
3170 .vsync_start = 640 + 4,
3171 .vsync_end = 640 + 4 + 2,
3172 .vtotal = 640 + 4 + 2 + 4,
3173 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3174 };
3175
3176 static const struct panel_desc ortustech_com37h3m = {
3177 .modes = &ortustech_com37h3m_mode,
3178 .num_modes = 1,
3179 .bpc = 8,
3180 .size = {
3181 .width = 56, /* 56.16mm */
3182 .height = 75, /* 74.88mm */
3183 },
3184 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3185 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3186 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3187 };
3188
3189 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
3190 .clock = 25000,
3191 .hdisplay = 480,
3192 .hsync_start = 480 + 10,
3193 .hsync_end = 480 + 10 + 10,
3194 .htotal = 480 + 10 + 10 + 15,
3195 .vdisplay = 800,
3196 .vsync_start = 800 + 3,
3197 .vsync_end = 800 + 3 + 3,
3198 .vtotal = 800 + 3 + 3 + 3,
3199 };
3200
3201 static const struct panel_desc ortustech_com43h4m85ulc = {
3202 .modes = &ortustech_com43h4m85ulc_mode,
3203 .num_modes = 1,
3204 .bpc = 6,
3205 .size = {
3206 .width = 56,
3207 .height = 93,
3208 },
3209 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3210 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3211 .connector_type = DRM_MODE_CONNECTOR_DPI,
3212 };
3213
3214 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
3215 .clock = 33000,
3216 .hdisplay = 800,
3217 .hsync_start = 800 + 210,
3218 .hsync_end = 800 + 210 + 30,
3219 .htotal = 800 + 210 + 30 + 16,
3220 .vdisplay = 480,
3221 .vsync_start = 480 + 22,
3222 .vsync_end = 480 + 22 + 13,
3223 .vtotal = 480 + 22 + 13 + 10,
3224 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3225 };
3226
3227 static const struct panel_desc osddisplays_osd070t1718_19ts = {
3228 .modes = &osddisplays_osd070t1718_19ts_mode,
3229 .num_modes = 1,
3230 .bpc = 8,
3231 .size = {
3232 .width = 152,
3233 .height = 91,
3234 },
3235 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3236 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3237 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3238 .connector_type = DRM_MODE_CONNECTOR_DPI,
3239 };
3240
3241 static const struct drm_display_mode pda_91_00156_a0_mode = {
3242 .clock = 33300,
3243 .hdisplay = 800,
3244 .hsync_start = 800 + 1,
3245 .hsync_end = 800 + 1 + 64,
3246 .htotal = 800 + 1 + 64 + 64,
3247 .vdisplay = 480,
3248 .vsync_start = 480 + 1,
3249 .vsync_end = 480 + 1 + 23,
3250 .vtotal = 480 + 1 + 23 + 22,
3251 };
3252
3253 static const struct panel_desc pda_91_00156_a0 = {
3254 .modes = &pda_91_00156_a0_mode,
3255 .num_modes = 1,
3256 .size = {
3257 .width = 152,
3258 .height = 91,
3259 },
3260 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3261 };
3262
3263 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = {
3264 .clock = 24750,
3265 .hdisplay = 800,
3266 .hsync_start = 800 + 54,
3267 .hsync_end = 800 + 54 + 2,
3268 .htotal = 800 + 54 + 2 + 44,
3269 .vdisplay = 480,
3270 .vsync_start = 480 + 49,
3271 .vsync_end = 480 + 49 + 2,
3272 .vtotal = 480 + 49 + 2 + 22,
3273 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3274 };
3275
3276 static const struct panel_desc powertip_ph800480t013_idf02 = {
3277 .modes = &powertip_ph800480t013_idf02_mode,
3278 .num_modes = 1,
3279 .bpc = 8,
3280 .size = {
3281 .width = 152,
3282 .height = 91,
3283 },
3284 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3285 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3286 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3287 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3288 .connector_type = DRM_MODE_CONNECTOR_DPI,
3289 };
3290
3291 static const struct drm_display_mode qd43003c0_40_mode = {
3292 .clock = 9000,
3293 .hdisplay = 480,
3294 .hsync_start = 480 + 8,
3295 .hsync_end = 480 + 8 + 4,
3296 .htotal = 480 + 8 + 4 + 39,
3297 .vdisplay = 272,
3298 .vsync_start = 272 + 4,
3299 .vsync_end = 272 + 4 + 10,
3300 .vtotal = 272 + 4 + 10 + 2,
3301 };
3302
3303 static const struct panel_desc qd43003c0_40 = {
3304 .modes = &qd43003c0_40_mode,
3305 .num_modes = 1,
3306 .bpc = 8,
3307 .size = {
3308 .width = 95,
3309 .height = 53,
3310 },
3311 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3312 };
3313
3314 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = {
3315 { /* 60 Hz */
3316 .clock = 10800,
3317 .hdisplay = 480,
3318 .hsync_start = 480 + 77,
3319 .hsync_end = 480 + 77 + 41,
3320 .htotal = 480 + 77 + 41 + 2,
3321 .vdisplay = 272,
3322 .vsync_start = 272 + 16,
3323 .vsync_end = 272 + 16 + 10,
3324 .vtotal = 272 + 16 + 10 + 2,
3325 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3326 },
3327 { /* 50 Hz */
3328 .clock = 10800,
3329 .hdisplay = 480,
3330 .hsync_start = 480 + 17,
3331 .hsync_end = 480 + 17 + 41,
3332 .htotal = 480 + 17 + 41 + 2,
3333 .vdisplay = 272,
3334 .vsync_start = 272 + 116,
3335 .vsync_end = 272 + 116 + 10,
3336 .vtotal = 272 + 116 + 10 + 2,
3337 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3338 },
3339 };
3340
3341 static const struct panel_desc qishenglong_gopher2b_lcd = {
3342 .modes = qishenglong_gopher2b_lcd_modes,
3343 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes),
3344 .bpc = 8,
3345 .size = {
3346 .width = 95,
3347 .height = 54,
3348 },
3349 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3350 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3351 .connector_type = DRM_MODE_CONNECTOR_DPI,
3352 };
3353
3354 static const struct display_timing rocktech_rk043fn48h_timing = {
3355 .pixelclock = { 6000000, 9000000, 12000000 },
3356 .hactive = { 480, 480, 480 },
3357 .hback_porch = { 8, 43, 43 },
3358 .hfront_porch = { 2, 8, 8 },
3359 .hsync_len = { 1, 1, 1 },
3360 .vactive = { 272, 272, 272 },
3361 .vback_porch = { 2, 12, 12 },
3362 .vfront_porch = { 1, 4, 4 },
3363 .vsync_len = { 1, 10, 10 },
3364 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW |
3365 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
3366 };
3367
3368 static const struct panel_desc rocktech_rk043fn48h = {
3369 .timings = &rocktech_rk043fn48h_timing,
3370 .num_timings = 1,
3371 .bpc = 8,
3372 .size = {
3373 .width = 95,
3374 .height = 54,
3375 },
3376 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3377 .connector_type = DRM_MODE_CONNECTOR_DPI,
3378 };
3379
3380 static const struct display_timing rocktech_rk070er9427_timing = {
3381 .pixelclock = { 26400000, 33300000, 46800000 },
3382 .hactive = { 800, 800, 800 },
3383 .hfront_porch = { 16, 210, 354 },
3384 .hback_porch = { 46, 46, 46 },
3385 .hsync_len = { 1, 1, 1 },
3386 .vactive = { 480, 480, 480 },
3387 .vfront_porch = { 7, 22, 147 },
3388 .vback_porch = { 23, 23, 23 },
3389 .vsync_len = { 1, 1, 1 },
3390 .flags = DISPLAY_FLAGS_DE_HIGH,
3391 };
3392
3393 static const struct panel_desc rocktech_rk070er9427 = {
3394 .timings = &rocktech_rk070er9427_timing,
3395 .num_timings = 1,
3396 .bpc = 6,
3397 .size = {
3398 .width = 154,
3399 .height = 86,
3400 },
3401 .delay = {
3402 .prepare = 41,
3403 .enable = 50,
3404 .unprepare = 41,
3405 .disable = 50,
3406 },
3407 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3408 };
3409
3410 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = {
3411 .clock = 71100,
3412 .hdisplay = 1280,
3413 .hsync_start = 1280 + 48,
3414 .hsync_end = 1280 + 48 + 32,
3415 .htotal = 1280 + 48 + 32 + 80,
3416 .vdisplay = 800,
3417 .vsync_start = 800 + 2,
3418 .vsync_end = 800 + 2 + 5,
3419 .vtotal = 800 + 2 + 5 + 16,
3420 };
3421
3422 static const struct panel_desc rocktech_rk101ii01d_ct = {
3423 .modes = &rocktech_rk101ii01d_ct_mode,
3424 .bpc = 8,
3425 .num_modes = 1,
3426 .size = {
3427 .width = 217,
3428 .height = 136,
3429 },
3430 .delay = {
3431 .prepare = 50,
3432 .disable = 50,
3433 },
3434 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3435 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3436 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3437 };
3438
3439 static const struct display_timing samsung_ltl101al01_timing = {
3440 .pixelclock = { 66663000, 66663000, 66663000 },
3441 .hactive = { 1280, 1280, 1280 },
3442 .hfront_porch = { 18, 18, 18 },
3443 .hback_porch = { 36, 36, 36 },
3444 .hsync_len = { 16, 16, 16 },
3445 .vactive = { 800, 800, 800 },
3446 .vfront_porch = { 4, 4, 4 },
3447 .vback_porch = { 16, 16, 16 },
3448 .vsync_len = { 3, 3, 3 },
3449 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
3450 };
3451
3452 static const struct panel_desc samsung_ltl101al01 = {
3453 .timings = &samsung_ltl101al01_timing,
3454 .num_timings = 1,
3455 .bpc = 8,
3456 .size = {
3457 .width = 217,
3458 .height = 135,
3459 },
3460 .delay = {
3461 .prepare = 40,
3462 .enable = 300,
3463 .disable = 200,
3464 .unprepare = 600,
3465 },
3466 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3467 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3468 };
3469
3470 static const struct drm_display_mode samsung_ltn101nt05_mode = {
3471 .clock = 54030,
3472 .hdisplay = 1024,
3473 .hsync_start = 1024 + 24,
3474 .hsync_end = 1024 + 24 + 136,
3475 .htotal = 1024 + 24 + 136 + 160,
3476 .vdisplay = 600,
3477 .vsync_start = 600 + 3,
3478 .vsync_end = 600 + 3 + 6,
3479 .vtotal = 600 + 3 + 6 + 61,
3480 };
3481
3482 static const struct panel_desc samsung_ltn101nt05 = {
3483 .modes = &samsung_ltn101nt05_mode,
3484 .num_modes = 1,
3485 .bpc = 6,
3486 .size = {
3487 .width = 223,
3488 .height = 125,
3489 },
3490 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3491 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3492 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3493 };
3494
3495 static const struct display_timing satoz_sat050at40h12r2_timing = {
3496 .pixelclock = {33300000, 33300000, 50000000},
3497 .hactive = {800, 800, 800},
3498 .hfront_porch = {16, 210, 354},
3499 .hback_porch = {46, 46, 46},
3500 .hsync_len = {1, 1, 40},
3501 .vactive = {480, 480, 480},
3502 .vfront_porch = {7, 22, 147},
3503 .vback_porch = {23, 23, 23},
3504 .vsync_len = {1, 1, 20},
3505 };
3506
3507 static const struct panel_desc satoz_sat050at40h12r2 = {
3508 .timings = &satoz_sat050at40h12r2_timing,
3509 .num_timings = 1,
3510 .bpc = 8,
3511 .size = {
3512 .width = 108,
3513 .height = 65,
3514 },
3515 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3516 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3517 };
3518
3519 static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
3520 .clock = 33260,
3521 .hdisplay = 800,
3522 .hsync_start = 800 + 64,
3523 .hsync_end = 800 + 64 + 128,
3524 .htotal = 800 + 64 + 128 + 64,
3525 .vdisplay = 480,
3526 .vsync_start = 480 + 8,
3527 .vsync_end = 480 + 8 + 2,
3528 .vtotal = 480 + 8 + 2 + 35,
3529 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3530 };
3531
3532 static const struct panel_desc sharp_lq070y3dg3b = {
3533 .modes = &sharp_lq070y3dg3b_mode,
3534 .num_modes = 1,
3535 .bpc = 8,
3536 .size = {
3537 .width = 152, /* 152.4mm */
3538 .height = 91, /* 91.4mm */
3539 },
3540 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3541 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3542 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3543 };
3544
3545 static const struct drm_display_mode sharp_lq035q7db03_mode = {
3546 .clock = 5500,
3547 .hdisplay = 240,
3548 .hsync_start = 240 + 16,
3549 .hsync_end = 240 + 16 + 7,
3550 .htotal = 240 + 16 + 7 + 5,
3551 .vdisplay = 320,
3552 .vsync_start = 320 + 9,
3553 .vsync_end = 320 + 9 + 1,
3554 .vtotal = 320 + 9 + 1 + 7,
3555 };
3556
3557 static const struct panel_desc sharp_lq035q7db03 = {
3558 .modes = &sharp_lq035q7db03_mode,
3559 .num_modes = 1,
3560 .bpc = 6,
3561 .size = {
3562 .width = 54,
3563 .height = 72,
3564 },
3565 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3566 };
3567
3568 static const struct display_timing sharp_lq101k1ly04_timing = {
3569 .pixelclock = { 60000000, 65000000, 80000000 },
3570 .hactive = { 1280, 1280, 1280 },
3571 .hfront_porch = { 20, 20, 20 },
3572 .hback_porch = { 20, 20, 20 },
3573 .hsync_len = { 10, 10, 10 },
3574 .vactive = { 800, 800, 800 },
3575 .vfront_porch = { 4, 4, 4 },
3576 .vback_porch = { 4, 4, 4 },
3577 .vsync_len = { 4, 4, 4 },
3578 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3579 };
3580
3581 static const struct panel_desc sharp_lq101k1ly04 = {
3582 .timings = &sharp_lq101k1ly04_timing,
3583 .num_timings = 1,
3584 .bpc = 8,
3585 .size = {
3586 .width = 217,
3587 .height = 136,
3588 },
3589 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3590 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3591 };
3592
3593 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = {
3594 { /* 50 Hz */
3595 .clock = 3000,
3596 .hdisplay = 240,
3597 .hsync_start = 240 + 58,
3598 .hsync_end = 240 + 58 + 1,
3599 .htotal = 240 + 58 + 1 + 1,
3600 .vdisplay = 160,
3601 .vsync_start = 160 + 24,
3602 .vsync_end = 160 + 24 + 10,
3603 .vtotal = 160 + 24 + 10 + 6,
3604 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3605 },
3606 { /* 60 Hz */
3607 .clock = 3000,
3608 .hdisplay = 240,
3609 .hsync_start = 240 + 8,
3610 .hsync_end = 240 + 8 + 1,
3611 .htotal = 240 + 8 + 1 + 1,
3612 .vdisplay = 160,
3613 .vsync_start = 160 + 24,
3614 .vsync_end = 160 + 24 + 10,
3615 .vtotal = 160 + 24 + 10 + 6,
3616 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3617 },
3618 };
3619
3620 static const struct panel_desc sharp_ls020b1dd01d = {
3621 .modes = sharp_ls020b1dd01d_modes,
3622 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes),
3623 .bpc = 6,
3624 .size = {
3625 .width = 42,
3626 .height = 28,
3627 },
3628 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
3629 .bus_flags = DRM_BUS_FLAG_DE_HIGH
3630 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
3631 | DRM_BUS_FLAG_SHARP_SIGNALS,
3632 };
3633
3634 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
3635 .clock = 33300,
3636 .hdisplay = 800,
3637 .hsync_start = 800 + 1,
3638 .hsync_end = 800 + 1 + 64,
3639 .htotal = 800 + 1 + 64 + 64,
3640 .vdisplay = 480,
3641 .vsync_start = 480 + 1,
3642 .vsync_end = 480 + 1 + 23,
3643 .vtotal = 480 + 1 + 23 + 22,
3644 };
3645
3646 static const struct panel_desc shelly_sca07010_bfn_lnn = {
3647 .modes = &shelly_sca07010_bfn_lnn_mode,
3648 .num_modes = 1,
3649 .size = {
3650 .width = 152,
3651 .height = 91,
3652 },
3653 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3654 };
3655
3656 static const struct drm_display_mode starry_kr070pe2t_mode = {
3657 .clock = 33000,
3658 .hdisplay = 800,
3659 .hsync_start = 800 + 209,
3660 .hsync_end = 800 + 209 + 1,
3661 .htotal = 800 + 209 + 1 + 45,
3662 .vdisplay = 480,
3663 .vsync_start = 480 + 22,
3664 .vsync_end = 480 + 22 + 1,
3665 .vtotal = 480 + 22 + 1 + 22,
3666 };
3667
3668 static const struct panel_desc starry_kr070pe2t = {
3669 .modes = &starry_kr070pe2t_mode,
3670 .num_modes = 1,
3671 .bpc = 8,
3672 .size = {
3673 .width = 152,
3674 .height = 86,
3675 },
3676 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3677 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
3678 .connector_type = DRM_MODE_CONNECTOR_DPI,
3679 };
3680
3681 static const struct display_timing startek_kd070wvfpa_mode = {
3682 .pixelclock = { 25200000, 27200000, 30500000 },
3683 .hactive = { 800, 800, 800 },
3684 .hfront_porch = { 19, 44, 115 },
3685 .hback_porch = { 5, 16, 101 },
3686 .hsync_len = { 1, 2, 100 },
3687 .vactive = { 480, 480, 480 },
3688 .vfront_porch = { 5, 43, 67 },
3689 .vback_porch = { 5, 5, 67 },
3690 .vsync_len = { 1, 2, 66 },
3691 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3692 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
3693 DISPLAY_FLAGS_SYNC_POSEDGE,
3694 };
3695
3696 static const struct panel_desc startek_kd070wvfpa = {
3697 .timings = &startek_kd070wvfpa_mode,
3698 .num_timings = 1,
3699 .bpc = 8,
3700 .size = {
3701 .width = 152,
3702 .height = 91,
3703 },
3704 .delay = {
3705 .prepare = 20,
3706 .enable = 200,
3707 .disable = 200,
3708 },
3709 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3710 .connector_type = DRM_MODE_CONNECTOR_DPI,
3711 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3712 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3713 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3714 };
3715
3716 static const struct display_timing tsd_tst043015cmhx_timing = {
3717 .pixelclock = { 5000000, 9000000, 12000000 },
3718 .hactive = { 480, 480, 480 },
3719 .hfront_porch = { 4, 5, 65 },
3720 .hback_porch = { 36, 40, 255 },
3721 .hsync_len = { 1, 1, 1 },
3722 .vactive = { 272, 272, 272 },
3723 .vfront_porch = { 2, 8, 97 },
3724 .vback_porch = { 3, 8, 31 },
3725 .vsync_len = { 1, 1, 1 },
3726
3727 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3728 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
3729 };
3730
3731 static const struct panel_desc tsd_tst043015cmhx = {
3732 .timings = &tsd_tst043015cmhx_timing,
3733 .num_timings = 1,
3734 .bpc = 8,
3735 .size = {
3736 .width = 105,
3737 .height = 67,
3738 },
3739 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3740 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3741 };
3742
3743 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
3744 .clock = 30000,
3745 .hdisplay = 800,
3746 .hsync_start = 800 + 39,
3747 .hsync_end = 800 + 39 + 47,
3748 .htotal = 800 + 39 + 47 + 39,
3749 .vdisplay = 480,
3750 .vsync_start = 480 + 13,
3751 .vsync_end = 480 + 13 + 2,
3752 .vtotal = 480 + 13 + 2 + 29,
3753 };
3754
3755 static const struct panel_desc tfc_s9700rtwv43tr_01b = {
3756 .modes = &tfc_s9700rtwv43tr_01b_mode,
3757 .num_modes = 1,
3758 .bpc = 8,
3759 .size = {
3760 .width = 155,
3761 .height = 90,
3762 },
3763 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3764 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3765 };
3766
3767 static const struct display_timing tianma_tm070jdhg30_timing = {
3768 .pixelclock = { 62600000, 68200000, 78100000 },
3769 .hactive = { 1280, 1280, 1280 },
3770 .hfront_porch = { 15, 64, 159 },
3771 .hback_porch = { 5, 5, 5 },
3772 .hsync_len = { 1, 1, 256 },
3773 .vactive = { 800, 800, 800 },
3774 .vfront_porch = { 3, 40, 99 },
3775 .vback_porch = { 2, 2, 2 },
3776 .vsync_len = { 1, 1, 128 },
3777 .flags = DISPLAY_FLAGS_DE_HIGH,
3778 };
3779
3780 static const struct panel_desc tianma_tm070jdhg30 = {
3781 .timings = &tianma_tm070jdhg30_timing,
3782 .num_timings = 1,
3783 .bpc = 8,
3784 .size = {
3785 .width = 151,
3786 .height = 95,
3787 },
3788 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3789 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3790 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3791 };
3792
3793 static const struct panel_desc tianma_tm070jvhg33 = {
3794 .timings = &tianma_tm070jdhg30_timing,
3795 .num_timings = 1,
3796 .bpc = 8,
3797 .size = {
3798 .width = 150,
3799 .height = 94,
3800 },
3801 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3802 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3803 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3804 };
3805
3806 static const struct display_timing tianma_tm070rvhg71_timing = {
3807 .pixelclock = { 27700000, 29200000, 39600000 },
3808 .hactive = { 800, 800, 800 },
3809 .hfront_porch = { 12, 40, 212 },
3810 .hback_porch = { 88, 88, 88 },
3811 .hsync_len = { 1, 1, 40 },
3812 .vactive = { 480, 480, 480 },
3813 .vfront_porch = { 1, 13, 88 },
3814 .vback_porch = { 32, 32, 32 },
3815 .vsync_len = { 1, 1, 3 },
3816 .flags = DISPLAY_FLAGS_DE_HIGH,
3817 };
3818
3819 static const struct panel_desc tianma_tm070rvhg71 = {
3820 .timings = &tianma_tm070rvhg71_timing,
3821 .num_timings = 1,
3822 .bpc = 8,
3823 .size = {
3824 .width = 154,
3825 .height = 86,
3826 },
3827 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3828 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3829 };
3830
3831 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
3832 {
3833 .clock = 10000,
3834 .hdisplay = 320,
3835 .hsync_start = 320 + 50,
3836 .hsync_end = 320 + 50 + 6,
3837 .htotal = 320 + 50 + 6 + 38,
3838 .vdisplay = 240,
3839 .vsync_start = 240 + 3,
3840 .vsync_end = 240 + 3 + 1,
3841 .vtotal = 240 + 3 + 1 + 17,
3842 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3843 },
3844 };
3845
3846 static const struct panel_desc ti_nspire_cx_lcd_panel = {
3847 .modes = ti_nspire_cx_lcd_mode,
3848 .num_modes = 1,
3849 .bpc = 8,
3850 .size = {
3851 .width = 65,
3852 .height = 49,
3853 },
3854 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3855 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
3856 };
3857
3858 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
3859 {
3860 .clock = 10000,
3861 .hdisplay = 320,
3862 .hsync_start = 320 + 6,
3863 .hsync_end = 320 + 6 + 6,
3864 .htotal = 320 + 6 + 6 + 6,
3865 .vdisplay = 240,
3866 .vsync_start = 240 + 0,
3867 .vsync_end = 240 + 0 + 1,
3868 .vtotal = 240 + 0 + 1 + 0,
3869 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3870 },
3871 };
3872
3873 static const struct panel_desc ti_nspire_classic_lcd_panel = {
3874 .modes = ti_nspire_classic_lcd_mode,
3875 .num_modes = 1,
3876 /* The grayscale panel has 8 bit for the color .. Y (black) */
3877 .bpc = 8,
3878 .size = {
3879 .width = 71,
3880 .height = 53,
3881 },
3882 /* This is the grayscale bus format */
3883 .bus_format = MEDIA_BUS_FMT_Y8_1X8,
3884 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3885 };
3886
3887 static const struct drm_display_mode toshiba_lt089ac29000_mode = {
3888 .clock = 79500,
3889 .hdisplay = 1280,
3890 .hsync_start = 1280 + 192,
3891 .hsync_end = 1280 + 192 + 128,
3892 .htotal = 1280 + 192 + 128 + 64,
3893 .vdisplay = 768,
3894 .vsync_start = 768 + 20,
3895 .vsync_end = 768 + 20 + 7,
3896 .vtotal = 768 + 20 + 7 + 3,
3897 };
3898
3899 static const struct panel_desc toshiba_lt089ac29000 = {
3900 .modes = &toshiba_lt089ac29000_mode,
3901 .num_modes = 1,
3902 .size = {
3903 .width = 194,
3904 .height = 116,
3905 },
3906 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3907 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3908 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3909 };
3910
3911 static const struct drm_display_mode tpk_f07a_0102_mode = {
3912 .clock = 33260,
3913 .hdisplay = 800,
3914 .hsync_start = 800 + 40,
3915 .hsync_end = 800 + 40 + 128,
3916 .htotal = 800 + 40 + 128 + 88,
3917 .vdisplay = 480,
3918 .vsync_start = 480 + 10,
3919 .vsync_end = 480 + 10 + 2,
3920 .vtotal = 480 + 10 + 2 + 33,
3921 };
3922
3923 static const struct panel_desc tpk_f07a_0102 = {
3924 .modes = &tpk_f07a_0102_mode,
3925 .num_modes = 1,
3926 .size = {
3927 .width = 152,
3928 .height = 91,
3929 },
3930 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3931 };
3932
3933 static const struct drm_display_mode tpk_f10a_0102_mode = {
3934 .clock = 45000,
3935 .hdisplay = 1024,
3936 .hsync_start = 1024 + 176,
3937 .hsync_end = 1024 + 176 + 5,
3938 .htotal = 1024 + 176 + 5 + 88,
3939 .vdisplay = 600,
3940 .vsync_start = 600 + 20,
3941 .vsync_end = 600 + 20 + 5,
3942 .vtotal = 600 + 20 + 5 + 25,
3943 };
3944
3945 static const struct panel_desc tpk_f10a_0102 = {
3946 .modes = &tpk_f10a_0102_mode,
3947 .num_modes = 1,
3948 .size = {
3949 .width = 223,
3950 .height = 125,
3951 },
3952 };
3953
3954 static const struct display_timing urt_umsh_8596md_timing = {
3955 .pixelclock = { 33260000, 33260000, 33260000 },
3956 .hactive = { 800, 800, 800 },
3957 .hfront_porch = { 41, 41, 41 },
3958 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
3959 .hsync_len = { 71, 128, 128 },
3960 .vactive = { 480, 480, 480 },
3961 .vfront_porch = { 10, 10, 10 },
3962 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
3963 .vsync_len = { 2, 2, 2 },
3964 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
3965 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
3966 };
3967
3968 static const struct panel_desc urt_umsh_8596md_lvds = {
3969 .timings = &urt_umsh_8596md_timing,
3970 .num_timings = 1,
3971 .bpc = 6,
3972 .size = {
3973 .width = 152,
3974 .height = 91,
3975 },
3976 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3977 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3978 };
3979
3980 static const struct panel_desc urt_umsh_8596md_parallel = {
3981 .timings = &urt_umsh_8596md_timing,
3982 .num_timings = 1,
3983 .bpc = 6,
3984 .size = {
3985 .width = 152,
3986 .height = 91,
3987 },
3988 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3989 };
3990
3991 static const struct drm_display_mode vivax_tpc9150_panel_mode = {
3992 .clock = 60000,
3993 .hdisplay = 1024,
3994 .hsync_start = 1024 + 160,
3995 .hsync_end = 1024 + 160 + 100,
3996 .htotal = 1024 + 160 + 100 + 60,
3997 .vdisplay = 600,
3998 .vsync_start = 600 + 12,
3999 .vsync_end = 600 + 12 + 10,
4000 .vtotal = 600 + 12 + 10 + 13,
4001 };
4002
4003 static const struct panel_desc vivax_tpc9150_panel = {
4004 .modes = &vivax_tpc9150_panel_mode,
4005 .num_modes = 1,
4006 .bpc = 6,
4007 .size = {
4008 .width = 200,
4009 .height = 115,
4010 },
4011 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
4012 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4013 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4014 };
4015
4016 static const struct drm_display_mode vl050_8048nt_c01_mode = {
4017 .clock = 33333,
4018 .hdisplay = 800,
4019 .hsync_start = 800 + 210,
4020 .hsync_end = 800 + 210 + 20,
4021 .htotal = 800 + 210 + 20 + 46,
4022 .vdisplay = 480,
4023 .vsync_start = 480 + 22,
4024 .vsync_end = 480 + 22 + 10,
4025 .vtotal = 480 + 22 + 10 + 23,
4026 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
4027 };
4028
4029 static const struct panel_desc vl050_8048nt_c01 = {
4030 .modes = &vl050_8048nt_c01_mode,
4031 .num_modes = 1,
4032 .bpc = 8,
4033 .size = {
4034 .width = 120,
4035 .height = 76,
4036 },
4037 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4038 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
4039 };
4040
4041 static const struct drm_display_mode winstar_wf35ltiacd_mode = {
4042 .clock = 6410,
4043 .hdisplay = 320,
4044 .hsync_start = 320 + 20,
4045 .hsync_end = 320 + 20 + 30,
4046 .htotal = 320 + 20 + 30 + 38,
4047 .vdisplay = 240,
4048 .vsync_start = 240 + 4,
4049 .vsync_end = 240 + 4 + 3,
4050 .vtotal = 240 + 4 + 3 + 15,
4051 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4052 };
4053
4054 static const struct panel_desc winstar_wf35ltiacd = {
4055 .modes = &winstar_wf35ltiacd_mode,
4056 .num_modes = 1,
4057 .bpc = 8,
4058 .size = {
4059 .width = 70,
4060 .height = 53,
4061 },
4062 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4063 };
4064
4065 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = {
4066 .clock = 51200,
4067 .hdisplay = 1024,
4068 .hsync_start = 1024 + 100,
4069 .hsync_end = 1024 + 100 + 100,
4070 .htotal = 1024 + 100 + 100 + 120,
4071 .vdisplay = 600,
4072 .vsync_start = 600 + 10,
4073 .vsync_end = 600 + 10 + 10,
4074 .vtotal = 600 + 10 + 10 + 15,
4075 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
4076 };
4077
4078 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = {
4079 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode,
4080 .num_modes = 1,
4081 .bpc = 8,
4082 .size = {
4083 .width = 154,
4084 .height = 90,
4085 },
4086 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4087 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4088 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4089 };
4090
4091 static const struct drm_display_mode mchp_ac69t88a_mode = {
4092 .clock = 25000,
4093 .hdisplay = 800,
4094 .hsync_start = 800 + 88,
4095 .hsync_end = 800 + 88 + 5,
4096 .htotal = 800 + 88 + 5 + 40,
4097 .vdisplay = 480,
4098 .vsync_start = 480 + 23,
4099 .vsync_end = 480 + 23 + 5,
4100 .vtotal = 480 + 23 + 5 + 1,
4101 };
4102
4103 static const struct panel_desc mchp_ac69t88a = {
4104 .modes = &mchp_ac69t88a_mode,
4105 .num_modes = 1,
4106 .bpc = 8,
4107 .size = {
4108 .width = 108,
4109 .height = 65,
4110 },
4111 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4112 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
4113 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4114 };
4115
4116 static const struct drm_display_mode arm_rtsm_mode[] = {
4117 {
4118 .clock = 65000,
4119 .hdisplay = 1024,
4120 .hsync_start = 1024 + 24,
4121 .hsync_end = 1024 + 24 + 136,
4122 .htotal = 1024 + 24 + 136 + 160,
4123 .vdisplay = 768,
4124 .vsync_start = 768 + 3,
4125 .vsync_end = 768 + 3 + 6,
4126 .vtotal = 768 + 3 + 6 + 29,
4127 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4128 },
4129 };
4130
4131 static const struct panel_desc arm_rtsm = {
4132 .modes = arm_rtsm_mode,
4133 .num_modes = 1,
4134 .bpc = 8,
4135 .size = {
4136 .width = 400,
4137 .height = 300,
4138 },
4139 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4140 };
4141
4142 static const struct of_device_id platform_of_match[] = {
4143 {
4144 .compatible = "ampire,am-1280800n3tzqw-t00h",
4145 .data = &ire_am_1280800n3tzqw_t00h,
4146 }, {
4147 .compatible = "ampire,am-480272h3tmqw-t01h",
4148 .data = &ire_am_480272h3tmqw_t01h,
4149 }, {
4150 .compatible = "ampire,am-800480l1tmqw-t00h",
4151 .data = &ire_am_800480l1tmqw_t00h,
4152 }, {
4153 .compatible = "ampire,am800480r3tmqwa1h",
4154 .data = &ire_am800480r3tmqwa1h,
4155 }, {
4156 .compatible = "ampire,am800600p5tmqw-tb8h",
4157 .data = &ire_am800600p5tmqwtb8h,
4158 }, {
4159 .compatible = "arm,rtsm-display",
4160 .data = &arm_rtsm,
4161 }, {
4162 .compatible = "armadeus,st0700-adapt",
4163 .data = &armadeus_st0700_adapt,
4164 }, {
4165 .compatible = "auo,b101aw03",
4166 .data = &auo_b101aw03,
4167 }, {
4168 .compatible = "auo,b101xtn01",
4169 .data = &auo_b101xtn01,
4170 }, {
4171 .compatible = "auo,b116xw03",
4172 .data = &auo_b116xw03,
4173 }, {
4174 .compatible = "auo,g070vvn01",
4175 .data = &auo_g070vvn01,
4176 }, {
4177 .compatible = "auo,g101evn010",
4178 .data = &auo_g101evn010,
4179 }, {
4180 .compatible = "auo,g104sn02",
4181 .data = &auo_g104sn02,
4182 }, {
4183 .compatible = "auo,g121ean01",
4184 .data = &auo_g121ean01,
4185 }, {
4186 .compatible = "auo,g133han01",
4187 .data = &auo_g133han01,
4188 }, {
4189 .compatible = "auo,g156xtn01",
4190 .data = &auo_g156xtn01,
4191 }, {
4192 .compatible = "auo,g185han01",
4193 .data = &auo_g185han01,
4194 }, {
4195 .compatible = "auo,g190ean01",
4196 .data = &auo_g190ean01,
4197 }, {
4198 .compatible = "auo,p320hvn03",
4199 .data = &auo_p320hvn03,
4200 }, {
4201 .compatible = "auo,t215hvn01",
4202 .data = &auo_t215hvn01,
4203 }, {
4204 .compatible = "avic,tm070ddh03",
4205 .data = &avic_tm070ddh03,
4206 }, {
4207 .compatible = "bananapi,s070wv20-ct16",
4208 .data = &bananapi_s070wv20_ct16,
4209 }, {
4210 .compatible = "boe,ev121wxm-n10-1850",
4211 .data = &boe_ev121wxm_n10_1850,
4212 }, {
4213 .compatible = "boe,hv070wsa-100",
4214 .data = &boe_hv070wsa
4215 }, {
4216 .compatible = "cdtech,s043wq26h-ct7",
4217 .data = &cdtech_s043wq26h_ct7,
4218 }, {
4219 .compatible = "cdtech,s070pws19hp-fc21",
4220 .data = &cdtech_s070pws19hp_fc21,
4221 }, {
4222 .compatible = "cdtech,s070swv29hg-dc44",
4223 .data = &cdtech_s070swv29hg_dc44,
4224 }, {
4225 .compatible = "cdtech,s070wv95-ct16",
4226 .data = &cdtech_s070wv95_ct16,
4227 }, {
4228 .compatible = "chefree,ch101olhlwh-002",
4229 .data = &chefree_ch101olhlwh_002,
4230 }, {
4231 .compatible = "chunghwa,claa070wp03xg",
4232 .data = &chunghwa_claa070wp03xg,
4233 }, {
4234 .compatible = "chunghwa,claa101wa01a",
4235 .data = &chunghwa_claa101wa01a
4236 }, {
4237 .compatible = "chunghwa,claa101wb01",
4238 .data = &chunghwa_claa101wb01
4239 }, {
4240 .compatible = "dataimage,fg040346dsswbg04",
4241 .data = &dataimage_fg040346dsswbg04,
4242 }, {
4243 .compatible = "dataimage,fg1001l0dsswmg01",
4244 .data = &dataimage_fg1001l0dsswmg01,
4245 }, {
4246 .compatible = "dataimage,scf0700c48ggu18",
4247 .data = &dataimage_scf0700c48ggu18,
4248 }, {
4249 .compatible = "dlc,dlc0700yzg-1",
4250 .data = &dlc_dlc0700yzg_1,
4251 }, {
4252 .compatible = "dlc,dlc1010gig",
4253 .data = &dlc_dlc1010gig,
4254 }, {
4255 .compatible = "edt,et035012dm6",
4256 .data = &edt_et035012dm6,
4257 }, {
4258 .compatible = "edt,etm0350g0dh6",
4259 .data = &edt_etm0350g0dh6,
4260 }, {
4261 .compatible = "edt,etm043080dh6gp",
4262 .data = &edt_etm043080dh6gp,
4263 }, {
4264 .compatible = "edt,etm0430g0dh6",
4265 .data = &edt_etm0430g0dh6,
4266 }, {
4267 .compatible = "edt,et057090dhu",
4268 .data = &edt_et057090dhu,
4269 }, {
4270 .compatible = "edt,et070080dh6",
4271 .data = &edt_etm0700g0dh6,
4272 }, {
4273 .compatible = "edt,etm0700g0dh6",
4274 .data = &edt_etm0700g0dh6,
4275 }, {
4276 .compatible = "edt,etm0700g0bdh6",
4277 .data = &edt_etm0700g0bdh6,
4278 }, {
4279 .compatible = "edt,etm0700g0edh6",
4280 .data = &edt_etm0700g0bdh6,
4281 }, {
4282 .compatible = "edt,etml0700y5dha",
4283 .data = &edt_etml0700y5dha,
4284 }, {
4285 .compatible = "edt,etmv570g2dhu",
4286 .data = &edt_etmv570g2dhu,
4287 }, {
4288 .compatible = "eink,vb3300-kca",
4289 .data = &eink_vb3300_kca,
4290 }, {
4291 .compatible = "evervision,vgg804821",
4292 .data = &evervision_vgg804821,
4293 }, {
4294 .compatible = "foxlink,fl500wvr00-a0t",
4295 .data = &foxlink_fl500wvr00_a0t,
4296 }, {
4297 .compatible = "frida,frd350h54004",
4298 .data = &frida_frd350h54004,
4299 }, {
4300 .compatible = "friendlyarm,hd702e",
4301 .data = &friendlyarm_hd702e,
4302 }, {
4303 .compatible = "giantplus,gpg482739qs5",
4304 .data = &giantplus_gpg482739qs5
4305 }, {
4306 .compatible = "giantplus,gpm940b0",
4307 .data = &giantplus_gpm940b0,
4308 }, {
4309 .compatible = "hannstar,hsd070pww1",
4310 .data = &hannstar_hsd070pww1,
4311 }, {
4312 .compatible = "hannstar,hsd100pxn1",
4313 .data = &hannstar_hsd100pxn1,
4314 }, {
4315 .compatible = "hannstar,hsd101pww2",
4316 .data = &hannstar_hsd101pww2,
4317 }, {
4318 .compatible = "hit,tx23d38vm0caa",
4319 .data = &hitachi_tx23d38vm0caa
4320 }, {
4321 .compatible = "innolux,at043tn24",
4322 .data = &innolux_at043tn24,
4323 }, {
4324 .compatible = "innolux,at070tn92",
4325 .data = &innolux_at070tn92,
4326 }, {
4327 .compatible = "innolux,g070ace-l01",
4328 .data = &innolux_g070ace_l01,
4329 }, {
4330 .compatible = "innolux,g070y2-l01",
4331 .data = &innolux_g070y2_l01,
4332 }, {
4333 .compatible = "innolux,g070y2-t02",
4334 .data = &innolux_g070y2_t02,
4335 }, {
4336 .compatible = "innolux,g101ice-l01",
4337 .data = &innolux_g101ice_l01
4338 }, {
4339 .compatible = "innolux,g121i1-l01",
4340 .data = &innolux_g121i1_l01
4341 }, {
4342 .compatible = "innolux,g121x1-l03",
4343 .data = &innolux_g121x1_l03,
4344 }, {
4345 .compatible = "innolux,g156hce-l01",
4346 .data = &innolux_g156hce_l01,
4347 }, {
4348 .compatible = "innolux,n156bge-l21",
4349 .data = &innolux_n156bge_l21,
4350 }, {
4351 .compatible = "innolux,zj070na-01p",
4352 .data = &innolux_zj070na_01p,
4353 }, {
4354 .compatible = "koe,tx14d24vm1bpa",
4355 .data = &koe_tx14d24vm1bpa,
4356 }, {
4357 .compatible = "koe,tx26d202vm0bwa",
4358 .data = &koe_tx26d202vm0bwa,
4359 }, {
4360 .compatible = "koe,tx31d200vm0baa",
4361 .data = &koe_tx31d200vm0baa,
4362 }, {
4363 .compatible = "kyo,tcg121xglp",
4364 .data = &kyo_tcg121xglp,
4365 }, {
4366 .compatible = "lemaker,bl035-rgb-002",
4367 .data = &lemaker_bl035_rgb_002,
4368 }, {
4369 .compatible = "lg,lb070wv8",
4370 .data = &lg_lb070wv8,
4371 }, {
4372 .compatible = "logicpd,type28",
4373 .data = &logicpd_type_28,
4374 }, {
4375 .compatible = "logictechno,lt161010-2nhc",
4376 .data = &logictechno_lt161010_2nh,
4377 }, {
4378 .compatible = "logictechno,lt161010-2nhr",
4379 .data = &logictechno_lt161010_2nh,
4380 }, {
4381 .compatible = "logictechno,lt170410-2whc",
4382 .data = &logictechno_lt170410_2whc,
4383 }, {
4384 .compatible = "logictechno,lttd800480070-l2rt",
4385 .data = &logictechno_lttd800480070_l2rt,
4386 }, {
4387 .compatible = "logictechno,lttd800480070-l6wh-rt",
4388 .data = &logictechno_lttd800480070_l6wh_rt,
4389 }, {
4390 .compatible = "mitsubishi,aa070mc01-ca1",
4391 .data = &mitsubishi_aa070mc01,
4392 }, {
4393 .compatible = "multi-inno,mi0700s4t-6",
4394 .data = &multi_inno_mi0700s4t_6,
4395 }, {
4396 .compatible = "multi-inno,mi0800ft-9",
4397 .data = &multi_inno_mi0800ft_9,
4398 }, {
4399 .compatible = "multi-inno,mi1010ait-1cp",
4400 .data = &multi_inno_mi1010ait_1cp,
4401 }, {
4402 .compatible = "nec,nl12880bc20-05",
4403 .data = &nec_nl12880bc20_05,
4404 }, {
4405 .compatible = "nec,nl4827hc19-05b",
4406 .data = &nec_nl4827hc19_05b,
4407 }, {
4408 .compatible = "netron-dy,e231732",
4409 .data = &netron_dy_e231732,
4410 }, {
4411 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
4412 .data = &newhaven_nhd_43_480272ef_atxl,
4413 }, {
4414 .compatible = "nlt,nl192108ac18-02d",
4415 .data = &nlt_nl192108ac18_02d,
4416 }, {
4417 .compatible = "nvd,9128",
4418 .data = &nvd_9128,
4419 }, {
4420 .compatible = "okaya,rs800480t-7x0gp",
4421 .data = &okaya_rs800480t_7x0gp,
4422 }, {
4423 .compatible = "olimex,lcd-olinuxino-43-ts",
4424 .data = &olimex_lcd_olinuxino_43ts,
4425 }, {
4426 .compatible = "ontat,yx700wv03",
4427 .data = &ontat_yx700wv03,
4428 }, {
4429 .compatible = "ortustech,com37h3m05dtc",
4430 .data = &ortustech_com37h3m,
4431 }, {
4432 .compatible = "ortustech,com37h3m99dtc",
4433 .data = &ortustech_com37h3m,
4434 }, {
4435 .compatible = "ortustech,com43h4m85ulc",
4436 .data = &ortustech_com43h4m85ulc,
4437 }, {
4438 .compatible = "osddisplays,osd070t1718-19ts",
4439 .data = &osddisplays_osd070t1718_19ts,
4440 }, {
4441 .compatible = "pda,91-00156-a0",
4442 .data = &pda_91_00156_a0,
4443 }, {
4444 .compatible = "powertip,ph800480t013-idf02",
4445 .data = &powertip_ph800480t013_idf02,
4446 }, {
4447 .compatible = "qiaodian,qd43003c0-40",
4448 .data = &qd43003c0_40,
4449 }, {
4450 .compatible = "qishenglong,gopher2b-lcd",
4451 .data = &qishenglong_gopher2b_lcd,
4452 }, {
4453 .compatible = "rocktech,rk043fn48h",
4454 .data = &rocktech_rk043fn48h,
4455 }, {
4456 .compatible = "rocktech,rk070er9427",
4457 .data = &rocktech_rk070er9427,
4458 }, {
4459 .compatible = "rocktech,rk101ii01d-ct",
4460 .data = &rocktech_rk101ii01d_ct,
4461 }, {
4462 .compatible = "samsung,ltl101al01",
4463 .data = &samsung_ltl101al01,
4464 }, {
4465 .compatible = "samsung,ltn101nt05",
4466 .data = &samsung_ltn101nt05,
4467 }, {
4468 .compatible = "satoz,sat050at40h12r2",
4469 .data = &satoz_sat050at40h12r2,
4470 }, {
4471 .compatible = "sharp,lq035q7db03",
4472 .data = &sharp_lq035q7db03,
4473 }, {
4474 .compatible = "sharp,lq070y3dg3b",
4475 .data = &sharp_lq070y3dg3b,
4476 }, {
4477 .compatible = "sharp,lq101k1ly04",
4478 .data = &sharp_lq101k1ly04,
4479 }, {
4480 .compatible = "sharp,ls020b1dd01d",
4481 .data = &sharp_ls020b1dd01d,
4482 }, {
4483 .compatible = "shelly,sca07010-bfn-lnn",
4484 .data = &shelly_sca07010_bfn_lnn,
4485 }, {
4486 .compatible = "starry,kr070pe2t",
4487 .data = &starry_kr070pe2t,
4488 }, {
4489 .compatible = "startek,kd070wvfpa",
4490 .data = &startek_kd070wvfpa,
4491 }, {
4492 .compatible = "team-source-display,tst043015cmhx",
4493 .data = &tsd_tst043015cmhx,
4494 }, {
4495 .compatible = "tfc,s9700rtwv43tr-01b",
4496 .data = &tfc_s9700rtwv43tr_01b,
4497 }, {
4498 .compatible = "tianma,tm070jdhg30",
4499 .data = &tianma_tm070jdhg30,
4500 }, {
4501 .compatible = "tianma,tm070jvhg33",
4502 .data = &tianma_tm070jvhg33,
4503 }, {
4504 .compatible = "tianma,tm070rvhg71",
4505 .data = &tianma_tm070rvhg71,
4506 }, {
4507 .compatible = "ti,nspire-cx-lcd-panel",
4508 .data = &ti_nspire_cx_lcd_panel,
4509 }, {
4510 .compatible = "ti,nspire-classic-lcd-panel",
4511 .data = &ti_nspire_classic_lcd_panel,
4512 }, {
4513 .compatible = "toshiba,lt089ac29000",
4514 .data = &toshiba_lt089ac29000,
4515 }, {
4516 .compatible = "tpk,f07a-0102",
4517 .data = &tpk_f07a_0102,
4518 }, {
4519 .compatible = "tpk,f10a-0102",
4520 .data = &tpk_f10a_0102,
4521 }, {
4522 .compatible = "urt,umsh-8596md-t",
4523 .data = &urt_umsh_8596md_parallel,
4524 }, {
4525 .compatible = "urt,umsh-8596md-1t",
4526 .data = &urt_umsh_8596md_parallel,
4527 }, {
4528 .compatible = "urt,umsh-8596md-7t",
4529 .data = &urt_umsh_8596md_parallel,
4530 }, {
4531 .compatible = "urt,umsh-8596md-11t",
4532 .data = &urt_umsh_8596md_lvds,
4533 }, {
4534 .compatible = "urt,umsh-8596md-19t",
4535 .data = &urt_umsh_8596md_lvds,
4536 }, {
4537 .compatible = "urt,umsh-8596md-20t",
4538 .data = &urt_umsh_8596md_parallel,
4539 }, {
4540 .compatible = "vivax,tpc9150-panel",
4541 .data = &vivax_tpc9150_panel,
4542 }, {
4543 .compatible = "vxt,vl050-8048nt-c01",
4544 .data = &vl050_8048nt_c01,
4545 }, {
4546 .compatible = "winstar,wf35ltiacd",
4547 .data = &winstar_wf35ltiacd,
4548 }, {
4549 .compatible = "yes-optoelectronics,ytc700tlag-05-201c",
4550 .data = &yes_optoelectronics_ytc700tlag_05_201c,
4551 }, {
4552 .compatible = "microchip,ac69t88a",
4553 .data = &mchp_ac69t88a,
4554 }, {
4555 /* Must be the last entry */
4556 .compatible = "panel-dpi",
4557 .data = &panel_dpi,
4558 }, {
4559 /* sentinel */
4560 }
4561 };
4562 MODULE_DEVICE_TABLE(of, platform_of_match);
4563
panel_simple_platform_probe(struct platform_device * pdev)4564 static int panel_simple_platform_probe(struct platform_device *pdev)
4565 {
4566 const struct panel_desc *desc;
4567
4568 desc = of_device_get_match_data(&pdev->dev);
4569 if (!desc)
4570 return -ENODEV;
4571
4572 return panel_simple_probe(&pdev->dev, desc);
4573 }
4574
panel_simple_platform_remove(struct platform_device * pdev)4575 static void panel_simple_platform_remove(struct platform_device *pdev)
4576 {
4577 panel_simple_remove(&pdev->dev);
4578 }
4579
panel_simple_platform_shutdown(struct platform_device * pdev)4580 static void panel_simple_platform_shutdown(struct platform_device *pdev)
4581 {
4582 panel_simple_shutdown(&pdev->dev);
4583 }
4584
4585 static const struct dev_pm_ops panel_simple_pm_ops = {
4586 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL)
4587 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
4588 pm_runtime_force_resume)
4589 };
4590
4591 static struct platform_driver panel_simple_platform_driver = {
4592 .driver = {
4593 .name = "panel-simple",
4594 .of_match_table = platform_of_match,
4595 .pm = &panel_simple_pm_ops,
4596 },
4597 .probe = panel_simple_platform_probe,
4598 .remove_new = panel_simple_platform_remove,
4599 .shutdown = panel_simple_platform_shutdown,
4600 };
4601
4602 struct panel_desc_dsi {
4603 struct panel_desc desc;
4604
4605 unsigned long flags;
4606 enum mipi_dsi_pixel_format format;
4607 unsigned int lanes;
4608 };
4609
4610 static const struct drm_display_mode auo_b080uan01_mode = {
4611 .clock = 154500,
4612 .hdisplay = 1200,
4613 .hsync_start = 1200 + 62,
4614 .hsync_end = 1200 + 62 + 4,
4615 .htotal = 1200 + 62 + 4 + 62,
4616 .vdisplay = 1920,
4617 .vsync_start = 1920 + 9,
4618 .vsync_end = 1920 + 9 + 2,
4619 .vtotal = 1920 + 9 + 2 + 8,
4620 };
4621
4622 static const struct panel_desc_dsi auo_b080uan01 = {
4623 .desc = {
4624 .modes = &auo_b080uan01_mode,
4625 .num_modes = 1,
4626 .bpc = 8,
4627 .size = {
4628 .width = 108,
4629 .height = 272,
4630 },
4631 .connector_type = DRM_MODE_CONNECTOR_DSI,
4632 },
4633 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4634 .format = MIPI_DSI_FMT_RGB888,
4635 .lanes = 4,
4636 };
4637
4638 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
4639 .clock = 160000,
4640 .hdisplay = 1200,
4641 .hsync_start = 1200 + 120,
4642 .hsync_end = 1200 + 120 + 20,
4643 .htotal = 1200 + 120 + 20 + 21,
4644 .vdisplay = 1920,
4645 .vsync_start = 1920 + 21,
4646 .vsync_end = 1920 + 21 + 3,
4647 .vtotal = 1920 + 21 + 3 + 18,
4648 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4649 };
4650
4651 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
4652 .desc = {
4653 .modes = &boe_tv080wum_nl0_mode,
4654 .num_modes = 1,
4655 .size = {
4656 .width = 107,
4657 .height = 172,
4658 },
4659 .connector_type = DRM_MODE_CONNECTOR_DSI,
4660 },
4661 .flags = MIPI_DSI_MODE_VIDEO |
4662 MIPI_DSI_MODE_VIDEO_BURST |
4663 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
4664 .format = MIPI_DSI_FMT_RGB888,
4665 .lanes = 4,
4666 };
4667
4668 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
4669 .clock = 71000,
4670 .hdisplay = 800,
4671 .hsync_start = 800 + 32,
4672 .hsync_end = 800 + 32 + 1,
4673 .htotal = 800 + 32 + 1 + 57,
4674 .vdisplay = 1280,
4675 .vsync_start = 1280 + 28,
4676 .vsync_end = 1280 + 28 + 1,
4677 .vtotal = 1280 + 28 + 1 + 14,
4678 };
4679
4680 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
4681 .desc = {
4682 .modes = &lg_ld070wx3_sl01_mode,
4683 .num_modes = 1,
4684 .bpc = 8,
4685 .size = {
4686 .width = 94,
4687 .height = 151,
4688 },
4689 .connector_type = DRM_MODE_CONNECTOR_DSI,
4690 },
4691 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4692 .format = MIPI_DSI_FMT_RGB888,
4693 .lanes = 4,
4694 };
4695
4696 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
4697 .clock = 67000,
4698 .hdisplay = 720,
4699 .hsync_start = 720 + 12,
4700 .hsync_end = 720 + 12 + 4,
4701 .htotal = 720 + 12 + 4 + 112,
4702 .vdisplay = 1280,
4703 .vsync_start = 1280 + 8,
4704 .vsync_end = 1280 + 8 + 4,
4705 .vtotal = 1280 + 8 + 4 + 12,
4706 };
4707
4708 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
4709 .desc = {
4710 .modes = &lg_lh500wx1_sd03_mode,
4711 .num_modes = 1,
4712 .bpc = 8,
4713 .size = {
4714 .width = 62,
4715 .height = 110,
4716 },
4717 .connector_type = DRM_MODE_CONNECTOR_DSI,
4718 },
4719 .flags = MIPI_DSI_MODE_VIDEO,
4720 .format = MIPI_DSI_FMT_RGB888,
4721 .lanes = 4,
4722 };
4723
4724 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
4725 .clock = 157200,
4726 .hdisplay = 1920,
4727 .hsync_start = 1920 + 154,
4728 .hsync_end = 1920 + 154 + 16,
4729 .htotal = 1920 + 154 + 16 + 32,
4730 .vdisplay = 1200,
4731 .vsync_start = 1200 + 17,
4732 .vsync_end = 1200 + 17 + 2,
4733 .vtotal = 1200 + 17 + 2 + 16,
4734 };
4735
4736 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
4737 .desc = {
4738 .modes = &panasonic_vvx10f004b00_mode,
4739 .num_modes = 1,
4740 .bpc = 8,
4741 .size = {
4742 .width = 217,
4743 .height = 136,
4744 },
4745 .connector_type = DRM_MODE_CONNECTOR_DSI,
4746 },
4747 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4748 MIPI_DSI_CLOCK_NON_CONTINUOUS,
4749 .format = MIPI_DSI_FMT_RGB888,
4750 .lanes = 4,
4751 };
4752
4753 static const struct drm_display_mode lg_acx467akm_7_mode = {
4754 .clock = 150000,
4755 .hdisplay = 1080,
4756 .hsync_start = 1080 + 2,
4757 .hsync_end = 1080 + 2 + 2,
4758 .htotal = 1080 + 2 + 2 + 2,
4759 .vdisplay = 1920,
4760 .vsync_start = 1920 + 2,
4761 .vsync_end = 1920 + 2 + 2,
4762 .vtotal = 1920 + 2 + 2 + 2,
4763 };
4764
4765 static const struct panel_desc_dsi lg_acx467akm_7 = {
4766 .desc = {
4767 .modes = &lg_acx467akm_7_mode,
4768 .num_modes = 1,
4769 .bpc = 8,
4770 .size = {
4771 .width = 62,
4772 .height = 110,
4773 },
4774 .connector_type = DRM_MODE_CONNECTOR_DSI,
4775 },
4776 .flags = 0,
4777 .format = MIPI_DSI_FMT_RGB888,
4778 .lanes = 4,
4779 };
4780
4781 static const struct drm_display_mode osd101t2045_53ts_mode = {
4782 .clock = 154500,
4783 .hdisplay = 1920,
4784 .hsync_start = 1920 + 112,
4785 .hsync_end = 1920 + 112 + 16,
4786 .htotal = 1920 + 112 + 16 + 32,
4787 .vdisplay = 1200,
4788 .vsync_start = 1200 + 16,
4789 .vsync_end = 1200 + 16 + 2,
4790 .vtotal = 1200 + 16 + 2 + 16,
4791 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
4792 };
4793
4794 static const struct panel_desc_dsi osd101t2045_53ts = {
4795 .desc = {
4796 .modes = &osd101t2045_53ts_mode,
4797 .num_modes = 1,
4798 .bpc = 8,
4799 .size = {
4800 .width = 217,
4801 .height = 136,
4802 },
4803 .connector_type = DRM_MODE_CONNECTOR_DSI,
4804 },
4805 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
4806 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4807 MIPI_DSI_MODE_NO_EOT_PACKET,
4808 .format = MIPI_DSI_FMT_RGB888,
4809 .lanes = 4,
4810 };
4811
4812 static const struct of_device_id dsi_of_match[] = {
4813 {
4814 .compatible = "auo,b080uan01",
4815 .data = &auo_b080uan01
4816 }, {
4817 .compatible = "boe,tv080wum-nl0",
4818 .data = &boe_tv080wum_nl0
4819 }, {
4820 .compatible = "lg,ld070wx3-sl01",
4821 .data = &lg_ld070wx3_sl01
4822 }, {
4823 .compatible = "lg,lh500wx1-sd03",
4824 .data = &lg_lh500wx1_sd03
4825 }, {
4826 .compatible = "panasonic,vvx10f004b00",
4827 .data = &panasonic_vvx10f004b00
4828 }, {
4829 .compatible = "lg,acx467akm-7",
4830 .data = &lg_acx467akm_7
4831 }, {
4832 .compatible = "osddisplays,osd101t2045-53ts",
4833 .data = &osd101t2045_53ts
4834 }, {
4835 /* sentinel */
4836 }
4837 };
4838 MODULE_DEVICE_TABLE(of, dsi_of_match);
4839
panel_simple_dsi_probe(struct mipi_dsi_device * dsi)4840 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
4841 {
4842 const struct panel_desc_dsi *desc;
4843 int err;
4844
4845 desc = of_device_get_match_data(&dsi->dev);
4846 if (!desc)
4847 return -ENODEV;
4848
4849 err = panel_simple_probe(&dsi->dev, &desc->desc);
4850 if (err < 0)
4851 return err;
4852
4853 dsi->mode_flags = desc->flags;
4854 dsi->format = desc->format;
4855 dsi->lanes = desc->lanes;
4856
4857 err = mipi_dsi_attach(dsi);
4858 if (err) {
4859 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi);
4860
4861 drm_panel_remove(&panel->base);
4862 }
4863
4864 return err;
4865 }
4866
panel_simple_dsi_remove(struct mipi_dsi_device * dsi)4867 static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
4868 {
4869 int err;
4870
4871 err = mipi_dsi_detach(dsi);
4872 if (err < 0)
4873 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
4874
4875 panel_simple_remove(&dsi->dev);
4876 }
4877
panel_simple_dsi_shutdown(struct mipi_dsi_device * dsi)4878 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
4879 {
4880 panel_simple_shutdown(&dsi->dev);
4881 }
4882
4883 static struct mipi_dsi_driver panel_simple_dsi_driver = {
4884 .driver = {
4885 .name = "panel-simple-dsi",
4886 .of_match_table = dsi_of_match,
4887 .pm = &panel_simple_pm_ops,
4888 },
4889 .probe = panel_simple_dsi_probe,
4890 .remove = panel_simple_dsi_remove,
4891 .shutdown = panel_simple_dsi_shutdown,
4892 };
4893
panel_simple_init(void)4894 static int __init panel_simple_init(void)
4895 {
4896 int err;
4897
4898 err = platform_driver_register(&panel_simple_platform_driver);
4899 if (err < 0)
4900 return err;
4901
4902 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
4903 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
4904 if (err < 0)
4905 goto err_did_platform_register;
4906 }
4907
4908 return 0;
4909
4910 err_did_platform_register:
4911 platform_driver_unregister(&panel_simple_platform_driver);
4912
4913 return err;
4914 }
4915 module_init(panel_simple_init);
4916
panel_simple_exit(void)4917 static void __exit panel_simple_exit(void)
4918 {
4919 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
4920 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
4921
4922 platform_driver_unregister(&panel_simple_platform_driver);
4923 }
4924 module_exit(panel_simple_exit);
4925
4926 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
4927 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
4928 MODULE_LICENSE("GPL and additional rights");
4929