1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2019 Intel Corporation
4 */
5
6 #include <linux/pm_runtime.h>
7 #include <linux/string_helpers.h>
8
9 #include "gem/i915_gem_region.h"
10 #include "i915_drv.h"
11 #include "i915_reg.h"
12 #include "i915_vgpu.h"
13 #include "intel_engine_regs.h"
14 #include "intel_gt.h"
15 #include "intel_gt_pm.h"
16 #include "intel_gt_regs.h"
17 #include "intel_pcode.h"
18 #include "intel_rc6.h"
19
20 /**
21 * DOC: RC6
22 *
23 * RC6 is a special power stage which allows the GPU to enter an very
24 * low-voltage mode when idle, using down to 0V while at this stage. This
25 * stage is entered automatically when the GPU is idle when RC6 support is
26 * enabled, and as soon as new workload arises GPU wakes up automatically as
27 * well.
28 *
29 * There are different RC6 modes available in Intel GPU, which differentiate
30 * among each other with the latency required to enter and leave RC6 and
31 * voltage consumed by the GPU in different states.
32 *
33 * The combination of the following flags define which states GPU is allowed
34 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
35 * RC6pp is deepest RC6. Their support by hardware varies according to the
36 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
37 * which brings the most power savings; deeper states save more power, but
38 * require higher latency to switch to and wake up.
39 */
40
rc6_to_gt(struct intel_rc6 * rc6)41 static struct intel_gt *rc6_to_gt(struct intel_rc6 *rc6)
42 {
43 return container_of(rc6, struct intel_gt, rc6);
44 }
45
rc6_to_uncore(struct intel_rc6 * rc)46 static struct intel_uncore *rc6_to_uncore(struct intel_rc6 *rc)
47 {
48 return rc6_to_gt(rc)->uncore;
49 }
50
rc6_to_i915(struct intel_rc6 * rc)51 static struct drm_i915_private *rc6_to_i915(struct intel_rc6 *rc)
52 {
53 return rc6_to_gt(rc)->i915;
54 }
55
gen11_rc6_enable(struct intel_rc6 * rc6)56 static void gen11_rc6_enable(struct intel_rc6 *rc6)
57 {
58 struct intel_gt *gt = rc6_to_gt(rc6);
59 struct intel_uncore *uncore = gt->uncore;
60 struct intel_engine_cs *engine;
61 enum intel_engine_id id;
62 u32 pg_enable;
63 int i;
64
65 /*
66 * With GuCRC, these parameters are set by GuC
67 */
68 if (!intel_uc_uses_guc_rc(>->uc)) {
69 /* 2b: Program RC6 thresholds.*/
70 intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
71 intel_uncore_write_fw(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
72
73 intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
74 intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
75 for_each_engine(engine, rc6_to_gt(rc6), id)
76 intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
77
78 intel_uncore_write_fw(uncore, GUC_MAX_IDLE_COUNT, 0xA);
79
80 intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
81
82 intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
83 }
84
85 /*
86 * 2c: Program Coarse Power Gating Policies.
87 *
88 * Bspec's guidance is to use 25us (really 25 * 1280ns) here. What we
89 * use instead is a more conservative estimate for the maximum time
90 * it takes us to service a CS interrupt and submit a new ELSP - that
91 * is the time which the GPU is idle waiting for the CPU to select the
92 * next request to execute. If the idle hysteresis is less than that
93 * interrupt service latency, the hardware will automatically gate
94 * the power well and we will then incur the wake up cost on top of
95 * the service latency. A similar guide from plane_state is that we
96 * do not want the enable hysteresis to less than the wakeup latency.
97 *
98 * igt/gem_exec_nop/sequential provides a rough estimate for the
99 * service latency, and puts it under 10us for Icelake, similar to
100 * Broadwell+, To be conservative, we want to factor in a context
101 * switch on top (due to ksoftirqd).
102 */
103 intel_uncore_write_fw(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 60);
104 intel_uncore_write_fw(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 60);
105
106 /* 3a: Enable RC6
107 *
108 * With GuCRC, we do not enable bit 31 of RC_CTL,
109 * thus allowing GuC to control RC6 entry/exit fully instead.
110 * We will not set the HW ENABLE and EI bits
111 */
112 if (!intel_guc_rc_enable(>->uc.guc))
113 rc6->ctl_enable = GEN6_RC_CTL_RC6_ENABLE;
114 else
115 rc6->ctl_enable =
116 GEN6_RC_CTL_HW_ENABLE |
117 GEN6_RC_CTL_RC6_ENABLE |
118 GEN6_RC_CTL_EI_MODE(1);
119
120 pg_enable =
121 GEN9_RENDER_PG_ENABLE |
122 GEN9_MEDIA_PG_ENABLE |
123 GEN11_MEDIA_SAMPLER_PG_ENABLE;
124
125 if (GRAPHICS_VER(gt->i915) >= 12 && !IS_DG1(gt->i915)) {
126 for (i = 0; i < I915_MAX_VCS; i++)
127 if (HAS_ENGINE(gt, _VCS(i)))
128 pg_enable |= (VDN_HCP_POWERGATE_ENABLE(i) |
129 VDN_MFX_POWERGATE_ENABLE(i));
130 }
131
132 intel_uncore_write_fw(uncore, GEN9_PG_ENABLE, pg_enable);
133 }
134
gen9_rc6_enable(struct intel_rc6 * rc6)135 static void gen9_rc6_enable(struct intel_rc6 *rc6)
136 {
137 struct intel_uncore *uncore = rc6_to_uncore(rc6);
138 struct intel_engine_cs *engine;
139 enum intel_engine_id id;
140
141 /* 2b: Program RC6 thresholds.*/
142 if (GRAPHICS_VER(rc6_to_i915(rc6)) >= 11) {
143 intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
144 intel_uncore_write_fw(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
145 } else if (IS_SKYLAKE(rc6_to_i915(rc6))) {
146 /*
147 * WaRsDoubleRc6WrlWithCoarsePowerGating:skl Doubling WRL only
148 * when CPG is enabled
149 */
150 intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
151 } else {
152 intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
153 }
154
155 intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
156 intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
157 for_each_engine(engine, rc6_to_gt(rc6), id)
158 intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
159
160 intel_uncore_write_fw(uncore, GUC_MAX_IDLE_COUNT, 0xA);
161
162 intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
163
164 /*
165 * 2c: Program Coarse Power Gating Policies.
166 *
167 * Bspec's guidance is to use 25us (really 25 * 1280ns) here. What we
168 * use instead is a more conservative estimate for the maximum time
169 * it takes us to service a CS interrupt and submit a new ELSP - that
170 * is the time which the GPU is idle waiting for the CPU to select the
171 * next request to execute. If the idle hysteresis is less than that
172 * interrupt service latency, the hardware will automatically gate
173 * the power well and we will then incur the wake up cost on top of
174 * the service latency. A similar guide from plane_state is that we
175 * do not want the enable hysteresis to less than the wakeup latency.
176 *
177 * igt/gem_exec_nop/sequential provides a rough estimate for the
178 * service latency, and puts it around 10us for Broadwell (and other
179 * big core) and around 40us for Broxton (and other low power cores).
180 * [Note that for legacy ringbuffer submission, this is less than 1us!]
181 * However, the wakeup latency on Broxton is closer to 100us. To be
182 * conservative, we have to factor in a context switch on top (due
183 * to ksoftirqd).
184 */
185 intel_uncore_write_fw(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 250);
186 intel_uncore_write_fw(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 250);
187
188 /* 3a: Enable RC6 */
189 intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
190
191 rc6->ctl_enable =
192 GEN6_RC_CTL_HW_ENABLE |
193 GEN6_RC_CTL_RC6_ENABLE |
194 GEN6_RC_CTL_EI_MODE(1);
195
196 /*
197 * WaRsDisableCoarsePowerGating:skl,cnl
198 * - Render/Media PG need to be disabled with RC6.
199 */
200 if (!NEEDS_WaRsDisableCoarsePowerGating(rc6_to_i915(rc6)))
201 intel_uncore_write_fw(uncore, GEN9_PG_ENABLE,
202 GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE);
203 }
204
gen8_rc6_enable(struct intel_rc6 * rc6)205 static void gen8_rc6_enable(struct intel_rc6 *rc6)
206 {
207 struct intel_uncore *uncore = rc6_to_uncore(rc6);
208 struct intel_engine_cs *engine;
209 enum intel_engine_id id;
210
211 /* 2b: Program RC6 thresholds.*/
212 intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
213 intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
214 intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
215 for_each_engine(engine, rc6_to_gt(rc6), id)
216 intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
217 intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
218 intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
219
220 /* 3: Enable RC6 */
221 rc6->ctl_enable =
222 GEN6_RC_CTL_HW_ENABLE |
223 GEN7_RC_CTL_TO_MODE |
224 GEN6_RC_CTL_RC6_ENABLE;
225 }
226
gen6_rc6_enable(struct intel_rc6 * rc6)227 static void gen6_rc6_enable(struct intel_rc6 *rc6)
228 {
229 struct intel_uncore *uncore = rc6_to_uncore(rc6);
230 struct drm_i915_private *i915 = rc6_to_i915(rc6);
231 struct intel_engine_cs *engine;
232 enum intel_engine_id id;
233 u32 rc6vids, rc6_mask;
234 int ret;
235
236 intel_uncore_write_fw(uncore, GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
237 intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
238 intel_uncore_write_fw(uncore, GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
239 intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);
240 intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);
241
242 for_each_engine(engine, rc6_to_gt(rc6), id)
243 intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
244
245 intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
246 intel_uncore_write_fw(uncore, GEN6_RC1e_THRESHOLD, 1000);
247 intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 50000);
248 intel_uncore_write_fw(uncore, GEN6_RC6p_THRESHOLD, 150000);
249 intel_uncore_write_fw(uncore, GEN6_RC6pp_THRESHOLD, 64000); /* unused */
250
251 /* We don't use those on Haswell */
252 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
253 if (HAS_RC6p(i915))
254 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
255 if (HAS_RC6pp(i915))
256 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
257 rc6->ctl_enable =
258 rc6_mask |
259 GEN6_RC_CTL_EI_MODE(1) |
260 GEN6_RC_CTL_HW_ENABLE;
261
262 rc6vids = 0;
263 ret = snb_pcode_read(rc6_to_gt(rc6)->uncore, GEN6_PCODE_READ_RC6VIDS, &rc6vids, NULL);
264 if (GRAPHICS_VER(i915) == 6 && ret) {
265 drm_dbg(&i915->drm, "Couldn't check for BIOS workaround\n");
266 } else if (GRAPHICS_VER(i915) == 6 &&
267 (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
268 drm_dbg(&i915->drm,
269 "You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
270 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
271 rc6vids &= 0xffff00;
272 rc6vids |= GEN6_ENCODE_RC6_VID(450);
273 ret = snb_pcode_write(rc6_to_gt(rc6)->uncore, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
274 if (ret)
275 drm_err(&i915->drm,
276 "Couldn't fix incorrect rc6 voltage\n");
277 }
278 }
279
280 /* Check that the pcbr address is not empty. */
chv_rc6_init(struct intel_rc6 * rc6)281 static int chv_rc6_init(struct intel_rc6 *rc6)
282 {
283 struct intel_uncore *uncore = rc6_to_uncore(rc6);
284 struct drm_i915_private *i915 = rc6_to_i915(rc6);
285 resource_size_t pctx_paddr, paddr;
286 resource_size_t pctx_size = 32 * SZ_1K;
287 u32 pcbr;
288
289 pcbr = intel_uncore_read(uncore, VLV_PCBR);
290 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
291 drm_dbg(&i915->drm, "BIOS didn't set up PCBR, fixing up\n");
292 paddr = i915->dsm.stolen.end + 1 - pctx_size;
293 GEM_BUG_ON(paddr > U32_MAX);
294
295 pctx_paddr = (paddr & ~4095);
296 intel_uncore_write(uncore, VLV_PCBR, pctx_paddr);
297 }
298
299 return 0;
300 }
301
vlv_rc6_init(struct intel_rc6 * rc6)302 static int vlv_rc6_init(struct intel_rc6 *rc6)
303 {
304 struct drm_i915_private *i915 = rc6_to_i915(rc6);
305 struct intel_uncore *uncore = rc6_to_uncore(rc6);
306 struct drm_i915_gem_object *pctx;
307 resource_size_t pctx_paddr;
308 resource_size_t pctx_size = 24 * SZ_1K;
309 u32 pcbr;
310
311 pcbr = intel_uncore_read(uncore, VLV_PCBR);
312 if (pcbr) {
313 /* BIOS set it up already, grab the pre-alloc'd space */
314 resource_size_t pcbr_offset;
315
316 pcbr_offset = (pcbr & ~4095) - i915->dsm.stolen.start;
317 pctx = i915_gem_object_create_region_at(i915->mm.stolen_region,
318 pcbr_offset,
319 pctx_size,
320 0);
321 if (IS_ERR(pctx))
322 return PTR_ERR(pctx);
323
324 goto out;
325 }
326
327 drm_dbg(&i915->drm, "BIOS didn't set up PCBR, fixing up\n");
328
329 /*
330 * From the Gunit register HAS:
331 * The Gfx driver is expected to program this register and ensure
332 * proper allocation within Gfx stolen memory. For example, this
333 * register should be programmed such than the PCBR range does not
334 * overlap with other ranges, such as the frame buffer, protected
335 * memory, or any other relevant ranges.
336 */
337 pctx = i915_gem_object_create_stolen(i915, pctx_size);
338 if (IS_ERR(pctx)) {
339 drm_dbg(&i915->drm,
340 "not enough stolen space for PCTX, disabling\n");
341 return PTR_ERR(pctx);
342 }
343
344 GEM_BUG_ON(range_overflows_end_t(u64,
345 i915->dsm.stolen.start,
346 pctx->stolen->start,
347 U32_MAX));
348 pctx_paddr = i915->dsm.stolen.start + pctx->stolen->start;
349 intel_uncore_write(uncore, VLV_PCBR, pctx_paddr);
350
351 out:
352 rc6->pctx = pctx;
353 return 0;
354 }
355
chv_rc6_enable(struct intel_rc6 * rc6)356 static void chv_rc6_enable(struct intel_rc6 *rc6)
357 {
358 struct intel_uncore *uncore = rc6_to_uncore(rc6);
359 struct intel_engine_cs *engine;
360 enum intel_engine_id id;
361
362 /* 2a: Program RC6 thresholds.*/
363 intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
364 intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
365 intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
366
367 for_each_engine(engine, rc6_to_gt(rc6), id)
368 intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
369 intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
370
371 /* TO threshold set to 500 us (0x186 * 1.28 us) */
372 intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 0x186);
373
374 /* Allows RC6 residency counter to work */
375 intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
376 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
377 VLV_MEDIA_RC6_COUNT_EN |
378 VLV_RENDER_RC6_COUNT_EN));
379
380 /* 3: Enable RC6 */
381 rc6->ctl_enable = GEN7_RC_CTL_TO_MODE;
382 }
383
vlv_rc6_enable(struct intel_rc6 * rc6)384 static void vlv_rc6_enable(struct intel_rc6 *rc6)
385 {
386 struct intel_uncore *uncore = rc6_to_uncore(rc6);
387 struct intel_engine_cs *engine;
388 enum intel_engine_id id;
389
390 intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
391 intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);
392 intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);
393
394 for_each_engine(engine, rc6_to_gt(rc6), id)
395 intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
396
397 intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 0x557);
398
399 /* Allows RC6 residency counter to work */
400 intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
401 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
402 VLV_MEDIA_RC0_COUNT_EN |
403 VLV_RENDER_RC0_COUNT_EN |
404 VLV_MEDIA_RC6_COUNT_EN |
405 VLV_RENDER_RC6_COUNT_EN));
406
407 rc6->ctl_enable =
408 GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
409 }
410
intel_check_bios_c6_setup(struct intel_rc6 * rc6)411 bool intel_check_bios_c6_setup(struct intel_rc6 *rc6)
412 {
413 if (!rc6->bios_state_captured) {
414 struct intel_uncore *uncore = rc6_to_uncore(rc6);
415 intel_wakeref_t wakeref;
416
417 with_intel_runtime_pm(uncore->rpm, wakeref)
418 rc6->bios_rc_state = intel_uncore_read(uncore, GEN6_RC_STATE);
419
420 rc6->bios_state_captured = true;
421 }
422
423 return rc6->bios_rc_state & RC_SW_TARGET_STATE_MASK;
424 }
425
bxt_check_bios_rc6_setup(struct intel_rc6 * rc6)426 static bool bxt_check_bios_rc6_setup(struct intel_rc6 *rc6)
427 {
428 struct intel_uncore *uncore = rc6_to_uncore(rc6);
429 struct drm_i915_private *i915 = rc6_to_i915(rc6);
430 u32 rc6_ctx_base, rc_ctl, rc_sw_target;
431 bool enable_rc6 = true;
432
433 rc_ctl = intel_uncore_read(uncore, GEN6_RC_CONTROL);
434 rc_sw_target = intel_uncore_read(uncore, GEN6_RC_STATE);
435 rc_sw_target &= RC_SW_TARGET_STATE_MASK;
436 rc_sw_target >>= RC_SW_TARGET_STATE_SHIFT;
437 drm_dbg(&i915->drm, "BIOS enabled RC states: "
438 "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
439 str_on_off(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
440 str_on_off(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
441 rc_sw_target);
442
443 if (!(intel_uncore_read(uncore, RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
444 drm_dbg(&i915->drm, "RC6 Base location not set properly.\n");
445 enable_rc6 = false;
446 }
447
448 /*
449 * The exact context size is not known for BXT, so assume a page size
450 * for this check.
451 */
452 rc6_ctx_base =
453 intel_uncore_read(uncore, RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
454 if (!(rc6_ctx_base >= i915->dsm.reserved.start &&
455 rc6_ctx_base + PAGE_SIZE < i915->dsm.reserved.end)) {
456 drm_dbg(&i915->drm, "RC6 Base address not as expected.\n");
457 enable_rc6 = false;
458 }
459
460 if (!((intel_uncore_read(uncore, PWRCTX_MAXCNT(RENDER_RING_BASE)) & IDLE_TIME_MASK) > 1 &&
461 (intel_uncore_read(uncore, PWRCTX_MAXCNT(GEN6_BSD_RING_BASE)) & IDLE_TIME_MASK) > 1 &&
462 (intel_uncore_read(uncore, PWRCTX_MAXCNT(BLT_RING_BASE)) & IDLE_TIME_MASK) > 1 &&
463 (intel_uncore_read(uncore, PWRCTX_MAXCNT(VEBOX_RING_BASE)) & IDLE_TIME_MASK) > 1)) {
464 drm_dbg(&i915->drm,
465 "Engine Idle wait time not set properly.\n");
466 enable_rc6 = false;
467 }
468
469 if (!intel_uncore_read(uncore, GEN8_PUSHBUS_CONTROL) ||
470 !intel_uncore_read(uncore, GEN8_PUSHBUS_ENABLE) ||
471 !intel_uncore_read(uncore, GEN8_PUSHBUS_SHIFT)) {
472 drm_dbg(&i915->drm, "Pushbus not setup properly.\n");
473 enable_rc6 = false;
474 }
475
476 if (!intel_uncore_read(uncore, GEN6_GFXPAUSE)) {
477 drm_dbg(&i915->drm, "GFX pause not setup properly.\n");
478 enable_rc6 = false;
479 }
480
481 if (!intel_uncore_read(uncore, GEN8_MISC_CTRL0)) {
482 drm_dbg(&i915->drm, "GPM control not setup properly.\n");
483 enable_rc6 = false;
484 }
485
486 return enable_rc6;
487 }
488
rc6_supported(struct intel_rc6 * rc6)489 static bool rc6_supported(struct intel_rc6 *rc6)
490 {
491 struct drm_i915_private *i915 = rc6_to_i915(rc6);
492 struct intel_gt *gt = rc6_to_gt(rc6);
493
494 if (!HAS_RC6(i915))
495 return false;
496
497 if (intel_vgpu_active(i915))
498 return false;
499
500 if (is_mock_gt(rc6_to_gt(rc6)))
501 return false;
502
503 if (IS_GEN9_LP(i915) && !bxt_check_bios_rc6_setup(rc6)) {
504 drm_notice(&i915->drm,
505 "RC6 and powersaving disabled by BIOS\n");
506 return false;
507 }
508
509 if (IS_METEORLAKE(gt->i915) &&
510 !intel_check_bios_c6_setup(rc6)) {
511 drm_notice(&i915->drm,
512 "C6 disabled by BIOS\n");
513 return false;
514 }
515
516 if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
517 gt->type == GT_MEDIA) {
518 drm_notice(&i915->drm,
519 "Media RC6 disabled on A step\n");
520 return false;
521 }
522
523 return true;
524 }
525
rpm_get(struct intel_rc6 * rc6)526 static void rpm_get(struct intel_rc6 *rc6)
527 {
528 GEM_BUG_ON(rc6->wakeref);
529 pm_runtime_get_sync(rc6_to_i915(rc6)->drm.dev);
530 rc6->wakeref = true;
531 }
532
rpm_put(struct intel_rc6 * rc6)533 static void rpm_put(struct intel_rc6 *rc6)
534 {
535 GEM_BUG_ON(!rc6->wakeref);
536 pm_runtime_put(rc6_to_i915(rc6)->drm.dev);
537 rc6->wakeref = false;
538 }
539
pctx_corrupted(struct intel_rc6 * rc6)540 static bool pctx_corrupted(struct intel_rc6 *rc6)
541 {
542 struct drm_i915_private *i915 = rc6_to_i915(rc6);
543
544 if (!NEEDS_RC6_CTX_CORRUPTION_WA(i915))
545 return false;
546
547 if (intel_uncore_read(rc6_to_uncore(rc6), GEN8_RC6_CTX_INFO))
548 return false;
549
550 drm_notice(&i915->drm,
551 "RC6 context corruption, disabling runtime power management\n");
552 return true;
553 }
554
__intel_rc6_disable(struct intel_rc6 * rc6)555 static void __intel_rc6_disable(struct intel_rc6 *rc6)
556 {
557 struct drm_i915_private *i915 = rc6_to_i915(rc6);
558 struct intel_uncore *uncore = rc6_to_uncore(rc6);
559 struct intel_gt *gt = rc6_to_gt(rc6);
560
561 /* Take control of RC6 back from GuC */
562 intel_guc_rc_disable(>->uc.guc);
563
564 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
565 if (GRAPHICS_VER(i915) >= 9)
566 intel_uncore_write_fw(uncore, GEN9_PG_ENABLE, 0);
567 intel_uncore_write_fw(uncore, GEN6_RC_CONTROL, 0);
568 intel_uncore_write_fw(uncore, GEN6_RC_STATE, 0);
569 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
570 }
571
rc6_res_reg_init(struct intel_rc6 * rc6)572 static void rc6_res_reg_init(struct intel_rc6 *rc6)
573 {
574 i915_reg_t res_reg[INTEL_RC6_RES_MAX] = {
575 [0 ... INTEL_RC6_RES_MAX - 1] = INVALID_MMIO_REG,
576 };
577
578 switch (rc6_to_gt(rc6)->type) {
579 case GT_MEDIA:
580 res_reg[INTEL_RC6_RES_RC6] = MTL_MEDIA_MC6;
581 break;
582 default:
583 res_reg[INTEL_RC6_RES_RC6_LOCKED] = GEN6_GT_GFX_RC6_LOCKED;
584 res_reg[INTEL_RC6_RES_RC6] = GEN6_GT_GFX_RC6;
585 res_reg[INTEL_RC6_RES_RC6p] = GEN6_GT_GFX_RC6p;
586 res_reg[INTEL_RC6_RES_RC6pp] = GEN6_GT_GFX_RC6pp;
587 break;
588 }
589
590 memcpy(rc6->res_reg, res_reg, sizeof(res_reg));
591 }
592
intel_rc6_init(struct intel_rc6 * rc6)593 void intel_rc6_init(struct intel_rc6 *rc6)
594 {
595 struct drm_i915_private *i915 = rc6_to_i915(rc6);
596 int err;
597
598 /* Disable runtime-pm until we can save the GPU state with rc6 pctx */
599 rpm_get(rc6);
600
601 if (!rc6_supported(rc6))
602 return;
603
604 rc6_res_reg_init(rc6);
605
606 if (IS_CHERRYVIEW(i915))
607 err = chv_rc6_init(rc6);
608 else if (IS_VALLEYVIEW(i915))
609 err = vlv_rc6_init(rc6);
610 else
611 err = 0;
612
613 /* Sanitize rc6, ensure it is disabled before we are ready. */
614 __intel_rc6_disable(rc6);
615
616 rc6->supported = err == 0;
617 }
618
intel_rc6_sanitize(struct intel_rc6 * rc6)619 void intel_rc6_sanitize(struct intel_rc6 *rc6)
620 {
621 memset(rc6->prev_hw_residency, 0, sizeof(rc6->prev_hw_residency));
622
623 if (rc6->enabled) { /* unbalanced suspend/resume */
624 rpm_get(rc6);
625 rc6->enabled = false;
626 }
627
628 if (rc6->supported)
629 __intel_rc6_disable(rc6);
630 }
631
intel_rc6_enable(struct intel_rc6 * rc6)632 void intel_rc6_enable(struct intel_rc6 *rc6)
633 {
634 struct drm_i915_private *i915 = rc6_to_i915(rc6);
635 struct intel_uncore *uncore = rc6_to_uncore(rc6);
636
637 if (!rc6->supported)
638 return;
639
640 GEM_BUG_ON(rc6->enabled);
641
642 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
643
644 if (IS_CHERRYVIEW(i915))
645 chv_rc6_enable(rc6);
646 else if (IS_VALLEYVIEW(i915))
647 vlv_rc6_enable(rc6);
648 else if (GRAPHICS_VER(i915) >= 11)
649 gen11_rc6_enable(rc6);
650 else if (GRAPHICS_VER(i915) >= 9)
651 gen9_rc6_enable(rc6);
652 else if (IS_BROADWELL(i915))
653 gen8_rc6_enable(rc6);
654 else if (GRAPHICS_VER(i915) >= 6)
655 gen6_rc6_enable(rc6);
656
657 rc6->manual = rc6->ctl_enable & GEN6_RC_CTL_RC6_ENABLE;
658 if (NEEDS_RC6_CTX_CORRUPTION_WA(i915))
659 rc6->ctl_enable = 0;
660
661 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
662
663 if (unlikely(pctx_corrupted(rc6)))
664 return;
665
666 /* rc6 is ready, runtime-pm is go! */
667 rpm_put(rc6);
668 rc6->enabled = true;
669 }
670
intel_rc6_unpark(struct intel_rc6 * rc6)671 void intel_rc6_unpark(struct intel_rc6 *rc6)
672 {
673 struct intel_uncore *uncore = rc6_to_uncore(rc6);
674
675 if (!rc6->enabled)
676 return;
677
678 /* Restore HW timers for automatic RC6 entry while busy */
679 intel_uncore_write_fw(uncore, GEN6_RC_CONTROL, rc6->ctl_enable);
680 }
681
intel_rc6_park(struct intel_rc6 * rc6)682 void intel_rc6_park(struct intel_rc6 *rc6)
683 {
684 struct intel_uncore *uncore = rc6_to_uncore(rc6);
685 unsigned int target;
686
687 if (!rc6->enabled)
688 return;
689
690 if (unlikely(pctx_corrupted(rc6))) {
691 intel_rc6_disable(rc6);
692 return;
693 }
694
695 if (!rc6->manual)
696 return;
697
698 /* Turn off the HW timers and go directly to rc6 */
699 intel_uncore_write_fw(uncore, GEN6_RC_CONTROL, GEN6_RC_CTL_RC6_ENABLE);
700
701 if (HAS_RC6pp(rc6_to_i915(rc6)))
702 target = 0x6; /* deepest rc6 */
703 else if (HAS_RC6p(rc6_to_i915(rc6)))
704 target = 0x5; /* deep rc6 */
705 else
706 target = 0x4; /* normal rc6 */
707 intel_uncore_write_fw(uncore, GEN6_RC_STATE, target << RC_SW_TARGET_STATE_SHIFT);
708 }
709
intel_rc6_disable(struct intel_rc6 * rc6)710 void intel_rc6_disable(struct intel_rc6 *rc6)
711 {
712 if (!rc6->enabled)
713 return;
714
715 rpm_get(rc6);
716 rc6->enabled = false;
717
718 __intel_rc6_disable(rc6);
719 }
720
intel_rc6_fini(struct intel_rc6 * rc6)721 void intel_rc6_fini(struct intel_rc6 *rc6)
722 {
723 struct drm_i915_gem_object *pctx;
724 struct intel_uncore *uncore = rc6_to_uncore(rc6);
725
726 intel_rc6_disable(rc6);
727
728 /* We want the BIOS C6 state preserved across loads for MTL */
729 if (IS_METEORLAKE(rc6_to_i915(rc6)) && rc6->bios_state_captured)
730 intel_uncore_write_fw(uncore, GEN6_RC_STATE, rc6->bios_rc_state);
731
732 pctx = fetch_and_zero(&rc6->pctx);
733 if (pctx)
734 i915_gem_object_put(pctx);
735
736 if (rc6->wakeref)
737 rpm_put(rc6);
738 }
739
vlv_residency_raw(struct intel_uncore * uncore,const i915_reg_t reg)740 static u64 vlv_residency_raw(struct intel_uncore *uncore, const i915_reg_t reg)
741 {
742 u32 lower, upper, tmp;
743 int loop = 2;
744
745 /*
746 * The register accessed do not need forcewake. We borrow
747 * uncore lock to prevent concurrent access to range reg.
748 */
749 lockdep_assert_held(&uncore->lock);
750
751 /*
752 * vlv and chv residency counters are 40 bits in width.
753 * With a control bit, we can choose between upper or lower
754 * 32bit window into this counter.
755 *
756 * Although we always use the counter in high-range mode elsewhere,
757 * userspace may attempt to read the value before rc6 is initialised,
758 * before we have set the default VLV_COUNTER_CONTROL value. So always
759 * set the high bit to be safe.
760 */
761 intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
762 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
763 upper = intel_uncore_read_fw(uncore, reg);
764 do {
765 tmp = upper;
766
767 intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
768 _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH));
769 lower = intel_uncore_read_fw(uncore, reg);
770
771 intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
772 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
773 upper = intel_uncore_read_fw(uncore, reg);
774 } while (upper != tmp && --loop);
775
776 /*
777 * Everywhere else we always use VLV_COUNTER_CONTROL with the
778 * VLV_COUNT_RANGE_HIGH bit set - so it is safe to leave it set
779 * now.
780 */
781
782 return lower | (u64)upper << 8;
783 }
784
intel_rc6_residency_ns(struct intel_rc6 * rc6,enum intel_rc6_res_type id)785 u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, enum intel_rc6_res_type id)
786 {
787 struct drm_i915_private *i915 = rc6_to_i915(rc6);
788 struct intel_uncore *uncore = rc6_to_uncore(rc6);
789 u64 time_hw, prev_hw, overflow_hw;
790 i915_reg_t reg = rc6->res_reg[id];
791 unsigned int fw_domains;
792 unsigned long flags;
793 u32 mul, div;
794
795 if (!rc6->supported)
796 return 0;
797
798 fw_domains = intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ);
799
800 spin_lock_irqsave(&uncore->lock, flags);
801 intel_uncore_forcewake_get__locked(uncore, fw_domains);
802
803 /* On VLV and CHV, residency time is in CZ units rather than 1.28us */
804 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
805 mul = 1000000;
806 div = i915->czclk_freq;
807 overflow_hw = BIT_ULL(40);
808 time_hw = vlv_residency_raw(uncore, reg);
809 } else {
810 /* 833.33ns units on Gen9LP, 1.28us elsewhere. */
811 if (IS_GEN9_LP(i915)) {
812 mul = 10000;
813 div = 12;
814 } else {
815 mul = 1280;
816 div = 1;
817 }
818
819 overflow_hw = BIT_ULL(32);
820 time_hw = intel_uncore_read_fw(uncore, reg);
821 }
822
823 /*
824 * Counter wrap handling.
825 *
826 * Store previous hw counter values for counter wrap-around handling. But
827 * relying on a sufficient frequency of queries otherwise counters can still wrap.
828 */
829 prev_hw = rc6->prev_hw_residency[id];
830 rc6->prev_hw_residency[id] = time_hw;
831
832 /* RC6 delta from last sample. */
833 if (time_hw >= prev_hw)
834 time_hw -= prev_hw;
835 else
836 time_hw += overflow_hw - prev_hw;
837
838 /* Add delta to RC6 extended raw driver copy. */
839 time_hw += rc6->cur_residency[id];
840 rc6->cur_residency[id] = time_hw;
841
842 intel_uncore_forcewake_put__locked(uncore, fw_domains);
843 spin_unlock_irqrestore(&uncore->lock, flags);
844
845 return mul_u64_u32_div(time_hw, mul, div);
846 }
847
intel_rc6_residency_us(struct intel_rc6 * rc6,enum intel_rc6_res_type id)848 u64 intel_rc6_residency_us(struct intel_rc6 *rc6, enum intel_rc6_res_type id)
849 {
850 return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(rc6, id), 1000);
851 }
852
intel_rc6_print_residency(struct seq_file * m,const char * title,enum intel_rc6_res_type id)853 void intel_rc6_print_residency(struct seq_file *m, const char *title,
854 enum intel_rc6_res_type id)
855 {
856 struct intel_gt *gt = m->private;
857 i915_reg_t reg = gt->rc6.res_reg[id];
858 intel_wakeref_t wakeref;
859
860 with_intel_runtime_pm(gt->uncore->rpm, wakeref)
861 seq_printf(m, "%s %u (%llu us)\n", title,
862 intel_uncore_read(gt->uncore, reg),
863 intel_rc6_residency_us(>->rc6, id));
864 }
865
866 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
867 #include "selftest_rc6.c"
868 #endif
869