1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Marvell 88e6xxx Ethernet switch single-chip support
4 *
5 * Copyright (c) 2008 Marvell Semiconductor
6 *
7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
8 *
9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
11 */
12
13 #include <linux/bitfield.h>
14 #include <linux/delay.h>
15 #include <linux/dsa/mv88e6xxx.h>
16 #include <linux/etherdevice.h>
17 #include <linux/ethtool.h>
18 #include <linux/if_bridge.h>
19 #include <linux/interrupt.h>
20 #include <linux/irq.h>
21 #include <linux/irqdomain.h>
22 #include <linux/jiffies.h>
23 #include <linux/list.h>
24 #include <linux/mdio.h>
25 #include <linux/module.h>
26 #include <linux/of.h>
27 #include <linux/of_irq.h>
28 #include <linux/of_mdio.h>
29 #include <linux/platform_data/mv88e6xxx.h>
30 #include <linux/netdevice.h>
31 #include <linux/gpio/consumer.h>
32 #include <linux/phylink.h>
33 #include <net/dsa.h>
34
35 #include "chip.h"
36 #include "devlink.h"
37 #include "global1.h"
38 #include "global2.h"
39 #include "hwtstamp.h"
40 #include "phy.h"
41 #include "port.h"
42 #include "ptp.h"
43 #include "serdes.h"
44 #include "smi.h"
45
assert_reg_lock(struct mv88e6xxx_chip * chip)46 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
47 {
48 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
49 dev_err(chip->dev, "Switch registers lock not held!\n");
50 dump_stack();
51 }
52 }
53
mv88e6xxx_read(struct mv88e6xxx_chip * chip,int addr,int reg,u16 * val)54 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
55 {
56 int err;
57
58 assert_reg_lock(chip);
59
60 err = mv88e6xxx_smi_read(chip, addr, reg, val);
61 if (err)
62 return err;
63
64 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
65 addr, reg, *val);
66
67 return 0;
68 }
69
mv88e6xxx_write(struct mv88e6xxx_chip * chip,int addr,int reg,u16 val)70 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
71 {
72 int err;
73
74 assert_reg_lock(chip);
75
76 err = mv88e6xxx_smi_write(chip, addr, reg, val);
77 if (err)
78 return err;
79
80 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
81 addr, reg, val);
82
83 return 0;
84 }
85
mv88e6xxx_wait_mask(struct mv88e6xxx_chip * chip,int addr,int reg,u16 mask,u16 val)86 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
87 u16 mask, u16 val)
88 {
89 const unsigned long timeout = jiffies + msecs_to_jiffies(50);
90 u16 data;
91 int err;
92 int i;
93
94 /* There's no bus specific operation to wait for a mask. Even
95 * if the initial poll takes longer than 50ms, always do at
96 * least one more attempt.
97 */
98 for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) {
99 err = mv88e6xxx_read(chip, addr, reg, &data);
100 if (err)
101 return err;
102
103 if ((data & mask) == val)
104 return 0;
105
106 if (i < 2)
107 cpu_relax();
108 else
109 usleep_range(1000, 2000);
110 }
111
112 err = mv88e6xxx_read(chip, addr, reg, &data);
113 if (err)
114 return err;
115
116 if ((data & mask) == val)
117 return 0;
118
119 dev_err(chip->dev, "Timeout while waiting for switch\n");
120 return -ETIMEDOUT;
121 }
122
mv88e6xxx_wait_bit(struct mv88e6xxx_chip * chip,int addr,int reg,int bit,int val)123 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
124 int bit, int val)
125 {
126 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit),
127 val ? BIT(bit) : 0x0000);
128 }
129
mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip * chip)130 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
131 {
132 struct mv88e6xxx_mdio_bus *mdio_bus;
133
134 mdio_bus = list_first_entry_or_null(&chip->mdios,
135 struct mv88e6xxx_mdio_bus, list);
136 if (!mdio_bus)
137 return NULL;
138
139 return mdio_bus->bus;
140 }
141
mv88e6xxx_g1_irq_mask(struct irq_data * d)142 static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
143 {
144 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
145 unsigned int n = d->hwirq;
146
147 chip->g1_irq.masked |= (1 << n);
148 }
149
mv88e6xxx_g1_irq_unmask(struct irq_data * d)150 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
151 {
152 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
153 unsigned int n = d->hwirq;
154
155 chip->g1_irq.masked &= ~(1 << n);
156 }
157
mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip * chip)158 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
159 {
160 unsigned int nhandled = 0;
161 unsigned int sub_irq;
162 unsigned int n;
163 u16 reg;
164 u16 ctl1;
165 int err;
166
167 mv88e6xxx_reg_lock(chip);
168 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
169 mv88e6xxx_reg_unlock(chip);
170
171 if (err)
172 goto out;
173
174 do {
175 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
176 if (reg & (1 << n)) {
177 sub_irq = irq_find_mapping(chip->g1_irq.domain,
178 n);
179 handle_nested_irq(sub_irq);
180 ++nhandled;
181 }
182 }
183
184 mv88e6xxx_reg_lock(chip);
185 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
186 if (err)
187 goto unlock;
188 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
189 unlock:
190 mv88e6xxx_reg_unlock(chip);
191 if (err)
192 goto out;
193 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
194 } while (reg & ctl1);
195
196 out:
197 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
198 }
199
mv88e6xxx_g1_irq_thread_fn(int irq,void * dev_id)200 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
201 {
202 struct mv88e6xxx_chip *chip = dev_id;
203
204 return mv88e6xxx_g1_irq_thread_work(chip);
205 }
206
mv88e6xxx_g1_irq_bus_lock(struct irq_data * d)207 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
208 {
209 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
210
211 mv88e6xxx_reg_lock(chip);
212 }
213
mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data * d)214 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
215 {
216 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
217 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
218 u16 reg;
219 int err;
220
221 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®);
222 if (err)
223 goto out;
224
225 reg &= ~mask;
226 reg |= (~chip->g1_irq.masked & mask);
227
228 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
229 if (err)
230 goto out;
231
232 out:
233 mv88e6xxx_reg_unlock(chip);
234 }
235
236 static const struct irq_chip mv88e6xxx_g1_irq_chip = {
237 .name = "mv88e6xxx-g1",
238 .irq_mask = mv88e6xxx_g1_irq_mask,
239 .irq_unmask = mv88e6xxx_g1_irq_unmask,
240 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
241 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
242 };
243
mv88e6xxx_g1_irq_domain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hwirq)244 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
245 unsigned int irq,
246 irq_hw_number_t hwirq)
247 {
248 struct mv88e6xxx_chip *chip = d->host_data;
249
250 irq_set_chip_data(irq, d->host_data);
251 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
252 irq_set_noprobe(irq);
253
254 return 0;
255 }
256
257 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
258 .map = mv88e6xxx_g1_irq_domain_map,
259 .xlate = irq_domain_xlate_twocell,
260 };
261
262 /* To be called with reg_lock held */
mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip * chip)263 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
264 {
265 int irq, virq;
266 u16 mask;
267
268 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
269 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
270 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
271
272 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
273 virq = irq_find_mapping(chip->g1_irq.domain, irq);
274 irq_dispose_mapping(virq);
275 }
276
277 irq_domain_remove(chip->g1_irq.domain);
278 }
279
mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip * chip)280 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
281 {
282 /*
283 * free_irq must be called without reg_lock taken because the irq
284 * handler takes this lock, too.
285 */
286 free_irq(chip->irq, chip);
287
288 mv88e6xxx_reg_lock(chip);
289 mv88e6xxx_g1_irq_free_common(chip);
290 mv88e6xxx_reg_unlock(chip);
291 }
292
mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip * chip)293 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
294 {
295 int err, irq, virq;
296 u16 reg, mask;
297
298 chip->g1_irq.nirqs = chip->info->g1_irqs;
299 chip->g1_irq.domain = irq_domain_add_simple(
300 NULL, chip->g1_irq.nirqs, 0,
301 &mv88e6xxx_g1_irq_domain_ops, chip);
302 if (!chip->g1_irq.domain)
303 return -ENOMEM;
304
305 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
306 irq_create_mapping(chip->g1_irq.domain, irq);
307
308 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
309 chip->g1_irq.masked = ~0;
310
311 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
312 if (err)
313 goto out_mapping;
314
315 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
316
317 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
318 if (err)
319 goto out_disable;
320
321 /* Reading the interrupt status clears (most of) them */
322 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
323 if (err)
324 goto out_disable;
325
326 return 0;
327
328 out_disable:
329 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
330 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
331
332 out_mapping:
333 for (irq = 0; irq < 16; irq++) {
334 virq = irq_find_mapping(chip->g1_irq.domain, irq);
335 irq_dispose_mapping(virq);
336 }
337
338 irq_domain_remove(chip->g1_irq.domain);
339
340 return err;
341 }
342
mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip * chip)343 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
344 {
345 static struct lock_class_key lock_key;
346 static struct lock_class_key request_key;
347 int err;
348
349 err = mv88e6xxx_g1_irq_setup_common(chip);
350 if (err)
351 return err;
352
353 /* These lock classes tells lockdep that global 1 irqs are in
354 * a different category than their parent GPIO, so it won't
355 * report false recursion.
356 */
357 irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
358
359 snprintf(chip->irq_name, sizeof(chip->irq_name),
360 "mv88e6xxx-%s", dev_name(chip->dev));
361
362 mv88e6xxx_reg_unlock(chip);
363 err = request_threaded_irq(chip->irq, NULL,
364 mv88e6xxx_g1_irq_thread_fn,
365 IRQF_ONESHOT | IRQF_SHARED,
366 chip->irq_name, chip);
367 mv88e6xxx_reg_lock(chip);
368 if (err)
369 mv88e6xxx_g1_irq_free_common(chip);
370
371 return err;
372 }
373
mv88e6xxx_irq_poll(struct kthread_work * work)374 static void mv88e6xxx_irq_poll(struct kthread_work *work)
375 {
376 struct mv88e6xxx_chip *chip = container_of(work,
377 struct mv88e6xxx_chip,
378 irq_poll_work.work);
379 mv88e6xxx_g1_irq_thread_work(chip);
380
381 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
382 msecs_to_jiffies(100));
383 }
384
mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip * chip)385 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
386 {
387 int err;
388
389 err = mv88e6xxx_g1_irq_setup_common(chip);
390 if (err)
391 return err;
392
393 kthread_init_delayed_work(&chip->irq_poll_work,
394 mv88e6xxx_irq_poll);
395
396 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev));
397 if (IS_ERR(chip->kworker))
398 return PTR_ERR(chip->kworker);
399
400 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
401 msecs_to_jiffies(100));
402
403 return 0;
404 }
405
mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip * chip)406 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
407 {
408 kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
409 kthread_destroy_worker(chip->kworker);
410
411 mv88e6xxx_reg_lock(chip);
412 mv88e6xxx_g1_irq_free_common(chip);
413 mv88e6xxx_reg_unlock(chip);
414 }
415
mv88e6xxx_port_config_interface(struct mv88e6xxx_chip * chip,int port,phy_interface_t interface)416 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip,
417 int port, phy_interface_t interface)
418 {
419 int err;
420
421 if (chip->info->ops->port_set_rgmii_delay) {
422 err = chip->info->ops->port_set_rgmii_delay(chip, port,
423 interface);
424 if (err && err != -EOPNOTSUPP)
425 return err;
426 }
427
428 if (chip->info->ops->port_set_cmode) {
429 err = chip->info->ops->port_set_cmode(chip, port,
430 interface);
431 if (err && err != -EOPNOTSUPP)
432 return err;
433 }
434
435 return 0;
436 }
437
mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip * chip,int port,int link,int speed,int duplex,int pause,phy_interface_t mode)438 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
439 int link, int speed, int duplex, int pause,
440 phy_interface_t mode)
441 {
442 int err;
443
444 if (!chip->info->ops->port_set_link)
445 return 0;
446
447 /* Port's MAC control must not be changed unless the link is down */
448 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
449 if (err)
450 return err;
451
452 if (chip->info->ops->port_set_speed_duplex) {
453 err = chip->info->ops->port_set_speed_duplex(chip, port,
454 speed, duplex);
455 if (err && err != -EOPNOTSUPP)
456 goto restore_link;
457 }
458
459 if (chip->info->ops->port_set_pause) {
460 err = chip->info->ops->port_set_pause(chip, port, pause);
461 if (err)
462 goto restore_link;
463 }
464
465 err = mv88e6xxx_port_config_interface(chip, port, mode);
466 restore_link:
467 if (chip->info->ops->port_set_link(chip, port, link))
468 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
469
470 return err;
471 }
472
mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip * chip,int port)473 static int mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip *chip, int port)
474 {
475 return port >= chip->info->internal_phys_offset &&
476 port < chip->info->num_internal_phys +
477 chip->info->internal_phys_offset;
478 }
479
mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip * chip,int port)480 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
481 {
482 u16 reg;
483 int err;
484
485 /* The 88e6250 family does not have the PHY detect bit. Instead,
486 * report whether the port is internal.
487 */
488 if (chip->info->family == MV88E6XXX_FAMILY_6250)
489 return mv88e6xxx_phy_is_internal(chip, port);
490
491 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
492 if (err) {
493 dev_err(chip->dev,
494 "p%d: %s: failed to read port status\n",
495 port, __func__);
496 return err;
497 }
498
499 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT);
500 }
501
502 static const u8 mv88e6185_phy_interface_modes[] = {
503 [MV88E6185_PORT_STS_CMODE_GMII_FD] = PHY_INTERFACE_MODE_GMII,
504 [MV88E6185_PORT_STS_CMODE_MII_100_FD_PS] = PHY_INTERFACE_MODE_MII,
505 [MV88E6185_PORT_STS_CMODE_MII_100] = PHY_INTERFACE_MODE_MII,
506 [MV88E6185_PORT_STS_CMODE_MII_10] = PHY_INTERFACE_MODE_MII,
507 [MV88E6185_PORT_STS_CMODE_SERDES] = PHY_INTERFACE_MODE_1000BASEX,
508 [MV88E6185_PORT_STS_CMODE_1000BASE_X] = PHY_INTERFACE_MODE_1000BASEX,
509 [MV88E6185_PORT_STS_CMODE_PHY] = PHY_INTERFACE_MODE_SGMII,
510 };
511
mv88e6095_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)512 static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
513 struct phylink_config *config)
514 {
515 u8 cmode = chip->ports[port].cmode;
516
517 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
518
519 if (mv88e6xxx_phy_is_internal(chip, port)) {
520 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
521 } else {
522 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) &&
523 mv88e6185_phy_interface_modes[cmode])
524 __set_bit(mv88e6185_phy_interface_modes[cmode],
525 config->supported_interfaces);
526
527 config->mac_capabilities |= MAC_1000FD;
528 }
529 }
530
mv88e6185_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)531 static void mv88e6185_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
532 struct phylink_config *config)
533 {
534 u8 cmode = chip->ports[port].cmode;
535
536 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) &&
537 mv88e6185_phy_interface_modes[cmode])
538 __set_bit(mv88e6185_phy_interface_modes[cmode],
539 config->supported_interfaces);
540
541 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
542 MAC_1000FD;
543 }
544
545 static const u8 mv88e6xxx_phy_interface_modes[] = {
546 [MV88E6XXX_PORT_STS_CMODE_MII_PHY] = PHY_INTERFACE_MODE_REVMII,
547 [MV88E6XXX_PORT_STS_CMODE_MII] = PHY_INTERFACE_MODE_MII,
548 [MV88E6XXX_PORT_STS_CMODE_GMII] = PHY_INTERFACE_MODE_GMII,
549 [MV88E6XXX_PORT_STS_CMODE_RMII_PHY] = PHY_INTERFACE_MODE_REVRMII,
550 [MV88E6XXX_PORT_STS_CMODE_RMII] = PHY_INTERFACE_MODE_RMII,
551 [MV88E6XXX_PORT_STS_CMODE_100BASEX] = PHY_INTERFACE_MODE_100BASEX,
552 [MV88E6XXX_PORT_STS_CMODE_1000BASEX] = PHY_INTERFACE_MODE_1000BASEX,
553 [MV88E6XXX_PORT_STS_CMODE_SGMII] = PHY_INTERFACE_MODE_SGMII,
554 /* higher interface modes are not needed here, since ports supporting
555 * them are writable, and so the supported interfaces are filled in the
556 * corresponding .phylink_set_interfaces() implementation below
557 */
558 };
559
mv88e6xxx_translate_cmode(u8 cmode,unsigned long * supported)560 static void mv88e6xxx_translate_cmode(u8 cmode, unsigned long *supported)
561 {
562 if (cmode < ARRAY_SIZE(mv88e6xxx_phy_interface_modes) &&
563 mv88e6xxx_phy_interface_modes[cmode])
564 __set_bit(mv88e6xxx_phy_interface_modes[cmode], supported);
565 else if (cmode == MV88E6XXX_PORT_STS_CMODE_RGMII)
566 phy_interface_set_rgmii(supported);
567 }
568
569 static void
mv88e6250_setup_supported_interfaces(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)570 mv88e6250_setup_supported_interfaces(struct mv88e6xxx_chip *chip, int port,
571 struct phylink_config *config)
572 {
573 unsigned long *supported = config->supported_interfaces;
574 int err;
575 u16 reg;
576
577 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
578 if (err) {
579 dev_err(chip->dev, "p%d: failed to read port status\n", port);
580 return;
581 }
582
583 switch (reg & MV88E6250_PORT_STS_PORTMODE_MASK) {
584 case MV88E6250_PORT_STS_PORTMODE_MII_10_HALF_PHY:
585 case MV88E6250_PORT_STS_PORTMODE_MII_100_HALF_PHY:
586 case MV88E6250_PORT_STS_PORTMODE_MII_10_FULL_PHY:
587 case MV88E6250_PORT_STS_PORTMODE_MII_100_FULL_PHY:
588 __set_bit(PHY_INTERFACE_MODE_REVMII, supported);
589 break;
590
591 case MV88E6250_PORT_STS_PORTMODE_MII_HALF:
592 case MV88E6250_PORT_STS_PORTMODE_MII_FULL:
593 __set_bit(PHY_INTERFACE_MODE_MII, supported);
594 break;
595
596 case MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL_PHY:
597 case MV88E6250_PORT_STS_PORTMODE_MII_200_RMII_FULL_PHY:
598 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_HALF_PHY:
599 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL_PHY:
600 __set_bit(PHY_INTERFACE_MODE_REVRMII, supported);
601 break;
602
603 case MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL:
604 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL:
605 __set_bit(PHY_INTERFACE_MODE_RMII, supported);
606 break;
607
608 case MV88E6250_PORT_STS_PORTMODE_MII_100_RGMII:
609 __set_bit(PHY_INTERFACE_MODE_RGMII, supported);
610 break;
611
612 default:
613 dev_err(chip->dev,
614 "p%d: invalid port mode in status register: %04x\n",
615 port, reg);
616 }
617 }
618
mv88e6250_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)619 static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
620 struct phylink_config *config)
621 {
622 if (!mv88e6xxx_phy_is_internal(chip, port))
623 mv88e6250_setup_supported_interfaces(chip, port, config);
624
625 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
626 }
627
mv88e6351_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)628 static void mv88e6351_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
629 struct phylink_config *config)
630 {
631 unsigned long *supported = config->supported_interfaces;
632
633 /* Translate the default cmode */
634 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
635
636 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
637 MAC_1000FD;
638 }
639
mv88e6352_get_port4_serdes_cmode(struct mv88e6xxx_chip * chip)640 static int mv88e6352_get_port4_serdes_cmode(struct mv88e6xxx_chip *chip)
641 {
642 u16 reg, val;
643 int err;
644
645 err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, ®);
646 if (err)
647 return err;
648
649 /* If PHY_DETECT is zero, then we are not in auto-media mode */
650 if (!(reg & MV88E6XXX_PORT_STS_PHY_DETECT))
651 return 0xf;
652
653 val = reg & ~MV88E6XXX_PORT_STS_PHY_DETECT;
654 err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, val);
655 if (err)
656 return err;
657
658 err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, &val);
659 if (err)
660 return err;
661
662 /* Restore PHY_DETECT value */
663 err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, reg);
664 if (err)
665 return err;
666
667 return val & MV88E6XXX_PORT_STS_CMODE_MASK;
668 }
669
mv88e6352_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)670 static void mv88e6352_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
671 struct phylink_config *config)
672 {
673 unsigned long *supported = config->supported_interfaces;
674 int err, cmode;
675
676 /* Translate the default cmode */
677 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
678
679 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
680 MAC_1000FD;
681
682 /* Port 4 supports automedia if the serdes is associated with it. */
683 if (port == 4) {
684 err = mv88e6352_g2_scratch_port_has_serdes(chip, port);
685 if (err < 0)
686 dev_err(chip->dev, "p%d: failed to read scratch\n",
687 port);
688 if (err <= 0)
689 return;
690
691 cmode = mv88e6352_get_port4_serdes_cmode(chip);
692 if (cmode < 0)
693 dev_err(chip->dev, "p%d: failed to read serdes cmode\n",
694 port);
695 else
696 mv88e6xxx_translate_cmode(cmode, supported);
697 }
698 }
699
mv88e632x_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)700 static void mv88e632x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
701 struct phylink_config *config)
702 {
703 unsigned long *supported = config->supported_interfaces;
704
705 /* Translate the default cmode */
706 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
707
708 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
709 MAC_1000FD;
710 }
711
mv88e6341_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)712 static void mv88e6341_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
713 struct phylink_config *config)
714 {
715 unsigned long *supported = config->supported_interfaces;
716
717 /* Translate the default cmode */
718 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
719
720 /* No ethtool bits for 200Mbps */
721 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
722 MAC_1000FD;
723
724 /* The C_Mode field is programmable on port 5 */
725 if (port == 5) {
726 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
727 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
728 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
729
730 config->mac_capabilities |= MAC_2500FD;
731 }
732 }
733
mv88e6390_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)734 static void mv88e6390_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
735 struct phylink_config *config)
736 {
737 unsigned long *supported = config->supported_interfaces;
738
739 /* Translate the default cmode */
740 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
741
742 /* No ethtool bits for 200Mbps */
743 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
744 MAC_1000FD;
745
746 /* The C_Mode field is programmable on ports 9 and 10 */
747 if (port == 9 || port == 10) {
748 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
749 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
750 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
751
752 config->mac_capabilities |= MAC_2500FD;
753 }
754 }
755
mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)756 static void mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
757 struct phylink_config *config)
758 {
759 unsigned long *supported = config->supported_interfaces;
760
761 mv88e6390_phylink_get_caps(chip, port, config);
762
763 /* For the 6x90X, ports 2-7 can be in automedia mode.
764 * (Note that 6x90 doesn't support RXAUI nor XAUI).
765 *
766 * Port 2 can also support 1000BASE-X in automedia mode if port 9 is
767 * configured for 1000BASE-X, SGMII or 2500BASE-X.
768 * Port 3-4 can also support 1000BASE-X in automedia mode if port 9 is
769 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X.
770 *
771 * Port 5 can also support 1000BASE-X in automedia mode if port 10 is
772 * configured for 1000BASE-X, SGMII or 2500BASE-X.
773 * Port 6-7 can also support 1000BASE-X in automedia mode if port 10 is
774 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X.
775 *
776 * For now, be permissive (as the old code was) and allow 1000BASE-X
777 * on ports 2..7.
778 */
779 if (port >= 2 && port <= 7)
780 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
781
782 /* The C_Mode field can also be programmed for 10G speeds */
783 if (port == 9 || port == 10) {
784 __set_bit(PHY_INTERFACE_MODE_XAUI, supported);
785 __set_bit(PHY_INTERFACE_MODE_RXAUI, supported);
786
787 config->mac_capabilities |= MAC_10000FD;
788 }
789 }
790
mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)791 static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
792 struct phylink_config *config)
793 {
794 unsigned long *supported = config->supported_interfaces;
795 bool is_6191x =
796 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X;
797 bool is_6361 =
798 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361;
799
800 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
801
802 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
803 MAC_1000FD;
804
805 /* The C_Mode field can be programmed for ports 0, 9 and 10 */
806 if (port == 0 || port == 9 || port == 10) {
807 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
808 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
809
810 /* 6191X supports >1G modes only on port 10 */
811 if (!is_6191x || port == 10) {
812 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
813 config->mac_capabilities |= MAC_2500FD;
814
815 /* 6361 only supports up to 2500BaseX */
816 if (!is_6361) {
817 __set_bit(PHY_INTERFACE_MODE_5GBASER, supported);
818 __set_bit(PHY_INTERFACE_MODE_10GBASER, supported);
819 __set_bit(PHY_INTERFACE_MODE_USXGMII, supported);
820 config->mac_capabilities |= MAC_5000FD |
821 MAC_10000FD;
822 }
823 }
824 }
825
826 if (port == 0) {
827 __set_bit(PHY_INTERFACE_MODE_RMII, supported);
828 __set_bit(PHY_INTERFACE_MODE_RGMII, supported);
829 __set_bit(PHY_INTERFACE_MODE_RGMII_ID, supported);
830 __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, supported);
831 __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, supported);
832 }
833 }
834
mv88e6xxx_get_caps(struct dsa_switch * ds,int port,struct phylink_config * config)835 static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port,
836 struct phylink_config *config)
837 {
838 struct mv88e6xxx_chip *chip = ds->priv;
839
840 mv88e6xxx_reg_lock(chip);
841 chip->info->ops->phylink_get_caps(chip, port, config);
842 mv88e6xxx_reg_unlock(chip);
843
844 if (mv88e6xxx_phy_is_internal(chip, port)) {
845 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
846 config->supported_interfaces);
847 /* Internal ports with no phy-mode need GMII for PHYLIB */
848 __set_bit(PHY_INTERFACE_MODE_GMII,
849 config->supported_interfaces);
850 }
851 }
852
mv88e6xxx_mac_select_pcs(struct dsa_switch * ds,int port,phy_interface_t interface)853 static struct phylink_pcs *mv88e6xxx_mac_select_pcs(struct dsa_switch *ds,
854 int port,
855 phy_interface_t interface)
856 {
857 struct mv88e6xxx_chip *chip = ds->priv;
858 struct phylink_pcs *pcs = ERR_PTR(-EOPNOTSUPP);
859
860 if (chip->info->ops->pcs_ops)
861 pcs = chip->info->ops->pcs_ops->pcs_select(chip, port,
862 interface);
863
864 return pcs;
865 }
866
mv88e6xxx_mac_prepare(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface)867 static int mv88e6xxx_mac_prepare(struct dsa_switch *ds, int port,
868 unsigned int mode, phy_interface_t interface)
869 {
870 struct mv88e6xxx_chip *chip = ds->priv;
871 int err = 0;
872
873 /* In inband mode, the link may come up at any time while the link
874 * is not forced down. Force the link down while we reconfigure the
875 * interface mode.
876 */
877 if (mode == MLO_AN_INBAND &&
878 chip->ports[port].interface != interface &&
879 chip->info->ops->port_set_link) {
880 mv88e6xxx_reg_lock(chip);
881 err = chip->info->ops->port_set_link(chip, port,
882 LINK_FORCED_DOWN);
883 mv88e6xxx_reg_unlock(chip);
884 }
885
886 return err;
887 }
888
mv88e6xxx_mac_config(struct dsa_switch * ds,int port,unsigned int mode,const struct phylink_link_state * state)889 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
890 unsigned int mode,
891 const struct phylink_link_state *state)
892 {
893 struct mv88e6xxx_chip *chip = ds->priv;
894 int err = 0;
895
896 mv88e6xxx_reg_lock(chip);
897
898 if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(chip, port)) {
899 err = mv88e6xxx_port_config_interface(chip, port,
900 state->interface);
901 if (err && err != -EOPNOTSUPP)
902 goto err_unlock;
903 }
904
905 err_unlock:
906 mv88e6xxx_reg_unlock(chip);
907
908 if (err && err != -EOPNOTSUPP)
909 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port);
910 }
911
mv88e6xxx_mac_finish(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface)912 static int mv88e6xxx_mac_finish(struct dsa_switch *ds, int port,
913 unsigned int mode, phy_interface_t interface)
914 {
915 struct mv88e6xxx_chip *chip = ds->priv;
916 int err = 0;
917
918 /* Undo the forced down state above after completing configuration
919 * irrespective of its state on entry, which allows the link to come
920 * up in the in-band case where there is no separate SERDES. Also
921 * ensure that the link can come up if the PPU is in use and we are
922 * in PHY mode (we treat the PPU as an effective in-band mechanism.)
923 */
924 mv88e6xxx_reg_lock(chip);
925
926 if (chip->info->ops->port_set_link &&
927 ((mode == MLO_AN_INBAND &&
928 chip->ports[port].interface != interface) ||
929 (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port))))
930 err = chip->info->ops->port_set_link(chip, port, LINK_UNFORCED);
931
932 mv88e6xxx_reg_unlock(chip);
933
934 chip->ports[port].interface = interface;
935
936 return err;
937 }
938
mv88e6xxx_mac_link_down(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface)939 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port,
940 unsigned int mode,
941 phy_interface_t interface)
942 {
943 struct mv88e6xxx_chip *chip = ds->priv;
944 const struct mv88e6xxx_ops *ops;
945 int err = 0;
946
947 ops = chip->info->ops;
948
949 mv88e6xxx_reg_lock(chip);
950 /* Force the link down if we know the port may not be automatically
951 * updated by the switch or if we are using fixed-link mode.
952 */
953 if ((!mv88e6xxx_port_ppu_updates(chip, port) ||
954 mode == MLO_AN_FIXED) && ops->port_sync_link)
955 err = ops->port_sync_link(chip, port, mode, false);
956
957 if (!err && ops->port_set_speed_duplex)
958 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED,
959 DUPLEX_UNFORCED);
960 mv88e6xxx_reg_unlock(chip);
961
962 if (err)
963 dev_err(chip->dev,
964 "p%d: failed to force MAC link down\n", port);
965 }
966
mv88e6xxx_mac_link_up(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface,struct phy_device * phydev,int speed,int duplex,bool tx_pause,bool rx_pause)967 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
968 unsigned int mode, phy_interface_t interface,
969 struct phy_device *phydev,
970 int speed, int duplex,
971 bool tx_pause, bool rx_pause)
972 {
973 struct mv88e6xxx_chip *chip = ds->priv;
974 const struct mv88e6xxx_ops *ops;
975 int err = 0;
976
977 ops = chip->info->ops;
978
979 mv88e6xxx_reg_lock(chip);
980 /* Configure and force the link up if we know that the port may not
981 * automatically updated by the switch or if we are using fixed-link
982 * mode.
983 */
984 if (!mv88e6xxx_port_ppu_updates(chip, port) ||
985 mode == MLO_AN_FIXED) {
986 if (ops->port_set_speed_duplex) {
987 err = ops->port_set_speed_duplex(chip, port,
988 speed, duplex);
989 if (err && err != -EOPNOTSUPP)
990 goto error;
991 }
992
993 if (ops->port_sync_link)
994 err = ops->port_sync_link(chip, port, mode, true);
995 }
996 error:
997 mv88e6xxx_reg_unlock(chip);
998
999 if (err && err != -EOPNOTSUPP)
1000 dev_err(ds->dev,
1001 "p%d: failed to configure MAC link up\n", port);
1002 }
1003
mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip * chip,int port)1004 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
1005 {
1006 if (!chip->info->ops->stats_snapshot)
1007 return -EOPNOTSUPP;
1008
1009 return chip->info->ops->stats_snapshot(chip, port);
1010 }
1011
1012 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
1013 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
1014 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
1015 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
1016 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
1017 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
1018 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
1019 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
1020 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
1021 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
1022 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
1023 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
1024 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
1025 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
1026 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
1027 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
1028 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
1029 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
1030 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
1031 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
1032 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
1033 { "single", 4, 0x14, STATS_TYPE_BANK0, },
1034 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
1035 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
1036 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
1037 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
1038 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
1039 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
1040 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
1041 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
1042 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
1043 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
1044 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
1045 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
1046 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
1047 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
1048 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
1049 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
1050 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
1051 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
1052 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
1053 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
1054 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
1055 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
1056 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
1057 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
1058 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
1059 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
1060 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
1061 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
1062 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
1063 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
1064 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
1065 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
1066 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
1067 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
1068 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
1069 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
1070 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
1071 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
1072 };
1073
_mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip * chip,struct mv88e6xxx_hw_stat * s,int port,u16 bank1_select,u16 histogram)1074 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
1075 struct mv88e6xxx_hw_stat *s,
1076 int port, u16 bank1_select,
1077 u16 histogram)
1078 {
1079 u32 low;
1080 u32 high = 0;
1081 u16 reg = 0;
1082 int err;
1083 u64 value;
1084
1085 switch (s->type) {
1086 case STATS_TYPE_PORT:
1087 err = mv88e6xxx_port_read(chip, port, s->reg, ®);
1088 if (err)
1089 return U64_MAX;
1090
1091 low = reg;
1092 if (s->size == 4) {
1093 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®);
1094 if (err)
1095 return U64_MAX;
1096 low |= ((u32)reg) << 16;
1097 }
1098 break;
1099 case STATS_TYPE_BANK1:
1100 reg = bank1_select;
1101 fallthrough;
1102 case STATS_TYPE_BANK0:
1103 reg |= s->reg | histogram;
1104 mv88e6xxx_g1_stats_read(chip, reg, &low);
1105 if (s->size == 8)
1106 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
1107 break;
1108 default:
1109 return U64_MAX;
1110 }
1111 value = (((u64)high) << 32) | low;
1112 return value;
1113 }
1114
mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip * chip,uint8_t * data,int types)1115 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
1116 uint8_t *data, int types)
1117 {
1118 struct mv88e6xxx_hw_stat *stat;
1119 int i, j;
1120
1121 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1122 stat = &mv88e6xxx_hw_stats[i];
1123 if (stat->type & types) {
1124 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
1125 ETH_GSTRING_LEN);
1126 j++;
1127 }
1128 }
1129
1130 return j;
1131 }
1132
mv88e6095_stats_get_strings(struct mv88e6xxx_chip * chip,uint8_t * data)1133 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
1134 uint8_t *data)
1135 {
1136 return mv88e6xxx_stats_get_strings(chip, data,
1137 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
1138 }
1139
mv88e6250_stats_get_strings(struct mv88e6xxx_chip * chip,uint8_t * data)1140 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip,
1141 uint8_t *data)
1142 {
1143 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0);
1144 }
1145
mv88e6320_stats_get_strings(struct mv88e6xxx_chip * chip,uint8_t * data)1146 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
1147 uint8_t *data)
1148 {
1149 return mv88e6xxx_stats_get_strings(chip, data,
1150 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
1151 }
1152
1153 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
1154 "atu_member_violation",
1155 "atu_miss_violation",
1156 "atu_full_violation",
1157 "vtu_member_violation",
1158 "vtu_miss_violation",
1159 };
1160
mv88e6xxx_atu_vtu_get_strings(uint8_t * data)1161 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
1162 {
1163 unsigned int i;
1164
1165 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
1166 strscpy(data + i * ETH_GSTRING_LEN,
1167 mv88e6xxx_atu_vtu_stats_strings[i],
1168 ETH_GSTRING_LEN);
1169 }
1170
mv88e6xxx_get_strings(struct dsa_switch * ds,int port,u32 stringset,uint8_t * data)1171 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
1172 u32 stringset, uint8_t *data)
1173 {
1174 struct mv88e6xxx_chip *chip = ds->priv;
1175 int count = 0;
1176
1177 if (stringset != ETH_SS_STATS)
1178 return;
1179
1180 mv88e6xxx_reg_lock(chip);
1181
1182 if (chip->info->ops->stats_get_strings)
1183 count = chip->info->ops->stats_get_strings(chip, data);
1184
1185 if (chip->info->ops->serdes_get_strings) {
1186 data += count * ETH_GSTRING_LEN;
1187 count = chip->info->ops->serdes_get_strings(chip, port, data);
1188 }
1189
1190 data += count * ETH_GSTRING_LEN;
1191 mv88e6xxx_atu_vtu_get_strings(data);
1192
1193 mv88e6xxx_reg_unlock(chip);
1194 }
1195
mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip * chip,int types)1196 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
1197 int types)
1198 {
1199 struct mv88e6xxx_hw_stat *stat;
1200 int i, j;
1201
1202 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1203 stat = &mv88e6xxx_hw_stats[i];
1204 if (stat->type & types)
1205 j++;
1206 }
1207 return j;
1208 }
1209
mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip * chip)1210 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1211 {
1212 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1213 STATS_TYPE_PORT);
1214 }
1215
mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip * chip)1216 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1217 {
1218 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0);
1219 }
1220
mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip * chip)1221 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1222 {
1223 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1224 STATS_TYPE_BANK1);
1225 }
1226
mv88e6xxx_get_sset_count(struct dsa_switch * ds,int port,int sset)1227 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
1228 {
1229 struct mv88e6xxx_chip *chip = ds->priv;
1230 int serdes_count = 0;
1231 int count = 0;
1232
1233 if (sset != ETH_SS_STATS)
1234 return 0;
1235
1236 mv88e6xxx_reg_lock(chip);
1237 if (chip->info->ops->stats_get_sset_count)
1238 count = chip->info->ops->stats_get_sset_count(chip);
1239 if (count < 0)
1240 goto out;
1241
1242 if (chip->info->ops->serdes_get_sset_count)
1243 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
1244 port);
1245 if (serdes_count < 0) {
1246 count = serdes_count;
1247 goto out;
1248 }
1249 count += serdes_count;
1250 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
1251
1252 out:
1253 mv88e6xxx_reg_unlock(chip);
1254
1255 return count;
1256 }
1257
mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data,int types,u16 bank1_select,u16 histogram)1258 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1259 uint64_t *data, int types,
1260 u16 bank1_select, u16 histogram)
1261 {
1262 struct mv88e6xxx_hw_stat *stat;
1263 int i, j;
1264
1265 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1266 stat = &mv88e6xxx_hw_stats[i];
1267 if (stat->type & types) {
1268 mv88e6xxx_reg_lock(chip);
1269 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1270 bank1_select,
1271 histogram);
1272 mv88e6xxx_reg_unlock(chip);
1273
1274 j++;
1275 }
1276 }
1277 return j;
1278 }
1279
mv88e6095_stats_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1280 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1281 uint64_t *data)
1282 {
1283 return mv88e6xxx_stats_get_stats(chip, port, data,
1284 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
1285 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1286 }
1287
mv88e6250_stats_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1288 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1289 uint64_t *data)
1290 {
1291 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0,
1292 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1293 }
1294
mv88e6320_stats_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1295 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1296 uint64_t *data)
1297 {
1298 return mv88e6xxx_stats_get_stats(chip, port, data,
1299 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1300 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
1301 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1302 }
1303
mv88e6390_stats_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1304 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1305 uint64_t *data)
1306 {
1307 return mv88e6xxx_stats_get_stats(chip, port, data,
1308 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1309 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
1310 0);
1311 }
1312
mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1313 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
1314 uint64_t *data)
1315 {
1316 *data++ = chip->ports[port].atu_member_violation;
1317 *data++ = chip->ports[port].atu_miss_violation;
1318 *data++ = chip->ports[port].atu_full_violation;
1319 *data++ = chip->ports[port].vtu_member_violation;
1320 *data++ = chip->ports[port].vtu_miss_violation;
1321 }
1322
mv88e6xxx_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1323 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1324 uint64_t *data)
1325 {
1326 int count = 0;
1327
1328 if (chip->info->ops->stats_get_stats)
1329 count = chip->info->ops->stats_get_stats(chip, port, data);
1330
1331 mv88e6xxx_reg_lock(chip);
1332 if (chip->info->ops->serdes_get_stats) {
1333 data += count;
1334 count = chip->info->ops->serdes_get_stats(chip, port, data);
1335 }
1336 data += count;
1337 mv88e6xxx_atu_vtu_get_stats(chip, port, data);
1338 mv88e6xxx_reg_unlock(chip);
1339 }
1340
mv88e6xxx_get_ethtool_stats(struct dsa_switch * ds,int port,uint64_t * data)1341 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1342 uint64_t *data)
1343 {
1344 struct mv88e6xxx_chip *chip = ds->priv;
1345 int ret;
1346
1347 mv88e6xxx_reg_lock(chip);
1348
1349 ret = mv88e6xxx_stats_snapshot(chip, port);
1350 mv88e6xxx_reg_unlock(chip);
1351
1352 if (ret < 0)
1353 return;
1354
1355 mv88e6xxx_get_stats(chip, port, data);
1356
1357 }
1358
mv88e6xxx_get_regs_len(struct dsa_switch * ds,int port)1359 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1360 {
1361 struct mv88e6xxx_chip *chip = ds->priv;
1362 int len;
1363
1364 len = 32 * sizeof(u16);
1365 if (chip->info->ops->serdes_get_regs_len)
1366 len += chip->info->ops->serdes_get_regs_len(chip, port);
1367
1368 return len;
1369 }
1370
mv88e6xxx_get_regs(struct dsa_switch * ds,int port,struct ethtool_regs * regs,void * _p)1371 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1372 struct ethtool_regs *regs, void *_p)
1373 {
1374 struct mv88e6xxx_chip *chip = ds->priv;
1375 int err;
1376 u16 reg;
1377 u16 *p = _p;
1378 int i;
1379
1380 regs->version = chip->info->prod_num;
1381
1382 memset(p, 0xff, 32 * sizeof(u16));
1383
1384 mv88e6xxx_reg_lock(chip);
1385
1386 for (i = 0; i < 32; i++) {
1387
1388 err = mv88e6xxx_port_read(chip, port, i, ®);
1389 if (!err)
1390 p[i] = reg;
1391 }
1392
1393 if (chip->info->ops->serdes_get_regs)
1394 chip->info->ops->serdes_get_regs(chip, port, &p[i]);
1395
1396 mv88e6xxx_reg_unlock(chip);
1397 }
1398
mv88e6xxx_get_mac_eee(struct dsa_switch * ds,int port,struct ethtool_eee * e)1399 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
1400 struct ethtool_eee *e)
1401 {
1402 /* Nothing to do on the port's MAC */
1403 return 0;
1404 }
1405
mv88e6xxx_set_mac_eee(struct dsa_switch * ds,int port,struct ethtool_eee * e)1406 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
1407 struct ethtool_eee *e)
1408 {
1409 /* Nothing to do on the port's MAC */
1410 return 0;
1411 }
1412
1413 /* Mask of the local ports allowed to receive frames from a given fabric port */
mv88e6xxx_port_vlan(struct mv88e6xxx_chip * chip,int dev,int port)1414 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1415 {
1416 struct dsa_switch *ds = chip->ds;
1417 struct dsa_switch_tree *dst = ds->dst;
1418 struct dsa_port *dp, *other_dp;
1419 bool found = false;
1420 u16 pvlan;
1421
1422 /* dev is a physical switch */
1423 if (dev <= dst->last_switch) {
1424 list_for_each_entry(dp, &dst->ports, list) {
1425 if (dp->ds->index == dev && dp->index == port) {
1426 /* dp might be a DSA link or a user port, so it
1427 * might or might not have a bridge.
1428 * Use the "found" variable for both cases.
1429 */
1430 found = true;
1431 break;
1432 }
1433 }
1434 /* dev is a virtual bridge */
1435 } else {
1436 list_for_each_entry(dp, &dst->ports, list) {
1437 unsigned int bridge_num = dsa_port_bridge_num_get(dp);
1438
1439 if (!bridge_num)
1440 continue;
1441
1442 if (bridge_num + dst->last_switch != dev)
1443 continue;
1444
1445 found = true;
1446 break;
1447 }
1448 }
1449
1450 /* Prevent frames from unknown switch or virtual bridge */
1451 if (!found)
1452 return 0;
1453
1454 /* Frames from DSA links and CPU ports can egress any local port */
1455 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA)
1456 return mv88e6xxx_port_mask(chip);
1457
1458 pvlan = 0;
1459
1460 /* Frames from standalone user ports can only egress on the
1461 * upstream port.
1462 */
1463 if (!dsa_port_bridge_dev_get(dp))
1464 return BIT(dsa_switch_upstream_port(ds));
1465
1466 /* Frames from bridged user ports can egress any local DSA
1467 * links and CPU ports, as well as any local member of their
1468 * bridge group.
1469 */
1470 dsa_switch_for_each_port(other_dp, ds)
1471 if (other_dp->type == DSA_PORT_TYPE_CPU ||
1472 other_dp->type == DSA_PORT_TYPE_DSA ||
1473 dsa_port_bridge_same(dp, other_dp))
1474 pvlan |= BIT(other_dp->index);
1475
1476 return pvlan;
1477 }
1478
mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip * chip,int port)1479 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1480 {
1481 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1482
1483 /* prevent frames from going back out of the port they came in on */
1484 output_ports &= ~BIT(port);
1485
1486 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1487 }
1488
mv88e6xxx_port_stp_state_set(struct dsa_switch * ds,int port,u8 state)1489 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1490 u8 state)
1491 {
1492 struct mv88e6xxx_chip *chip = ds->priv;
1493 int err;
1494
1495 mv88e6xxx_reg_lock(chip);
1496 err = mv88e6xxx_port_set_state(chip, port, state);
1497 mv88e6xxx_reg_unlock(chip);
1498
1499 if (err)
1500 dev_err(ds->dev, "p%d: failed to update state\n", port);
1501 }
1502
mv88e6xxx_pri_setup(struct mv88e6xxx_chip * chip)1503 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
1504 {
1505 int err;
1506
1507 if (chip->info->ops->ieee_pri_map) {
1508 err = chip->info->ops->ieee_pri_map(chip);
1509 if (err)
1510 return err;
1511 }
1512
1513 if (chip->info->ops->ip_pri_map) {
1514 err = chip->info->ops->ip_pri_map(chip);
1515 if (err)
1516 return err;
1517 }
1518
1519 return 0;
1520 }
1521
mv88e6xxx_devmap_setup(struct mv88e6xxx_chip * chip)1522 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1523 {
1524 struct dsa_switch *ds = chip->ds;
1525 int target, port;
1526 int err;
1527
1528 if (!chip->info->global2_addr)
1529 return 0;
1530
1531 /* Initialize the routing port to the 32 possible target devices */
1532 for (target = 0; target < 32; target++) {
1533 port = dsa_routing_port(ds, target);
1534 if (port == ds->num_ports)
1535 port = 0x1f;
1536
1537 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1538 if (err)
1539 return err;
1540 }
1541
1542 if (chip->info->ops->set_cascade_port) {
1543 port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
1544 err = chip->info->ops->set_cascade_port(chip, port);
1545 if (err)
1546 return err;
1547 }
1548
1549 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
1550 if (err)
1551 return err;
1552
1553 return 0;
1554 }
1555
mv88e6xxx_trunk_setup(struct mv88e6xxx_chip * chip)1556 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1557 {
1558 /* Clear all trunk masks and mapping */
1559 if (chip->info->global2_addr)
1560 return mv88e6xxx_g2_trunk_clear(chip);
1561
1562 return 0;
1563 }
1564
mv88e6xxx_rmu_setup(struct mv88e6xxx_chip * chip)1565 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1566 {
1567 if (chip->info->ops->rmu_disable)
1568 return chip->info->ops->rmu_disable(chip);
1569
1570 return 0;
1571 }
1572
mv88e6xxx_pot_setup(struct mv88e6xxx_chip * chip)1573 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1574 {
1575 if (chip->info->ops->pot_clear)
1576 return chip->info->ops->pot_clear(chip);
1577
1578 return 0;
1579 }
1580
mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip * chip)1581 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1582 {
1583 if (chip->info->ops->mgmt_rsvd2cpu)
1584 return chip->info->ops->mgmt_rsvd2cpu(chip);
1585
1586 return 0;
1587 }
1588
mv88e6xxx_atu_setup(struct mv88e6xxx_chip * chip)1589 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1590 {
1591 int err;
1592
1593 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1594 if (err)
1595 return err;
1596
1597 /* The chips that have a "learn2all" bit in Global1, ATU
1598 * Control are precisely those whose port registers have a
1599 * Message Port bit in Port Control 1 and hence implement
1600 * ->port_setup_message_port.
1601 */
1602 if (chip->info->ops->port_setup_message_port) {
1603 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1604 if (err)
1605 return err;
1606 }
1607
1608 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1609 }
1610
mv88e6xxx_irl_setup(struct mv88e6xxx_chip * chip)1611 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1612 {
1613 int port;
1614 int err;
1615
1616 if (!chip->info->ops->irl_init_all)
1617 return 0;
1618
1619 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1620 /* Disable ingress rate limiting by resetting all per port
1621 * ingress rate limit resources to their initial state.
1622 */
1623 err = chip->info->ops->irl_init_all(chip, port);
1624 if (err)
1625 return err;
1626 }
1627
1628 return 0;
1629 }
1630
mv88e6xxx_mac_setup(struct mv88e6xxx_chip * chip)1631 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1632 {
1633 if (chip->info->ops->set_switch_mac) {
1634 u8 addr[ETH_ALEN];
1635
1636 eth_random_addr(addr);
1637
1638 return chip->info->ops->set_switch_mac(chip, addr);
1639 }
1640
1641 return 0;
1642 }
1643
mv88e6xxx_pvt_map(struct mv88e6xxx_chip * chip,int dev,int port)1644 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1645 {
1646 struct dsa_switch_tree *dst = chip->ds->dst;
1647 struct dsa_switch *ds;
1648 struct dsa_port *dp;
1649 u16 pvlan = 0;
1650
1651 if (!mv88e6xxx_has_pvt(chip))
1652 return 0;
1653
1654 /* Skip the local source device, which uses in-chip port VLAN */
1655 if (dev != chip->ds->index) {
1656 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1657
1658 ds = dsa_switch_find(dst->index, dev);
1659 dp = ds ? dsa_to_port(ds, port) : NULL;
1660 if (dp && dp->lag) {
1661 /* As the PVT is used to limit flooding of
1662 * FORWARD frames, which use the LAG ID as the
1663 * source port, we must translate dev/port to
1664 * the special "LAG device" in the PVT, using
1665 * the LAG ID (one-based) as the port number
1666 * (zero-based).
1667 */
1668 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK;
1669 port = dsa_port_lag_id_get(dp) - 1;
1670 }
1671 }
1672
1673 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1674 }
1675
mv88e6xxx_pvt_setup(struct mv88e6xxx_chip * chip)1676 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1677 {
1678 int dev, port;
1679 int err;
1680
1681 if (!mv88e6xxx_has_pvt(chip))
1682 return 0;
1683
1684 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1685 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1686 */
1687 err = mv88e6xxx_g2_misc_4_bit_port(chip);
1688 if (err)
1689 return err;
1690
1691 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1692 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1693 err = mv88e6xxx_pvt_map(chip, dev, port);
1694 if (err)
1695 return err;
1696 }
1697 }
1698
1699 return 0;
1700 }
1701
mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip * chip,int port,u16 fid)1702 static int mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip *chip, int port,
1703 u16 fid)
1704 {
1705 if (dsa_to_port(chip->ds, port)->lag)
1706 /* Hardware is incapable of fast-aging a LAG through a
1707 * regular ATU move operation. Until we have something
1708 * more fancy in place this is a no-op.
1709 */
1710 return -EOPNOTSUPP;
1711
1712 return mv88e6xxx_g1_atu_remove(chip, fid, port, false);
1713 }
1714
mv88e6xxx_port_fast_age(struct dsa_switch * ds,int port)1715 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1716 {
1717 struct mv88e6xxx_chip *chip = ds->priv;
1718 int err;
1719
1720 mv88e6xxx_reg_lock(chip);
1721 err = mv88e6xxx_port_fast_age_fid(chip, port, 0);
1722 mv88e6xxx_reg_unlock(chip);
1723
1724 if (err)
1725 dev_err(chip->ds->dev, "p%d: failed to flush ATU: %d\n",
1726 port, err);
1727 }
1728
mv88e6xxx_vtu_setup(struct mv88e6xxx_chip * chip)1729 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1730 {
1731 if (!mv88e6xxx_max_vid(chip))
1732 return 0;
1733
1734 return mv88e6xxx_g1_vtu_flush(chip);
1735 }
1736
mv88e6xxx_vtu_get(struct mv88e6xxx_chip * chip,u16 vid,struct mv88e6xxx_vtu_entry * entry)1737 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1738 struct mv88e6xxx_vtu_entry *entry)
1739 {
1740 int err;
1741
1742 if (!chip->info->ops->vtu_getnext)
1743 return -EOPNOTSUPP;
1744
1745 memset(entry, 0, sizeof(*entry));
1746
1747 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip);
1748 entry->valid = false;
1749
1750 err = chip->info->ops->vtu_getnext(chip, entry);
1751
1752 if (entry->vid != vid)
1753 entry->valid = false;
1754
1755 return err;
1756 }
1757
mv88e6xxx_vtu_walk(struct mv88e6xxx_chip * chip,int (* cb)(struct mv88e6xxx_chip * chip,const struct mv88e6xxx_vtu_entry * entry,void * priv),void * priv)1758 int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip,
1759 int (*cb)(struct mv88e6xxx_chip *chip,
1760 const struct mv88e6xxx_vtu_entry *entry,
1761 void *priv),
1762 void *priv)
1763 {
1764 struct mv88e6xxx_vtu_entry entry = {
1765 .vid = mv88e6xxx_max_vid(chip),
1766 .valid = false,
1767 };
1768 int err;
1769
1770 if (!chip->info->ops->vtu_getnext)
1771 return -EOPNOTSUPP;
1772
1773 do {
1774 err = chip->info->ops->vtu_getnext(chip, &entry);
1775 if (err)
1776 return err;
1777
1778 if (!entry.valid)
1779 break;
1780
1781 err = cb(chip, &entry, priv);
1782 if (err)
1783 return err;
1784 } while (entry.vid < mv88e6xxx_max_vid(chip));
1785
1786 return 0;
1787 }
1788
mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip * chip,struct mv88e6xxx_vtu_entry * entry)1789 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1790 struct mv88e6xxx_vtu_entry *entry)
1791 {
1792 if (!chip->info->ops->vtu_loadpurge)
1793 return -EOPNOTSUPP;
1794
1795 return chip->info->ops->vtu_loadpurge(chip, entry);
1796 }
1797
mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip * chip,const struct mv88e6xxx_vtu_entry * entry,void * _fid_bitmap)1798 static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip,
1799 const struct mv88e6xxx_vtu_entry *entry,
1800 void *_fid_bitmap)
1801 {
1802 unsigned long *fid_bitmap = _fid_bitmap;
1803
1804 set_bit(entry->fid, fid_bitmap);
1805 return 0;
1806 }
1807
mv88e6xxx_fid_map(struct mv88e6xxx_chip * chip,unsigned long * fid_bitmap)1808 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap)
1809 {
1810 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1811
1812 /* Every FID has an associated VID, so walking the VTU
1813 * will discover the full set of FIDs in use.
1814 */
1815 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap);
1816 }
1817
mv88e6xxx_atu_new(struct mv88e6xxx_chip * chip,u16 * fid)1818 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1819 {
1820 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1821 int err;
1822
1823 err = mv88e6xxx_fid_map(chip, fid_bitmap);
1824 if (err)
1825 return err;
1826
1827 *fid = find_first_zero_bit(fid_bitmap, MV88E6XXX_N_FID);
1828 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1829 return -ENOSPC;
1830
1831 /* Clear the database */
1832 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1833 }
1834
mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip * chip,struct mv88e6xxx_stu_entry * entry)1835 static int mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
1836 struct mv88e6xxx_stu_entry *entry)
1837 {
1838 if (!chip->info->ops->stu_loadpurge)
1839 return -EOPNOTSUPP;
1840
1841 return chip->info->ops->stu_loadpurge(chip, entry);
1842 }
1843
mv88e6xxx_stu_setup(struct mv88e6xxx_chip * chip)1844 static int mv88e6xxx_stu_setup(struct mv88e6xxx_chip *chip)
1845 {
1846 struct mv88e6xxx_stu_entry stu = {
1847 .valid = true,
1848 .sid = 0
1849 };
1850
1851 if (!mv88e6xxx_has_stu(chip))
1852 return 0;
1853
1854 /* Make sure that SID 0 is always valid. This is used by VTU
1855 * entries that do not make use of the STU, e.g. when creating
1856 * a VLAN upper on a port that is also part of a VLAN
1857 * filtering bridge.
1858 */
1859 return mv88e6xxx_stu_loadpurge(chip, &stu);
1860 }
1861
mv88e6xxx_sid_get(struct mv88e6xxx_chip * chip,u8 * sid)1862 static int mv88e6xxx_sid_get(struct mv88e6xxx_chip *chip, u8 *sid)
1863 {
1864 DECLARE_BITMAP(busy, MV88E6XXX_N_SID) = { 0 };
1865 struct mv88e6xxx_mst *mst;
1866
1867 __set_bit(0, busy);
1868
1869 list_for_each_entry(mst, &chip->msts, node)
1870 __set_bit(mst->stu.sid, busy);
1871
1872 *sid = find_first_zero_bit(busy, MV88E6XXX_N_SID);
1873
1874 return (*sid >= mv88e6xxx_max_sid(chip)) ? -ENOSPC : 0;
1875 }
1876
mv88e6xxx_mst_put(struct mv88e6xxx_chip * chip,u8 sid)1877 static int mv88e6xxx_mst_put(struct mv88e6xxx_chip *chip, u8 sid)
1878 {
1879 struct mv88e6xxx_mst *mst, *tmp;
1880 int err;
1881
1882 /* If the SID is zero, it is for a VLAN mapped to the default MSTI,
1883 * and mv88e6xxx_stu_setup() made sure it is always present, and thus,
1884 * should not be removed here.
1885 *
1886 * If the chip lacks STU support, numerically the "sid" variable will
1887 * happen to also be zero, but we don't want to rely on that fact, so
1888 * we explicitly test that first. In that case, there is also nothing
1889 * to do here.
1890 */
1891 if (!mv88e6xxx_has_stu(chip) || !sid)
1892 return 0;
1893
1894 list_for_each_entry_safe(mst, tmp, &chip->msts, node) {
1895 if (mst->stu.sid != sid)
1896 continue;
1897
1898 if (!refcount_dec_and_test(&mst->refcnt))
1899 return 0;
1900
1901 mst->stu.valid = false;
1902 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
1903 if (err) {
1904 refcount_set(&mst->refcnt, 1);
1905 return err;
1906 }
1907
1908 list_del(&mst->node);
1909 kfree(mst);
1910 return 0;
1911 }
1912
1913 return -ENOENT;
1914 }
1915
mv88e6xxx_mst_get(struct mv88e6xxx_chip * chip,struct net_device * br,u16 msti,u8 * sid)1916 static int mv88e6xxx_mst_get(struct mv88e6xxx_chip *chip, struct net_device *br,
1917 u16 msti, u8 *sid)
1918 {
1919 struct mv88e6xxx_mst *mst;
1920 int err, i;
1921
1922 if (!mv88e6xxx_has_stu(chip)) {
1923 err = -EOPNOTSUPP;
1924 goto err;
1925 }
1926
1927 if (!msti) {
1928 *sid = 0;
1929 return 0;
1930 }
1931
1932 list_for_each_entry(mst, &chip->msts, node) {
1933 if (mst->br == br && mst->msti == msti) {
1934 refcount_inc(&mst->refcnt);
1935 *sid = mst->stu.sid;
1936 return 0;
1937 }
1938 }
1939
1940 err = mv88e6xxx_sid_get(chip, sid);
1941 if (err)
1942 goto err;
1943
1944 mst = kzalloc(sizeof(*mst), GFP_KERNEL);
1945 if (!mst) {
1946 err = -ENOMEM;
1947 goto err;
1948 }
1949
1950 INIT_LIST_HEAD(&mst->node);
1951 refcount_set(&mst->refcnt, 1);
1952 mst->br = br;
1953 mst->msti = msti;
1954 mst->stu.valid = true;
1955 mst->stu.sid = *sid;
1956
1957 /* The bridge starts out all ports in the disabled state. But
1958 * a STU state of disabled means to go by the port-global
1959 * state. So we set all user port's initial state to blocking,
1960 * to match the bridge's behavior.
1961 */
1962 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
1963 mst->stu.state[i] = dsa_is_user_port(chip->ds, i) ?
1964 MV88E6XXX_PORT_CTL0_STATE_BLOCKING :
1965 MV88E6XXX_PORT_CTL0_STATE_DISABLED;
1966
1967 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
1968 if (err)
1969 goto err_free;
1970
1971 list_add_tail(&mst->node, &chip->msts);
1972 return 0;
1973
1974 err_free:
1975 kfree(mst);
1976 err:
1977 return err;
1978 }
1979
mv88e6xxx_port_mst_state_set(struct dsa_switch * ds,int port,const struct switchdev_mst_state * st)1980 static int mv88e6xxx_port_mst_state_set(struct dsa_switch *ds, int port,
1981 const struct switchdev_mst_state *st)
1982 {
1983 struct dsa_port *dp = dsa_to_port(ds, port);
1984 struct mv88e6xxx_chip *chip = ds->priv;
1985 struct mv88e6xxx_mst *mst;
1986 u8 state;
1987 int err;
1988
1989 if (!mv88e6xxx_has_stu(chip))
1990 return -EOPNOTSUPP;
1991
1992 switch (st->state) {
1993 case BR_STATE_DISABLED:
1994 case BR_STATE_BLOCKING:
1995 case BR_STATE_LISTENING:
1996 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING;
1997 break;
1998 case BR_STATE_LEARNING:
1999 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING;
2000 break;
2001 case BR_STATE_FORWARDING:
2002 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
2003 break;
2004 default:
2005 return -EINVAL;
2006 }
2007
2008 list_for_each_entry(mst, &chip->msts, node) {
2009 if (mst->br == dsa_port_bridge_dev_get(dp) &&
2010 mst->msti == st->msti) {
2011 if (mst->stu.state[port] == state)
2012 return 0;
2013
2014 mst->stu.state[port] = state;
2015 mv88e6xxx_reg_lock(chip);
2016 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
2017 mv88e6xxx_reg_unlock(chip);
2018 return err;
2019 }
2020 }
2021
2022 return -ENOENT;
2023 }
2024
mv88e6xxx_port_check_hw_vlan(struct dsa_switch * ds,int port,u16 vid)2025 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
2026 u16 vid)
2027 {
2028 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp;
2029 struct mv88e6xxx_chip *chip = ds->priv;
2030 struct mv88e6xxx_vtu_entry vlan;
2031 int err;
2032
2033 /* DSA and CPU ports have to be members of multiple vlans */
2034 if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp))
2035 return 0;
2036
2037 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2038 if (err)
2039 return err;
2040
2041 if (!vlan.valid)
2042 return 0;
2043
2044 dsa_switch_for_each_user_port(other_dp, ds) {
2045 struct net_device *other_br;
2046
2047 if (vlan.member[other_dp->index] ==
2048 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2049 continue;
2050
2051 if (dsa_port_bridge_same(dp, other_dp))
2052 break; /* same bridge, check next VLAN */
2053
2054 other_br = dsa_port_bridge_dev_get(other_dp);
2055 if (!other_br)
2056 continue;
2057
2058 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
2059 port, vlan.vid, other_dp->index, netdev_name(other_br));
2060 return -EOPNOTSUPP;
2061 }
2062
2063 return 0;
2064 }
2065
mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip * chip,int port)2066 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port)
2067 {
2068 struct dsa_port *dp = dsa_to_port(chip->ds, port);
2069 struct net_device *br = dsa_port_bridge_dev_get(dp);
2070 struct mv88e6xxx_port *p = &chip->ports[port];
2071 u16 pvid = MV88E6XXX_VID_STANDALONE;
2072 bool drop_untagged = false;
2073 int err;
2074
2075 if (br) {
2076 if (br_vlan_enabled(br)) {
2077 pvid = p->bridge_pvid.vid;
2078 drop_untagged = !p->bridge_pvid.valid;
2079 } else {
2080 pvid = MV88E6XXX_VID_BRIDGED;
2081 }
2082 }
2083
2084 err = mv88e6xxx_port_set_pvid(chip, port, pvid);
2085 if (err)
2086 return err;
2087
2088 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged);
2089 }
2090
mv88e6xxx_port_vlan_filtering(struct dsa_switch * ds,int port,bool vlan_filtering,struct netlink_ext_ack * extack)2091 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
2092 bool vlan_filtering,
2093 struct netlink_ext_ack *extack)
2094 {
2095 struct mv88e6xxx_chip *chip = ds->priv;
2096 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
2097 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
2098 int err;
2099
2100 if (!mv88e6xxx_max_vid(chip))
2101 return -EOPNOTSUPP;
2102
2103 mv88e6xxx_reg_lock(chip);
2104
2105 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
2106 if (err)
2107 goto unlock;
2108
2109 err = mv88e6xxx_port_commit_pvid(chip, port);
2110 if (err)
2111 goto unlock;
2112
2113 unlock:
2114 mv88e6xxx_reg_unlock(chip);
2115
2116 return err;
2117 }
2118
2119 static int
mv88e6xxx_port_vlan_prepare(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)2120 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
2121 const struct switchdev_obj_port_vlan *vlan)
2122 {
2123 struct mv88e6xxx_chip *chip = ds->priv;
2124 int err;
2125
2126 if (!mv88e6xxx_max_vid(chip))
2127 return -EOPNOTSUPP;
2128
2129 /* If the requested port doesn't belong to the same bridge as the VLAN
2130 * members, do not support it (yet) and fallback to software VLAN.
2131 */
2132 mv88e6xxx_reg_lock(chip);
2133 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid);
2134 mv88e6xxx_reg_unlock(chip);
2135
2136 return err;
2137 }
2138
mv88e6xxx_port_db_get(struct mv88e6xxx_chip * chip,const unsigned char * addr,u16 vid,u16 * fid,struct mv88e6xxx_atu_entry * entry)2139 static int mv88e6xxx_port_db_get(struct mv88e6xxx_chip *chip,
2140 const unsigned char *addr, u16 vid,
2141 u16 *fid, struct mv88e6xxx_atu_entry *entry)
2142 {
2143 struct mv88e6xxx_vtu_entry vlan;
2144 int err;
2145
2146 /* Ports have two private address databases: one for when the port is
2147 * standalone and one for when the port is under a bridge and the
2148 * 802.1Q mode is disabled. When the port is standalone, DSA wants its
2149 * address database to remain 100% empty, so we never load an ATU entry
2150 * into a standalone port's database. Therefore, translate the null
2151 * VLAN ID into the port's database used for VLAN-unaware bridging.
2152 */
2153 if (vid == 0) {
2154 *fid = MV88E6XXX_FID_BRIDGED;
2155 } else {
2156 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2157 if (err)
2158 return err;
2159
2160 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
2161 if (!vlan.valid)
2162 return -EOPNOTSUPP;
2163
2164 *fid = vlan.fid;
2165 }
2166
2167 entry->state = 0;
2168 ether_addr_copy(entry->mac, addr);
2169 eth_addr_dec(entry->mac);
2170
2171 return mv88e6xxx_g1_atu_getnext(chip, *fid, entry);
2172 }
2173
mv88e6xxx_port_db_find(struct mv88e6xxx_chip * chip,const unsigned char * addr,u16 vid)2174 static bool mv88e6xxx_port_db_find(struct mv88e6xxx_chip *chip,
2175 const unsigned char *addr, u16 vid)
2176 {
2177 struct mv88e6xxx_atu_entry entry;
2178 u16 fid;
2179 int err;
2180
2181 err = mv88e6xxx_port_db_get(chip, addr, vid, &fid, &entry);
2182 if (err)
2183 return false;
2184
2185 return entry.state && ether_addr_equal(entry.mac, addr);
2186 }
2187
mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip * chip,int port,const unsigned char * addr,u16 vid,u8 state)2188 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
2189 const unsigned char *addr, u16 vid,
2190 u8 state)
2191 {
2192 struct mv88e6xxx_atu_entry entry;
2193 u16 fid;
2194 int err;
2195
2196 err = mv88e6xxx_port_db_get(chip, addr, vid, &fid, &entry);
2197 if (err)
2198 return err;
2199
2200 /* Initialize a fresh ATU entry if it isn't found */
2201 if (!entry.state || !ether_addr_equal(entry.mac, addr)) {
2202 memset(&entry, 0, sizeof(entry));
2203 ether_addr_copy(entry.mac, addr);
2204 }
2205
2206 /* Purge the ATU entry only if no port is using it anymore */
2207 if (!state) {
2208 entry.portvec &= ~BIT(port);
2209 if (!entry.portvec)
2210 entry.state = 0;
2211 } else {
2212 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC)
2213 entry.portvec = BIT(port);
2214 else
2215 entry.portvec |= BIT(port);
2216
2217 entry.state = state;
2218 }
2219
2220 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry);
2221 }
2222
mv88e6xxx_policy_apply(struct mv88e6xxx_chip * chip,int port,const struct mv88e6xxx_policy * policy)2223 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port,
2224 const struct mv88e6xxx_policy *policy)
2225 {
2226 enum mv88e6xxx_policy_mapping mapping = policy->mapping;
2227 enum mv88e6xxx_policy_action action = policy->action;
2228 const u8 *addr = policy->addr;
2229 u16 vid = policy->vid;
2230 u8 state;
2231 int err;
2232 int id;
2233
2234 if (!chip->info->ops->port_set_policy)
2235 return -EOPNOTSUPP;
2236
2237 switch (mapping) {
2238 case MV88E6XXX_POLICY_MAPPING_DA:
2239 case MV88E6XXX_POLICY_MAPPING_SA:
2240 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
2241 state = 0; /* Dissociate the port and address */
2242 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
2243 is_multicast_ether_addr(addr))
2244 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY;
2245 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
2246 is_unicast_ether_addr(addr))
2247 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY;
2248 else
2249 return -EOPNOTSUPP;
2250
2251 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2252 state);
2253 if (err)
2254 return err;
2255 break;
2256 default:
2257 return -EOPNOTSUPP;
2258 }
2259
2260 /* Skip the port's policy clearing if the mapping is still in use */
2261 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
2262 idr_for_each_entry(&chip->policies, policy, id)
2263 if (policy->port == port &&
2264 policy->mapping == mapping &&
2265 policy->action != action)
2266 return 0;
2267
2268 return chip->info->ops->port_set_policy(chip, port, mapping, action);
2269 }
2270
mv88e6xxx_policy_insert(struct mv88e6xxx_chip * chip,int port,struct ethtool_rx_flow_spec * fs)2271 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port,
2272 struct ethtool_rx_flow_spec *fs)
2273 {
2274 struct ethhdr *mac_entry = &fs->h_u.ether_spec;
2275 struct ethhdr *mac_mask = &fs->m_u.ether_spec;
2276 enum mv88e6xxx_policy_mapping mapping;
2277 enum mv88e6xxx_policy_action action;
2278 struct mv88e6xxx_policy *policy;
2279 u16 vid = 0;
2280 u8 *addr;
2281 int err;
2282 int id;
2283
2284 if (fs->location != RX_CLS_LOC_ANY)
2285 return -EINVAL;
2286
2287 if (fs->ring_cookie == RX_CLS_FLOW_DISC)
2288 action = MV88E6XXX_POLICY_ACTION_DISCARD;
2289 else
2290 return -EOPNOTSUPP;
2291
2292 switch (fs->flow_type & ~FLOW_EXT) {
2293 case ETHER_FLOW:
2294 if (!is_zero_ether_addr(mac_mask->h_dest) &&
2295 is_zero_ether_addr(mac_mask->h_source)) {
2296 mapping = MV88E6XXX_POLICY_MAPPING_DA;
2297 addr = mac_entry->h_dest;
2298 } else if (is_zero_ether_addr(mac_mask->h_dest) &&
2299 !is_zero_ether_addr(mac_mask->h_source)) {
2300 mapping = MV88E6XXX_POLICY_MAPPING_SA;
2301 addr = mac_entry->h_source;
2302 } else {
2303 /* Cannot support DA and SA mapping in the same rule */
2304 return -EOPNOTSUPP;
2305 }
2306 break;
2307 default:
2308 return -EOPNOTSUPP;
2309 }
2310
2311 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) {
2312 if (fs->m_ext.vlan_tci != htons(0xffff))
2313 return -EOPNOTSUPP;
2314 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK;
2315 }
2316
2317 idr_for_each_entry(&chip->policies, policy, id) {
2318 if (policy->port == port && policy->mapping == mapping &&
2319 policy->action == action && policy->vid == vid &&
2320 ether_addr_equal(policy->addr, addr))
2321 return -EEXIST;
2322 }
2323
2324 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL);
2325 if (!policy)
2326 return -ENOMEM;
2327
2328 fs->location = 0;
2329 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff,
2330 GFP_KERNEL);
2331 if (err) {
2332 devm_kfree(chip->dev, policy);
2333 return err;
2334 }
2335
2336 memcpy(&policy->fs, fs, sizeof(*fs));
2337 ether_addr_copy(policy->addr, addr);
2338 policy->mapping = mapping;
2339 policy->action = action;
2340 policy->port = port;
2341 policy->vid = vid;
2342
2343 err = mv88e6xxx_policy_apply(chip, port, policy);
2344 if (err) {
2345 idr_remove(&chip->policies, fs->location);
2346 devm_kfree(chip->dev, policy);
2347 return err;
2348 }
2349
2350 return 0;
2351 }
2352
mv88e6xxx_get_rxnfc(struct dsa_switch * ds,int port,struct ethtool_rxnfc * rxnfc,u32 * rule_locs)2353 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port,
2354 struct ethtool_rxnfc *rxnfc, u32 *rule_locs)
2355 {
2356 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
2357 struct mv88e6xxx_chip *chip = ds->priv;
2358 struct mv88e6xxx_policy *policy;
2359 int err;
2360 int id;
2361
2362 mv88e6xxx_reg_lock(chip);
2363
2364 switch (rxnfc->cmd) {
2365 case ETHTOOL_GRXCLSRLCNT:
2366 rxnfc->data = 0;
2367 rxnfc->data |= RX_CLS_LOC_SPECIAL;
2368 rxnfc->rule_cnt = 0;
2369 idr_for_each_entry(&chip->policies, policy, id)
2370 if (policy->port == port)
2371 rxnfc->rule_cnt++;
2372 err = 0;
2373 break;
2374 case ETHTOOL_GRXCLSRULE:
2375 err = -ENOENT;
2376 policy = idr_find(&chip->policies, fs->location);
2377 if (policy) {
2378 memcpy(fs, &policy->fs, sizeof(*fs));
2379 err = 0;
2380 }
2381 break;
2382 case ETHTOOL_GRXCLSRLALL:
2383 rxnfc->data = 0;
2384 rxnfc->rule_cnt = 0;
2385 idr_for_each_entry(&chip->policies, policy, id)
2386 if (policy->port == port)
2387 rule_locs[rxnfc->rule_cnt++] = id;
2388 err = 0;
2389 break;
2390 default:
2391 err = -EOPNOTSUPP;
2392 break;
2393 }
2394
2395 mv88e6xxx_reg_unlock(chip);
2396
2397 return err;
2398 }
2399
mv88e6xxx_set_rxnfc(struct dsa_switch * ds,int port,struct ethtool_rxnfc * rxnfc)2400 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port,
2401 struct ethtool_rxnfc *rxnfc)
2402 {
2403 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
2404 struct mv88e6xxx_chip *chip = ds->priv;
2405 struct mv88e6xxx_policy *policy;
2406 int err;
2407
2408 mv88e6xxx_reg_lock(chip);
2409
2410 switch (rxnfc->cmd) {
2411 case ETHTOOL_SRXCLSRLINS:
2412 err = mv88e6xxx_policy_insert(chip, port, fs);
2413 break;
2414 case ETHTOOL_SRXCLSRLDEL:
2415 err = -ENOENT;
2416 policy = idr_remove(&chip->policies, fs->location);
2417 if (policy) {
2418 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL;
2419 err = mv88e6xxx_policy_apply(chip, port, policy);
2420 devm_kfree(chip->dev, policy);
2421 }
2422 break;
2423 default:
2424 err = -EOPNOTSUPP;
2425 break;
2426 }
2427
2428 mv88e6xxx_reg_unlock(chip);
2429
2430 return err;
2431 }
2432
mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip * chip,int port,u16 vid)2433 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
2434 u16 vid)
2435 {
2436 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
2437 u8 broadcast[ETH_ALEN];
2438
2439 eth_broadcast_addr(broadcast);
2440
2441 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
2442 }
2443
mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip * chip,u16 vid)2444 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
2445 {
2446 int port;
2447 int err;
2448
2449 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2450 struct dsa_port *dp = dsa_to_port(chip->ds, port);
2451 struct net_device *brport;
2452
2453 if (dsa_is_unused_port(chip->ds, port))
2454 continue;
2455
2456 brport = dsa_port_to_bridge_port(dp);
2457 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD))
2458 /* Skip bridged user ports where broadcast
2459 * flooding is disabled.
2460 */
2461 continue;
2462
2463 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
2464 if (err)
2465 return err;
2466 }
2467
2468 return 0;
2469 }
2470
2471 struct mv88e6xxx_port_broadcast_sync_ctx {
2472 int port;
2473 bool flood;
2474 };
2475
2476 static int
mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip * chip,const struct mv88e6xxx_vtu_entry * vlan,void * _ctx)2477 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip,
2478 const struct mv88e6xxx_vtu_entry *vlan,
2479 void *_ctx)
2480 {
2481 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx;
2482 u8 broadcast[ETH_ALEN];
2483 u8 state;
2484
2485 if (ctx->flood)
2486 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
2487 else
2488 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED;
2489
2490 eth_broadcast_addr(broadcast);
2491
2492 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast,
2493 vlan->vid, state);
2494 }
2495
mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip * chip,int port,bool flood)2496 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port,
2497 bool flood)
2498 {
2499 struct mv88e6xxx_port_broadcast_sync_ctx ctx = {
2500 .port = port,
2501 .flood = flood,
2502 };
2503 struct mv88e6xxx_vtu_entry vid0 = {
2504 .vid = 0,
2505 };
2506 int err;
2507
2508 /* Update the port's private database... */
2509 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx);
2510 if (err)
2511 return err;
2512
2513 /* ...and the database for all VLANs. */
2514 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan,
2515 &ctx);
2516 }
2517
mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip * chip,int port,u16 vid,u8 member,bool warn)2518 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port,
2519 u16 vid, u8 member, bool warn)
2520 {
2521 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2522 struct mv88e6xxx_vtu_entry vlan;
2523 int i, err;
2524
2525 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2526 if (err)
2527 return err;
2528
2529 if (!vlan.valid) {
2530 memset(&vlan, 0, sizeof(vlan));
2531
2532 if (vid == MV88E6XXX_VID_STANDALONE)
2533 vlan.policy = true;
2534
2535 err = mv88e6xxx_atu_new(chip, &vlan.fid);
2536 if (err)
2537 return err;
2538
2539 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
2540 if (i == port)
2541 vlan.member[i] = member;
2542 else
2543 vlan.member[i] = non_member;
2544
2545 vlan.vid = vid;
2546 vlan.valid = true;
2547
2548 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2549 if (err)
2550 return err;
2551
2552 err = mv88e6xxx_broadcast_setup(chip, vlan.vid);
2553 if (err)
2554 return err;
2555 } else if (vlan.member[port] != member) {
2556 vlan.member[port] = member;
2557
2558 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2559 if (err)
2560 return err;
2561 } else if (warn) {
2562 dev_info(chip->dev, "p%d: already a member of VLAN %d\n",
2563 port, vid);
2564 }
2565
2566 return 0;
2567 }
2568
mv88e6xxx_port_vlan_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan,struct netlink_ext_ack * extack)2569 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
2570 const struct switchdev_obj_port_vlan *vlan,
2571 struct netlink_ext_ack *extack)
2572 {
2573 struct mv88e6xxx_chip *chip = ds->priv;
2574 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
2575 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
2576 struct mv88e6xxx_port *p = &chip->ports[port];
2577 bool warn;
2578 u8 member;
2579 int err;
2580
2581 if (!vlan->vid)
2582 return 0;
2583
2584 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan);
2585 if (err)
2586 return err;
2587
2588 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
2589 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
2590 else if (untagged)
2591 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
2592 else
2593 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
2594
2595 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port
2596 * and then the CPU port. Do not warn for duplicates for the CPU port.
2597 */
2598 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port);
2599
2600 mv88e6xxx_reg_lock(chip);
2601
2602 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn);
2603 if (err) {
2604 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
2605 vlan->vid, untagged ? 'u' : 't');
2606 goto out;
2607 }
2608
2609 if (pvid) {
2610 p->bridge_pvid.vid = vlan->vid;
2611 p->bridge_pvid.valid = true;
2612
2613 err = mv88e6xxx_port_commit_pvid(chip, port);
2614 if (err)
2615 goto out;
2616 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) {
2617 /* The old pvid was reinstalled as a non-pvid VLAN */
2618 p->bridge_pvid.valid = false;
2619
2620 err = mv88e6xxx_port_commit_pvid(chip, port);
2621 if (err)
2622 goto out;
2623 }
2624
2625 out:
2626 mv88e6xxx_reg_unlock(chip);
2627
2628 return err;
2629 }
2630
mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip * chip,int port,u16 vid)2631 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip,
2632 int port, u16 vid)
2633 {
2634 struct mv88e6xxx_vtu_entry vlan;
2635 int i, err;
2636
2637 if (!vid)
2638 return 0;
2639
2640 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2641 if (err)
2642 return err;
2643
2644 /* If the VLAN doesn't exist in hardware or the port isn't a member,
2645 * tell switchdev that this VLAN is likely handled in software.
2646 */
2647 if (!vlan.valid ||
2648 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2649 return -EOPNOTSUPP;
2650
2651 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2652
2653 /* keep the VLAN unless all ports are excluded */
2654 vlan.valid = false;
2655 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
2656 if (vlan.member[i] !=
2657 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
2658 vlan.valid = true;
2659 break;
2660 }
2661 }
2662
2663 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2664 if (err)
2665 return err;
2666
2667 if (!vlan.valid) {
2668 err = mv88e6xxx_mst_put(chip, vlan.sid);
2669 if (err)
2670 return err;
2671 }
2672
2673 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
2674 }
2675
mv88e6xxx_port_vlan_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)2676 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2677 const struct switchdev_obj_port_vlan *vlan)
2678 {
2679 struct mv88e6xxx_chip *chip = ds->priv;
2680 struct mv88e6xxx_port *p = &chip->ports[port];
2681 int err = 0;
2682 u16 pvid;
2683
2684 if (!mv88e6xxx_max_vid(chip))
2685 return -EOPNOTSUPP;
2686
2687 /* The ATU removal procedure needs the FID to be mapped in the VTU,
2688 * but FDB deletion runs concurrently with VLAN deletion. Flush the DSA
2689 * switchdev workqueue to ensure that all FDB entries are deleted
2690 * before we remove the VLAN.
2691 */
2692 dsa_flush_workqueue();
2693
2694 mv88e6xxx_reg_lock(chip);
2695
2696 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
2697 if (err)
2698 goto unlock;
2699
2700 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid);
2701 if (err)
2702 goto unlock;
2703
2704 if (vlan->vid == pvid) {
2705 p->bridge_pvid.valid = false;
2706
2707 err = mv88e6xxx_port_commit_pvid(chip, port);
2708 if (err)
2709 goto unlock;
2710 }
2711
2712 unlock:
2713 mv88e6xxx_reg_unlock(chip);
2714
2715 return err;
2716 }
2717
mv88e6xxx_port_vlan_fast_age(struct dsa_switch * ds,int port,u16 vid)2718 static int mv88e6xxx_port_vlan_fast_age(struct dsa_switch *ds, int port, u16 vid)
2719 {
2720 struct mv88e6xxx_chip *chip = ds->priv;
2721 struct mv88e6xxx_vtu_entry vlan;
2722 int err;
2723
2724 mv88e6xxx_reg_lock(chip);
2725
2726 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2727 if (err)
2728 goto unlock;
2729
2730 err = mv88e6xxx_port_fast_age_fid(chip, port, vlan.fid);
2731
2732 unlock:
2733 mv88e6xxx_reg_unlock(chip);
2734
2735 return err;
2736 }
2737
mv88e6xxx_vlan_msti_set(struct dsa_switch * ds,struct dsa_bridge bridge,const struct switchdev_vlan_msti * msti)2738 static int mv88e6xxx_vlan_msti_set(struct dsa_switch *ds,
2739 struct dsa_bridge bridge,
2740 const struct switchdev_vlan_msti *msti)
2741 {
2742 struct mv88e6xxx_chip *chip = ds->priv;
2743 struct mv88e6xxx_vtu_entry vlan;
2744 u8 old_sid, new_sid;
2745 int err;
2746
2747 if (!mv88e6xxx_has_stu(chip))
2748 return -EOPNOTSUPP;
2749
2750 mv88e6xxx_reg_lock(chip);
2751
2752 err = mv88e6xxx_vtu_get(chip, msti->vid, &vlan);
2753 if (err)
2754 goto unlock;
2755
2756 if (!vlan.valid) {
2757 err = -EINVAL;
2758 goto unlock;
2759 }
2760
2761 old_sid = vlan.sid;
2762
2763 err = mv88e6xxx_mst_get(chip, bridge.dev, msti->msti, &new_sid);
2764 if (err)
2765 goto unlock;
2766
2767 if (new_sid != old_sid) {
2768 vlan.sid = new_sid;
2769
2770 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2771 if (err) {
2772 mv88e6xxx_mst_put(chip, new_sid);
2773 goto unlock;
2774 }
2775 }
2776
2777 err = mv88e6xxx_mst_put(chip, old_sid);
2778
2779 unlock:
2780 mv88e6xxx_reg_unlock(chip);
2781 return err;
2782 }
2783
mv88e6xxx_port_fdb_add(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)2784 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2785 const unsigned char *addr, u16 vid,
2786 struct dsa_db db)
2787 {
2788 struct mv88e6xxx_chip *chip = ds->priv;
2789 int err;
2790
2791 mv88e6xxx_reg_lock(chip);
2792 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2793 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2794 if (err)
2795 goto out;
2796
2797 if (!mv88e6xxx_port_db_find(chip, addr, vid))
2798 err = -ENOSPC;
2799
2800 out:
2801 mv88e6xxx_reg_unlock(chip);
2802
2803 return err;
2804 }
2805
mv88e6xxx_port_fdb_del(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)2806 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2807 const unsigned char *addr, u16 vid,
2808 struct dsa_db db)
2809 {
2810 struct mv88e6xxx_chip *chip = ds->priv;
2811 int err;
2812
2813 mv88e6xxx_reg_lock(chip);
2814 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0);
2815 mv88e6xxx_reg_unlock(chip);
2816
2817 return err;
2818 }
2819
mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip * chip,u16 fid,u16 vid,int port,dsa_fdb_dump_cb_t * cb,void * data)2820 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2821 u16 fid, u16 vid, int port,
2822 dsa_fdb_dump_cb_t *cb, void *data)
2823 {
2824 struct mv88e6xxx_atu_entry addr;
2825 bool is_static;
2826 int err;
2827
2828 addr.state = 0;
2829 eth_broadcast_addr(addr.mac);
2830
2831 do {
2832 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
2833 if (err)
2834 return err;
2835
2836 if (!addr.state)
2837 break;
2838
2839 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
2840 continue;
2841
2842 if (!is_unicast_ether_addr(addr.mac))
2843 continue;
2844
2845 is_static = (addr.state ==
2846 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2847 err = cb(addr.mac, vid, is_static, data);
2848 if (err)
2849 return err;
2850 } while (!is_broadcast_ether_addr(addr.mac));
2851
2852 return err;
2853 }
2854
2855 struct mv88e6xxx_port_db_dump_vlan_ctx {
2856 int port;
2857 dsa_fdb_dump_cb_t *cb;
2858 void *data;
2859 };
2860
mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip * chip,const struct mv88e6xxx_vtu_entry * entry,void * _data)2861 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip,
2862 const struct mv88e6xxx_vtu_entry *entry,
2863 void *_data)
2864 {
2865 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data;
2866
2867 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid,
2868 ctx->port, ctx->cb, ctx->data);
2869 }
2870
mv88e6xxx_port_db_dump(struct mv88e6xxx_chip * chip,int port,dsa_fdb_dump_cb_t * cb,void * data)2871 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2872 dsa_fdb_dump_cb_t *cb, void *data)
2873 {
2874 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = {
2875 .port = port,
2876 .cb = cb,
2877 .data = data,
2878 };
2879 u16 fid;
2880 int err;
2881
2882 /* Dump port's default Filtering Information Database (VLAN ID 0) */
2883 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2884 if (err)
2885 return err;
2886
2887 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
2888 if (err)
2889 return err;
2890
2891 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx);
2892 }
2893
mv88e6xxx_port_fdb_dump(struct dsa_switch * ds,int port,dsa_fdb_dump_cb_t * cb,void * data)2894 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2895 dsa_fdb_dump_cb_t *cb, void *data)
2896 {
2897 struct mv88e6xxx_chip *chip = ds->priv;
2898 int err;
2899
2900 mv88e6xxx_reg_lock(chip);
2901 err = mv88e6xxx_port_db_dump(chip, port, cb, data);
2902 mv88e6xxx_reg_unlock(chip);
2903
2904 return err;
2905 }
2906
mv88e6xxx_bridge_map(struct mv88e6xxx_chip * chip,struct dsa_bridge bridge)2907 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
2908 struct dsa_bridge bridge)
2909 {
2910 struct dsa_switch *ds = chip->ds;
2911 struct dsa_switch_tree *dst = ds->dst;
2912 struct dsa_port *dp;
2913 int err;
2914
2915 list_for_each_entry(dp, &dst->ports, list) {
2916 if (dsa_port_offloads_bridge(dp, &bridge)) {
2917 if (dp->ds == ds) {
2918 /* This is a local bridge group member,
2919 * remap its Port VLAN Map.
2920 */
2921 err = mv88e6xxx_port_vlan_map(chip, dp->index);
2922 if (err)
2923 return err;
2924 } else {
2925 /* This is an external bridge group member,
2926 * remap its cross-chip Port VLAN Table entry.
2927 */
2928 err = mv88e6xxx_pvt_map(chip, dp->ds->index,
2929 dp->index);
2930 if (err)
2931 return err;
2932 }
2933 }
2934 }
2935
2936 return 0;
2937 }
2938
2939 /* Treat the software bridge as a virtual single-port switch behind the
2940 * CPU and map in the PVT. First dst->last_switch elements are taken by
2941 * physical switches, so start from beyond that range.
2942 */
mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch * ds,unsigned int bridge_num)2943 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds,
2944 unsigned int bridge_num)
2945 {
2946 u8 dev = bridge_num + ds->dst->last_switch;
2947 struct mv88e6xxx_chip *chip = ds->priv;
2948
2949 return mv88e6xxx_pvt_map(chip, dev, 0);
2950 }
2951
mv88e6xxx_port_bridge_join(struct dsa_switch * ds,int port,struct dsa_bridge bridge,bool * tx_fwd_offload,struct netlink_ext_ack * extack)2952 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2953 struct dsa_bridge bridge,
2954 bool *tx_fwd_offload,
2955 struct netlink_ext_ack *extack)
2956 {
2957 struct mv88e6xxx_chip *chip = ds->priv;
2958 int err;
2959
2960 mv88e6xxx_reg_lock(chip);
2961
2962 err = mv88e6xxx_bridge_map(chip, bridge);
2963 if (err)
2964 goto unlock;
2965
2966 err = mv88e6xxx_port_set_map_da(chip, port, true);
2967 if (err)
2968 goto unlock;
2969
2970 err = mv88e6xxx_port_commit_pvid(chip, port);
2971 if (err)
2972 goto unlock;
2973
2974 if (mv88e6xxx_has_pvt(chip)) {
2975 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num);
2976 if (err)
2977 goto unlock;
2978
2979 *tx_fwd_offload = true;
2980 }
2981
2982 unlock:
2983 mv88e6xxx_reg_unlock(chip);
2984
2985 return err;
2986 }
2987
mv88e6xxx_port_bridge_leave(struct dsa_switch * ds,int port,struct dsa_bridge bridge)2988 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
2989 struct dsa_bridge bridge)
2990 {
2991 struct mv88e6xxx_chip *chip = ds->priv;
2992 int err;
2993
2994 mv88e6xxx_reg_lock(chip);
2995
2996 if (bridge.tx_fwd_offload &&
2997 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num))
2998 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
2999
3000 if (mv88e6xxx_bridge_map(chip, bridge) ||
3001 mv88e6xxx_port_vlan_map(chip, port))
3002 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
3003
3004 err = mv88e6xxx_port_set_map_da(chip, port, false);
3005 if (err)
3006 dev_err(ds->dev,
3007 "port %d failed to restore map-DA: %pe\n",
3008 port, ERR_PTR(err));
3009
3010 err = mv88e6xxx_port_commit_pvid(chip, port);
3011 if (err)
3012 dev_err(ds->dev,
3013 "port %d failed to restore standalone pvid: %pe\n",
3014 port, ERR_PTR(err));
3015
3016 mv88e6xxx_reg_unlock(chip);
3017 }
3018
mv88e6xxx_crosschip_bridge_join(struct dsa_switch * ds,int tree_index,int sw_index,int port,struct dsa_bridge bridge,struct netlink_ext_ack * extack)3019 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds,
3020 int tree_index, int sw_index,
3021 int port, struct dsa_bridge bridge,
3022 struct netlink_ext_ack *extack)
3023 {
3024 struct mv88e6xxx_chip *chip = ds->priv;
3025 int err;
3026
3027 if (tree_index != ds->dst->index)
3028 return 0;
3029
3030 mv88e6xxx_reg_lock(chip);
3031 err = mv88e6xxx_pvt_map(chip, sw_index, port);
3032 err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num);
3033 mv88e6xxx_reg_unlock(chip);
3034
3035 return err;
3036 }
3037
mv88e6xxx_crosschip_bridge_leave(struct dsa_switch * ds,int tree_index,int sw_index,int port,struct dsa_bridge bridge)3038 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds,
3039 int tree_index, int sw_index,
3040 int port, struct dsa_bridge bridge)
3041 {
3042 struct mv88e6xxx_chip *chip = ds->priv;
3043
3044 if (tree_index != ds->dst->index)
3045 return;
3046
3047 mv88e6xxx_reg_lock(chip);
3048 if (mv88e6xxx_pvt_map(chip, sw_index, port) ||
3049 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num))
3050 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
3051 mv88e6xxx_reg_unlock(chip);
3052 }
3053
mv88e6xxx_software_reset(struct mv88e6xxx_chip * chip)3054 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
3055 {
3056 if (chip->info->ops->reset)
3057 return chip->info->ops->reset(chip);
3058
3059 return 0;
3060 }
3061
mv88e6xxx_hardware_reset(struct mv88e6xxx_chip * chip)3062 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
3063 {
3064 struct gpio_desc *gpiod = chip->reset;
3065 int err;
3066
3067 /* If there is a GPIO connected to the reset pin, toggle it */
3068 if (gpiod) {
3069 /* If the switch has just been reset and not yet completed
3070 * loading EEPROM, the reset may interrupt the I2C transaction
3071 * mid-byte, causing the first EEPROM read after the reset
3072 * from the wrong location resulting in the switch booting
3073 * to wrong mode and inoperable.
3074 * For this reason, switch families with EEPROM support
3075 * generally wait for EEPROM loads to complete as their pre-
3076 * and post-reset handlers.
3077 */
3078 if (chip->info->ops->hardware_reset_pre) {
3079 err = chip->info->ops->hardware_reset_pre(chip);
3080 if (err)
3081 dev_err(chip->dev, "pre-reset error: %d\n", err);
3082 }
3083
3084 gpiod_set_value_cansleep(gpiod, 1);
3085 usleep_range(10000, 20000);
3086 gpiod_set_value_cansleep(gpiod, 0);
3087 usleep_range(10000, 20000);
3088
3089 if (chip->info->ops->hardware_reset_post) {
3090 err = chip->info->ops->hardware_reset_post(chip);
3091 if (err)
3092 dev_err(chip->dev, "post-reset error: %d\n", err);
3093 }
3094 }
3095 }
3096
mv88e6xxx_disable_ports(struct mv88e6xxx_chip * chip)3097 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
3098 {
3099 int i, err;
3100
3101 /* Set all ports to the Disabled state */
3102 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3103 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
3104 if (err)
3105 return err;
3106 }
3107
3108 /* Wait for transmit queues to drain,
3109 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
3110 */
3111 usleep_range(2000, 4000);
3112
3113 return 0;
3114 }
3115
mv88e6xxx_switch_reset(struct mv88e6xxx_chip * chip)3116 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
3117 {
3118 int err;
3119
3120 err = mv88e6xxx_disable_ports(chip);
3121 if (err)
3122 return err;
3123
3124 mv88e6xxx_hardware_reset(chip);
3125
3126 return mv88e6xxx_software_reset(chip);
3127 }
3128
mv88e6xxx_set_port_mode(struct mv88e6xxx_chip * chip,int port,enum mv88e6xxx_frame_mode frame,enum mv88e6xxx_egress_mode egress,u16 etype)3129 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
3130 enum mv88e6xxx_frame_mode frame,
3131 enum mv88e6xxx_egress_mode egress, u16 etype)
3132 {
3133 int err;
3134
3135 if (!chip->info->ops->port_set_frame_mode)
3136 return -EOPNOTSUPP;
3137
3138 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
3139 if (err)
3140 return err;
3141
3142 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
3143 if (err)
3144 return err;
3145
3146 if (chip->info->ops->port_set_ether_type)
3147 return chip->info->ops->port_set_ether_type(chip, port, etype);
3148
3149 return 0;
3150 }
3151
mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip * chip,int port)3152 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
3153 {
3154 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
3155 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
3156 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
3157 }
3158
mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip * chip,int port)3159 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
3160 {
3161 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
3162 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
3163 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
3164 }
3165
mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip * chip,int port)3166 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
3167 {
3168 return mv88e6xxx_set_port_mode(chip, port,
3169 MV88E6XXX_FRAME_MODE_ETHERTYPE,
3170 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
3171 ETH_P_EDSA);
3172 }
3173
mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip * chip,int port)3174 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
3175 {
3176 if (dsa_is_dsa_port(chip->ds, port))
3177 return mv88e6xxx_set_port_mode_dsa(chip, port);
3178
3179 if (dsa_is_user_port(chip->ds, port))
3180 return mv88e6xxx_set_port_mode_normal(chip, port);
3181
3182 /* Setup CPU port mode depending on its supported tag format */
3183 if (chip->tag_protocol == DSA_TAG_PROTO_DSA)
3184 return mv88e6xxx_set_port_mode_dsa(chip, port);
3185
3186 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA)
3187 return mv88e6xxx_set_port_mode_edsa(chip, port);
3188
3189 return -EINVAL;
3190 }
3191
mv88e6xxx_setup_message_port(struct mv88e6xxx_chip * chip,int port)3192 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
3193 {
3194 bool message = dsa_is_dsa_port(chip->ds, port);
3195
3196 return mv88e6xxx_port_set_message_port(chip, port, message);
3197 }
3198
mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip * chip,int port)3199 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
3200 {
3201 int err;
3202
3203 if (chip->info->ops->port_set_ucast_flood) {
3204 err = chip->info->ops->port_set_ucast_flood(chip, port, true);
3205 if (err)
3206 return err;
3207 }
3208 if (chip->info->ops->port_set_mcast_flood) {
3209 err = chip->info->ops->port_set_mcast_flood(chip, port, true);
3210 if (err)
3211 return err;
3212 }
3213
3214 return 0;
3215 }
3216
mv88e6xxx_set_egress_port(struct mv88e6xxx_chip * chip,enum mv88e6xxx_egress_direction direction,int port)3217 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip,
3218 enum mv88e6xxx_egress_direction direction,
3219 int port)
3220 {
3221 int err;
3222
3223 if (!chip->info->ops->set_egress_port)
3224 return -EOPNOTSUPP;
3225
3226 err = chip->info->ops->set_egress_port(chip, direction, port);
3227 if (err)
3228 return err;
3229
3230 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS)
3231 chip->ingress_dest_port = port;
3232 else
3233 chip->egress_dest_port = port;
3234
3235 return 0;
3236 }
3237
mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip * chip,int port)3238 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
3239 {
3240 struct dsa_switch *ds = chip->ds;
3241 int upstream_port;
3242 int err;
3243
3244 upstream_port = dsa_upstream_port(ds, port);
3245 if (chip->info->ops->port_set_upstream_port) {
3246 err = chip->info->ops->port_set_upstream_port(chip, port,
3247 upstream_port);
3248 if (err)
3249 return err;
3250 }
3251
3252 if (port == upstream_port) {
3253 if (chip->info->ops->set_cpu_port) {
3254 err = chip->info->ops->set_cpu_port(chip,
3255 upstream_port);
3256 if (err)
3257 return err;
3258 }
3259
3260 err = mv88e6xxx_set_egress_port(chip,
3261 MV88E6XXX_EGRESS_DIR_INGRESS,
3262 upstream_port);
3263 if (err && err != -EOPNOTSUPP)
3264 return err;
3265
3266 err = mv88e6xxx_set_egress_port(chip,
3267 MV88E6XXX_EGRESS_DIR_EGRESS,
3268 upstream_port);
3269 if (err && err != -EOPNOTSUPP)
3270 return err;
3271 }
3272
3273 return 0;
3274 }
3275
mv88e6xxx_setup_port(struct mv88e6xxx_chip * chip,int port)3276 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
3277 {
3278 struct device_node *phy_handle = NULL;
3279 struct dsa_switch *ds = chip->ds;
3280 struct dsa_port *dp;
3281 int tx_amp;
3282 int err;
3283 u16 reg;
3284
3285 chip->ports[port].chip = chip;
3286 chip->ports[port].port = port;
3287
3288 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
3289 SPEED_UNFORCED, DUPLEX_UNFORCED,
3290 PAUSE_ON, PHY_INTERFACE_MODE_NA);
3291 if (err)
3292 return err;
3293
3294 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
3295 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
3296 * tunneling, determine priority by looking at 802.1p and IP
3297 * priority fields (IP prio has precedence), and set STP state
3298 * to Forwarding.
3299 *
3300 * If this is the CPU link, use DSA or EDSA tagging depending
3301 * on which tagging mode was configured.
3302 *
3303 * If this is a link to another switch, use DSA tagging mode.
3304 *
3305 * If this is the upstream port for this switch, enable
3306 * forwarding of unknown unicasts and multicasts.
3307 */
3308 reg = MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
3309 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
3310 /* Forward any IPv4 IGMP or IPv6 MLD frames received
3311 * by a USER port to the CPU port to allow snooping.
3312 */
3313 if (dsa_is_user_port(ds, port))
3314 reg |= MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP;
3315
3316 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
3317 if (err)
3318 return err;
3319
3320 err = mv88e6xxx_setup_port_mode(chip, port);
3321 if (err)
3322 return err;
3323
3324 err = mv88e6xxx_setup_egress_floods(chip, port);
3325 if (err)
3326 return err;
3327
3328 /* Port Control 2: don't force a good FCS, set the MTU size to
3329 * 10222 bytes, disable 802.1q tags checking, don't discard
3330 * tagged or untagged frames on this port, skip destination
3331 * address lookup on user ports, disable ARP mirroring and don't
3332 * send a copy of all transmitted/received frames on this port
3333 * to the CPU.
3334 */
3335 err = mv88e6xxx_port_set_map_da(chip, port, !dsa_is_user_port(ds, port));
3336 if (err)
3337 return err;
3338
3339 err = mv88e6xxx_setup_upstream_port(chip, port);
3340 if (err)
3341 return err;
3342
3343 /* On chips that support it, set all downstream DSA ports'
3344 * VLAN policy to TRAP. In combination with loading
3345 * MV88E6XXX_VID_STANDALONE as a policy entry in the VTU, this
3346 * provides a better isolation barrier between standalone
3347 * ports, as the ATU is bypassed on any intermediate switches
3348 * between the incoming port and the CPU.
3349 */
3350 if (dsa_is_downstream_port(ds, port) &&
3351 chip->info->ops->port_set_policy) {
3352 err = chip->info->ops->port_set_policy(chip, port,
3353 MV88E6XXX_POLICY_MAPPING_VTU,
3354 MV88E6XXX_POLICY_ACTION_TRAP);
3355 if (err)
3356 return err;
3357 }
3358
3359 /* User ports start out in standalone mode and 802.1Q is
3360 * therefore disabled. On DSA ports, all valid VIDs are always
3361 * loaded in the VTU - therefore, enable 802.1Q in order to take
3362 * advantage of VLAN policy on chips that supports it.
3363 */
3364 err = mv88e6xxx_port_set_8021q_mode(chip, port,
3365 dsa_is_user_port(ds, port) ?
3366 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED :
3367 MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE);
3368 if (err)
3369 return err;
3370
3371 /* Bind MV88E6XXX_VID_STANDALONE to MV88E6XXX_FID_STANDALONE by
3372 * virtue of the fact that mv88e6xxx_atu_new() will pick it as
3373 * the first free FID. This will be used as the private PVID for
3374 * unbridged ports. Shared (DSA and CPU) ports must also be
3375 * members of this VID, in order to trap all frames assigned to
3376 * it to the CPU.
3377 */
3378 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_STANDALONE,
3379 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED,
3380 false);
3381 if (err)
3382 return err;
3383
3384 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the
3385 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as
3386 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used
3387 * as the private PVID on ports under a VLAN-unaware bridge.
3388 * Shared (DSA and CPU) ports must also be members of it, to translate
3389 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of
3390 * relying on their port default FID.
3391 */
3392 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED,
3393 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED,
3394 false);
3395 if (err)
3396 return err;
3397
3398 if (chip->info->ops->port_set_jumbo_size) {
3399 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218);
3400 if (err)
3401 return err;
3402 }
3403
3404 /* Port Association Vector: disable automatic address learning
3405 * on all user ports since they start out in standalone
3406 * mode. When joining a bridge, learning will be configured to
3407 * match the bridge port settings. Enable learning on all
3408 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the
3409 * learning process.
3410 *
3411 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData,
3412 * and RefreshLocked. I.e. setup standard automatic learning.
3413 */
3414 if (dsa_is_user_port(ds, port))
3415 reg = 0;
3416 else
3417 reg = 1 << port;
3418
3419 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
3420 reg);
3421 if (err)
3422 return err;
3423
3424 /* Egress rate control 2: disable egress rate control. */
3425 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
3426 0x0000);
3427 if (err)
3428 return err;
3429
3430 if (chip->info->ops->port_pause_limit) {
3431 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
3432 if (err)
3433 return err;
3434 }
3435
3436 if (chip->info->ops->port_disable_learn_limit) {
3437 err = chip->info->ops->port_disable_learn_limit(chip, port);
3438 if (err)
3439 return err;
3440 }
3441
3442 if (chip->info->ops->port_disable_pri_override) {
3443 err = chip->info->ops->port_disable_pri_override(chip, port);
3444 if (err)
3445 return err;
3446 }
3447
3448 if (chip->info->ops->port_tag_remap) {
3449 err = chip->info->ops->port_tag_remap(chip, port);
3450 if (err)
3451 return err;
3452 }
3453
3454 if (chip->info->ops->port_egress_rate_limiting) {
3455 err = chip->info->ops->port_egress_rate_limiting(chip, port);
3456 if (err)
3457 return err;
3458 }
3459
3460 if (chip->info->ops->port_setup_message_port) {
3461 err = chip->info->ops->port_setup_message_port(chip, port);
3462 if (err)
3463 return err;
3464 }
3465
3466 if (chip->info->ops->serdes_set_tx_amplitude) {
3467 dp = dsa_to_port(ds, port);
3468 if (dp)
3469 phy_handle = of_parse_phandle(dp->dn, "phy-handle", 0);
3470
3471 if (phy_handle && !of_property_read_u32(phy_handle,
3472 "tx-p2p-microvolt",
3473 &tx_amp))
3474 err = chip->info->ops->serdes_set_tx_amplitude(chip,
3475 port, tx_amp);
3476 if (phy_handle) {
3477 of_node_put(phy_handle);
3478 if (err)
3479 return err;
3480 }
3481 }
3482
3483 /* Port based VLAN map: give each port the same default address
3484 * database, and allow bidirectional communication between the
3485 * CPU and DSA port(s), and the other ports.
3486 */
3487 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE);
3488 if (err)
3489 return err;
3490
3491 err = mv88e6xxx_port_vlan_map(chip, port);
3492 if (err)
3493 return err;
3494
3495 /* Default VLAN ID and priority: don't set a default VLAN
3496 * ID, and set the default packet priority to zero.
3497 */
3498 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
3499 }
3500
mv88e6xxx_get_max_mtu(struct dsa_switch * ds,int port)3501 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port)
3502 {
3503 struct mv88e6xxx_chip *chip = ds->priv;
3504
3505 if (chip->info->ops->port_set_jumbo_size)
3506 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
3507 else if (chip->info->ops->set_max_frame_size)
3508 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
3509 return ETH_DATA_LEN;
3510 }
3511
mv88e6xxx_change_mtu(struct dsa_switch * ds,int port,int new_mtu)3512 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
3513 {
3514 struct mv88e6xxx_chip *chip = ds->priv;
3515 int ret = 0;
3516
3517 /* For families where we don't know how to alter the MTU,
3518 * just accept any value up to ETH_DATA_LEN
3519 */
3520 if (!chip->info->ops->port_set_jumbo_size &&
3521 !chip->info->ops->set_max_frame_size) {
3522 if (new_mtu > ETH_DATA_LEN)
3523 return -EINVAL;
3524
3525 return 0;
3526 }
3527
3528 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
3529 new_mtu += EDSA_HLEN;
3530
3531 mv88e6xxx_reg_lock(chip);
3532 if (chip->info->ops->port_set_jumbo_size)
3533 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu);
3534 else if (chip->info->ops->set_max_frame_size &&
3535 dsa_is_cpu_port(ds, port))
3536 ret = chip->info->ops->set_max_frame_size(chip, new_mtu);
3537 mv88e6xxx_reg_unlock(chip);
3538
3539 return ret;
3540 }
3541
mv88e6xxx_set_ageing_time(struct dsa_switch * ds,unsigned int ageing_time)3542 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
3543 unsigned int ageing_time)
3544 {
3545 struct mv88e6xxx_chip *chip = ds->priv;
3546 int err;
3547
3548 mv88e6xxx_reg_lock(chip);
3549 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
3550 mv88e6xxx_reg_unlock(chip);
3551
3552 return err;
3553 }
3554
mv88e6xxx_stats_setup(struct mv88e6xxx_chip * chip)3555 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
3556 {
3557 int err;
3558
3559 /* Initialize the statistics unit */
3560 if (chip->info->ops->stats_set_histogram) {
3561 err = chip->info->ops->stats_set_histogram(chip);
3562 if (err)
3563 return err;
3564 }
3565
3566 return mv88e6xxx_g1_stats_clear(chip);
3567 }
3568
mv88e6320_setup_errata(struct mv88e6xxx_chip * chip)3569 static int mv88e6320_setup_errata(struct mv88e6xxx_chip *chip)
3570 {
3571 u16 dummy;
3572 int err;
3573
3574 /* Workaround for erratum
3575 * 3.3 RGMII timing may be out of spec when transmit delay is enabled
3576 */
3577 err = mv88e6xxx_port_hidden_write(chip, 0, 0xf, 0x7, 0xe000);
3578 if (err)
3579 return err;
3580
3581 return mv88e6xxx_port_hidden_read(chip, 0, 0xf, 0x7, &dummy);
3582 }
3583
3584 /* Check if the errata has already been applied. */
mv88e6390_setup_errata_applied(struct mv88e6xxx_chip * chip)3585 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
3586 {
3587 int port;
3588 int err;
3589 u16 val;
3590
3591 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3592 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val);
3593 if (err) {
3594 dev_err(chip->dev,
3595 "Error reading hidden register: %d\n", err);
3596 return false;
3597 }
3598 if (val != 0x01c0)
3599 return false;
3600 }
3601
3602 return true;
3603 }
3604
3605 /* The 6390 copper ports have an errata which require poking magic
3606 * values into undocumented hidden registers and then performing a
3607 * software reset.
3608 */
mv88e6390_setup_errata(struct mv88e6xxx_chip * chip)3609 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
3610 {
3611 int port;
3612 int err;
3613
3614 if (mv88e6390_setup_errata_applied(chip))
3615 return 0;
3616
3617 /* Set the ports into blocking mode */
3618 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3619 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
3620 if (err)
3621 return err;
3622 }
3623
3624 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3625 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0);
3626 if (err)
3627 return err;
3628 }
3629
3630 return mv88e6xxx_software_reset(chip);
3631 }
3632
3633 /* prod_id for switch families which do not have a PHY model number */
3634 static const u16 family_prod_id_table[] = {
3635 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
3636 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
3637 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
3638 };
3639
mv88e6xxx_mdio_read(struct mii_bus * bus,int phy,int reg)3640 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
3641 {
3642 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3643 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3644 u16 prod_id;
3645 u16 val;
3646 int err;
3647
3648 if (!chip->info->ops->phy_read)
3649 return -EOPNOTSUPP;
3650
3651 mv88e6xxx_reg_lock(chip);
3652 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
3653 mv88e6xxx_reg_unlock(chip);
3654
3655 /* Some internal PHYs don't have a model number. */
3656 if (reg == MII_PHYSID2 && !(val & 0x3f0) &&
3657 chip->info->family < ARRAY_SIZE(family_prod_id_table)) {
3658 prod_id = family_prod_id_table[chip->info->family];
3659 if (prod_id)
3660 val |= prod_id >> 4;
3661 }
3662
3663 return err ? err : val;
3664 }
3665
mv88e6xxx_mdio_read_c45(struct mii_bus * bus,int phy,int devad,int reg)3666 static int mv88e6xxx_mdio_read_c45(struct mii_bus *bus, int phy, int devad,
3667 int reg)
3668 {
3669 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3670 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3671 u16 val;
3672 int err;
3673
3674 if (!chip->info->ops->phy_read_c45)
3675 return 0xffff;
3676
3677 mv88e6xxx_reg_lock(chip);
3678 err = chip->info->ops->phy_read_c45(chip, bus, phy, devad, reg, &val);
3679 mv88e6xxx_reg_unlock(chip);
3680
3681 return err ? err : val;
3682 }
3683
mv88e6xxx_mdio_write(struct mii_bus * bus,int phy,int reg,u16 val)3684 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
3685 {
3686 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3687 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3688 int err;
3689
3690 if (!chip->info->ops->phy_write)
3691 return -EOPNOTSUPP;
3692
3693 mv88e6xxx_reg_lock(chip);
3694 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
3695 mv88e6xxx_reg_unlock(chip);
3696
3697 return err;
3698 }
3699
mv88e6xxx_mdio_write_c45(struct mii_bus * bus,int phy,int devad,int reg,u16 val)3700 static int mv88e6xxx_mdio_write_c45(struct mii_bus *bus, int phy, int devad,
3701 int reg, u16 val)
3702 {
3703 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3704 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3705 int err;
3706
3707 if (!chip->info->ops->phy_write_c45)
3708 return -EOPNOTSUPP;
3709
3710 mv88e6xxx_reg_lock(chip);
3711 err = chip->info->ops->phy_write_c45(chip, bus, phy, devad, reg, val);
3712 mv88e6xxx_reg_unlock(chip);
3713
3714 return err;
3715 }
3716
mv88e6xxx_mdio_register(struct mv88e6xxx_chip * chip,struct device_node * np,bool external)3717 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
3718 struct device_node *np,
3719 bool external)
3720 {
3721 static int index;
3722 struct mv88e6xxx_mdio_bus *mdio_bus;
3723 struct mii_bus *bus;
3724 int err;
3725
3726 if (external) {
3727 mv88e6xxx_reg_lock(chip);
3728 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
3729 mv88e6xxx_reg_unlock(chip);
3730
3731 if (err)
3732 return err;
3733 }
3734
3735 bus = mdiobus_alloc_size(sizeof(*mdio_bus));
3736 if (!bus)
3737 return -ENOMEM;
3738
3739 mdio_bus = bus->priv;
3740 mdio_bus->bus = bus;
3741 mdio_bus->chip = chip;
3742 INIT_LIST_HEAD(&mdio_bus->list);
3743 mdio_bus->external = external;
3744
3745 if (np) {
3746 bus->name = np->full_name;
3747 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
3748 } else {
3749 bus->name = "mv88e6xxx SMI";
3750 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3751 }
3752
3753 bus->read = mv88e6xxx_mdio_read;
3754 bus->write = mv88e6xxx_mdio_write;
3755 bus->read_c45 = mv88e6xxx_mdio_read_c45;
3756 bus->write_c45 = mv88e6xxx_mdio_write_c45;
3757 bus->parent = chip->dev;
3758 bus->phy_mask = ~GENMASK(chip->info->phy_base_addr +
3759 mv88e6xxx_num_ports(chip) - 1,
3760 chip->info->phy_base_addr);
3761
3762 if (!external) {
3763 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
3764 if (err)
3765 goto out;
3766 }
3767
3768 err = of_mdiobus_register(bus, np);
3769 if (err) {
3770 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
3771 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3772 goto out;
3773 }
3774
3775 if (external)
3776 list_add_tail(&mdio_bus->list, &chip->mdios);
3777 else
3778 list_add(&mdio_bus->list, &chip->mdios);
3779
3780 return 0;
3781
3782 out:
3783 mdiobus_free(bus);
3784 return err;
3785 }
3786
mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip * chip)3787 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
3788
3789 {
3790 struct mv88e6xxx_mdio_bus *mdio_bus, *p;
3791 struct mii_bus *bus;
3792
3793 list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) {
3794 bus = mdio_bus->bus;
3795
3796 if (!mdio_bus->external)
3797 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3798
3799 mdiobus_unregister(bus);
3800 mdiobus_free(bus);
3801 }
3802 }
3803
mv88e6xxx_mdios_register(struct mv88e6xxx_chip * chip)3804 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip)
3805 {
3806 struct device_node *np = chip->dev->of_node;
3807 struct device_node *child;
3808 int err;
3809
3810 /* Always register one mdio bus for the internal/default mdio
3811 * bus. This maybe represented in the device tree, but is
3812 * optional.
3813 */
3814 child = of_get_child_by_name(np, "mdio");
3815 err = mv88e6xxx_mdio_register(chip, child, false);
3816 of_node_put(child);
3817 if (err)
3818 return err;
3819
3820 /* Walk the device tree, and see if there are any other nodes
3821 * which say they are compatible with the external mdio
3822 * bus.
3823 */
3824 for_each_available_child_of_node(np, child) {
3825 if (of_device_is_compatible(
3826 child, "marvell,mv88e6xxx-mdio-external")) {
3827 err = mv88e6xxx_mdio_register(chip, child, true);
3828 if (err) {
3829 mv88e6xxx_mdios_unregister(chip);
3830 of_node_put(child);
3831 return err;
3832 }
3833 }
3834 }
3835
3836 return 0;
3837 }
3838
mv88e6xxx_teardown(struct dsa_switch * ds)3839 static void mv88e6xxx_teardown(struct dsa_switch *ds)
3840 {
3841 struct mv88e6xxx_chip *chip = ds->priv;
3842
3843 mv88e6xxx_teardown_devlink_params(ds);
3844 dsa_devlink_resources_unregister(ds);
3845 mv88e6xxx_teardown_devlink_regions_global(ds);
3846 mv88e6xxx_mdios_unregister(chip);
3847 }
3848
mv88e6xxx_setup(struct dsa_switch * ds)3849 static int mv88e6xxx_setup(struct dsa_switch *ds)
3850 {
3851 struct mv88e6xxx_chip *chip = ds->priv;
3852 u8 cmode;
3853 int err;
3854 int i;
3855
3856 err = mv88e6xxx_mdios_register(chip);
3857 if (err)
3858 return err;
3859
3860 chip->ds = ds;
3861 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
3862
3863 /* Since virtual bridges are mapped in the PVT, the number we support
3864 * depends on the physical switch topology. We need to let DSA figure
3865 * that out and therefore we cannot set this at dsa_register_switch()
3866 * time.
3867 */
3868 if (mv88e6xxx_has_pvt(chip))
3869 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES -
3870 ds->dst->last_switch - 1;
3871
3872 mv88e6xxx_reg_lock(chip);
3873
3874 if (chip->info->ops->setup_errata) {
3875 err = chip->info->ops->setup_errata(chip);
3876 if (err)
3877 goto unlock;
3878 }
3879
3880 /* Cache the cmode of each port. */
3881 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3882 if (chip->info->ops->port_get_cmode) {
3883 err = chip->info->ops->port_get_cmode(chip, i, &cmode);
3884 if (err)
3885 goto unlock;
3886
3887 chip->ports[i].cmode = cmode;
3888 }
3889 }
3890
3891 err = mv88e6xxx_vtu_setup(chip);
3892 if (err)
3893 goto unlock;
3894
3895 /* Must be called after mv88e6xxx_vtu_setup (which flushes the
3896 * VTU, thereby also flushing the STU).
3897 */
3898 err = mv88e6xxx_stu_setup(chip);
3899 if (err)
3900 goto unlock;
3901
3902 /* Setup Switch Port Registers */
3903 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3904 if (dsa_is_unused_port(ds, i))
3905 continue;
3906
3907 /* Prevent the use of an invalid port. */
3908 if (mv88e6xxx_is_invalid_port(chip, i)) {
3909 dev_err(chip->dev, "port %d is invalid\n", i);
3910 err = -EINVAL;
3911 goto unlock;
3912 }
3913
3914 err = mv88e6xxx_setup_port(chip, i);
3915 if (err)
3916 goto unlock;
3917 }
3918
3919 err = mv88e6xxx_irl_setup(chip);
3920 if (err)
3921 goto unlock;
3922
3923 err = mv88e6xxx_mac_setup(chip);
3924 if (err)
3925 goto unlock;
3926
3927 err = mv88e6xxx_phy_setup(chip);
3928 if (err)
3929 goto unlock;
3930
3931 err = mv88e6xxx_pvt_setup(chip);
3932 if (err)
3933 goto unlock;
3934
3935 err = mv88e6xxx_atu_setup(chip);
3936 if (err)
3937 goto unlock;
3938
3939 err = mv88e6xxx_broadcast_setup(chip, 0);
3940 if (err)
3941 goto unlock;
3942
3943 err = mv88e6xxx_pot_setup(chip);
3944 if (err)
3945 goto unlock;
3946
3947 err = mv88e6xxx_rmu_setup(chip);
3948 if (err)
3949 goto unlock;
3950
3951 err = mv88e6xxx_rsvd2cpu_setup(chip);
3952 if (err)
3953 goto unlock;
3954
3955 err = mv88e6xxx_trunk_setup(chip);
3956 if (err)
3957 goto unlock;
3958
3959 err = mv88e6xxx_devmap_setup(chip);
3960 if (err)
3961 goto unlock;
3962
3963 err = mv88e6xxx_pri_setup(chip);
3964 if (err)
3965 goto unlock;
3966
3967 /* Setup PTP Hardware Clock and timestamping */
3968 if (chip->info->ptp_support) {
3969 err = mv88e6xxx_ptp_setup(chip);
3970 if (err)
3971 goto unlock;
3972
3973 err = mv88e6xxx_hwtstamp_setup(chip);
3974 if (err)
3975 goto unlock;
3976 }
3977
3978 err = mv88e6xxx_stats_setup(chip);
3979 if (err)
3980 goto unlock;
3981
3982 unlock:
3983 mv88e6xxx_reg_unlock(chip);
3984
3985 if (err)
3986 goto out_mdios;
3987
3988 /* Have to be called without holding the register lock, since
3989 * they take the devlink lock, and we later take the locks in
3990 * the reverse order when getting/setting parameters or
3991 * resource occupancy.
3992 */
3993 err = mv88e6xxx_setup_devlink_resources(ds);
3994 if (err)
3995 goto out_mdios;
3996
3997 err = mv88e6xxx_setup_devlink_params(ds);
3998 if (err)
3999 goto out_resources;
4000
4001 err = mv88e6xxx_setup_devlink_regions_global(ds);
4002 if (err)
4003 goto out_params;
4004
4005 return 0;
4006
4007 out_params:
4008 mv88e6xxx_teardown_devlink_params(ds);
4009 out_resources:
4010 dsa_devlink_resources_unregister(ds);
4011 out_mdios:
4012 mv88e6xxx_mdios_unregister(chip);
4013
4014 return err;
4015 }
4016
mv88e6xxx_port_setup(struct dsa_switch * ds,int port)4017 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port)
4018 {
4019 struct mv88e6xxx_chip *chip = ds->priv;
4020 int err;
4021
4022 if (chip->info->ops->pcs_ops &&
4023 chip->info->ops->pcs_ops->pcs_init) {
4024 err = chip->info->ops->pcs_ops->pcs_init(chip, port);
4025 if (err)
4026 return err;
4027 }
4028
4029 return mv88e6xxx_setup_devlink_regions_port(ds, port);
4030 }
4031
mv88e6xxx_port_teardown(struct dsa_switch * ds,int port)4032 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port)
4033 {
4034 struct mv88e6xxx_chip *chip = ds->priv;
4035
4036 mv88e6xxx_teardown_devlink_regions_port(ds, port);
4037
4038 if (chip->info->ops->pcs_ops &&
4039 chip->info->ops->pcs_ops->pcs_teardown)
4040 chip->info->ops->pcs_ops->pcs_teardown(chip, port);
4041 }
4042
mv88e6xxx_get_eeprom_len(struct dsa_switch * ds)4043 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
4044 {
4045 struct mv88e6xxx_chip *chip = ds->priv;
4046
4047 return chip->eeprom_len;
4048 }
4049
mv88e6xxx_get_eeprom(struct dsa_switch * ds,struct ethtool_eeprom * eeprom,u8 * data)4050 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
4051 struct ethtool_eeprom *eeprom, u8 *data)
4052 {
4053 struct mv88e6xxx_chip *chip = ds->priv;
4054 int err;
4055
4056 if (!chip->info->ops->get_eeprom)
4057 return -EOPNOTSUPP;
4058
4059 mv88e6xxx_reg_lock(chip);
4060 err = chip->info->ops->get_eeprom(chip, eeprom, data);
4061 mv88e6xxx_reg_unlock(chip);
4062
4063 if (err)
4064 return err;
4065
4066 eeprom->magic = 0xc3ec4951;
4067
4068 return 0;
4069 }
4070
mv88e6xxx_set_eeprom(struct dsa_switch * ds,struct ethtool_eeprom * eeprom,u8 * data)4071 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
4072 struct ethtool_eeprom *eeprom, u8 *data)
4073 {
4074 struct mv88e6xxx_chip *chip = ds->priv;
4075 int err;
4076
4077 if (!chip->info->ops->set_eeprom)
4078 return -EOPNOTSUPP;
4079
4080 if (eeprom->magic != 0xc3ec4951)
4081 return -EINVAL;
4082
4083 mv88e6xxx_reg_lock(chip);
4084 err = chip->info->ops->set_eeprom(chip, eeprom, data);
4085 mv88e6xxx_reg_unlock(chip);
4086
4087 return err;
4088 }
4089
4090 static const struct mv88e6xxx_ops mv88e6085_ops = {
4091 /* MV88E6XXX_FAMILY_6097 */
4092 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4093 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4094 .irl_init_all = mv88e6352_g2_irl_init_all,
4095 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4096 .phy_read = mv88e6185_phy_ppu_read,
4097 .phy_write = mv88e6185_phy_ppu_write,
4098 .port_set_link = mv88e6xxx_port_set_link,
4099 .port_sync_link = mv88e6xxx_port_sync_link,
4100 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4101 .port_tag_remap = mv88e6095_port_tag_remap,
4102 .port_set_policy = mv88e6352_port_set_policy,
4103 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4104 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4105 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4106 .port_set_ether_type = mv88e6351_port_set_ether_type,
4107 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4108 .port_pause_limit = mv88e6097_port_pause_limit,
4109 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4110 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4111 .port_get_cmode = mv88e6185_port_get_cmode,
4112 .port_setup_message_port = mv88e6xxx_setup_message_port,
4113 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4114 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4115 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4116 .stats_get_strings = mv88e6095_stats_get_strings,
4117 .stats_get_stats = mv88e6095_stats_get_stats,
4118 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4119 .set_egress_port = mv88e6095_g1_set_egress_port,
4120 .watchdog_ops = &mv88e6097_watchdog_ops,
4121 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4122 .pot_clear = mv88e6xxx_g2_pot_clear,
4123 .ppu_enable = mv88e6185_g1_ppu_enable,
4124 .ppu_disable = mv88e6185_g1_ppu_disable,
4125 .reset = mv88e6185_g1_reset,
4126 .rmu_disable = mv88e6085_g1_rmu_disable,
4127 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4128 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4129 .stu_getnext = mv88e6352_g1_stu_getnext,
4130 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4131 .phylink_get_caps = mv88e6185_phylink_get_caps,
4132 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4133 };
4134
4135 static const struct mv88e6xxx_ops mv88e6095_ops = {
4136 /* MV88E6XXX_FAMILY_6095 */
4137 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4138 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4139 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4140 .phy_read = mv88e6185_phy_ppu_read,
4141 .phy_write = mv88e6185_phy_ppu_write,
4142 .port_set_link = mv88e6xxx_port_set_link,
4143 .port_sync_link = mv88e6185_port_sync_link,
4144 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4145 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4146 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4147 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4148 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4149 .port_get_cmode = mv88e6185_port_get_cmode,
4150 .port_setup_message_port = mv88e6xxx_setup_message_port,
4151 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4152 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4153 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4154 .stats_get_strings = mv88e6095_stats_get_strings,
4155 .stats_get_stats = mv88e6095_stats_get_stats,
4156 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4157 .ppu_enable = mv88e6185_g1_ppu_enable,
4158 .ppu_disable = mv88e6185_g1_ppu_disable,
4159 .reset = mv88e6185_g1_reset,
4160 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4161 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4162 .phylink_get_caps = mv88e6095_phylink_get_caps,
4163 .pcs_ops = &mv88e6185_pcs_ops,
4164 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4165 };
4166
4167 static const struct mv88e6xxx_ops mv88e6097_ops = {
4168 /* MV88E6XXX_FAMILY_6097 */
4169 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4170 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4171 .irl_init_all = mv88e6352_g2_irl_init_all,
4172 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4173 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4174 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4175 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4176 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4177 .port_set_link = mv88e6xxx_port_set_link,
4178 .port_sync_link = mv88e6185_port_sync_link,
4179 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4180 .port_tag_remap = mv88e6095_port_tag_remap,
4181 .port_set_policy = mv88e6352_port_set_policy,
4182 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4183 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4184 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4185 .port_set_ether_type = mv88e6351_port_set_ether_type,
4186 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
4187 .port_pause_limit = mv88e6097_port_pause_limit,
4188 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4189 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4190 .port_get_cmode = mv88e6185_port_get_cmode,
4191 .port_setup_message_port = mv88e6xxx_setup_message_port,
4192 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4193 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4194 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4195 .stats_get_strings = mv88e6095_stats_get_strings,
4196 .stats_get_stats = mv88e6095_stats_get_stats,
4197 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4198 .set_egress_port = mv88e6095_g1_set_egress_port,
4199 .watchdog_ops = &mv88e6097_watchdog_ops,
4200 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4201 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4202 .pot_clear = mv88e6xxx_g2_pot_clear,
4203 .reset = mv88e6352_g1_reset,
4204 .rmu_disable = mv88e6085_g1_rmu_disable,
4205 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4206 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4207 .phylink_get_caps = mv88e6095_phylink_get_caps,
4208 .pcs_ops = &mv88e6185_pcs_ops,
4209 .stu_getnext = mv88e6352_g1_stu_getnext,
4210 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4211 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4212 };
4213
4214 static const struct mv88e6xxx_ops mv88e6123_ops = {
4215 /* MV88E6XXX_FAMILY_6165 */
4216 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4217 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4218 .irl_init_all = mv88e6352_g2_irl_init_all,
4219 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4220 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4221 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4222 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4223 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4224 .port_set_link = mv88e6xxx_port_set_link,
4225 .port_sync_link = mv88e6xxx_port_sync_link,
4226 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4227 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4228 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4229 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4230 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4231 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4232 .port_get_cmode = mv88e6185_port_get_cmode,
4233 .port_setup_message_port = mv88e6xxx_setup_message_port,
4234 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4235 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4236 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4237 .stats_get_strings = mv88e6095_stats_get_strings,
4238 .stats_get_stats = mv88e6095_stats_get_stats,
4239 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4240 .set_egress_port = mv88e6095_g1_set_egress_port,
4241 .watchdog_ops = &mv88e6097_watchdog_ops,
4242 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4243 .pot_clear = mv88e6xxx_g2_pot_clear,
4244 .reset = mv88e6352_g1_reset,
4245 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4246 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4247 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4248 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4249 .stu_getnext = mv88e6352_g1_stu_getnext,
4250 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4251 .phylink_get_caps = mv88e6185_phylink_get_caps,
4252 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4253 };
4254
4255 static const struct mv88e6xxx_ops mv88e6131_ops = {
4256 /* MV88E6XXX_FAMILY_6185 */
4257 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4258 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4259 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4260 .phy_read = mv88e6185_phy_ppu_read,
4261 .phy_write = mv88e6185_phy_ppu_write,
4262 .port_set_link = mv88e6xxx_port_set_link,
4263 .port_sync_link = mv88e6xxx_port_sync_link,
4264 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4265 .port_tag_remap = mv88e6095_port_tag_remap,
4266 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4267 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4268 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4269 .port_set_ether_type = mv88e6351_port_set_ether_type,
4270 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4271 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4272 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4273 .port_pause_limit = mv88e6097_port_pause_limit,
4274 .port_set_pause = mv88e6185_port_set_pause,
4275 .port_get_cmode = mv88e6185_port_get_cmode,
4276 .port_setup_message_port = mv88e6xxx_setup_message_port,
4277 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4278 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4279 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4280 .stats_get_strings = mv88e6095_stats_get_strings,
4281 .stats_get_stats = mv88e6095_stats_get_stats,
4282 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4283 .set_egress_port = mv88e6095_g1_set_egress_port,
4284 .watchdog_ops = &mv88e6097_watchdog_ops,
4285 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4286 .ppu_enable = mv88e6185_g1_ppu_enable,
4287 .set_cascade_port = mv88e6185_g1_set_cascade_port,
4288 .ppu_disable = mv88e6185_g1_ppu_disable,
4289 .reset = mv88e6185_g1_reset,
4290 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4291 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4292 .phylink_get_caps = mv88e6185_phylink_get_caps,
4293 };
4294
4295 static const struct mv88e6xxx_ops mv88e6141_ops = {
4296 /* MV88E6XXX_FAMILY_6341 */
4297 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4298 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4299 .irl_init_all = mv88e6352_g2_irl_init_all,
4300 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4301 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4302 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4303 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4304 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4305 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4306 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4307 .port_set_link = mv88e6xxx_port_set_link,
4308 .port_sync_link = mv88e6xxx_port_sync_link,
4309 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4310 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
4311 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
4312 .port_tag_remap = mv88e6095_port_tag_remap,
4313 .port_set_policy = mv88e6352_port_set_policy,
4314 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4315 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4316 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4317 .port_set_ether_type = mv88e6351_port_set_ether_type,
4318 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4319 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4320 .port_pause_limit = mv88e6097_port_pause_limit,
4321 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4322 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4323 .port_get_cmode = mv88e6352_port_get_cmode,
4324 .port_set_cmode = mv88e6341_port_set_cmode,
4325 .port_setup_message_port = mv88e6xxx_setup_message_port,
4326 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4327 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4328 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4329 .stats_get_strings = mv88e6320_stats_get_strings,
4330 .stats_get_stats = mv88e6390_stats_get_stats,
4331 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4332 .set_egress_port = mv88e6390_g1_set_egress_port,
4333 .watchdog_ops = &mv88e6390_watchdog_ops,
4334 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4335 .pot_clear = mv88e6xxx_g2_pot_clear,
4336 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4337 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4338 .reset = mv88e6352_g1_reset,
4339 .rmu_disable = mv88e6390_g1_rmu_disable,
4340 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4341 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4342 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4343 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4344 .stu_getnext = mv88e6352_g1_stu_getnext,
4345 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4346 .serdes_get_lane = mv88e6341_serdes_get_lane,
4347 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4348 .gpio_ops = &mv88e6352_gpio_ops,
4349 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4350 .serdes_get_strings = mv88e6390_serdes_get_strings,
4351 .serdes_get_stats = mv88e6390_serdes_get_stats,
4352 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4353 .serdes_get_regs = mv88e6390_serdes_get_regs,
4354 .phylink_get_caps = mv88e6341_phylink_get_caps,
4355 .pcs_ops = &mv88e6390_pcs_ops,
4356 };
4357
4358 static const struct mv88e6xxx_ops mv88e6161_ops = {
4359 /* MV88E6XXX_FAMILY_6165 */
4360 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4361 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4362 .irl_init_all = mv88e6352_g2_irl_init_all,
4363 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4364 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4365 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4366 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4367 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4368 .port_set_link = mv88e6xxx_port_set_link,
4369 .port_sync_link = mv88e6xxx_port_sync_link,
4370 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4371 .port_tag_remap = mv88e6095_port_tag_remap,
4372 .port_set_policy = mv88e6352_port_set_policy,
4373 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4374 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4375 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4376 .port_set_ether_type = mv88e6351_port_set_ether_type,
4377 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4378 .port_pause_limit = mv88e6097_port_pause_limit,
4379 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4380 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4381 .port_get_cmode = mv88e6185_port_get_cmode,
4382 .port_setup_message_port = mv88e6xxx_setup_message_port,
4383 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4384 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4385 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4386 .stats_get_strings = mv88e6095_stats_get_strings,
4387 .stats_get_stats = mv88e6095_stats_get_stats,
4388 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4389 .set_egress_port = mv88e6095_g1_set_egress_port,
4390 .watchdog_ops = &mv88e6097_watchdog_ops,
4391 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4392 .pot_clear = mv88e6xxx_g2_pot_clear,
4393 .reset = mv88e6352_g1_reset,
4394 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4395 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4396 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4397 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4398 .stu_getnext = mv88e6352_g1_stu_getnext,
4399 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4400 .avb_ops = &mv88e6165_avb_ops,
4401 .ptp_ops = &mv88e6165_ptp_ops,
4402 .phylink_get_caps = mv88e6185_phylink_get_caps,
4403 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4404 };
4405
4406 static const struct mv88e6xxx_ops mv88e6165_ops = {
4407 /* MV88E6XXX_FAMILY_6165 */
4408 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4409 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4410 .irl_init_all = mv88e6352_g2_irl_init_all,
4411 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4412 .phy_read = mv88e6165_phy_read,
4413 .phy_write = mv88e6165_phy_write,
4414 .port_set_link = mv88e6xxx_port_set_link,
4415 .port_sync_link = mv88e6xxx_port_sync_link,
4416 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4417 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4418 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4419 .port_get_cmode = mv88e6185_port_get_cmode,
4420 .port_setup_message_port = mv88e6xxx_setup_message_port,
4421 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4422 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4423 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4424 .stats_get_strings = mv88e6095_stats_get_strings,
4425 .stats_get_stats = mv88e6095_stats_get_stats,
4426 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4427 .set_egress_port = mv88e6095_g1_set_egress_port,
4428 .watchdog_ops = &mv88e6097_watchdog_ops,
4429 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4430 .pot_clear = mv88e6xxx_g2_pot_clear,
4431 .reset = mv88e6352_g1_reset,
4432 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4433 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4434 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4435 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4436 .stu_getnext = mv88e6352_g1_stu_getnext,
4437 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4438 .avb_ops = &mv88e6165_avb_ops,
4439 .ptp_ops = &mv88e6165_ptp_ops,
4440 .phylink_get_caps = mv88e6185_phylink_get_caps,
4441 };
4442
4443 static const struct mv88e6xxx_ops mv88e6171_ops = {
4444 /* MV88E6XXX_FAMILY_6351 */
4445 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4446 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4447 .irl_init_all = mv88e6352_g2_irl_init_all,
4448 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4449 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4450 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4451 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4452 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4453 .port_set_link = mv88e6xxx_port_set_link,
4454 .port_sync_link = mv88e6xxx_port_sync_link,
4455 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4456 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4457 .port_tag_remap = mv88e6095_port_tag_remap,
4458 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4459 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4460 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4461 .port_set_ether_type = mv88e6351_port_set_ether_type,
4462 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4463 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4464 .port_pause_limit = mv88e6097_port_pause_limit,
4465 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4466 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4467 .port_get_cmode = mv88e6352_port_get_cmode,
4468 .port_setup_message_port = mv88e6xxx_setup_message_port,
4469 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4470 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4471 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4472 .stats_get_strings = mv88e6095_stats_get_strings,
4473 .stats_get_stats = mv88e6095_stats_get_stats,
4474 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4475 .set_egress_port = mv88e6095_g1_set_egress_port,
4476 .watchdog_ops = &mv88e6097_watchdog_ops,
4477 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4478 .pot_clear = mv88e6xxx_g2_pot_clear,
4479 .reset = mv88e6352_g1_reset,
4480 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4481 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4482 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4483 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4484 .stu_getnext = mv88e6352_g1_stu_getnext,
4485 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4486 .phylink_get_caps = mv88e6351_phylink_get_caps,
4487 };
4488
4489 static const struct mv88e6xxx_ops mv88e6172_ops = {
4490 /* MV88E6XXX_FAMILY_6352 */
4491 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4492 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4493 .irl_init_all = mv88e6352_g2_irl_init_all,
4494 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4495 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4496 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4497 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4498 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4499 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4500 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4501 .port_set_link = mv88e6xxx_port_set_link,
4502 .port_sync_link = mv88e6xxx_port_sync_link,
4503 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4504 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4505 .port_tag_remap = mv88e6095_port_tag_remap,
4506 .port_set_policy = mv88e6352_port_set_policy,
4507 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4508 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4509 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4510 .port_set_ether_type = mv88e6351_port_set_ether_type,
4511 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4512 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4513 .port_pause_limit = mv88e6097_port_pause_limit,
4514 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4515 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4516 .port_get_cmode = mv88e6352_port_get_cmode,
4517 .port_setup_message_port = mv88e6xxx_setup_message_port,
4518 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4519 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4520 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4521 .stats_get_strings = mv88e6095_stats_get_strings,
4522 .stats_get_stats = mv88e6095_stats_get_stats,
4523 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4524 .set_egress_port = mv88e6095_g1_set_egress_port,
4525 .watchdog_ops = &mv88e6097_watchdog_ops,
4526 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4527 .pot_clear = mv88e6xxx_g2_pot_clear,
4528 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4529 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4530 .reset = mv88e6352_g1_reset,
4531 .rmu_disable = mv88e6352_g1_rmu_disable,
4532 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4533 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4534 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4535 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4536 .stu_getnext = mv88e6352_g1_stu_getnext,
4537 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4538 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4539 .serdes_get_regs = mv88e6352_serdes_get_regs,
4540 .gpio_ops = &mv88e6352_gpio_ops,
4541 .phylink_get_caps = mv88e6352_phylink_get_caps,
4542 .pcs_ops = &mv88e6352_pcs_ops,
4543 };
4544
4545 static const struct mv88e6xxx_ops mv88e6175_ops = {
4546 /* MV88E6XXX_FAMILY_6351 */
4547 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4548 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4549 .irl_init_all = mv88e6352_g2_irl_init_all,
4550 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4551 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4552 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4553 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4554 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4555 .port_set_link = mv88e6xxx_port_set_link,
4556 .port_sync_link = mv88e6xxx_port_sync_link,
4557 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4558 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4559 .port_tag_remap = mv88e6095_port_tag_remap,
4560 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4561 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4562 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4563 .port_set_ether_type = mv88e6351_port_set_ether_type,
4564 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4565 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4566 .port_pause_limit = mv88e6097_port_pause_limit,
4567 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4568 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4569 .port_get_cmode = mv88e6352_port_get_cmode,
4570 .port_setup_message_port = mv88e6xxx_setup_message_port,
4571 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4572 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4573 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4574 .stats_get_strings = mv88e6095_stats_get_strings,
4575 .stats_get_stats = mv88e6095_stats_get_stats,
4576 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4577 .set_egress_port = mv88e6095_g1_set_egress_port,
4578 .watchdog_ops = &mv88e6097_watchdog_ops,
4579 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4580 .pot_clear = mv88e6xxx_g2_pot_clear,
4581 .reset = mv88e6352_g1_reset,
4582 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4583 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4584 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4585 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4586 .stu_getnext = mv88e6352_g1_stu_getnext,
4587 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4588 .phylink_get_caps = mv88e6351_phylink_get_caps,
4589 };
4590
4591 static const struct mv88e6xxx_ops mv88e6176_ops = {
4592 /* MV88E6XXX_FAMILY_6352 */
4593 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4594 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4595 .irl_init_all = mv88e6352_g2_irl_init_all,
4596 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4597 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4598 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4599 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4600 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4601 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4602 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4603 .port_set_link = mv88e6xxx_port_set_link,
4604 .port_sync_link = mv88e6xxx_port_sync_link,
4605 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4606 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4607 .port_tag_remap = mv88e6095_port_tag_remap,
4608 .port_set_policy = mv88e6352_port_set_policy,
4609 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4610 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4611 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4612 .port_set_ether_type = mv88e6351_port_set_ether_type,
4613 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4614 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4615 .port_pause_limit = mv88e6097_port_pause_limit,
4616 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4617 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4618 .port_get_cmode = mv88e6352_port_get_cmode,
4619 .port_setup_message_port = mv88e6xxx_setup_message_port,
4620 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4621 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4622 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4623 .stats_get_strings = mv88e6095_stats_get_strings,
4624 .stats_get_stats = mv88e6095_stats_get_stats,
4625 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4626 .set_egress_port = mv88e6095_g1_set_egress_port,
4627 .watchdog_ops = &mv88e6097_watchdog_ops,
4628 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4629 .pot_clear = mv88e6xxx_g2_pot_clear,
4630 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4631 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4632 .reset = mv88e6352_g1_reset,
4633 .rmu_disable = mv88e6352_g1_rmu_disable,
4634 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4635 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4636 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4637 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4638 .stu_getnext = mv88e6352_g1_stu_getnext,
4639 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4640 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4641 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4642 .serdes_get_regs = mv88e6352_serdes_get_regs,
4643 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
4644 .gpio_ops = &mv88e6352_gpio_ops,
4645 .phylink_get_caps = mv88e6352_phylink_get_caps,
4646 .pcs_ops = &mv88e6352_pcs_ops,
4647 };
4648
4649 static const struct mv88e6xxx_ops mv88e6185_ops = {
4650 /* MV88E6XXX_FAMILY_6185 */
4651 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4652 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4653 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4654 .phy_read = mv88e6185_phy_ppu_read,
4655 .phy_write = mv88e6185_phy_ppu_write,
4656 .port_set_link = mv88e6xxx_port_set_link,
4657 .port_sync_link = mv88e6185_port_sync_link,
4658 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4659 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4660 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4661 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4662 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
4663 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4664 .port_set_pause = mv88e6185_port_set_pause,
4665 .port_get_cmode = mv88e6185_port_get_cmode,
4666 .port_setup_message_port = mv88e6xxx_setup_message_port,
4667 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4668 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4669 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4670 .stats_get_strings = mv88e6095_stats_get_strings,
4671 .stats_get_stats = mv88e6095_stats_get_stats,
4672 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4673 .set_egress_port = mv88e6095_g1_set_egress_port,
4674 .watchdog_ops = &mv88e6097_watchdog_ops,
4675 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4676 .set_cascade_port = mv88e6185_g1_set_cascade_port,
4677 .ppu_enable = mv88e6185_g1_ppu_enable,
4678 .ppu_disable = mv88e6185_g1_ppu_disable,
4679 .reset = mv88e6185_g1_reset,
4680 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4681 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4682 .phylink_get_caps = mv88e6185_phylink_get_caps,
4683 .pcs_ops = &mv88e6185_pcs_ops,
4684 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4685 };
4686
4687 static const struct mv88e6xxx_ops mv88e6190_ops = {
4688 /* MV88E6XXX_FAMILY_6390 */
4689 .setup_errata = mv88e6390_setup_errata,
4690 .irl_init_all = mv88e6390_g2_irl_init_all,
4691 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4692 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4693 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4694 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4695 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4696 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4697 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4698 .port_set_link = mv88e6xxx_port_set_link,
4699 .port_sync_link = mv88e6xxx_port_sync_link,
4700 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4701 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4702 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4703 .port_tag_remap = mv88e6390_port_tag_remap,
4704 .port_set_policy = mv88e6352_port_set_policy,
4705 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4706 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4707 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4708 .port_set_ether_type = mv88e6351_port_set_ether_type,
4709 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4710 .port_pause_limit = mv88e6390_port_pause_limit,
4711 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4712 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4713 .port_get_cmode = mv88e6352_port_get_cmode,
4714 .port_set_cmode = mv88e6390_port_set_cmode,
4715 .port_setup_message_port = mv88e6xxx_setup_message_port,
4716 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4717 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4718 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4719 .stats_get_strings = mv88e6320_stats_get_strings,
4720 .stats_get_stats = mv88e6390_stats_get_stats,
4721 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4722 .set_egress_port = mv88e6390_g1_set_egress_port,
4723 .watchdog_ops = &mv88e6390_watchdog_ops,
4724 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4725 .pot_clear = mv88e6xxx_g2_pot_clear,
4726 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4727 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4728 .reset = mv88e6352_g1_reset,
4729 .rmu_disable = mv88e6390_g1_rmu_disable,
4730 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4731 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4732 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4733 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4734 .stu_getnext = mv88e6390_g1_stu_getnext,
4735 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4736 .serdes_get_lane = mv88e6390_serdes_get_lane,
4737 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4738 .serdes_get_strings = mv88e6390_serdes_get_strings,
4739 .serdes_get_stats = mv88e6390_serdes_get_stats,
4740 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4741 .serdes_get_regs = mv88e6390_serdes_get_regs,
4742 .gpio_ops = &mv88e6352_gpio_ops,
4743 .phylink_get_caps = mv88e6390_phylink_get_caps,
4744 .pcs_ops = &mv88e6390_pcs_ops,
4745 };
4746
4747 static const struct mv88e6xxx_ops mv88e6190x_ops = {
4748 /* MV88E6XXX_FAMILY_6390 */
4749 .setup_errata = mv88e6390_setup_errata,
4750 .irl_init_all = mv88e6390_g2_irl_init_all,
4751 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4752 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4753 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4754 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4755 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4756 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4757 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4758 .port_set_link = mv88e6xxx_port_set_link,
4759 .port_sync_link = mv88e6xxx_port_sync_link,
4760 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4761 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
4762 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
4763 .port_tag_remap = mv88e6390_port_tag_remap,
4764 .port_set_policy = mv88e6352_port_set_policy,
4765 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4766 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4767 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4768 .port_set_ether_type = mv88e6351_port_set_ether_type,
4769 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4770 .port_pause_limit = mv88e6390_port_pause_limit,
4771 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4772 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4773 .port_get_cmode = mv88e6352_port_get_cmode,
4774 .port_set_cmode = mv88e6390x_port_set_cmode,
4775 .port_setup_message_port = mv88e6xxx_setup_message_port,
4776 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4777 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4778 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4779 .stats_get_strings = mv88e6320_stats_get_strings,
4780 .stats_get_stats = mv88e6390_stats_get_stats,
4781 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4782 .set_egress_port = mv88e6390_g1_set_egress_port,
4783 .watchdog_ops = &mv88e6390_watchdog_ops,
4784 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4785 .pot_clear = mv88e6xxx_g2_pot_clear,
4786 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4787 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4788 .reset = mv88e6352_g1_reset,
4789 .rmu_disable = mv88e6390_g1_rmu_disable,
4790 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4791 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4792 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4793 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4794 .stu_getnext = mv88e6390_g1_stu_getnext,
4795 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4796 .serdes_get_lane = mv88e6390x_serdes_get_lane,
4797 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4798 .serdes_get_strings = mv88e6390_serdes_get_strings,
4799 .serdes_get_stats = mv88e6390_serdes_get_stats,
4800 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4801 .serdes_get_regs = mv88e6390_serdes_get_regs,
4802 .gpio_ops = &mv88e6352_gpio_ops,
4803 .phylink_get_caps = mv88e6390x_phylink_get_caps,
4804 .pcs_ops = &mv88e6390_pcs_ops,
4805 };
4806
4807 static const struct mv88e6xxx_ops mv88e6191_ops = {
4808 /* MV88E6XXX_FAMILY_6390 */
4809 .setup_errata = mv88e6390_setup_errata,
4810 .irl_init_all = mv88e6390_g2_irl_init_all,
4811 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4812 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4813 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4814 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4815 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4816 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4817 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4818 .port_set_link = mv88e6xxx_port_set_link,
4819 .port_sync_link = mv88e6xxx_port_sync_link,
4820 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4821 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4822 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4823 .port_tag_remap = mv88e6390_port_tag_remap,
4824 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4825 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4826 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4827 .port_set_ether_type = mv88e6351_port_set_ether_type,
4828 .port_pause_limit = mv88e6390_port_pause_limit,
4829 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4830 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4831 .port_get_cmode = mv88e6352_port_get_cmode,
4832 .port_set_cmode = mv88e6390_port_set_cmode,
4833 .port_setup_message_port = mv88e6xxx_setup_message_port,
4834 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4835 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4836 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4837 .stats_get_strings = mv88e6320_stats_get_strings,
4838 .stats_get_stats = mv88e6390_stats_get_stats,
4839 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4840 .set_egress_port = mv88e6390_g1_set_egress_port,
4841 .watchdog_ops = &mv88e6390_watchdog_ops,
4842 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4843 .pot_clear = mv88e6xxx_g2_pot_clear,
4844 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4845 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4846 .reset = mv88e6352_g1_reset,
4847 .rmu_disable = mv88e6390_g1_rmu_disable,
4848 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4849 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4850 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4851 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4852 .stu_getnext = mv88e6390_g1_stu_getnext,
4853 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4854 .serdes_get_lane = mv88e6390_serdes_get_lane,
4855 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4856 .serdes_get_strings = mv88e6390_serdes_get_strings,
4857 .serdes_get_stats = mv88e6390_serdes_get_stats,
4858 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4859 .serdes_get_regs = mv88e6390_serdes_get_regs,
4860 .avb_ops = &mv88e6390_avb_ops,
4861 .ptp_ops = &mv88e6352_ptp_ops,
4862 .phylink_get_caps = mv88e6390_phylink_get_caps,
4863 .pcs_ops = &mv88e6390_pcs_ops,
4864 };
4865
4866 static const struct mv88e6xxx_ops mv88e6240_ops = {
4867 /* MV88E6XXX_FAMILY_6352 */
4868 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4869 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4870 .irl_init_all = mv88e6352_g2_irl_init_all,
4871 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4872 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4873 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4874 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4875 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4876 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4877 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4878 .port_set_link = mv88e6xxx_port_set_link,
4879 .port_sync_link = mv88e6xxx_port_sync_link,
4880 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4881 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4882 .port_tag_remap = mv88e6095_port_tag_remap,
4883 .port_set_policy = mv88e6352_port_set_policy,
4884 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4885 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4886 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4887 .port_set_ether_type = mv88e6351_port_set_ether_type,
4888 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4889 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4890 .port_pause_limit = mv88e6097_port_pause_limit,
4891 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4892 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4893 .port_get_cmode = mv88e6352_port_get_cmode,
4894 .port_setup_message_port = mv88e6xxx_setup_message_port,
4895 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4896 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4897 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4898 .stats_get_strings = mv88e6095_stats_get_strings,
4899 .stats_get_stats = mv88e6095_stats_get_stats,
4900 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4901 .set_egress_port = mv88e6095_g1_set_egress_port,
4902 .watchdog_ops = &mv88e6097_watchdog_ops,
4903 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4904 .pot_clear = mv88e6xxx_g2_pot_clear,
4905 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4906 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4907 .reset = mv88e6352_g1_reset,
4908 .rmu_disable = mv88e6352_g1_rmu_disable,
4909 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4910 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4911 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4912 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4913 .stu_getnext = mv88e6352_g1_stu_getnext,
4914 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4915 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4916 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4917 .serdes_get_regs = mv88e6352_serdes_get_regs,
4918 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
4919 .gpio_ops = &mv88e6352_gpio_ops,
4920 .avb_ops = &mv88e6352_avb_ops,
4921 .ptp_ops = &mv88e6352_ptp_ops,
4922 .phylink_get_caps = mv88e6352_phylink_get_caps,
4923 .pcs_ops = &mv88e6352_pcs_ops,
4924 };
4925
4926 static const struct mv88e6xxx_ops mv88e6250_ops = {
4927 /* MV88E6XXX_FAMILY_6250 */
4928 .ieee_pri_map = mv88e6250_g1_ieee_pri_map,
4929 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4930 .irl_init_all = mv88e6352_g2_irl_init_all,
4931 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4932 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4933 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4934 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4935 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4936 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4937 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4938 .port_set_link = mv88e6xxx_port_set_link,
4939 .port_sync_link = mv88e6xxx_port_sync_link,
4940 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4941 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex,
4942 .port_tag_remap = mv88e6095_port_tag_remap,
4943 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4944 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4945 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4946 .port_set_ether_type = mv88e6351_port_set_ether_type,
4947 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4948 .port_pause_limit = mv88e6097_port_pause_limit,
4949 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4950 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4951 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4952 .stats_get_sset_count = mv88e6250_stats_get_sset_count,
4953 .stats_get_strings = mv88e6250_stats_get_strings,
4954 .stats_get_stats = mv88e6250_stats_get_stats,
4955 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4956 .set_egress_port = mv88e6095_g1_set_egress_port,
4957 .watchdog_ops = &mv88e6250_watchdog_ops,
4958 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4959 .pot_clear = mv88e6xxx_g2_pot_clear,
4960 .hardware_reset_pre = mv88e6250_g1_wait_eeprom_done_prereset,
4961 .hardware_reset_post = mv88e6xxx_g1_wait_eeprom_done,
4962 .reset = mv88e6250_g1_reset,
4963 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4964 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4965 .avb_ops = &mv88e6352_avb_ops,
4966 .ptp_ops = &mv88e6250_ptp_ops,
4967 .phylink_get_caps = mv88e6250_phylink_get_caps,
4968 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4969 };
4970
4971 static const struct mv88e6xxx_ops mv88e6290_ops = {
4972 /* MV88E6XXX_FAMILY_6390 */
4973 .setup_errata = mv88e6390_setup_errata,
4974 .irl_init_all = mv88e6390_g2_irl_init_all,
4975 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4976 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4977 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4978 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4979 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4980 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4981 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4982 .port_set_link = mv88e6xxx_port_set_link,
4983 .port_sync_link = mv88e6xxx_port_sync_link,
4984 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4985 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4986 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4987 .port_tag_remap = mv88e6390_port_tag_remap,
4988 .port_set_policy = mv88e6352_port_set_policy,
4989 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4990 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4991 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4992 .port_set_ether_type = mv88e6351_port_set_ether_type,
4993 .port_pause_limit = mv88e6390_port_pause_limit,
4994 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4995 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4996 .port_get_cmode = mv88e6352_port_get_cmode,
4997 .port_set_cmode = mv88e6390_port_set_cmode,
4998 .port_setup_message_port = mv88e6xxx_setup_message_port,
4999 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5000 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5001 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5002 .stats_get_strings = mv88e6320_stats_get_strings,
5003 .stats_get_stats = mv88e6390_stats_get_stats,
5004 .set_cpu_port = mv88e6390_g1_set_cpu_port,
5005 .set_egress_port = mv88e6390_g1_set_egress_port,
5006 .watchdog_ops = &mv88e6390_watchdog_ops,
5007 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5008 .pot_clear = mv88e6xxx_g2_pot_clear,
5009 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5010 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5011 .reset = mv88e6352_g1_reset,
5012 .rmu_disable = mv88e6390_g1_rmu_disable,
5013 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5014 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5015 .vtu_getnext = mv88e6390_g1_vtu_getnext,
5016 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5017 .stu_getnext = mv88e6390_g1_stu_getnext,
5018 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5019 .serdes_get_lane = mv88e6390_serdes_get_lane,
5020 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5021 .serdes_get_strings = mv88e6390_serdes_get_strings,
5022 .serdes_get_stats = mv88e6390_serdes_get_stats,
5023 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5024 .serdes_get_regs = mv88e6390_serdes_get_regs,
5025 .gpio_ops = &mv88e6352_gpio_ops,
5026 .avb_ops = &mv88e6390_avb_ops,
5027 .ptp_ops = &mv88e6390_ptp_ops,
5028 .phylink_get_caps = mv88e6390_phylink_get_caps,
5029 .pcs_ops = &mv88e6390_pcs_ops,
5030 };
5031
5032 static const struct mv88e6xxx_ops mv88e6320_ops = {
5033 /* MV88E6XXX_FAMILY_6320 */
5034 .setup_errata = mv88e6320_setup_errata,
5035 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5036 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5037 .irl_init_all = mv88e6352_g2_irl_init_all,
5038 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5039 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5040 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5041 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5042 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5043 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5044 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5045 .port_set_link = mv88e6xxx_port_set_link,
5046 .port_sync_link = mv88e6xxx_port_sync_link,
5047 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay,
5048 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5049 .port_tag_remap = mv88e6095_port_tag_remap,
5050 .port_set_policy = mv88e6352_port_set_policy,
5051 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5052 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5053 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5054 .port_set_ether_type = mv88e6351_port_set_ether_type,
5055 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5056 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5057 .port_pause_limit = mv88e6097_port_pause_limit,
5058 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5059 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5060 .port_get_cmode = mv88e6352_port_get_cmode,
5061 .port_setup_message_port = mv88e6xxx_setup_message_port,
5062 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5063 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5064 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5065 .stats_get_strings = mv88e6320_stats_get_strings,
5066 .stats_get_stats = mv88e6320_stats_get_stats,
5067 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5068 .set_egress_port = mv88e6095_g1_set_egress_port,
5069 .watchdog_ops = &mv88e6390_watchdog_ops,
5070 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5071 .pot_clear = mv88e6xxx_g2_pot_clear,
5072 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5073 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5074 .reset = mv88e6352_g1_reset,
5075 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5076 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5077 .stu_getnext = mv88e6352_g1_stu_getnext,
5078 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5079 .gpio_ops = &mv88e6352_gpio_ops,
5080 .avb_ops = &mv88e6352_avb_ops,
5081 .ptp_ops = &mv88e6352_ptp_ops,
5082 .phylink_get_caps = mv88e632x_phylink_get_caps,
5083 };
5084
5085 static const struct mv88e6xxx_ops mv88e6321_ops = {
5086 /* MV88E6XXX_FAMILY_6320 */
5087 .setup_errata = mv88e6320_setup_errata,
5088 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5089 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5090 .irl_init_all = mv88e6352_g2_irl_init_all,
5091 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5092 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5093 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5094 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5095 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5096 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5097 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5098 .port_set_link = mv88e6xxx_port_set_link,
5099 .port_sync_link = mv88e6xxx_port_sync_link,
5100 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay,
5101 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5102 .port_tag_remap = mv88e6095_port_tag_remap,
5103 .port_set_policy = mv88e6352_port_set_policy,
5104 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5105 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5106 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5107 .port_set_ether_type = mv88e6351_port_set_ether_type,
5108 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5109 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5110 .port_pause_limit = mv88e6097_port_pause_limit,
5111 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5112 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5113 .port_get_cmode = mv88e6352_port_get_cmode,
5114 .port_setup_message_port = mv88e6xxx_setup_message_port,
5115 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5116 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5117 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5118 .stats_get_strings = mv88e6320_stats_get_strings,
5119 .stats_get_stats = mv88e6320_stats_get_stats,
5120 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5121 .set_egress_port = mv88e6095_g1_set_egress_port,
5122 .watchdog_ops = &mv88e6390_watchdog_ops,
5123 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5124 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5125 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5126 .reset = mv88e6352_g1_reset,
5127 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5128 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5129 .stu_getnext = mv88e6352_g1_stu_getnext,
5130 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5131 .gpio_ops = &mv88e6352_gpio_ops,
5132 .avb_ops = &mv88e6352_avb_ops,
5133 .ptp_ops = &mv88e6352_ptp_ops,
5134 .phylink_get_caps = mv88e632x_phylink_get_caps,
5135 };
5136
5137 static const struct mv88e6xxx_ops mv88e6341_ops = {
5138 /* MV88E6XXX_FAMILY_6341 */
5139 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5140 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5141 .irl_init_all = mv88e6352_g2_irl_init_all,
5142 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5143 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5144 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5145 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5146 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5147 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5148 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5149 .port_set_link = mv88e6xxx_port_set_link,
5150 .port_sync_link = mv88e6xxx_port_sync_link,
5151 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5152 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
5153 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
5154 .port_tag_remap = mv88e6095_port_tag_remap,
5155 .port_set_policy = mv88e6352_port_set_policy,
5156 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5157 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5158 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5159 .port_set_ether_type = mv88e6351_port_set_ether_type,
5160 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5161 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5162 .port_pause_limit = mv88e6097_port_pause_limit,
5163 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5164 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5165 .port_get_cmode = mv88e6352_port_get_cmode,
5166 .port_set_cmode = mv88e6341_port_set_cmode,
5167 .port_setup_message_port = mv88e6xxx_setup_message_port,
5168 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5169 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5170 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5171 .stats_get_strings = mv88e6320_stats_get_strings,
5172 .stats_get_stats = mv88e6390_stats_get_stats,
5173 .set_cpu_port = mv88e6390_g1_set_cpu_port,
5174 .set_egress_port = mv88e6390_g1_set_egress_port,
5175 .watchdog_ops = &mv88e6390_watchdog_ops,
5176 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5177 .pot_clear = mv88e6xxx_g2_pot_clear,
5178 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5179 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5180 .reset = mv88e6352_g1_reset,
5181 .rmu_disable = mv88e6390_g1_rmu_disable,
5182 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5183 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5184 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5185 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5186 .stu_getnext = mv88e6352_g1_stu_getnext,
5187 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5188 .serdes_get_lane = mv88e6341_serdes_get_lane,
5189 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5190 .gpio_ops = &mv88e6352_gpio_ops,
5191 .avb_ops = &mv88e6390_avb_ops,
5192 .ptp_ops = &mv88e6352_ptp_ops,
5193 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5194 .serdes_get_strings = mv88e6390_serdes_get_strings,
5195 .serdes_get_stats = mv88e6390_serdes_get_stats,
5196 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5197 .serdes_get_regs = mv88e6390_serdes_get_regs,
5198 .phylink_get_caps = mv88e6341_phylink_get_caps,
5199 .pcs_ops = &mv88e6390_pcs_ops,
5200 };
5201
5202 static const struct mv88e6xxx_ops mv88e6350_ops = {
5203 /* MV88E6XXX_FAMILY_6351 */
5204 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5205 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5206 .irl_init_all = mv88e6352_g2_irl_init_all,
5207 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5208 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5209 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5210 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5211 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5212 .port_set_link = mv88e6xxx_port_set_link,
5213 .port_sync_link = mv88e6xxx_port_sync_link,
5214 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5215 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5216 .port_tag_remap = mv88e6095_port_tag_remap,
5217 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5218 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5219 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5220 .port_set_ether_type = mv88e6351_port_set_ether_type,
5221 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5222 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5223 .port_pause_limit = mv88e6097_port_pause_limit,
5224 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5225 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5226 .port_get_cmode = mv88e6352_port_get_cmode,
5227 .port_setup_message_port = mv88e6xxx_setup_message_port,
5228 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5229 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5230 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5231 .stats_get_strings = mv88e6095_stats_get_strings,
5232 .stats_get_stats = mv88e6095_stats_get_stats,
5233 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5234 .set_egress_port = mv88e6095_g1_set_egress_port,
5235 .watchdog_ops = &mv88e6097_watchdog_ops,
5236 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5237 .pot_clear = mv88e6xxx_g2_pot_clear,
5238 .reset = mv88e6352_g1_reset,
5239 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5240 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5241 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5242 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5243 .stu_getnext = mv88e6352_g1_stu_getnext,
5244 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5245 .phylink_get_caps = mv88e6351_phylink_get_caps,
5246 };
5247
5248 static const struct mv88e6xxx_ops mv88e6351_ops = {
5249 /* MV88E6XXX_FAMILY_6351 */
5250 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5251 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5252 .irl_init_all = mv88e6352_g2_irl_init_all,
5253 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5254 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5255 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5256 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5257 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5258 .port_set_link = mv88e6xxx_port_set_link,
5259 .port_sync_link = mv88e6xxx_port_sync_link,
5260 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5261 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5262 .port_tag_remap = mv88e6095_port_tag_remap,
5263 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5264 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5265 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5266 .port_set_ether_type = mv88e6351_port_set_ether_type,
5267 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5268 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5269 .port_pause_limit = mv88e6097_port_pause_limit,
5270 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5271 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5272 .port_get_cmode = mv88e6352_port_get_cmode,
5273 .port_setup_message_port = mv88e6xxx_setup_message_port,
5274 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5275 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5276 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5277 .stats_get_strings = mv88e6095_stats_get_strings,
5278 .stats_get_stats = mv88e6095_stats_get_stats,
5279 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5280 .set_egress_port = mv88e6095_g1_set_egress_port,
5281 .watchdog_ops = &mv88e6097_watchdog_ops,
5282 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5283 .pot_clear = mv88e6xxx_g2_pot_clear,
5284 .reset = mv88e6352_g1_reset,
5285 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5286 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5287 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5288 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5289 .stu_getnext = mv88e6352_g1_stu_getnext,
5290 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5291 .avb_ops = &mv88e6352_avb_ops,
5292 .ptp_ops = &mv88e6352_ptp_ops,
5293 .phylink_get_caps = mv88e6351_phylink_get_caps,
5294 };
5295
5296 static const struct mv88e6xxx_ops mv88e6352_ops = {
5297 /* MV88E6XXX_FAMILY_6352 */
5298 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5299 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5300 .irl_init_all = mv88e6352_g2_irl_init_all,
5301 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5302 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5303 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5304 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5305 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5306 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5307 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5308 .port_set_link = mv88e6xxx_port_set_link,
5309 .port_sync_link = mv88e6xxx_port_sync_link,
5310 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5311 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
5312 .port_tag_remap = mv88e6095_port_tag_remap,
5313 .port_set_policy = mv88e6352_port_set_policy,
5314 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5315 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5316 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5317 .port_set_ether_type = mv88e6351_port_set_ether_type,
5318 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5319 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5320 .port_pause_limit = mv88e6097_port_pause_limit,
5321 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5322 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5323 .port_get_cmode = mv88e6352_port_get_cmode,
5324 .port_setup_message_port = mv88e6xxx_setup_message_port,
5325 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5326 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5327 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5328 .stats_get_strings = mv88e6095_stats_get_strings,
5329 .stats_get_stats = mv88e6095_stats_get_stats,
5330 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5331 .set_egress_port = mv88e6095_g1_set_egress_port,
5332 .watchdog_ops = &mv88e6097_watchdog_ops,
5333 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5334 .pot_clear = mv88e6xxx_g2_pot_clear,
5335 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5336 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5337 .reset = mv88e6352_g1_reset,
5338 .rmu_disable = mv88e6352_g1_rmu_disable,
5339 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5340 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5341 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5342 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5343 .stu_getnext = mv88e6352_g1_stu_getnext,
5344 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5345 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
5346 .gpio_ops = &mv88e6352_gpio_ops,
5347 .avb_ops = &mv88e6352_avb_ops,
5348 .ptp_ops = &mv88e6352_ptp_ops,
5349 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
5350 .serdes_get_strings = mv88e6352_serdes_get_strings,
5351 .serdes_get_stats = mv88e6352_serdes_get_stats,
5352 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
5353 .serdes_get_regs = mv88e6352_serdes_get_regs,
5354 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
5355 .phylink_get_caps = mv88e6352_phylink_get_caps,
5356 .pcs_ops = &mv88e6352_pcs_ops,
5357 };
5358
5359 static const struct mv88e6xxx_ops mv88e6390_ops = {
5360 /* MV88E6XXX_FAMILY_6390 */
5361 .setup_errata = mv88e6390_setup_errata,
5362 .irl_init_all = mv88e6390_g2_irl_init_all,
5363 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5364 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5365 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5366 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5367 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5368 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5369 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5370 .port_set_link = mv88e6xxx_port_set_link,
5371 .port_sync_link = mv88e6xxx_port_sync_link,
5372 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5373 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
5374 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
5375 .port_tag_remap = mv88e6390_port_tag_remap,
5376 .port_set_policy = mv88e6352_port_set_policy,
5377 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5378 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5379 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5380 .port_set_ether_type = mv88e6351_port_set_ether_type,
5381 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5382 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5383 .port_pause_limit = mv88e6390_port_pause_limit,
5384 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5385 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5386 .port_get_cmode = mv88e6352_port_get_cmode,
5387 .port_set_cmode = mv88e6390_port_set_cmode,
5388 .port_setup_message_port = mv88e6xxx_setup_message_port,
5389 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5390 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5391 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5392 .stats_get_strings = mv88e6320_stats_get_strings,
5393 .stats_get_stats = mv88e6390_stats_get_stats,
5394 .set_cpu_port = mv88e6390_g1_set_cpu_port,
5395 .set_egress_port = mv88e6390_g1_set_egress_port,
5396 .watchdog_ops = &mv88e6390_watchdog_ops,
5397 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5398 .pot_clear = mv88e6xxx_g2_pot_clear,
5399 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5400 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5401 .reset = mv88e6352_g1_reset,
5402 .rmu_disable = mv88e6390_g1_rmu_disable,
5403 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5404 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5405 .vtu_getnext = mv88e6390_g1_vtu_getnext,
5406 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5407 .stu_getnext = mv88e6390_g1_stu_getnext,
5408 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5409 .serdes_get_lane = mv88e6390_serdes_get_lane,
5410 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5411 .gpio_ops = &mv88e6352_gpio_ops,
5412 .avb_ops = &mv88e6390_avb_ops,
5413 .ptp_ops = &mv88e6390_ptp_ops,
5414 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5415 .serdes_get_strings = mv88e6390_serdes_get_strings,
5416 .serdes_get_stats = mv88e6390_serdes_get_stats,
5417 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5418 .serdes_get_regs = mv88e6390_serdes_get_regs,
5419 .phylink_get_caps = mv88e6390_phylink_get_caps,
5420 .pcs_ops = &mv88e6390_pcs_ops,
5421 };
5422
5423 static const struct mv88e6xxx_ops mv88e6390x_ops = {
5424 /* MV88E6XXX_FAMILY_6390 */
5425 .setup_errata = mv88e6390_setup_errata,
5426 .irl_init_all = mv88e6390_g2_irl_init_all,
5427 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5428 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5429 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5430 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5431 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5432 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5433 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5434 .port_set_link = mv88e6xxx_port_set_link,
5435 .port_sync_link = mv88e6xxx_port_sync_link,
5436 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5437 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
5438 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
5439 .port_tag_remap = mv88e6390_port_tag_remap,
5440 .port_set_policy = mv88e6352_port_set_policy,
5441 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5442 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5443 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5444 .port_set_ether_type = mv88e6351_port_set_ether_type,
5445 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5446 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5447 .port_pause_limit = mv88e6390_port_pause_limit,
5448 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5449 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5450 .port_get_cmode = mv88e6352_port_get_cmode,
5451 .port_set_cmode = mv88e6390x_port_set_cmode,
5452 .port_setup_message_port = mv88e6xxx_setup_message_port,
5453 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5454 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5455 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5456 .stats_get_strings = mv88e6320_stats_get_strings,
5457 .stats_get_stats = mv88e6390_stats_get_stats,
5458 .set_cpu_port = mv88e6390_g1_set_cpu_port,
5459 .set_egress_port = mv88e6390_g1_set_egress_port,
5460 .watchdog_ops = &mv88e6390_watchdog_ops,
5461 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5462 .pot_clear = mv88e6xxx_g2_pot_clear,
5463 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5464 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5465 .reset = mv88e6352_g1_reset,
5466 .rmu_disable = mv88e6390_g1_rmu_disable,
5467 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5468 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5469 .vtu_getnext = mv88e6390_g1_vtu_getnext,
5470 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5471 .stu_getnext = mv88e6390_g1_stu_getnext,
5472 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5473 .serdes_get_lane = mv88e6390x_serdes_get_lane,
5474 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5475 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5476 .serdes_get_strings = mv88e6390_serdes_get_strings,
5477 .serdes_get_stats = mv88e6390_serdes_get_stats,
5478 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5479 .serdes_get_regs = mv88e6390_serdes_get_regs,
5480 .gpio_ops = &mv88e6352_gpio_ops,
5481 .avb_ops = &mv88e6390_avb_ops,
5482 .ptp_ops = &mv88e6390_ptp_ops,
5483 .phylink_get_caps = mv88e6390x_phylink_get_caps,
5484 .pcs_ops = &mv88e6390_pcs_ops,
5485 };
5486
5487 static const struct mv88e6xxx_ops mv88e6393x_ops = {
5488 /* MV88E6XXX_FAMILY_6393 */
5489 .irl_init_all = mv88e6390_g2_irl_init_all,
5490 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5491 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5492 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5493 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5494 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5495 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5496 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5497 .port_set_link = mv88e6xxx_port_set_link,
5498 .port_sync_link = mv88e6xxx_port_sync_link,
5499 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5500 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex,
5501 .port_max_speed_mode = mv88e6393x_port_max_speed_mode,
5502 .port_tag_remap = mv88e6390_port_tag_remap,
5503 .port_set_policy = mv88e6393x_port_set_policy,
5504 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5505 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5506 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5507 .port_set_ether_type = mv88e6393x_port_set_ether_type,
5508 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5509 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5510 .port_pause_limit = mv88e6390_port_pause_limit,
5511 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5512 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5513 .port_get_cmode = mv88e6352_port_get_cmode,
5514 .port_set_cmode = mv88e6393x_port_set_cmode,
5515 .port_setup_message_port = mv88e6xxx_setup_message_port,
5516 .port_set_upstream_port = mv88e6393x_port_set_upstream_port,
5517 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5518 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5519 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5520 .stats_get_strings = mv88e6320_stats_get_strings,
5521 .stats_get_stats = mv88e6390_stats_get_stats,
5522 /* .set_cpu_port is missing because this family does not support a global
5523 * CPU port, only per port CPU port which is set via
5524 * .port_set_upstream_port method.
5525 */
5526 .set_egress_port = mv88e6393x_set_egress_port,
5527 .watchdog_ops = &mv88e6393x_watchdog_ops,
5528 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu,
5529 .pot_clear = mv88e6xxx_g2_pot_clear,
5530 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5531 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5532 .reset = mv88e6352_g1_reset,
5533 .rmu_disable = mv88e6390_g1_rmu_disable,
5534 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5535 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5536 .vtu_getnext = mv88e6390_g1_vtu_getnext,
5537 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5538 .stu_getnext = mv88e6390_g1_stu_getnext,
5539 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5540 .serdes_get_lane = mv88e6393x_serdes_get_lane,
5541 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5542 /* TODO: serdes stats */
5543 .gpio_ops = &mv88e6352_gpio_ops,
5544 .avb_ops = &mv88e6390_avb_ops,
5545 .ptp_ops = &mv88e6352_ptp_ops,
5546 .phylink_get_caps = mv88e6393x_phylink_get_caps,
5547 .pcs_ops = &mv88e6393x_pcs_ops,
5548 };
5549
5550 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
5551 [MV88E6020] = {
5552 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6020,
5553 .family = MV88E6XXX_FAMILY_6250,
5554 .name = "Marvell 88E6020",
5555 .num_databases = 64,
5556 /* Ports 2-4 are not routed to pins
5557 * => usable ports 0, 1, 5, 6
5558 */
5559 .num_ports = 7,
5560 .num_internal_phys = 2,
5561 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
5562 .max_vid = 4095,
5563 .port_base_addr = 0x8,
5564 .phy_base_addr = 0x0,
5565 .global1_addr = 0xf,
5566 .global2_addr = 0x7,
5567 .age_time_coeff = 15000,
5568 .g1_irqs = 9,
5569 .g2_irqs = 5,
5570 .atu_move_port_mask = 0xf,
5571 .dual_chip = true,
5572 .ops = &mv88e6250_ops,
5573 },
5574
5575 [MV88E6071] = {
5576 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6071,
5577 .family = MV88E6XXX_FAMILY_6250,
5578 .name = "Marvell 88E6071",
5579 .num_databases = 64,
5580 .num_ports = 7,
5581 .num_internal_phys = 5,
5582 .max_vid = 4095,
5583 .port_base_addr = 0x08,
5584 .phy_base_addr = 0x00,
5585 .global1_addr = 0x0f,
5586 .global2_addr = 0x07,
5587 .age_time_coeff = 15000,
5588 .g1_irqs = 9,
5589 .g2_irqs = 5,
5590 .atu_move_port_mask = 0xf,
5591 .dual_chip = true,
5592 .ops = &mv88e6250_ops,
5593 },
5594
5595 [MV88E6085] = {
5596 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
5597 .family = MV88E6XXX_FAMILY_6097,
5598 .name = "Marvell 88E6085",
5599 .num_databases = 4096,
5600 .num_macs = 8192,
5601 .num_ports = 10,
5602 .num_internal_phys = 5,
5603 .max_vid = 4095,
5604 .max_sid = 63,
5605 .port_base_addr = 0x10,
5606 .phy_base_addr = 0x0,
5607 .global1_addr = 0x1b,
5608 .global2_addr = 0x1c,
5609 .age_time_coeff = 15000,
5610 .g1_irqs = 8,
5611 .g2_irqs = 10,
5612 .atu_move_port_mask = 0xf,
5613 .pvt = true,
5614 .multi_chip = true,
5615 .ops = &mv88e6085_ops,
5616 },
5617
5618 [MV88E6095] = {
5619 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
5620 .family = MV88E6XXX_FAMILY_6095,
5621 .name = "Marvell 88E6095/88E6095F",
5622 .num_databases = 256,
5623 .num_macs = 8192,
5624 .num_ports = 11,
5625 .num_internal_phys = 0,
5626 .max_vid = 4095,
5627 .port_base_addr = 0x10,
5628 .phy_base_addr = 0x0,
5629 .global1_addr = 0x1b,
5630 .global2_addr = 0x1c,
5631 .age_time_coeff = 15000,
5632 .g1_irqs = 8,
5633 .atu_move_port_mask = 0xf,
5634 .multi_chip = true,
5635 .ops = &mv88e6095_ops,
5636 },
5637
5638 [MV88E6097] = {
5639 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
5640 .family = MV88E6XXX_FAMILY_6097,
5641 .name = "Marvell 88E6097/88E6097F",
5642 .num_databases = 4096,
5643 .num_macs = 8192,
5644 .num_ports = 11,
5645 .num_internal_phys = 8,
5646 .max_vid = 4095,
5647 .max_sid = 63,
5648 .port_base_addr = 0x10,
5649 .phy_base_addr = 0x0,
5650 .global1_addr = 0x1b,
5651 .global2_addr = 0x1c,
5652 .age_time_coeff = 15000,
5653 .g1_irqs = 8,
5654 .g2_irqs = 10,
5655 .atu_move_port_mask = 0xf,
5656 .pvt = true,
5657 .multi_chip = true,
5658 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5659 .ops = &mv88e6097_ops,
5660 },
5661
5662 [MV88E6123] = {
5663 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
5664 .family = MV88E6XXX_FAMILY_6165,
5665 .name = "Marvell 88E6123",
5666 .num_databases = 4096,
5667 .num_macs = 1024,
5668 .num_ports = 3,
5669 .num_internal_phys = 5,
5670 .max_vid = 4095,
5671 .max_sid = 63,
5672 .port_base_addr = 0x10,
5673 .phy_base_addr = 0x0,
5674 .global1_addr = 0x1b,
5675 .global2_addr = 0x1c,
5676 .age_time_coeff = 15000,
5677 .g1_irqs = 9,
5678 .g2_irqs = 10,
5679 .atu_move_port_mask = 0xf,
5680 .pvt = true,
5681 .multi_chip = true,
5682 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5683 .ops = &mv88e6123_ops,
5684 },
5685
5686 [MV88E6131] = {
5687 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
5688 .family = MV88E6XXX_FAMILY_6185,
5689 .name = "Marvell 88E6131",
5690 .num_databases = 256,
5691 .num_macs = 8192,
5692 .num_ports = 8,
5693 .num_internal_phys = 0,
5694 .max_vid = 4095,
5695 .port_base_addr = 0x10,
5696 .phy_base_addr = 0x0,
5697 .global1_addr = 0x1b,
5698 .global2_addr = 0x1c,
5699 .age_time_coeff = 15000,
5700 .g1_irqs = 9,
5701 .atu_move_port_mask = 0xf,
5702 .multi_chip = true,
5703 .ops = &mv88e6131_ops,
5704 },
5705
5706 [MV88E6141] = {
5707 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
5708 .family = MV88E6XXX_FAMILY_6341,
5709 .name = "Marvell 88E6141",
5710 .num_databases = 256,
5711 .num_macs = 2048,
5712 .num_ports = 6,
5713 .num_internal_phys = 5,
5714 .num_gpio = 11,
5715 .max_vid = 4095,
5716 .max_sid = 63,
5717 .port_base_addr = 0x10,
5718 .phy_base_addr = 0x10,
5719 .global1_addr = 0x1b,
5720 .global2_addr = 0x1c,
5721 .age_time_coeff = 3750,
5722 .atu_move_port_mask = 0xf,
5723 .g1_irqs = 9,
5724 .g2_irqs = 10,
5725 .pvt = true,
5726 .multi_chip = true,
5727 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5728 .ops = &mv88e6141_ops,
5729 },
5730
5731 [MV88E6161] = {
5732 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
5733 .family = MV88E6XXX_FAMILY_6165,
5734 .name = "Marvell 88E6161",
5735 .num_databases = 4096,
5736 .num_macs = 1024,
5737 .num_ports = 6,
5738 .num_internal_phys = 5,
5739 .max_vid = 4095,
5740 .max_sid = 63,
5741 .port_base_addr = 0x10,
5742 .phy_base_addr = 0x0,
5743 .global1_addr = 0x1b,
5744 .global2_addr = 0x1c,
5745 .age_time_coeff = 15000,
5746 .g1_irqs = 9,
5747 .g2_irqs = 10,
5748 .atu_move_port_mask = 0xf,
5749 .pvt = true,
5750 .multi_chip = true,
5751 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5752 .ptp_support = true,
5753 .ops = &mv88e6161_ops,
5754 },
5755
5756 [MV88E6165] = {
5757 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
5758 .family = MV88E6XXX_FAMILY_6165,
5759 .name = "Marvell 88E6165",
5760 .num_databases = 4096,
5761 .num_macs = 8192,
5762 .num_ports = 6,
5763 .num_internal_phys = 0,
5764 .max_vid = 4095,
5765 .max_sid = 63,
5766 .port_base_addr = 0x10,
5767 .phy_base_addr = 0x0,
5768 .global1_addr = 0x1b,
5769 .global2_addr = 0x1c,
5770 .age_time_coeff = 15000,
5771 .g1_irqs = 9,
5772 .g2_irqs = 10,
5773 .atu_move_port_mask = 0xf,
5774 .pvt = true,
5775 .multi_chip = true,
5776 .ptp_support = true,
5777 .ops = &mv88e6165_ops,
5778 },
5779
5780 [MV88E6171] = {
5781 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
5782 .family = MV88E6XXX_FAMILY_6351,
5783 .name = "Marvell 88E6171",
5784 .num_databases = 4096,
5785 .num_macs = 8192,
5786 .num_ports = 7,
5787 .num_internal_phys = 5,
5788 .max_vid = 4095,
5789 .max_sid = 63,
5790 .port_base_addr = 0x10,
5791 .phy_base_addr = 0x0,
5792 .global1_addr = 0x1b,
5793 .global2_addr = 0x1c,
5794 .age_time_coeff = 15000,
5795 .g1_irqs = 9,
5796 .g2_irqs = 10,
5797 .atu_move_port_mask = 0xf,
5798 .pvt = true,
5799 .multi_chip = true,
5800 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5801 .ops = &mv88e6171_ops,
5802 },
5803
5804 [MV88E6172] = {
5805 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
5806 .family = MV88E6XXX_FAMILY_6352,
5807 .name = "Marvell 88E6172",
5808 .num_databases = 4096,
5809 .num_macs = 8192,
5810 .num_ports = 7,
5811 .num_internal_phys = 5,
5812 .num_gpio = 15,
5813 .max_vid = 4095,
5814 .max_sid = 63,
5815 .port_base_addr = 0x10,
5816 .phy_base_addr = 0x0,
5817 .global1_addr = 0x1b,
5818 .global2_addr = 0x1c,
5819 .age_time_coeff = 15000,
5820 .g1_irqs = 9,
5821 .g2_irqs = 10,
5822 .atu_move_port_mask = 0xf,
5823 .pvt = true,
5824 .multi_chip = true,
5825 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5826 .ops = &mv88e6172_ops,
5827 },
5828
5829 [MV88E6175] = {
5830 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
5831 .family = MV88E6XXX_FAMILY_6351,
5832 .name = "Marvell 88E6175",
5833 .num_databases = 4096,
5834 .num_macs = 8192,
5835 .num_ports = 7,
5836 .num_internal_phys = 5,
5837 .max_vid = 4095,
5838 .max_sid = 63,
5839 .port_base_addr = 0x10,
5840 .phy_base_addr = 0x0,
5841 .global1_addr = 0x1b,
5842 .global2_addr = 0x1c,
5843 .age_time_coeff = 15000,
5844 .g1_irqs = 9,
5845 .g2_irqs = 10,
5846 .atu_move_port_mask = 0xf,
5847 .pvt = true,
5848 .multi_chip = true,
5849 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5850 .ops = &mv88e6175_ops,
5851 },
5852
5853 [MV88E6176] = {
5854 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
5855 .family = MV88E6XXX_FAMILY_6352,
5856 .name = "Marvell 88E6176",
5857 .num_databases = 4096,
5858 .num_macs = 8192,
5859 .num_ports = 7,
5860 .num_internal_phys = 5,
5861 .num_gpio = 15,
5862 .max_vid = 4095,
5863 .max_sid = 63,
5864 .port_base_addr = 0x10,
5865 .phy_base_addr = 0x0,
5866 .global1_addr = 0x1b,
5867 .global2_addr = 0x1c,
5868 .age_time_coeff = 15000,
5869 .g1_irqs = 9,
5870 .g2_irqs = 10,
5871 .atu_move_port_mask = 0xf,
5872 .pvt = true,
5873 .multi_chip = true,
5874 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5875 .ops = &mv88e6176_ops,
5876 },
5877
5878 [MV88E6185] = {
5879 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
5880 .family = MV88E6XXX_FAMILY_6185,
5881 .name = "Marvell 88E6185",
5882 .num_databases = 256,
5883 .num_macs = 8192,
5884 .num_ports = 10,
5885 .num_internal_phys = 0,
5886 .max_vid = 4095,
5887 .port_base_addr = 0x10,
5888 .phy_base_addr = 0x0,
5889 .global1_addr = 0x1b,
5890 .global2_addr = 0x1c,
5891 .age_time_coeff = 15000,
5892 .g1_irqs = 8,
5893 .atu_move_port_mask = 0xf,
5894 .multi_chip = true,
5895 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5896 .ops = &mv88e6185_ops,
5897 },
5898
5899 [MV88E6190] = {
5900 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
5901 .family = MV88E6XXX_FAMILY_6390,
5902 .name = "Marvell 88E6190",
5903 .num_databases = 4096,
5904 .num_macs = 16384,
5905 .num_ports = 11, /* 10 + Z80 */
5906 .num_internal_phys = 9,
5907 .num_gpio = 16,
5908 .max_vid = 8191,
5909 .max_sid = 63,
5910 .port_base_addr = 0x0,
5911 .phy_base_addr = 0x0,
5912 .global1_addr = 0x1b,
5913 .global2_addr = 0x1c,
5914 .age_time_coeff = 3750,
5915 .g1_irqs = 9,
5916 .g2_irqs = 14,
5917 .pvt = true,
5918 .multi_chip = true,
5919 .atu_move_port_mask = 0x1f,
5920 .ops = &mv88e6190_ops,
5921 },
5922
5923 [MV88E6190X] = {
5924 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
5925 .family = MV88E6XXX_FAMILY_6390,
5926 .name = "Marvell 88E6190X",
5927 .num_databases = 4096,
5928 .num_macs = 16384,
5929 .num_ports = 11, /* 10 + Z80 */
5930 .num_internal_phys = 9,
5931 .num_gpio = 16,
5932 .max_vid = 8191,
5933 .max_sid = 63,
5934 .port_base_addr = 0x0,
5935 .phy_base_addr = 0x0,
5936 .global1_addr = 0x1b,
5937 .global2_addr = 0x1c,
5938 .age_time_coeff = 3750,
5939 .g1_irqs = 9,
5940 .g2_irqs = 14,
5941 .atu_move_port_mask = 0x1f,
5942 .pvt = true,
5943 .multi_chip = true,
5944 .ops = &mv88e6190x_ops,
5945 },
5946
5947 [MV88E6191] = {
5948 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
5949 .family = MV88E6XXX_FAMILY_6390,
5950 .name = "Marvell 88E6191",
5951 .num_databases = 4096,
5952 .num_macs = 16384,
5953 .num_ports = 11, /* 10 + Z80 */
5954 .num_internal_phys = 9,
5955 .max_vid = 8191,
5956 .max_sid = 63,
5957 .port_base_addr = 0x0,
5958 .phy_base_addr = 0x0,
5959 .global1_addr = 0x1b,
5960 .global2_addr = 0x1c,
5961 .age_time_coeff = 3750,
5962 .g1_irqs = 9,
5963 .g2_irqs = 14,
5964 .atu_move_port_mask = 0x1f,
5965 .pvt = true,
5966 .multi_chip = true,
5967 .ptp_support = true,
5968 .ops = &mv88e6191_ops,
5969 },
5970
5971 [MV88E6191X] = {
5972 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X,
5973 .family = MV88E6XXX_FAMILY_6393,
5974 .name = "Marvell 88E6191X",
5975 .num_databases = 4096,
5976 .num_ports = 11, /* 10 + Z80 */
5977 .num_internal_phys = 8,
5978 .internal_phys_offset = 1,
5979 .max_vid = 8191,
5980 .max_sid = 63,
5981 .port_base_addr = 0x0,
5982 .phy_base_addr = 0x0,
5983 .global1_addr = 0x1b,
5984 .global2_addr = 0x1c,
5985 .age_time_coeff = 3750,
5986 .g1_irqs = 10,
5987 .g2_irqs = 14,
5988 .atu_move_port_mask = 0x1f,
5989 .pvt = true,
5990 .multi_chip = true,
5991 .ptp_support = true,
5992 .ops = &mv88e6393x_ops,
5993 },
5994
5995 [MV88E6193X] = {
5996 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X,
5997 .family = MV88E6XXX_FAMILY_6393,
5998 .name = "Marvell 88E6193X",
5999 .num_databases = 4096,
6000 .num_ports = 11, /* 10 + Z80 */
6001 .num_internal_phys = 8,
6002 .internal_phys_offset = 1,
6003 .max_vid = 8191,
6004 .max_sid = 63,
6005 .port_base_addr = 0x0,
6006 .phy_base_addr = 0x0,
6007 .global1_addr = 0x1b,
6008 .global2_addr = 0x1c,
6009 .age_time_coeff = 3750,
6010 .g1_irqs = 10,
6011 .g2_irqs = 14,
6012 .atu_move_port_mask = 0x1f,
6013 .pvt = true,
6014 .multi_chip = true,
6015 .ptp_support = true,
6016 .ops = &mv88e6393x_ops,
6017 },
6018
6019 [MV88E6220] = {
6020 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220,
6021 .family = MV88E6XXX_FAMILY_6250,
6022 .name = "Marvell 88E6220",
6023 .num_databases = 64,
6024
6025 /* Ports 2-4 are not routed to pins
6026 * => usable ports 0, 1, 5, 6
6027 */
6028 .num_ports = 7,
6029 .num_internal_phys = 2,
6030 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
6031 .max_vid = 4095,
6032 .port_base_addr = 0x08,
6033 .phy_base_addr = 0x00,
6034 .global1_addr = 0x0f,
6035 .global2_addr = 0x07,
6036 .age_time_coeff = 15000,
6037 .g1_irqs = 9,
6038 .g2_irqs = 10,
6039 .atu_move_port_mask = 0xf,
6040 .dual_chip = true,
6041 .ptp_support = true,
6042 .ops = &mv88e6250_ops,
6043 },
6044
6045 [MV88E6240] = {
6046 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
6047 .family = MV88E6XXX_FAMILY_6352,
6048 .name = "Marvell 88E6240",
6049 .num_databases = 4096,
6050 .num_macs = 8192,
6051 .num_ports = 7,
6052 .num_internal_phys = 5,
6053 .num_gpio = 15,
6054 .max_vid = 4095,
6055 .max_sid = 63,
6056 .port_base_addr = 0x10,
6057 .phy_base_addr = 0x0,
6058 .global1_addr = 0x1b,
6059 .global2_addr = 0x1c,
6060 .age_time_coeff = 15000,
6061 .g1_irqs = 9,
6062 .g2_irqs = 10,
6063 .atu_move_port_mask = 0xf,
6064 .pvt = true,
6065 .multi_chip = true,
6066 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6067 .ptp_support = true,
6068 .ops = &mv88e6240_ops,
6069 },
6070
6071 [MV88E6250] = {
6072 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250,
6073 .family = MV88E6XXX_FAMILY_6250,
6074 .name = "Marvell 88E6250",
6075 .num_databases = 64,
6076 .num_ports = 7,
6077 .num_internal_phys = 5,
6078 .max_vid = 4095,
6079 .port_base_addr = 0x08,
6080 .phy_base_addr = 0x00,
6081 .global1_addr = 0x0f,
6082 .global2_addr = 0x07,
6083 .age_time_coeff = 15000,
6084 .g1_irqs = 9,
6085 .g2_irqs = 10,
6086 .atu_move_port_mask = 0xf,
6087 .dual_chip = true,
6088 .ptp_support = true,
6089 .ops = &mv88e6250_ops,
6090 },
6091
6092 [MV88E6290] = {
6093 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
6094 .family = MV88E6XXX_FAMILY_6390,
6095 .name = "Marvell 88E6290",
6096 .num_databases = 4096,
6097 .num_ports = 11, /* 10 + Z80 */
6098 .num_internal_phys = 9,
6099 .num_gpio = 16,
6100 .max_vid = 8191,
6101 .max_sid = 63,
6102 .port_base_addr = 0x0,
6103 .phy_base_addr = 0x0,
6104 .global1_addr = 0x1b,
6105 .global2_addr = 0x1c,
6106 .age_time_coeff = 3750,
6107 .g1_irqs = 9,
6108 .g2_irqs = 14,
6109 .atu_move_port_mask = 0x1f,
6110 .pvt = true,
6111 .multi_chip = true,
6112 .ptp_support = true,
6113 .ops = &mv88e6290_ops,
6114 },
6115
6116 [MV88E6320] = {
6117 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
6118 .family = MV88E6XXX_FAMILY_6320,
6119 .name = "Marvell 88E6320",
6120 .num_databases = 4096,
6121 .num_macs = 8192,
6122 .num_ports = 7,
6123 .num_internal_phys = 2,
6124 .internal_phys_offset = 3,
6125 .num_gpio = 15,
6126 .max_vid = 4095,
6127 .max_sid = 63,
6128 .port_base_addr = 0x10,
6129 .phy_base_addr = 0x0,
6130 .global1_addr = 0x1b,
6131 .global2_addr = 0x1c,
6132 .age_time_coeff = 15000,
6133 .g1_irqs = 8,
6134 .g2_irqs = 10,
6135 .atu_move_port_mask = 0xf,
6136 .pvt = true,
6137 .multi_chip = true,
6138 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6139 .ptp_support = true,
6140 .ops = &mv88e6320_ops,
6141 },
6142
6143 [MV88E6321] = {
6144 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
6145 .family = MV88E6XXX_FAMILY_6320,
6146 .name = "Marvell 88E6321",
6147 .num_databases = 4096,
6148 .num_macs = 8192,
6149 .num_ports = 7,
6150 .num_internal_phys = 2,
6151 .internal_phys_offset = 3,
6152 .num_gpio = 15,
6153 .max_vid = 4095,
6154 .max_sid = 63,
6155 .port_base_addr = 0x10,
6156 .phy_base_addr = 0x0,
6157 .global1_addr = 0x1b,
6158 .global2_addr = 0x1c,
6159 .age_time_coeff = 15000,
6160 .g1_irqs = 8,
6161 .g2_irqs = 10,
6162 .atu_move_port_mask = 0xf,
6163 .pvt = true,
6164 .multi_chip = true,
6165 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6166 .ptp_support = true,
6167 .ops = &mv88e6321_ops,
6168 },
6169
6170 [MV88E6341] = {
6171 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
6172 .family = MV88E6XXX_FAMILY_6341,
6173 .name = "Marvell 88E6341",
6174 .num_databases = 256,
6175 .num_macs = 2048,
6176 .num_internal_phys = 5,
6177 .num_ports = 6,
6178 .num_gpio = 11,
6179 .max_vid = 4095,
6180 .max_sid = 63,
6181 .port_base_addr = 0x10,
6182 .phy_base_addr = 0x10,
6183 .global1_addr = 0x1b,
6184 .global2_addr = 0x1c,
6185 .age_time_coeff = 3750,
6186 .atu_move_port_mask = 0xf,
6187 .g1_irqs = 9,
6188 .g2_irqs = 10,
6189 .pvt = true,
6190 .multi_chip = true,
6191 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6192 .ptp_support = true,
6193 .ops = &mv88e6341_ops,
6194 },
6195
6196 [MV88E6350] = {
6197 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
6198 .family = MV88E6XXX_FAMILY_6351,
6199 .name = "Marvell 88E6350",
6200 .num_databases = 4096,
6201 .num_macs = 8192,
6202 .num_ports = 7,
6203 .num_internal_phys = 5,
6204 .max_vid = 4095,
6205 .max_sid = 63,
6206 .port_base_addr = 0x10,
6207 .phy_base_addr = 0x0,
6208 .global1_addr = 0x1b,
6209 .global2_addr = 0x1c,
6210 .age_time_coeff = 15000,
6211 .g1_irqs = 9,
6212 .g2_irqs = 10,
6213 .atu_move_port_mask = 0xf,
6214 .pvt = true,
6215 .multi_chip = true,
6216 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6217 .ops = &mv88e6350_ops,
6218 },
6219
6220 [MV88E6351] = {
6221 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
6222 .family = MV88E6XXX_FAMILY_6351,
6223 .name = "Marvell 88E6351",
6224 .num_databases = 4096,
6225 .num_macs = 8192,
6226 .num_ports = 7,
6227 .num_internal_phys = 5,
6228 .max_vid = 4095,
6229 .max_sid = 63,
6230 .port_base_addr = 0x10,
6231 .phy_base_addr = 0x0,
6232 .global1_addr = 0x1b,
6233 .global2_addr = 0x1c,
6234 .age_time_coeff = 15000,
6235 .g1_irqs = 9,
6236 .g2_irqs = 10,
6237 .atu_move_port_mask = 0xf,
6238 .pvt = true,
6239 .multi_chip = true,
6240 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6241 .ops = &mv88e6351_ops,
6242 },
6243
6244 [MV88E6352] = {
6245 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
6246 .family = MV88E6XXX_FAMILY_6352,
6247 .name = "Marvell 88E6352",
6248 .num_databases = 4096,
6249 .num_macs = 8192,
6250 .num_ports = 7,
6251 .num_internal_phys = 5,
6252 .num_gpio = 15,
6253 .max_vid = 4095,
6254 .max_sid = 63,
6255 .port_base_addr = 0x10,
6256 .phy_base_addr = 0x0,
6257 .global1_addr = 0x1b,
6258 .global2_addr = 0x1c,
6259 .age_time_coeff = 15000,
6260 .g1_irqs = 9,
6261 .g2_irqs = 10,
6262 .atu_move_port_mask = 0xf,
6263 .pvt = true,
6264 .multi_chip = true,
6265 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6266 .ptp_support = true,
6267 .ops = &mv88e6352_ops,
6268 },
6269 [MV88E6361] = {
6270 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6361,
6271 .family = MV88E6XXX_FAMILY_6393,
6272 .name = "Marvell 88E6361",
6273 .num_databases = 4096,
6274 .num_macs = 16384,
6275 .num_ports = 11,
6276 /* Ports 1, 2 and 8 are not routed */
6277 .invalid_port_mask = BIT(1) | BIT(2) | BIT(8),
6278 .num_internal_phys = 5,
6279 .internal_phys_offset = 3,
6280 .max_vid = 8191,
6281 .max_sid = 63,
6282 .port_base_addr = 0x0,
6283 .phy_base_addr = 0x0,
6284 .global1_addr = 0x1b,
6285 .global2_addr = 0x1c,
6286 .age_time_coeff = 3750,
6287 .g1_irqs = 10,
6288 .g2_irqs = 14,
6289 .atu_move_port_mask = 0x1f,
6290 .pvt = true,
6291 .multi_chip = true,
6292 .ptp_support = true,
6293 .ops = &mv88e6393x_ops,
6294 },
6295 [MV88E6390] = {
6296 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
6297 .family = MV88E6XXX_FAMILY_6390,
6298 .name = "Marvell 88E6390",
6299 .num_databases = 4096,
6300 .num_macs = 16384,
6301 .num_ports = 11, /* 10 + Z80 */
6302 .num_internal_phys = 9,
6303 .num_gpio = 16,
6304 .max_vid = 8191,
6305 .max_sid = 63,
6306 .port_base_addr = 0x0,
6307 .phy_base_addr = 0x0,
6308 .global1_addr = 0x1b,
6309 .global2_addr = 0x1c,
6310 .age_time_coeff = 3750,
6311 .g1_irqs = 9,
6312 .g2_irqs = 14,
6313 .atu_move_port_mask = 0x1f,
6314 .pvt = true,
6315 .multi_chip = true,
6316 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
6317 .ptp_support = true,
6318 .ops = &mv88e6390_ops,
6319 },
6320 [MV88E6390X] = {
6321 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
6322 .family = MV88E6XXX_FAMILY_6390,
6323 .name = "Marvell 88E6390X",
6324 .num_databases = 4096,
6325 .num_macs = 16384,
6326 .num_ports = 11, /* 10 + Z80 */
6327 .num_internal_phys = 9,
6328 .num_gpio = 16,
6329 .max_vid = 8191,
6330 .max_sid = 63,
6331 .port_base_addr = 0x0,
6332 .phy_base_addr = 0x0,
6333 .global1_addr = 0x1b,
6334 .global2_addr = 0x1c,
6335 .age_time_coeff = 3750,
6336 .g1_irqs = 9,
6337 .g2_irqs = 14,
6338 .atu_move_port_mask = 0x1f,
6339 .pvt = true,
6340 .multi_chip = true,
6341 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
6342 .ptp_support = true,
6343 .ops = &mv88e6390x_ops,
6344 },
6345
6346 [MV88E6393X] = {
6347 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
6348 .family = MV88E6XXX_FAMILY_6393,
6349 .name = "Marvell 88E6393X",
6350 .num_databases = 4096,
6351 .num_ports = 11, /* 10 + Z80 */
6352 .num_internal_phys = 8,
6353 .internal_phys_offset = 1,
6354 .max_vid = 8191,
6355 .max_sid = 63,
6356 .port_base_addr = 0x0,
6357 .phy_base_addr = 0x0,
6358 .global1_addr = 0x1b,
6359 .global2_addr = 0x1c,
6360 .age_time_coeff = 3750,
6361 .g1_irqs = 10,
6362 .g2_irqs = 14,
6363 .atu_move_port_mask = 0x1f,
6364 .pvt = true,
6365 .multi_chip = true,
6366 .ptp_support = true,
6367 .ops = &mv88e6393x_ops,
6368 },
6369 };
6370
mv88e6xxx_lookup_info(unsigned int prod_num)6371 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
6372 {
6373 int i;
6374
6375 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
6376 if (mv88e6xxx_table[i].prod_num == prod_num)
6377 return &mv88e6xxx_table[i];
6378
6379 return NULL;
6380 }
6381
mv88e6xxx_detect(struct mv88e6xxx_chip * chip)6382 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
6383 {
6384 const struct mv88e6xxx_info *info;
6385 unsigned int prod_num, rev;
6386 u16 id;
6387 int err;
6388
6389 mv88e6xxx_reg_lock(chip);
6390 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
6391 mv88e6xxx_reg_unlock(chip);
6392 if (err)
6393 return err;
6394
6395 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
6396 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
6397
6398 info = mv88e6xxx_lookup_info(prod_num);
6399 if (!info)
6400 return -ENODEV;
6401
6402 /* Update the compatible info with the probed one */
6403 chip->info = info;
6404
6405 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
6406 chip->info->prod_num, chip->info->name, rev);
6407
6408 return 0;
6409 }
6410
mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip * chip,struct mdio_device * mdiodev)6411 static int mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip *chip,
6412 struct mdio_device *mdiodev)
6413 {
6414 int err;
6415
6416 /* dual_chip takes precedence over single/multi-chip modes */
6417 if (chip->info->dual_chip)
6418 return -EINVAL;
6419
6420 /* If the mdio addr is 16 indicating the first port address of a switch
6421 * (e.g. mv88e6*41) in single chip addressing mode the device may be
6422 * configured in single chip addressing mode. Setup the smi access as
6423 * single chip addressing mode and attempt to detect the model of the
6424 * switch, if this fails the device is not configured in single chip
6425 * addressing mode.
6426 */
6427 if (mdiodev->addr != 16)
6428 return -EINVAL;
6429
6430 err = mv88e6xxx_smi_init(chip, mdiodev->bus, 0);
6431 if (err)
6432 return err;
6433
6434 return mv88e6xxx_detect(chip);
6435 }
6436
mv88e6xxx_alloc_chip(struct device * dev)6437 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
6438 {
6439 struct mv88e6xxx_chip *chip;
6440
6441 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
6442 if (!chip)
6443 return NULL;
6444
6445 chip->dev = dev;
6446
6447 mutex_init(&chip->reg_lock);
6448 INIT_LIST_HEAD(&chip->mdios);
6449 idr_init(&chip->policies);
6450 INIT_LIST_HEAD(&chip->msts);
6451
6452 return chip;
6453 }
6454
mv88e6xxx_get_tag_protocol(struct dsa_switch * ds,int port,enum dsa_tag_protocol m)6455 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
6456 int port,
6457 enum dsa_tag_protocol m)
6458 {
6459 struct mv88e6xxx_chip *chip = ds->priv;
6460
6461 return chip->tag_protocol;
6462 }
6463
mv88e6xxx_change_tag_protocol(struct dsa_switch * ds,enum dsa_tag_protocol proto)6464 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds,
6465 enum dsa_tag_protocol proto)
6466 {
6467 struct mv88e6xxx_chip *chip = ds->priv;
6468 enum dsa_tag_protocol old_protocol;
6469 struct dsa_port *cpu_dp;
6470 int err;
6471
6472 switch (proto) {
6473 case DSA_TAG_PROTO_EDSA:
6474 switch (chip->info->edsa_support) {
6475 case MV88E6XXX_EDSA_UNSUPPORTED:
6476 return -EPROTONOSUPPORT;
6477 case MV88E6XXX_EDSA_UNDOCUMENTED:
6478 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n");
6479 fallthrough;
6480 case MV88E6XXX_EDSA_SUPPORTED:
6481 break;
6482 }
6483 break;
6484 case DSA_TAG_PROTO_DSA:
6485 break;
6486 default:
6487 return -EPROTONOSUPPORT;
6488 }
6489
6490 old_protocol = chip->tag_protocol;
6491 chip->tag_protocol = proto;
6492
6493 mv88e6xxx_reg_lock(chip);
6494 dsa_switch_for_each_cpu_port(cpu_dp, ds) {
6495 err = mv88e6xxx_setup_port_mode(chip, cpu_dp->index);
6496 if (err) {
6497 mv88e6xxx_reg_unlock(chip);
6498 goto unwind;
6499 }
6500 }
6501 mv88e6xxx_reg_unlock(chip);
6502
6503 return 0;
6504
6505 unwind:
6506 chip->tag_protocol = old_protocol;
6507
6508 mv88e6xxx_reg_lock(chip);
6509 dsa_switch_for_each_cpu_port_continue_reverse(cpu_dp, ds)
6510 mv88e6xxx_setup_port_mode(chip, cpu_dp->index);
6511 mv88e6xxx_reg_unlock(chip);
6512
6513 return err;
6514 }
6515
mv88e6xxx_port_mdb_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)6516 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
6517 const struct switchdev_obj_port_mdb *mdb,
6518 struct dsa_db db)
6519 {
6520 struct mv88e6xxx_chip *chip = ds->priv;
6521 int err;
6522
6523 mv88e6xxx_reg_lock(chip);
6524 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
6525 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC);
6526 if (err)
6527 goto out;
6528
6529 if (!mv88e6xxx_port_db_find(chip, mdb->addr, mdb->vid))
6530 err = -ENOSPC;
6531
6532 out:
6533 mv88e6xxx_reg_unlock(chip);
6534
6535 return err;
6536 }
6537
mv88e6xxx_port_mdb_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)6538 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
6539 const struct switchdev_obj_port_mdb *mdb,
6540 struct dsa_db db)
6541 {
6542 struct mv88e6xxx_chip *chip = ds->priv;
6543 int err;
6544
6545 mv88e6xxx_reg_lock(chip);
6546 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0);
6547 mv88e6xxx_reg_unlock(chip);
6548
6549 return err;
6550 }
6551
mv88e6xxx_port_mirror_add(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror,bool ingress,struct netlink_ext_ack * extack)6552 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port,
6553 struct dsa_mall_mirror_tc_entry *mirror,
6554 bool ingress,
6555 struct netlink_ext_ack *extack)
6556 {
6557 enum mv88e6xxx_egress_direction direction = ingress ?
6558 MV88E6XXX_EGRESS_DIR_INGRESS :
6559 MV88E6XXX_EGRESS_DIR_EGRESS;
6560 struct mv88e6xxx_chip *chip = ds->priv;
6561 bool other_mirrors = false;
6562 int i;
6563 int err;
6564
6565 mutex_lock(&chip->reg_lock);
6566 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) !=
6567 mirror->to_local_port) {
6568 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
6569 other_mirrors |= ingress ?
6570 chip->ports[i].mirror_ingress :
6571 chip->ports[i].mirror_egress;
6572
6573 /* Can't change egress port when other mirror is active */
6574 if (other_mirrors) {
6575 err = -EBUSY;
6576 goto out;
6577 }
6578
6579 err = mv88e6xxx_set_egress_port(chip, direction,
6580 mirror->to_local_port);
6581 if (err)
6582 goto out;
6583 }
6584
6585 err = mv88e6xxx_port_set_mirror(chip, port, direction, true);
6586 out:
6587 mutex_unlock(&chip->reg_lock);
6588
6589 return err;
6590 }
6591
mv88e6xxx_port_mirror_del(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror)6592 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port,
6593 struct dsa_mall_mirror_tc_entry *mirror)
6594 {
6595 enum mv88e6xxx_egress_direction direction = mirror->ingress ?
6596 MV88E6XXX_EGRESS_DIR_INGRESS :
6597 MV88E6XXX_EGRESS_DIR_EGRESS;
6598 struct mv88e6xxx_chip *chip = ds->priv;
6599 bool other_mirrors = false;
6600 int i;
6601
6602 mutex_lock(&chip->reg_lock);
6603 if (mv88e6xxx_port_set_mirror(chip, port, direction, false))
6604 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port);
6605
6606 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
6607 other_mirrors |= mirror->ingress ?
6608 chip->ports[i].mirror_ingress :
6609 chip->ports[i].mirror_egress;
6610
6611 /* Reset egress port when no other mirror is active */
6612 if (!other_mirrors) {
6613 if (mv88e6xxx_set_egress_port(chip, direction,
6614 dsa_upstream_port(ds, port)))
6615 dev_err(ds->dev, "failed to set egress port\n");
6616 }
6617
6618 mutex_unlock(&chip->reg_lock);
6619 }
6620
mv88e6xxx_port_pre_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)6621 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port,
6622 struct switchdev_brport_flags flags,
6623 struct netlink_ext_ack *extack)
6624 {
6625 struct mv88e6xxx_chip *chip = ds->priv;
6626 const struct mv88e6xxx_ops *ops;
6627
6628 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
6629 BR_BCAST_FLOOD | BR_PORT_LOCKED | BR_PORT_MAB))
6630 return -EINVAL;
6631
6632 ops = chip->info->ops;
6633
6634 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood)
6635 return -EINVAL;
6636
6637 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood)
6638 return -EINVAL;
6639
6640 return 0;
6641 }
6642
mv88e6xxx_port_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)6643 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port,
6644 struct switchdev_brport_flags flags,
6645 struct netlink_ext_ack *extack)
6646 {
6647 struct mv88e6xxx_chip *chip = ds->priv;
6648 int err = 0;
6649
6650 mv88e6xxx_reg_lock(chip);
6651
6652 if (flags.mask & BR_LEARNING) {
6653 bool learning = !!(flags.val & BR_LEARNING);
6654 u16 pav = learning ? (1 << port) : 0;
6655
6656 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav);
6657 if (err)
6658 goto out;
6659 }
6660
6661 if (flags.mask & BR_FLOOD) {
6662 bool unicast = !!(flags.val & BR_FLOOD);
6663
6664 err = chip->info->ops->port_set_ucast_flood(chip, port,
6665 unicast);
6666 if (err)
6667 goto out;
6668 }
6669
6670 if (flags.mask & BR_MCAST_FLOOD) {
6671 bool multicast = !!(flags.val & BR_MCAST_FLOOD);
6672
6673 err = chip->info->ops->port_set_mcast_flood(chip, port,
6674 multicast);
6675 if (err)
6676 goto out;
6677 }
6678
6679 if (flags.mask & BR_BCAST_FLOOD) {
6680 bool broadcast = !!(flags.val & BR_BCAST_FLOOD);
6681
6682 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast);
6683 if (err)
6684 goto out;
6685 }
6686
6687 if (flags.mask & BR_PORT_MAB) {
6688 bool mab = !!(flags.val & BR_PORT_MAB);
6689
6690 mv88e6xxx_port_set_mab(chip, port, mab);
6691 }
6692
6693 if (flags.mask & BR_PORT_LOCKED) {
6694 bool locked = !!(flags.val & BR_PORT_LOCKED);
6695
6696 err = mv88e6xxx_port_set_lock(chip, port, locked);
6697 if (err)
6698 goto out;
6699 }
6700 out:
6701 mv88e6xxx_reg_unlock(chip);
6702
6703 return err;
6704 }
6705
mv88e6xxx_lag_can_offload(struct dsa_switch * ds,struct dsa_lag lag,struct netdev_lag_upper_info * info,struct netlink_ext_ack * extack)6706 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds,
6707 struct dsa_lag lag,
6708 struct netdev_lag_upper_info *info,
6709 struct netlink_ext_ack *extack)
6710 {
6711 struct mv88e6xxx_chip *chip = ds->priv;
6712 struct dsa_port *dp;
6713 int members = 0;
6714
6715 if (!mv88e6xxx_has_lag(chip)) {
6716 NL_SET_ERR_MSG_MOD(extack, "Chip does not support LAG offload");
6717 return false;
6718 }
6719
6720 if (!lag.id)
6721 return false;
6722
6723 dsa_lag_foreach_port(dp, ds->dst, &lag)
6724 /* Includes the port joining the LAG */
6725 members++;
6726
6727 if (members > 8) {
6728 NL_SET_ERR_MSG_MOD(extack,
6729 "Cannot offload more than 8 LAG ports");
6730 return false;
6731 }
6732
6733 /* We could potentially relax this to include active
6734 * backup in the future.
6735 */
6736 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
6737 NL_SET_ERR_MSG_MOD(extack,
6738 "Can only offload LAG using hash TX type");
6739 return false;
6740 }
6741
6742 /* Ideally we would also validate that the hash type matches
6743 * the hardware. Alas, this is always set to unknown on team
6744 * interfaces.
6745 */
6746 return true;
6747 }
6748
mv88e6xxx_lag_sync_map(struct dsa_switch * ds,struct dsa_lag lag)6749 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct dsa_lag lag)
6750 {
6751 struct mv88e6xxx_chip *chip = ds->priv;
6752 struct dsa_port *dp;
6753 u16 map = 0;
6754 int id;
6755
6756 /* DSA LAG IDs are one-based, hardware is zero-based */
6757 id = lag.id - 1;
6758
6759 /* Build the map of all ports to distribute flows destined for
6760 * this LAG. This can be either a local user port, or a DSA
6761 * port if the LAG port is on a remote chip.
6762 */
6763 dsa_lag_foreach_port(dp, ds->dst, &lag)
6764 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index));
6765
6766 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map);
6767 }
6768
6769 static const u8 mv88e6xxx_lag_mask_table[8][8] = {
6770 /* Row number corresponds to the number of active members in a
6771 * LAG. Each column states which of the eight hash buckets are
6772 * mapped to the column:th port in the LAG.
6773 *
6774 * Example: In a LAG with three active ports, the second port
6775 * ([2][1]) would be selected for traffic mapped to buckets
6776 * 3,4,5 (0x38).
6777 */
6778 { 0xff, 0, 0, 0, 0, 0, 0, 0 },
6779 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 },
6780 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 },
6781 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 },
6782 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 },
6783 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 },
6784 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 },
6785 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 },
6786 };
6787
mv88e6xxx_lag_set_port_mask(u16 * mask,int port,int num_tx,int nth)6788 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port,
6789 int num_tx, int nth)
6790 {
6791 u8 active = 0;
6792 int i;
6793
6794 num_tx = num_tx <= 8 ? num_tx : 8;
6795 if (nth < num_tx)
6796 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth];
6797
6798 for (i = 0; i < 8; i++) {
6799 if (BIT(i) & active)
6800 mask[i] |= BIT(port);
6801 }
6802 }
6803
mv88e6xxx_lag_sync_masks(struct dsa_switch * ds)6804 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds)
6805 {
6806 struct mv88e6xxx_chip *chip = ds->priv;
6807 unsigned int id, num_tx;
6808 struct dsa_port *dp;
6809 struct dsa_lag *lag;
6810 int i, err, nth;
6811 u16 mask[8];
6812 u16 ivec;
6813
6814 /* Assume no port is a member of any LAG. */
6815 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1;
6816
6817 /* Disable all masks for ports that _are_ members of a LAG. */
6818 dsa_switch_for_each_port(dp, ds) {
6819 if (!dp->lag)
6820 continue;
6821
6822 ivec &= ~BIT(dp->index);
6823 }
6824
6825 for (i = 0; i < 8; i++)
6826 mask[i] = ivec;
6827
6828 /* Enable the correct subset of masks for all LAG ports that
6829 * are in the Tx set.
6830 */
6831 dsa_lags_foreach_id(id, ds->dst) {
6832 lag = dsa_lag_by_id(ds->dst, id);
6833 if (!lag)
6834 continue;
6835
6836 num_tx = 0;
6837 dsa_lag_foreach_port(dp, ds->dst, lag) {
6838 if (dp->lag_tx_enabled)
6839 num_tx++;
6840 }
6841
6842 if (!num_tx)
6843 continue;
6844
6845 nth = 0;
6846 dsa_lag_foreach_port(dp, ds->dst, lag) {
6847 if (!dp->lag_tx_enabled)
6848 continue;
6849
6850 if (dp->ds == ds)
6851 mv88e6xxx_lag_set_port_mask(mask, dp->index,
6852 num_tx, nth);
6853
6854 nth++;
6855 }
6856 }
6857
6858 for (i = 0; i < 8; i++) {
6859 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]);
6860 if (err)
6861 return err;
6862 }
6863
6864 return 0;
6865 }
6866
mv88e6xxx_lag_sync_masks_map(struct dsa_switch * ds,struct dsa_lag lag)6867 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds,
6868 struct dsa_lag lag)
6869 {
6870 int err;
6871
6872 err = mv88e6xxx_lag_sync_masks(ds);
6873
6874 if (!err)
6875 err = mv88e6xxx_lag_sync_map(ds, lag);
6876
6877 return err;
6878 }
6879
mv88e6xxx_port_lag_change(struct dsa_switch * ds,int port)6880 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port)
6881 {
6882 struct mv88e6xxx_chip *chip = ds->priv;
6883 int err;
6884
6885 mv88e6xxx_reg_lock(chip);
6886 err = mv88e6xxx_lag_sync_masks(ds);
6887 mv88e6xxx_reg_unlock(chip);
6888 return err;
6889 }
6890
mv88e6xxx_port_lag_join(struct dsa_switch * ds,int port,struct dsa_lag lag,struct netdev_lag_upper_info * info,struct netlink_ext_ack * extack)6891 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port,
6892 struct dsa_lag lag,
6893 struct netdev_lag_upper_info *info,
6894 struct netlink_ext_ack *extack)
6895 {
6896 struct mv88e6xxx_chip *chip = ds->priv;
6897 int err, id;
6898
6899 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack))
6900 return -EOPNOTSUPP;
6901
6902 /* DSA LAG IDs are one-based */
6903 id = lag.id - 1;
6904
6905 mv88e6xxx_reg_lock(chip);
6906
6907 err = mv88e6xxx_port_set_trunk(chip, port, true, id);
6908 if (err)
6909 goto err_unlock;
6910
6911 err = mv88e6xxx_lag_sync_masks_map(ds, lag);
6912 if (err)
6913 goto err_clear_trunk;
6914
6915 mv88e6xxx_reg_unlock(chip);
6916 return 0;
6917
6918 err_clear_trunk:
6919 mv88e6xxx_port_set_trunk(chip, port, false, 0);
6920 err_unlock:
6921 mv88e6xxx_reg_unlock(chip);
6922 return err;
6923 }
6924
mv88e6xxx_port_lag_leave(struct dsa_switch * ds,int port,struct dsa_lag lag)6925 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port,
6926 struct dsa_lag lag)
6927 {
6928 struct mv88e6xxx_chip *chip = ds->priv;
6929 int err_sync, err_trunk;
6930
6931 mv88e6xxx_reg_lock(chip);
6932 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
6933 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0);
6934 mv88e6xxx_reg_unlock(chip);
6935 return err_sync ? : err_trunk;
6936 }
6937
mv88e6xxx_crosschip_lag_change(struct dsa_switch * ds,int sw_index,int port)6938 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index,
6939 int port)
6940 {
6941 struct mv88e6xxx_chip *chip = ds->priv;
6942 int err;
6943
6944 mv88e6xxx_reg_lock(chip);
6945 err = mv88e6xxx_lag_sync_masks(ds);
6946 mv88e6xxx_reg_unlock(chip);
6947 return err;
6948 }
6949
mv88e6xxx_crosschip_lag_join(struct dsa_switch * ds,int sw_index,int port,struct dsa_lag lag,struct netdev_lag_upper_info * info,struct netlink_ext_ack * extack)6950 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index,
6951 int port, struct dsa_lag lag,
6952 struct netdev_lag_upper_info *info,
6953 struct netlink_ext_ack *extack)
6954 {
6955 struct mv88e6xxx_chip *chip = ds->priv;
6956 int err;
6957
6958 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack))
6959 return -EOPNOTSUPP;
6960
6961 mv88e6xxx_reg_lock(chip);
6962
6963 err = mv88e6xxx_lag_sync_masks_map(ds, lag);
6964 if (err)
6965 goto unlock;
6966
6967 err = mv88e6xxx_pvt_map(chip, sw_index, port);
6968
6969 unlock:
6970 mv88e6xxx_reg_unlock(chip);
6971 return err;
6972 }
6973
mv88e6xxx_crosschip_lag_leave(struct dsa_switch * ds,int sw_index,int port,struct dsa_lag lag)6974 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index,
6975 int port, struct dsa_lag lag)
6976 {
6977 struct mv88e6xxx_chip *chip = ds->priv;
6978 int err_sync, err_pvt;
6979
6980 mv88e6xxx_reg_lock(chip);
6981 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
6982 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port);
6983 mv88e6xxx_reg_unlock(chip);
6984 return err_sync ? : err_pvt;
6985 }
6986
6987 static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
6988 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
6989 .change_tag_protocol = mv88e6xxx_change_tag_protocol,
6990 .setup = mv88e6xxx_setup,
6991 .teardown = mv88e6xxx_teardown,
6992 .port_setup = mv88e6xxx_port_setup,
6993 .port_teardown = mv88e6xxx_port_teardown,
6994 .phylink_get_caps = mv88e6xxx_get_caps,
6995 .phylink_mac_select_pcs = mv88e6xxx_mac_select_pcs,
6996 .phylink_mac_prepare = mv88e6xxx_mac_prepare,
6997 .phylink_mac_config = mv88e6xxx_mac_config,
6998 .phylink_mac_finish = mv88e6xxx_mac_finish,
6999 .phylink_mac_link_down = mv88e6xxx_mac_link_down,
7000 .phylink_mac_link_up = mv88e6xxx_mac_link_up,
7001 .get_strings = mv88e6xxx_get_strings,
7002 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
7003 .get_sset_count = mv88e6xxx_get_sset_count,
7004 .port_max_mtu = mv88e6xxx_get_max_mtu,
7005 .port_change_mtu = mv88e6xxx_change_mtu,
7006 .get_mac_eee = mv88e6xxx_get_mac_eee,
7007 .set_mac_eee = mv88e6xxx_set_mac_eee,
7008 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
7009 .get_eeprom = mv88e6xxx_get_eeprom,
7010 .set_eeprom = mv88e6xxx_set_eeprom,
7011 .get_regs_len = mv88e6xxx_get_regs_len,
7012 .get_regs = mv88e6xxx_get_regs,
7013 .get_rxnfc = mv88e6xxx_get_rxnfc,
7014 .set_rxnfc = mv88e6xxx_set_rxnfc,
7015 .set_ageing_time = mv88e6xxx_set_ageing_time,
7016 .port_bridge_join = mv88e6xxx_port_bridge_join,
7017 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
7018 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags,
7019 .port_bridge_flags = mv88e6xxx_port_bridge_flags,
7020 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
7021 .port_mst_state_set = mv88e6xxx_port_mst_state_set,
7022 .port_fast_age = mv88e6xxx_port_fast_age,
7023 .port_vlan_fast_age = mv88e6xxx_port_vlan_fast_age,
7024 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
7025 .port_vlan_add = mv88e6xxx_port_vlan_add,
7026 .port_vlan_del = mv88e6xxx_port_vlan_del,
7027 .vlan_msti_set = mv88e6xxx_vlan_msti_set,
7028 .port_fdb_add = mv88e6xxx_port_fdb_add,
7029 .port_fdb_del = mv88e6xxx_port_fdb_del,
7030 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
7031 .port_mdb_add = mv88e6xxx_port_mdb_add,
7032 .port_mdb_del = mv88e6xxx_port_mdb_del,
7033 .port_mirror_add = mv88e6xxx_port_mirror_add,
7034 .port_mirror_del = mv88e6xxx_port_mirror_del,
7035 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
7036 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
7037 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set,
7038 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get,
7039 .port_txtstamp = mv88e6xxx_port_txtstamp,
7040 .port_rxtstamp = mv88e6xxx_port_rxtstamp,
7041 .get_ts_info = mv88e6xxx_get_ts_info,
7042 .devlink_param_get = mv88e6xxx_devlink_param_get,
7043 .devlink_param_set = mv88e6xxx_devlink_param_set,
7044 .devlink_info_get = mv88e6xxx_devlink_info_get,
7045 .port_lag_change = mv88e6xxx_port_lag_change,
7046 .port_lag_join = mv88e6xxx_port_lag_join,
7047 .port_lag_leave = mv88e6xxx_port_lag_leave,
7048 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change,
7049 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join,
7050 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave,
7051 };
7052
mv88e6xxx_register_switch(struct mv88e6xxx_chip * chip)7053 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
7054 {
7055 struct device *dev = chip->dev;
7056 struct dsa_switch *ds;
7057
7058 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
7059 if (!ds)
7060 return -ENOMEM;
7061
7062 ds->dev = dev;
7063 ds->num_ports = mv88e6xxx_num_ports(chip);
7064 ds->priv = chip;
7065 ds->dev = dev;
7066 ds->ops = &mv88e6xxx_switch_ops;
7067 ds->ageing_time_min = chip->info->age_time_coeff;
7068 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
7069
7070 /* Some chips support up to 32, but that requires enabling the
7071 * 5-bit port mode, which we do not support. 640k^W16 ought to
7072 * be enough for anyone.
7073 */
7074 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0;
7075
7076 dev_set_drvdata(dev, ds);
7077
7078 return dsa_register_switch(ds);
7079 }
7080
mv88e6xxx_unregister_switch(struct mv88e6xxx_chip * chip)7081 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
7082 {
7083 dsa_unregister_switch(chip->ds);
7084 }
7085
pdata_device_get_match_data(struct device * dev)7086 static const void *pdata_device_get_match_data(struct device *dev)
7087 {
7088 const struct of_device_id *matches = dev->driver->of_match_table;
7089 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;
7090
7091 for (; matches->name[0] || matches->type[0] || matches->compatible[0];
7092 matches++) {
7093 if (!strcmp(pdata->compatible, matches->compatible))
7094 return matches->data;
7095 }
7096 return NULL;
7097 }
7098
7099 /* There is no suspend to RAM support at DSA level yet, the switch configuration
7100 * would be lost after a power cycle so prevent it to be suspended.
7101 */
mv88e6xxx_suspend(struct device * dev)7102 static int __maybe_unused mv88e6xxx_suspend(struct device *dev)
7103 {
7104 return -EOPNOTSUPP;
7105 }
7106
mv88e6xxx_resume(struct device * dev)7107 static int __maybe_unused mv88e6xxx_resume(struct device *dev)
7108 {
7109 return 0;
7110 }
7111
7112 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume);
7113
mv88e6xxx_probe(struct mdio_device * mdiodev)7114 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
7115 {
7116 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
7117 const struct mv88e6xxx_info *compat_info = NULL;
7118 struct device *dev = &mdiodev->dev;
7119 struct device_node *np = dev->of_node;
7120 struct mv88e6xxx_chip *chip;
7121 int port;
7122 int err;
7123
7124 if (!np && !pdata)
7125 return -EINVAL;
7126
7127 if (np)
7128 compat_info = of_device_get_match_data(dev);
7129
7130 if (pdata) {
7131 compat_info = pdata_device_get_match_data(dev);
7132
7133 if (!pdata->netdev)
7134 return -EINVAL;
7135
7136 for (port = 0; port < DSA_MAX_PORTS; port++) {
7137 if (!(pdata->enabled_ports & (1 << port)))
7138 continue;
7139 if (strcmp(pdata->cd.port_names[port], "cpu"))
7140 continue;
7141 pdata->cd.netdev[port] = &pdata->netdev->dev;
7142 break;
7143 }
7144 }
7145
7146 if (!compat_info)
7147 return -EINVAL;
7148
7149 chip = mv88e6xxx_alloc_chip(dev);
7150 if (!chip) {
7151 err = -ENOMEM;
7152 goto out;
7153 }
7154
7155 chip->info = compat_info;
7156
7157 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
7158 if (IS_ERR(chip->reset)) {
7159 err = PTR_ERR(chip->reset);
7160 goto out;
7161 }
7162 if (chip->reset)
7163 usleep_range(10000, 20000);
7164
7165 /* Detect if the device is configured in single chip addressing mode,
7166 * otherwise continue with address specific smi init/detection.
7167 */
7168 err = mv88e6xxx_single_chip_detect(chip, mdiodev);
7169 if (err) {
7170 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
7171 if (err)
7172 goto out;
7173
7174 err = mv88e6xxx_detect(chip);
7175 if (err)
7176 goto out;
7177 }
7178
7179 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED)
7180 chip->tag_protocol = DSA_TAG_PROTO_EDSA;
7181 else
7182 chip->tag_protocol = DSA_TAG_PROTO_DSA;
7183
7184 mv88e6xxx_phy_init(chip);
7185
7186 if (chip->info->ops->get_eeprom) {
7187 if (np)
7188 of_property_read_u32(np, "eeprom-length",
7189 &chip->eeprom_len);
7190 else
7191 chip->eeprom_len = pdata->eeprom_len;
7192 }
7193
7194 mv88e6xxx_reg_lock(chip);
7195 err = mv88e6xxx_switch_reset(chip);
7196 mv88e6xxx_reg_unlock(chip);
7197 if (err)
7198 goto out_phy;
7199
7200 if (np) {
7201 chip->irq = of_irq_get(np, 0);
7202 if (chip->irq == -EPROBE_DEFER) {
7203 err = chip->irq;
7204 goto out_phy;
7205 }
7206 }
7207
7208 if (pdata)
7209 chip->irq = pdata->irq;
7210
7211 /* Has to be performed before the MDIO bus is created, because
7212 * the PHYs will link their interrupts to these interrupt
7213 * controllers
7214 */
7215 mv88e6xxx_reg_lock(chip);
7216 if (chip->irq > 0)
7217 err = mv88e6xxx_g1_irq_setup(chip);
7218 else
7219 err = mv88e6xxx_irq_poll_setup(chip);
7220 mv88e6xxx_reg_unlock(chip);
7221
7222 if (err)
7223 goto out_phy;
7224
7225 if (chip->info->g2_irqs > 0) {
7226 err = mv88e6xxx_g2_irq_setup(chip);
7227 if (err)
7228 goto out_g1_irq;
7229 }
7230
7231 err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
7232 if (err)
7233 goto out_g2_irq;
7234
7235 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
7236 if (err)
7237 goto out_g1_atu_prob_irq;
7238
7239 err = mv88e6xxx_register_switch(chip);
7240 if (err)
7241 goto out_g1_vtu_prob_irq;
7242
7243 return 0;
7244
7245 out_g1_vtu_prob_irq:
7246 mv88e6xxx_g1_vtu_prob_irq_free(chip);
7247 out_g1_atu_prob_irq:
7248 mv88e6xxx_g1_atu_prob_irq_free(chip);
7249 out_g2_irq:
7250 if (chip->info->g2_irqs > 0)
7251 mv88e6xxx_g2_irq_free(chip);
7252 out_g1_irq:
7253 if (chip->irq > 0)
7254 mv88e6xxx_g1_irq_free(chip);
7255 else
7256 mv88e6xxx_irq_poll_free(chip);
7257 out_phy:
7258 mv88e6xxx_phy_destroy(chip);
7259 out:
7260 if (pdata)
7261 dev_put(pdata->netdev);
7262
7263 return err;
7264 }
7265
mv88e6xxx_remove(struct mdio_device * mdiodev)7266 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
7267 {
7268 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
7269 struct mv88e6xxx_chip *chip;
7270
7271 if (!ds)
7272 return;
7273
7274 chip = ds->priv;
7275
7276 if (chip->info->ptp_support) {
7277 mv88e6xxx_hwtstamp_free(chip);
7278 mv88e6xxx_ptp_free(chip);
7279 }
7280
7281 mv88e6xxx_unregister_switch(chip);
7282
7283 mv88e6xxx_g1_vtu_prob_irq_free(chip);
7284 mv88e6xxx_g1_atu_prob_irq_free(chip);
7285
7286 if (chip->info->g2_irqs > 0)
7287 mv88e6xxx_g2_irq_free(chip);
7288
7289 if (chip->irq > 0)
7290 mv88e6xxx_g1_irq_free(chip);
7291 else
7292 mv88e6xxx_irq_poll_free(chip);
7293
7294 mv88e6xxx_phy_destroy(chip);
7295 }
7296
mv88e6xxx_shutdown(struct mdio_device * mdiodev)7297 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev)
7298 {
7299 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
7300
7301 if (!ds)
7302 return;
7303
7304 dsa_switch_shutdown(ds);
7305
7306 dev_set_drvdata(&mdiodev->dev, NULL);
7307 }
7308
7309 static const struct of_device_id mv88e6xxx_of_match[] = {
7310 {
7311 .compatible = "marvell,mv88e6085",
7312 .data = &mv88e6xxx_table[MV88E6085],
7313 },
7314 {
7315 .compatible = "marvell,mv88e6190",
7316 .data = &mv88e6xxx_table[MV88E6190],
7317 },
7318 {
7319 .compatible = "marvell,mv88e6250",
7320 .data = &mv88e6xxx_table[MV88E6250],
7321 },
7322 { /* sentinel */ },
7323 };
7324
7325 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
7326
7327 static struct mdio_driver mv88e6xxx_driver = {
7328 .probe = mv88e6xxx_probe,
7329 .remove = mv88e6xxx_remove,
7330 .shutdown = mv88e6xxx_shutdown,
7331 .mdiodrv.driver = {
7332 .name = "mv88e6085",
7333 .of_match_table = mv88e6xxx_of_match,
7334 .pm = &mv88e6xxx_pm_ops,
7335 },
7336 };
7337
7338 mdio_module_driver(mv88e6xxx_driver);
7339
7340 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
7341 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
7342 MODULE_LICENSE("GPL");
7343