1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
4 *
5 * Based on original Kirkwood support which is
6 * (C) Copyright 2009
7 * Marvell Semiconductor <www.marvell.com>
8 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
9 */
10
11 #include <common.h>
12 #include <netdev.h>
13 #include <asm/cache.h>
14 #include <asm/io.h>
15 #include <u-boot/md5.h>
16 #include <asm/arch/cpu.h>
17
18 #define BUFLEN 16
19
reset_cpu(unsigned long ignored)20 void reset_cpu(unsigned long ignored)
21 {
22 struct orion5x_cpu_registers *cpureg =
23 (struct orion5x_cpu_registers *)ORION5X_CPU_REG_BASE;
24
25 writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
26 &cpureg->rstoutn_mask);
27 writel(readl(&cpureg->sys_soft_rst) | 1,
28 &cpureg->sys_soft_rst);
29 while (1)
30 ;
31 }
32
33 /*
34 * Compute Window Size field value from size expressed in bytes
35 * Used with the Base register to set the address window size and location.
36 * Must be programmed from LSB to MSB as sequence of ones followed by
37 * sequence of zeros. The number of ones specifies the size of the window in
38 * 64 KiB granularity (e.g., a value of 0x00FF specifies 256 = 16 MiB).
39 * NOTES:
40 * 1) A sizeval equal to 0x0 specifies 4 GiB.
41 * 2) A return value of 0x0 specifies 64 KiB.
42 */
orion5x_winctrl_calcsize(unsigned int sizeval)43 unsigned int orion5x_winctrl_calcsize(unsigned int sizeval)
44 {
45 /*
46 * Calculate the number of 64 KiB blocks needed minus one (rounding up).
47 * For sizeval > 0 this is equivalent to:
48 * sizeval = (u32) ceil((double) sizeval / 65536.0) - 1
49 */
50 sizeval = (sizeval - 1) >> 16;
51
52 /*
53 * Propagate 'one' bits to the right by 'oring' them.
54 * We need only treat bits 15-0.
55 */
56 sizeval |= sizeval >> 1; /* 'Or' bit 15 onto bit 14 */
57 sizeval |= sizeval >> 2; /* 'Or' bits 15-14 onto bits 13-12 */
58 sizeval |= sizeval >> 4; /* 'Or' bits 15-12 onto bits 11-8 */
59 sizeval |= sizeval >> 8; /* 'Or' bits 15-8 onto bits 7-0*/
60
61 return sizeval;
62 }
63
64 /*
65 * orion5x_config_adr_windows - Configure address Windows
66 *
67 * There are 8 address windows supported by Orion5x Soc to addess different
68 * devices. Each window can be configured for size, BAR and remap addr
69 * Below configuration is standard for most of the cases
70 *
71 * If remap function not used, remap_lo must be set as base
72 *
73 * NOTES:
74 *
75 * 1) in order to avoid windows with inconsistent control and base values
76 * (which could prevent access to BOOTCS and hence execution from FLASH)
77 * always disable window before writing the base value then reenable it
78 * by writing the control value.
79 *
80 * 2) in order to avoid losing access to BOOTCS when disabling window 7,
81 * first configure window 6 for BOOTCS, then configure window 7 for BOOTCS,
82 * then configure windows 6 for its own target.
83 *
84 * Reference Documentation:
85 * Mbus-L to Mbus Bridge Registers Configuration.
86 * (Sec 25.1 and 25.3 of Datasheet)
87 */
orion5x_config_adr_windows(void)88 int orion5x_config_adr_windows(void)
89 {
90 struct orion5x_win_registers *winregs =
91 (struct orion5x_win_registers *)ORION5X_CPU_WIN_BASE;
92
93 /* Disable window 0, configure it for its intended target, enable it. */
94 writel(0, &winregs[0].ctrl);
95 writel(ORION5X_ADR_PCIE_MEM, &winregs[0].base);
96 writel(ORION5X_ADR_PCIE_MEM_REMAP_LO, &winregs[0].remap_lo);
97 writel(ORION5X_ADR_PCIE_MEM_REMAP_HI, &winregs[0].remap_hi);
98 writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_MEM,
99 ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_MEM,
100 ORION5X_WIN_ENABLE), &winregs[0].ctrl);
101 /* Disable window 1, configure it for its intended target, enable it. */
102 writel(0, &winregs[1].ctrl);
103 writel(ORION5X_ADR_PCIE_IO, &winregs[1].base);
104 writel(ORION5X_ADR_PCIE_IO_REMAP_LO, &winregs[1].remap_lo);
105 writel(ORION5X_ADR_PCIE_IO_REMAP_HI, &winregs[1].remap_hi);
106 writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_IO,
107 ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_IO,
108 ORION5X_WIN_ENABLE), &winregs[1].ctrl);
109 /* Disable window 2, configure it for its intended target, enable it. */
110 writel(0, &winregs[2].ctrl);
111 writel(ORION5X_ADR_PCI_MEM, &winregs[2].base);
112 writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_MEM,
113 ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_MEM,
114 ORION5X_WIN_ENABLE), &winregs[2].ctrl);
115 /* Disable window 3, configure it for its intended target, enable it. */
116 writel(0, &winregs[3].ctrl);
117 writel(ORION5X_ADR_PCI_IO, &winregs[3].base);
118 writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_IO,
119 ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_IO,
120 ORION5X_WIN_ENABLE), &winregs[3].ctrl);
121 /* Disable window 4, configure it for its intended target, enable it. */
122 writel(0, &winregs[4].ctrl);
123 writel(ORION5X_ADR_DEV_CS0, &winregs[4].base);
124 writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS0,
125 ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS0,
126 ORION5X_WIN_ENABLE), &winregs[4].ctrl);
127 /* Disable window 5, configure it for its intended target, enable it. */
128 writel(0, &winregs[5].ctrl);
129 writel(ORION5X_ADR_DEV_CS1, &winregs[5].base);
130 writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS1,
131 ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS1,
132 ORION5X_WIN_ENABLE), &winregs[5].ctrl);
133 /* Disable window 6, configure it for FLASH, enable it. */
134 writel(0, &winregs[6].ctrl);
135 writel(ORION5X_ADR_BOOTROM, &winregs[6].base);
136 writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM,
137 ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM,
138 ORION5X_WIN_ENABLE), &winregs[6].ctrl);
139 /* Disable window 7, configure it for FLASH, enable it. */
140 writel(0, &winregs[7].ctrl);
141 writel(ORION5X_ADR_BOOTROM, &winregs[7].base);
142 writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM,
143 ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM,
144 ORION5X_WIN_ENABLE), &winregs[7].ctrl);
145 /* Disable window 6, configure it for its intended target, enable it. */
146 writel(0, &winregs[6].ctrl);
147 writel(ORION5X_ADR_DEV_CS2, &winregs[6].base);
148 writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS2,
149 ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS2,
150 ORION5X_WIN_ENABLE), &winregs[6].ctrl);
151
152 return 0;
153 }
154
155 /*
156 * Orion5x identification is done through PCIE space.
157 */
158
orion5x_device_id(void)159 u32 orion5x_device_id(void)
160 {
161 return readl(PCIE_DEV_ID_OFF) >> 16;
162 }
163
orion5x_device_rev(void)164 u32 orion5x_device_rev(void)
165 {
166 return readl(PCIE_DEV_REV_OFF) & 0xff;
167 }
168
169 #if defined(CONFIG_DISPLAY_CPUINFO)
170
171 /* Display device and revision IDs.
172 * This function must cover all known device/revision
173 * combinations, not only the one for which u-boot is
174 * compiled; this way, one can identify actual HW in
175 * case of a mismatch.
176 */
print_cpuinfo(void)177 int print_cpuinfo(void)
178 {
179 char dev_str[7]; /* room enough for 0x0000 plus null byte */
180 char rev_str[5]; /* room enough for 0x00 plus null byte */
181 char *dev_name = NULL;
182 char *rev_name = NULL;
183
184 u32 dev = orion5x_device_id();
185 u32 rev = orion5x_device_rev();
186
187 if (dev == MV88F5181_DEV_ID) {
188 dev_name = "MV88F5181";
189 if (rev == MV88F5181_REV_B1)
190 rev_name = "B1";
191 else if (rev == MV88F5181L_REV_A1) {
192 dev_name = "MV88F5181L";
193 rev_name = "A1";
194 } else if (rev == MV88F5181L_REV_A0) {
195 dev_name = "MV88F5181L";
196 rev_name = "A0";
197 }
198 } else if (dev == MV88F5182_DEV_ID) {
199 dev_name = "MV88F5182";
200 if (rev == MV88F5182_REV_A2)
201 rev_name = "A2";
202 } else if (dev == MV88F5281_DEV_ID) {
203 dev_name = "MV88F5281";
204 if (rev == MV88F5281_REV_D2)
205 rev_name = "D2";
206 else if (rev == MV88F5281_REV_D1)
207 rev_name = "D1";
208 else if (rev == MV88F5281_REV_D0)
209 rev_name = "D0";
210 } else if (dev == MV88F6183_DEV_ID) {
211 dev_name = "MV88F6183";
212 if (rev == MV88F6183_REV_B0)
213 rev_name = "B0";
214 }
215 if (dev_name == NULL) {
216 sprintf(dev_str, "0x%04x", dev);
217 dev_name = dev_str;
218 }
219 if (rev_name == NULL) {
220 sprintf(rev_str, "0x%02x", rev);
221 rev_name = rev_str;
222 }
223
224 printf("SoC: Orion5x %s-%s\n", dev_name, rev_name);
225
226 return 0;
227 }
228 #endif /* CONFIG_DISPLAY_CPUINFO */
229
230 #ifdef CONFIG_ARCH_CPU_INIT
arch_cpu_init(void)231 int arch_cpu_init(void)
232 {
233 /* Enable and invalidate L2 cache in write through mode */
234 invalidate_l2_cache();
235
236 #ifdef CONFIG_SPL_BUILD
237 orion5x_config_adr_windows();
238 #endif
239
240 return 0;
241 }
242 #endif /* CONFIG_ARCH_CPU_INIT */
243
244 /*
245 * SOC specific misc init
246 */
247 #if defined(CONFIG_ARCH_MISC_INIT)
arch_misc_init(void)248 int arch_misc_init(void)
249 {
250 u32 temp;
251
252 /*CPU streaming & write allocate */
253 temp = readfr_extra_feature_reg();
254 temp &= ~(1 << 28); /* disable wr alloc */
255 writefr_extra_feature_reg(temp);
256
257 temp = readfr_extra_feature_reg();
258 temp &= ~(1 << 29); /* streaming disabled */
259 writefr_extra_feature_reg(temp);
260
261 /* L2Cache settings */
262 temp = readfr_extra_feature_reg();
263 /* Disable L2C pre fetch - Set bit 24 */
264 temp |= (1 << 24);
265 /* enable L2C - Set bit 22 */
266 temp |= (1 << 22);
267 writefr_extra_feature_reg(temp);
268
269 icache_enable();
270 /* Change reset vector to address 0x0 */
271 temp = get_cr();
272 set_cr(temp & ~CR_V);
273
274 /* Set CPIOs and MPPs - values provided by board
275 include file */
276 writel(ORION5X_MPP0_7, ORION5X_MPP_BASE+0x00);
277 writel(ORION5X_MPP8_15, ORION5X_MPP_BASE+0x04);
278 writel(ORION5X_MPP16_23, ORION5X_MPP_BASE+0x50);
279 writel(ORION5X_GPIO_OUT_VALUE, ORION5X_GPIO_BASE+0x00);
280 writel(ORION5X_GPIO_OUT_ENABLE, ORION5X_GPIO_BASE+0x04);
281 writel(ORION5X_GPIO_IN_POLARITY, ORION5X_GPIO_BASE+0x0c);
282
283 /* initialize timer */
284 timer_init_r();
285 return 0;
286 }
287 #endif /* CONFIG_ARCH_MISC_INIT */
288
289 #ifdef CONFIG_MVGBE
cpu_eth_init(bd_t * bis)290 int cpu_eth_init(bd_t *bis)
291 {
292 mvgbe_initialize(bis);
293 return 0;
294 }
295 #endif
296