1 /*
2  * Copyright 2022 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 /* FILE POLICY AND INTENDED USAGE:
27  * This file implements dp specific link capability retrieval sequence. It is
28  * responsible for retrieving, parsing, overriding, deciding capability obtained
29  * from dp link. Link capability consists of encoders, DPRXs, cables, retimers,
30  * usb and all other possible backend capabilities. Other components should
31  * include this header file in order to access link capability. Accessing link
32  * capability by dereferencing dc_link outside dp_link_capability is not a
33  * recommended method as it makes the component dependent on the underlying data
34  * structure used to represent link capability instead of function interfaces.
35  */
36 
37 #include "link_dp_capability.h"
38 #include "link_ddc.h"
39 #include "link_dpcd.h"
40 #include "link_dp_dpia.h"
41 #include "link_dp_phy.h"
42 #include "link_edp_panel_control.h"
43 #include "link_dp_irq_handler.h"
44 #include "link/accessories/link_dp_trace.h"
45 #include "link/link_detection.h"
46 #include "link/link_validation.h"
47 #include "link_dp_training.h"
48 #include "atomfirmware.h"
49 #include "resource.h"
50 #include "link_enc_cfg.h"
51 #include "dc_dmub_srv.h"
52 #include "gpio_service_interface.h"
53 
54 #define DC_LOGGER \
55 	link->ctx->logger
56 #define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
57 
58 #ifndef MAX
59 #define MAX(X, Y) ((X) > (Y) ? (X) : (Y))
60 #endif
61 #ifndef MIN
62 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
63 #endif
64 
65 struct dp_lt_fallback_entry {
66 	enum dc_lane_count lane_count;
67 	enum dc_link_rate link_rate;
68 };
69 
70 static const struct dp_lt_fallback_entry dp_lt_fallbacks[] = {
71 		/* This link training fallback array is ordered by
72 		 * link bandwidth from highest to lowest.
73 		 * DP specs makes it a normative policy to always
74 		 * choose the next highest link bandwidth during
75 		 * link training fallback.
76 		 */
77 		{LANE_COUNT_FOUR, LINK_RATE_UHBR20},
78 		{LANE_COUNT_FOUR, LINK_RATE_UHBR13_5},
79 		{LANE_COUNT_TWO, LINK_RATE_UHBR20},
80 		{LANE_COUNT_FOUR, LINK_RATE_UHBR10},
81 		{LANE_COUNT_TWO, LINK_RATE_UHBR13_5},
82 		{LANE_COUNT_FOUR, LINK_RATE_HIGH3},
83 		{LANE_COUNT_ONE, LINK_RATE_UHBR20},
84 		{LANE_COUNT_TWO, LINK_RATE_UHBR10},
85 		{LANE_COUNT_FOUR, LINK_RATE_HIGH2},
86 		{LANE_COUNT_ONE, LINK_RATE_UHBR13_5},
87 		{LANE_COUNT_TWO, LINK_RATE_HIGH3},
88 		{LANE_COUNT_ONE, LINK_RATE_UHBR10},
89 		{LANE_COUNT_TWO, LINK_RATE_HIGH2},
90 		{LANE_COUNT_FOUR, LINK_RATE_HIGH},
91 		{LANE_COUNT_ONE, LINK_RATE_HIGH3},
92 		{LANE_COUNT_FOUR, LINK_RATE_LOW},
93 		{LANE_COUNT_ONE, LINK_RATE_HIGH2},
94 		{LANE_COUNT_TWO, LINK_RATE_HIGH},
95 		{LANE_COUNT_TWO, LINK_RATE_LOW},
96 		{LANE_COUNT_ONE, LINK_RATE_HIGH},
97 		{LANE_COUNT_ONE, LINK_RATE_LOW},
98 };
99 
100 static const struct dc_link_settings fail_safe_link_settings = {
101 		.lane_count = LANE_COUNT_ONE,
102 		.link_rate = LINK_RATE_LOW,
103 		.link_spread = LINK_SPREAD_DISABLED,
104 };
105 
is_dp_active_dongle(const struct dc_link * link)106 bool is_dp_active_dongle(const struct dc_link *link)
107 {
108 	return (link->dpcd_caps.dongle_type >= DISPLAY_DONGLE_DP_VGA_CONVERTER) &&
109 				(link->dpcd_caps.dongle_type <= DISPLAY_DONGLE_DP_HDMI_CONVERTER);
110 }
111 
is_dp_branch_device(const struct dc_link * link)112 bool is_dp_branch_device(const struct dc_link *link)
113 {
114 	return link->dpcd_caps.is_branch_dev;
115 }
116 
translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)117 static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)
118 {
119 	switch (bpc) {
120 	case DOWN_STREAM_MAX_8BPC:
121 		return 8;
122 	case DOWN_STREAM_MAX_10BPC:
123 		return 10;
124 	case DOWN_STREAM_MAX_12BPC:
125 		return 12;
126 	case DOWN_STREAM_MAX_16BPC:
127 		return 16;
128 	default:
129 		break;
130 	}
131 
132 	return -1;
133 }
134 
dp_parse_lttpr_repeater_count(uint8_t lttpr_repeater_count)135 uint8_t dp_parse_lttpr_repeater_count(uint8_t lttpr_repeater_count)
136 {
137 	switch (lttpr_repeater_count) {
138 	case 0x80: // 1 lttpr repeater
139 		return 1;
140 	case 0x40: // 2 lttpr repeaters
141 		return 2;
142 	case 0x20: // 3 lttpr repeaters
143 		return 3;
144 	case 0x10: // 4 lttpr repeaters
145 		return 4;
146 	case 0x08: // 5 lttpr repeaters
147 		return 5;
148 	case 0x04: // 6 lttpr repeaters
149 		return 6;
150 	case 0x02: // 7 lttpr repeaters
151 		return 7;
152 	case 0x01: // 8 lttpr repeaters
153 		return 8;
154 	default:
155 		break;
156 	}
157 	return 0; // invalid value
158 }
159 
link_bw_kbps_from_raw_frl_link_rate_data(uint8_t bw)160 uint32_t link_bw_kbps_from_raw_frl_link_rate_data(uint8_t bw)
161 {
162 	switch (bw) {
163 	case 0b001:
164 		return 9000000;
165 	case 0b010:
166 		return 18000000;
167 	case 0b011:
168 		return 24000000;
169 	case 0b100:
170 		return 32000000;
171 	case 0b101:
172 		return 40000000;
173 	case 0b110:
174 		return 48000000;
175 	}
176 
177 	return 0;
178 }
179 
linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz)180 static enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz)
181 {
182 	enum dc_link_rate link_rate;
183 	// LinkRate is normally stored as a multiplier of 0.27 Gbps per lane. Do the translation.
184 	switch (link_rate_in_khz) {
185 	case 1620000:
186 		link_rate = LINK_RATE_LOW;	// Rate_1 (RBR)	- 1.62 Gbps/Lane
187 		break;
188 	case 2160000:
189 		link_rate = LINK_RATE_RATE_2;	// Rate_2	- 2.16 Gbps/Lane
190 		break;
191 	case 2430000:
192 		link_rate = LINK_RATE_RATE_3;	// Rate_3	- 2.43 Gbps/Lane
193 		break;
194 	case 2700000:
195 		link_rate = LINK_RATE_HIGH;	// Rate_4 (HBR)	- 2.70 Gbps/Lane
196 		break;
197 	case 3240000:
198 		link_rate = LINK_RATE_RBR2;	// Rate_5 (RBR2)- 3.24 Gbps/Lane
199 		break;
200 	case 4320000:
201 		link_rate = LINK_RATE_RATE_6;	// Rate_6	- 4.32 Gbps/Lane
202 		break;
203 	case 5400000:
204 		link_rate = LINK_RATE_HIGH2;	// Rate_7 (HBR2)- 5.40 Gbps/Lane
205 		break;
206 	case 6750000:
207 		link_rate = LINK_RATE_RATE_8;	// Rate_8	- 6.75 Gbps/Lane
208 		break;
209 	case 8100000:
210 		link_rate = LINK_RATE_HIGH3;	// Rate_9 (HBR3)- 8.10 Gbps/Lane
211 		break;
212 	default:
213 		link_rate = LINK_RATE_UNKNOWN;
214 		break;
215 	}
216 	return link_rate;
217 }
218 
intersect_cable_id(union dp_cable_id * a,union dp_cable_id * b)219 static union dp_cable_id intersect_cable_id(
220 		union dp_cable_id *a, union dp_cable_id *b)
221 {
222 	union dp_cable_id out;
223 
224 	out.bits.UHBR10_20_CAPABILITY = MIN(a->bits.UHBR10_20_CAPABILITY,
225 			b->bits.UHBR10_20_CAPABILITY);
226 	out.bits.UHBR13_5_CAPABILITY = MIN(a->bits.UHBR13_5_CAPABILITY,
227 			b->bits.UHBR13_5_CAPABILITY);
228 	out.bits.CABLE_TYPE = MAX(a->bits.CABLE_TYPE, b->bits.CABLE_TYPE);
229 
230 	return out;
231 }
232 
233 /*
234  * Return PCON's post FRL link training supported BW if its non-zero, otherwise return max_supported_frl_bw.
235  */
intersect_frl_link_bw_support(const uint32_t max_supported_frl_bw_in_kbps,const union hdmi_encoded_link_bw hdmi_encoded_link_bw)236 static uint32_t intersect_frl_link_bw_support(
237 	const uint32_t max_supported_frl_bw_in_kbps,
238 	const union hdmi_encoded_link_bw hdmi_encoded_link_bw)
239 {
240 	uint32_t supported_bw_in_kbps = max_supported_frl_bw_in_kbps;
241 
242 	// HDMI_ENCODED_LINK_BW bits are only valid if HDMI Link Configuration bit is 1 (FRL mode)
243 	if (hdmi_encoded_link_bw.bits.FRL_MODE) {
244 		if (hdmi_encoded_link_bw.bits.BW_48Gbps)
245 			supported_bw_in_kbps = 48000000;
246 		else if (hdmi_encoded_link_bw.bits.BW_40Gbps)
247 			supported_bw_in_kbps = 40000000;
248 		else if (hdmi_encoded_link_bw.bits.BW_32Gbps)
249 			supported_bw_in_kbps = 32000000;
250 		else if (hdmi_encoded_link_bw.bits.BW_24Gbps)
251 			supported_bw_in_kbps = 24000000;
252 		else if (hdmi_encoded_link_bw.bits.BW_18Gbps)
253 			supported_bw_in_kbps = 18000000;
254 		else if (hdmi_encoded_link_bw.bits.BW_9Gbps)
255 			supported_bw_in_kbps = 9000000;
256 	}
257 
258 	return supported_bw_in_kbps;
259 }
260 
get_clock_source_id(struct dc_link * link)261 static enum clock_source_id get_clock_source_id(struct dc_link *link)
262 {
263 	enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_UNDEFINED;
264 	struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source;
265 
266 	if (dp_cs != NULL) {
267 		dp_cs_id = dp_cs->id;
268 	} else {
269 		/*
270 		 * dp clock source is not initialized for some reason.
271 		 * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
272 		 */
273 		ASSERT(dp_cs);
274 	}
275 
276 	return dp_cs_id;
277 }
278 
dp_wa_power_up_0010FA(struct dc_link * link,uint8_t * dpcd_data,int length)279 static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
280 		int length)
281 {
282 	int retry = 0;
283 
284 	if (!link->dpcd_caps.dpcd_rev.raw) {
285 		do {
286 			dpcd_write_rx_power_ctrl(link, true);
287 			core_link_read_dpcd(link, DP_DPCD_REV,
288 							dpcd_data, length);
289 			link->dpcd_caps.dpcd_rev.raw = dpcd_data[
290 				DP_DPCD_REV -
291 				DP_DPCD_REV];
292 		} while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
293 	}
294 
295 	if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
296 		switch (link->dpcd_caps.branch_dev_id) {
297 		/* 0010FA active dongles (DP-VGA, DP-DLDVI converters) power down
298 		 * all internal circuits including AUX communication preventing
299 		 * reading DPCD table and EDID (spec violation).
300 		 * Encoder will skip DP RX power down on disable_output to
301 		 * keep receiver powered all the time.*/
302 		case DP_BRANCH_DEVICE_ID_0010FA:
303 		case DP_BRANCH_DEVICE_ID_0080E1:
304 		case DP_BRANCH_DEVICE_ID_00E04C:
305 			link->wa_flags.dp_keep_receiver_powered = true;
306 			break;
307 
308 		/* TODO: May need work around for other dongles. */
309 		default:
310 			link->wa_flags.dp_keep_receiver_powered = false;
311 			break;
312 		}
313 	} else
314 		link->wa_flags.dp_keep_receiver_powered = false;
315 }
316 
dp_is_fec_supported(const struct dc_link * link)317 bool dp_is_fec_supported(const struct dc_link *link)
318 {
319 	/* TODO - use asic cap instead of link_enc->features
320 	 * we no longer know which link enc to use for this link before commit
321 	 */
322 	struct link_encoder *link_enc = NULL;
323 
324 	link_enc = link_enc_cfg_get_link_enc(link);
325 	ASSERT(link_enc);
326 
327 	return (dc_is_dp_signal(link->connector_signal) && link_enc &&
328 			link_enc->features.fec_supported &&
329 			link->dpcd_caps.fec_cap.bits.FEC_CAPABLE);
330 }
331 
dp_should_enable_fec(const struct dc_link * link)332 bool dp_should_enable_fec(const struct dc_link *link)
333 {
334 	bool force_disable = false;
335 
336 	if (link->fec_state == dc_link_fec_enabled)
337 		force_disable = false;
338 	else if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT_MST &&
339 			link->local_sink &&
340 			link->local_sink->edid_caps.panel_patch.disable_fec)
341 		force_disable = true;
342 	else if (link->connector_signal == SIGNAL_TYPE_EDP
343 			&& (link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.
344 			 dsc_support.DSC_SUPPORT == false
345 				|| link->panel_config.dsc.disable_dsc_edp
346 				|| !link->dc->caps.edp_dsc_support))
347 		force_disable = true;
348 
349 	return !force_disable && dp_is_fec_supported(link);
350 }
351 
dp_is_128b_132b_signal(struct pipe_ctx * pipe_ctx)352 bool dp_is_128b_132b_signal(struct pipe_ctx *pipe_ctx)
353 {
354 	/* If this assert is hit then we have a link encoder dynamic management issue */
355 	ASSERT(pipe_ctx->stream_res.hpo_dp_stream_enc ? pipe_ctx->link_res.hpo_dp_link_enc != NULL : true);
356 	return (pipe_ctx->stream_res.hpo_dp_stream_enc &&
357 			pipe_ctx->link_res.hpo_dp_link_enc &&
358 			dc_is_dp_signal(pipe_ctx->stream->signal));
359 }
360 
dp_is_lttpr_present(struct dc_link * link)361 bool dp_is_lttpr_present(struct dc_link *link)
362 {
363 	return (dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) != 0 &&
364 			link->dpcd_caps.lttpr_caps.max_lane_count > 0 &&
365 			link->dpcd_caps.lttpr_caps.max_lane_count <= 4 &&
366 			link->dpcd_caps.lttpr_caps.revision.raw >= 0x14);
367 }
368 
369 /* in DP compliance test, DPR-120 may have
370  * a random value in its MAX_LINK_BW dpcd field.
371  * We map it to the maximum supported link rate that
372  * is smaller than MAX_LINK_BW in this case.
373  */
get_link_rate_from_max_link_bw(uint8_t max_link_bw)374 static enum dc_link_rate get_link_rate_from_max_link_bw(
375 		 uint8_t max_link_bw)
376 {
377 	enum dc_link_rate link_rate;
378 
379 	if (max_link_bw >= LINK_RATE_HIGH3) {
380 		link_rate = LINK_RATE_HIGH3;
381 	} else if (max_link_bw < LINK_RATE_HIGH3
382 			&& max_link_bw >= LINK_RATE_HIGH2) {
383 		link_rate = LINK_RATE_HIGH2;
384 	} else if (max_link_bw < LINK_RATE_HIGH2
385 			&& max_link_bw >= LINK_RATE_HIGH) {
386 		link_rate = LINK_RATE_HIGH;
387 	} else if (max_link_bw < LINK_RATE_HIGH
388 			&& max_link_bw >= LINK_RATE_LOW) {
389 		link_rate = LINK_RATE_LOW;
390 	} else {
391 		link_rate = LINK_RATE_UNKNOWN;
392 	}
393 
394 	return link_rate;
395 }
396 
get_lttpr_max_link_rate(struct dc_link * link)397 static enum dc_link_rate get_lttpr_max_link_rate(struct dc_link *link)
398 {
399 	enum dc_link_rate lttpr_max_link_rate = link->dpcd_caps.lttpr_caps.max_link_rate;
400 
401 	if (link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR20)
402 		lttpr_max_link_rate = LINK_RATE_UHBR20;
403 	else if (link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR13_5)
404 		lttpr_max_link_rate = LINK_RATE_UHBR13_5;
405 	else if (link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR10)
406 		lttpr_max_link_rate = LINK_RATE_UHBR10;
407 
408 	return lttpr_max_link_rate;
409 }
410 
get_cable_max_link_rate(struct dc_link * link)411 static enum dc_link_rate get_cable_max_link_rate(struct dc_link *link)
412 {
413 	enum dc_link_rate cable_max_link_rate = LINK_RATE_UNKNOWN;
414 
415 	if (link->dpcd_caps.cable_id.bits.UHBR10_20_CAPABILITY & DP_UHBR20)
416 		cable_max_link_rate = LINK_RATE_UHBR20;
417 	else if (link->dpcd_caps.cable_id.bits.UHBR13_5_CAPABILITY)
418 		cable_max_link_rate = LINK_RATE_UHBR13_5;
419 	else if (link->dpcd_caps.cable_id.bits.UHBR10_20_CAPABILITY & DP_UHBR10)
420 		cable_max_link_rate = LINK_RATE_UHBR10;
421 
422 	return cable_max_link_rate;
423 }
424 
reached_minimum_lane_count(enum dc_lane_count lane_count)425 static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count)
426 {
427 	return lane_count <= LANE_COUNT_ONE;
428 }
429 
reached_minimum_link_rate(enum dc_link_rate link_rate)430 static inline bool reached_minimum_link_rate(enum dc_link_rate link_rate)
431 {
432 	return link_rate <= LINK_RATE_LOW;
433 }
434 
reduce_lane_count(enum dc_lane_count lane_count)435 static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count)
436 {
437 	switch (lane_count) {
438 	case LANE_COUNT_FOUR:
439 		return LANE_COUNT_TWO;
440 	case LANE_COUNT_TWO:
441 		return LANE_COUNT_ONE;
442 	case LANE_COUNT_ONE:
443 		return LANE_COUNT_UNKNOWN;
444 	default:
445 		return LANE_COUNT_UNKNOWN;
446 	}
447 }
448 
reduce_link_rate(const struct dc_link * link,enum dc_link_rate link_rate)449 static enum dc_link_rate reduce_link_rate(const struct dc_link *link, enum dc_link_rate link_rate)
450 {
451 	// NEEDSWORK: provide some details about why this function never returns some of the
452 	// obscure link rates such as 4.32 Gbps or 3.24 Gbps and if such behavior is intended.
453 	//
454 
455 	switch (link_rate) {
456 	case LINK_RATE_UHBR20:
457 		return LINK_RATE_UHBR13_5;
458 	case LINK_RATE_UHBR13_5:
459 		return LINK_RATE_UHBR10;
460 	case LINK_RATE_UHBR10:
461 		return LINK_RATE_HIGH3;
462 	case LINK_RATE_HIGH3:
463 		if (link->connector_signal == SIGNAL_TYPE_EDP && link->dc->debug.support_eDP1_5)
464 			return LINK_RATE_RATE_8;
465 		return LINK_RATE_HIGH2;
466 	case LINK_RATE_RATE_8:
467 		return LINK_RATE_HIGH2;
468 	case LINK_RATE_HIGH2:
469 		return LINK_RATE_HIGH;
470 	case LINK_RATE_RATE_6:
471 	case LINK_RATE_RBR2:
472 		return LINK_RATE_HIGH;
473 	case LINK_RATE_HIGH:
474 		return LINK_RATE_LOW;
475 	case LINK_RATE_RATE_3:
476 	case LINK_RATE_RATE_2:
477 		return LINK_RATE_LOW;
478 	case LINK_RATE_LOW:
479 	default:
480 		return LINK_RATE_UNKNOWN;
481 	}
482 }
483 
increase_lane_count(enum dc_lane_count lane_count)484 static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count)
485 {
486 	switch (lane_count) {
487 	case LANE_COUNT_ONE:
488 		return LANE_COUNT_TWO;
489 	case LANE_COUNT_TWO:
490 		return LANE_COUNT_FOUR;
491 	default:
492 		return LANE_COUNT_UNKNOWN;
493 	}
494 }
495 
increase_link_rate(struct dc_link * link,enum dc_link_rate link_rate)496 static enum dc_link_rate increase_link_rate(struct dc_link *link,
497 		enum dc_link_rate link_rate)
498 {
499 	switch (link_rate) {
500 	case LINK_RATE_LOW:
501 		return LINK_RATE_HIGH;
502 	case LINK_RATE_HIGH:
503 		return LINK_RATE_HIGH2;
504 	case LINK_RATE_HIGH2:
505 		return LINK_RATE_HIGH3;
506 	case LINK_RATE_HIGH3:
507 		return LINK_RATE_UHBR10;
508 	case LINK_RATE_UHBR10:
509 		/* upto DP2.x specs UHBR13.5 is the only link rate that could be
510 		 * not supported by DPRX when higher link rate is supported.
511 		 * so we treat it as a special case for code simplicity. When we
512 		 * have new specs with more link rates like this, we should
513 		 * consider a more generic solution to handle discrete link
514 		 * rate capabilities.
515 		 */
516 		return link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR13_5 ?
517 				LINK_RATE_UHBR13_5 : LINK_RATE_UHBR20;
518 	case LINK_RATE_UHBR13_5:
519 		return LINK_RATE_UHBR20;
520 	default:
521 		return LINK_RATE_UNKNOWN;
522 	}
523 }
524 
decide_fallback_link_setting_max_bw_policy(struct dc_link * link,const struct dc_link_settings * max,struct dc_link_settings * cur,enum link_training_result training_result)525 static bool decide_fallback_link_setting_max_bw_policy(
526 		struct dc_link *link,
527 		const struct dc_link_settings *max,
528 		struct dc_link_settings *cur,
529 		enum link_training_result training_result)
530 {
531 	uint32_t cur_idx = 0, next_idx;
532 	bool found = false;
533 
534 	if (training_result == LINK_TRAINING_ABORT)
535 		return false;
536 
537 	while (cur_idx < ARRAY_SIZE(dp_lt_fallbacks))
538 		/* find current index */
539 		if (dp_lt_fallbacks[cur_idx].lane_count == cur->lane_count &&
540 				dp_lt_fallbacks[cur_idx].link_rate == cur->link_rate)
541 			break;
542 		else
543 			cur_idx++;
544 
545 	next_idx = cur_idx + 1;
546 
547 	while (next_idx < ARRAY_SIZE(dp_lt_fallbacks))
548 		/* find next index */
549 		if (dp_lt_fallbacks[next_idx].lane_count > max->lane_count ||
550 				dp_lt_fallbacks[next_idx].link_rate > max->link_rate)
551 			next_idx++;
552 		else if (dp_lt_fallbacks[next_idx].link_rate == LINK_RATE_UHBR13_5 &&
553 				link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR13_5 == 0)
554 			/* upto DP2.x specs UHBR13.5 is the only link rate that
555 			 * could be not supported by DPRX when higher link rate
556 			 * is supported. so we treat it as a special case for
557 			 * code simplicity. When we have new specs with more
558 			 * link rates like this, we should consider a more
559 			 * generic solution to handle discrete link rate
560 			 * capabilities.
561 			 */
562 			next_idx++;
563 		else
564 			break;
565 
566 	if (next_idx < ARRAY_SIZE(dp_lt_fallbacks)) {
567 		cur->lane_count = dp_lt_fallbacks[next_idx].lane_count;
568 		cur->link_rate = dp_lt_fallbacks[next_idx].link_rate;
569 		found = true;
570 	}
571 
572 	return found;
573 }
574 
575 /*
576  * function: set link rate and lane count fallback based
577  * on current link setting and last link training result
578  * return value:
579  *			true - link setting could be set
580  *			false - has reached minimum setting
581  *					and no further fallback could be done
582  */
decide_fallback_link_setting(struct dc_link * link,struct dc_link_settings * max,struct dc_link_settings * cur,enum link_training_result training_result)583 bool decide_fallback_link_setting(
584 		struct dc_link *link,
585 		struct dc_link_settings *max,
586 		struct dc_link_settings *cur,
587 		enum link_training_result training_result)
588 {
589 	if (link_dp_get_encoding_format(max) == DP_128b_132b_ENCODING ||
590 			link->dc->debug.force_dp2_lt_fallback_method)
591 		return decide_fallback_link_setting_max_bw_policy(link, max,
592 				cur, training_result);
593 
594 	switch (training_result) {
595 	case LINK_TRAINING_CR_FAIL_LANE0:
596 	case LINK_TRAINING_CR_FAIL_LANE1:
597 	case LINK_TRAINING_CR_FAIL_LANE23:
598 	case LINK_TRAINING_LQA_FAIL:
599 	{
600 		if (!reached_minimum_link_rate(cur->link_rate)) {
601 			cur->link_rate = reduce_link_rate(link, cur->link_rate);
602 		} else if (!reached_minimum_lane_count(cur->lane_count)) {
603 			cur->link_rate = max->link_rate;
604 			if (training_result == LINK_TRAINING_CR_FAIL_LANE0)
605 				return false;
606 			else if (training_result == LINK_TRAINING_CR_FAIL_LANE1)
607 				cur->lane_count = LANE_COUNT_ONE;
608 			else if (training_result == LINK_TRAINING_CR_FAIL_LANE23)
609 				cur->lane_count = LANE_COUNT_TWO;
610 			else
611 				cur->lane_count = reduce_lane_count(cur->lane_count);
612 		} else {
613 			return false;
614 		}
615 		break;
616 	}
617 	case LINK_TRAINING_EQ_FAIL_EQ:
618 	case LINK_TRAINING_EQ_FAIL_CR_PARTIAL:
619 	{
620 		if (!reached_minimum_lane_count(cur->lane_count)) {
621 			cur->lane_count = reduce_lane_count(cur->lane_count);
622 		} else if (!reached_minimum_link_rate(cur->link_rate)) {
623 			cur->link_rate = reduce_link_rate(link, cur->link_rate);
624 			/* Reduce max link rate to avoid potential infinite loop.
625 			 * Needed so that any subsequent CR_FAIL fallback can't
626 			 * re-set the link rate higher than the link rate from
627 			 * the latest EQ_FAIL fallback.
628 			 */
629 			max->link_rate = cur->link_rate;
630 			cur->lane_count = max->lane_count;
631 		} else {
632 			return false;
633 		}
634 		break;
635 	}
636 	case LINK_TRAINING_EQ_FAIL_CR:
637 	{
638 		if (!reached_minimum_link_rate(cur->link_rate)) {
639 			cur->link_rate = reduce_link_rate(link, cur->link_rate);
640 			/* Reduce max link rate to avoid potential infinite loop.
641 			 * Needed so that any subsequent CR_FAIL fallback can't
642 			 * re-set the link rate higher than the link rate from
643 			 * the latest EQ_FAIL fallback.
644 			 */
645 			max->link_rate = cur->link_rate;
646 			cur->lane_count = max->lane_count;
647 		} else {
648 			return false;
649 		}
650 		break;
651 	}
652 	default:
653 		return false;
654 	}
655 	return true;
656 }
decide_dp_link_settings(struct dc_link * link,struct dc_link_settings * link_setting,uint32_t req_bw)657 static bool decide_dp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
658 {
659 	struct dc_link_settings initial_link_setting = {
660 		LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED, false, 0};
661 	struct dc_link_settings current_link_setting =
662 			initial_link_setting;
663 	uint32_t link_bw;
664 
665 	if (req_bw > dp_link_bandwidth_kbps(link, &link->verified_link_cap))
666 		return false;
667 
668 	/* search for the minimum link setting that:
669 	 * 1. is supported according to the link training result
670 	 * 2. could support the b/w requested by the timing
671 	 */
672 	while (current_link_setting.link_rate <=
673 			link->verified_link_cap.link_rate) {
674 		link_bw = dp_link_bandwidth_kbps(
675 				link,
676 				&current_link_setting);
677 		if (req_bw <= link_bw) {
678 			*link_setting = current_link_setting;
679 			return true;
680 		}
681 
682 		if (current_link_setting.lane_count <
683 				link->verified_link_cap.lane_count) {
684 			current_link_setting.lane_count =
685 					increase_lane_count(
686 							current_link_setting.lane_count);
687 		} else {
688 			current_link_setting.link_rate =
689 					increase_link_rate(link,
690 							current_link_setting.link_rate);
691 			current_link_setting.lane_count =
692 					initial_link_setting.lane_count;
693 		}
694 	}
695 
696 	return false;
697 }
698 
edp_decide_link_settings(struct dc_link * link,struct dc_link_settings * link_setting,uint32_t req_bw)699 bool edp_decide_link_settings(struct dc_link *link,
700 		struct dc_link_settings *link_setting, uint32_t req_bw)
701 {
702 	struct dc_link_settings initial_link_setting;
703 	struct dc_link_settings current_link_setting;
704 	uint32_t link_bw;
705 
706 	/*
707 	 * edp_supported_link_rates_count is only valid for eDP v1.4 or higher.
708 	 * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
709 	 */
710 	if (!edp_is_ilr_optimization_enabled(link)) {
711 		*link_setting = link->verified_link_cap;
712 		return true;
713 	}
714 
715 	memset(&initial_link_setting, 0, sizeof(initial_link_setting));
716 	initial_link_setting.lane_count = LANE_COUNT_ONE;
717 	initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0];
718 	initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
719 	initial_link_setting.use_link_rate_set = true;
720 	initial_link_setting.link_rate_set = 0;
721 	current_link_setting = initial_link_setting;
722 
723 	/* search for the minimum link setting that:
724 	 * 1. is supported according to the link training result
725 	 * 2. could support the b/w requested by the timing
726 	 */
727 	while (current_link_setting.link_rate <=
728 			link->verified_link_cap.link_rate) {
729 		link_bw = dp_link_bandwidth_kbps(
730 				link,
731 				&current_link_setting);
732 		if (req_bw <= link_bw) {
733 			*link_setting = current_link_setting;
734 			return true;
735 		}
736 
737 		if (current_link_setting.lane_count <
738 				link->verified_link_cap.lane_count) {
739 			current_link_setting.lane_count =
740 					increase_lane_count(
741 							current_link_setting.lane_count);
742 		} else {
743 			if (current_link_setting.link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
744 				current_link_setting.link_rate_set++;
745 				current_link_setting.link_rate =
746 					link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
747 				current_link_setting.lane_count =
748 									initial_link_setting.lane_count;
749 			} else
750 				break;
751 		}
752 	}
753 	return false;
754 }
755 
decide_edp_link_settings_with_dsc(struct dc_link * link,struct dc_link_settings * link_setting,uint32_t req_bw,enum dc_link_rate max_link_rate)756 bool decide_edp_link_settings_with_dsc(struct dc_link *link,
757 		struct dc_link_settings *link_setting,
758 		uint32_t req_bw,
759 		enum dc_link_rate max_link_rate)
760 {
761 	struct dc_link_settings initial_link_setting;
762 	struct dc_link_settings current_link_setting;
763 	uint32_t link_bw;
764 
765 	unsigned int policy = 0;
766 
767 	policy = link->panel_config.dsc.force_dsc_edp_policy;
768 	if (max_link_rate == LINK_RATE_UNKNOWN)
769 		max_link_rate = link->verified_link_cap.link_rate;
770 	/*
771 	 * edp_supported_link_rates_count is only valid for eDP v1.4 or higher.
772 	 * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
773 	 */
774 	if (!edp_is_ilr_optimization_enabled(link)) {
775 		/* for DSC enabled case, we search for minimum lane count */
776 		memset(&initial_link_setting, 0, sizeof(initial_link_setting));
777 		initial_link_setting.lane_count = LANE_COUNT_ONE;
778 		initial_link_setting.link_rate = LINK_RATE_LOW;
779 		initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
780 		initial_link_setting.use_link_rate_set = false;
781 		initial_link_setting.link_rate_set = 0;
782 		current_link_setting = initial_link_setting;
783 		if (req_bw > dp_link_bandwidth_kbps(link, &link->verified_link_cap))
784 			return false;
785 
786 		/* search for the minimum link setting that:
787 		 * 1. is supported according to the link training result
788 		 * 2. could support the b/w requested by the timing
789 		 */
790 		while (current_link_setting.link_rate <=
791 				max_link_rate) {
792 			link_bw = dp_link_bandwidth_kbps(
793 					link,
794 					&current_link_setting);
795 			if (req_bw <= link_bw) {
796 				*link_setting = current_link_setting;
797 				return true;
798 			}
799 			if (policy) {
800 				/* minimize lane */
801 				if (current_link_setting.link_rate < max_link_rate) {
802 					current_link_setting.link_rate =
803 							increase_link_rate(link,
804 									current_link_setting.link_rate);
805 				} else {
806 					if (current_link_setting.lane_count <
807 									link->verified_link_cap.lane_count) {
808 						current_link_setting.lane_count =
809 								increase_lane_count(
810 										current_link_setting.lane_count);
811 						current_link_setting.link_rate = initial_link_setting.link_rate;
812 					} else
813 						break;
814 				}
815 			} else {
816 				/* minimize link rate */
817 				if (current_link_setting.lane_count <
818 						link->verified_link_cap.lane_count) {
819 					current_link_setting.lane_count =
820 							increase_lane_count(
821 									current_link_setting.lane_count);
822 				} else {
823 					current_link_setting.link_rate =
824 							increase_link_rate(link,
825 									current_link_setting.link_rate);
826 					current_link_setting.lane_count =
827 							initial_link_setting.lane_count;
828 				}
829 			}
830 		}
831 		return false;
832 	}
833 
834 	/* if optimize edp link is supported */
835 	memset(&initial_link_setting, 0, sizeof(initial_link_setting));
836 	initial_link_setting.lane_count = LANE_COUNT_ONE;
837 	initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0];
838 	initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
839 	initial_link_setting.use_link_rate_set = true;
840 	initial_link_setting.link_rate_set = 0;
841 	current_link_setting = initial_link_setting;
842 
843 	/* search for the minimum link setting that:
844 	 * 1. is supported according to the link training result
845 	 * 2. could support the b/w requested by the timing
846 	 */
847 	while (current_link_setting.link_rate <=
848 			max_link_rate) {
849 		link_bw = dp_link_bandwidth_kbps(
850 				link,
851 				&current_link_setting);
852 		if (req_bw <= link_bw) {
853 			*link_setting = current_link_setting;
854 			return true;
855 		}
856 		if (policy) {
857 			/* minimize lane */
858 			if (current_link_setting.link_rate_set <
859 					link->dpcd_caps.edp_supported_link_rates_count
860 					&& current_link_setting.link_rate < max_link_rate) {
861 				current_link_setting.link_rate_set++;
862 				current_link_setting.link_rate =
863 					link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
864 			} else {
865 				if (current_link_setting.lane_count < link->verified_link_cap.lane_count) {
866 					current_link_setting.lane_count =
867 							increase_lane_count(
868 									current_link_setting.lane_count);
869 					current_link_setting.link_rate_set = initial_link_setting.link_rate_set;
870 					current_link_setting.link_rate =
871 						link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
872 				} else
873 					break;
874 			}
875 		} else {
876 			/* minimize link rate */
877 			if (current_link_setting.lane_count <
878 					link->verified_link_cap.lane_count) {
879 				current_link_setting.lane_count =
880 						increase_lane_count(
881 								current_link_setting.lane_count);
882 			} else {
883 				if (current_link_setting.link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
884 					current_link_setting.link_rate_set++;
885 					current_link_setting.link_rate =
886 						link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
887 					current_link_setting.lane_count =
888 						initial_link_setting.lane_count;
889 				} else
890 					break;
891 			}
892 		}
893 	}
894 	return false;
895 }
896 
decide_mst_link_settings(const struct dc_link * link,struct dc_link_settings * link_setting)897 static bool decide_mst_link_settings(const struct dc_link *link, struct dc_link_settings *link_setting)
898 {
899 	*link_setting = link->verified_link_cap;
900 	return true;
901 }
902 
link_decide_link_settings(struct dc_stream_state * stream,struct dc_link_settings * link_setting)903 bool link_decide_link_settings(struct dc_stream_state *stream,
904 	struct dc_link_settings *link_setting)
905 {
906 	struct dc_link *link = stream->link;
907 	uint32_t req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing, dc_link_get_highest_encoding_format(link));
908 
909 	memset(link_setting, 0, sizeof(*link_setting));
910 
911 	if (dc_is_dp_signal(stream->signal)  &&
912 			link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN &&
913 			link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) {
914 		/* if preferred is specified through AMDDP, use it, if it's enough
915 		 * to drive the mode
916 		 */
917 		*link_setting = link->preferred_link_setting;
918 	} else if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
919 		/* MST doesn't perform link training for now
920 		 * TODO: add MST specific link training routine
921 		 */
922 		decide_mst_link_settings(link, link_setting);
923 	} else if (link->connector_signal == SIGNAL_TYPE_EDP) {
924 		/* enable edp link optimization for DSC eDP case */
925 		if (stream->timing.flags.DSC) {
926 			enum dc_link_rate max_link_rate = LINK_RATE_UNKNOWN;
927 
928 			if (link->panel_config.dsc.force_dsc_edp_policy) {
929 				/* calculate link max link rate cap*/
930 				struct dc_link_settings tmp_link_setting;
931 				struct dc_crtc_timing tmp_timing = stream->timing;
932 				uint32_t orig_req_bw;
933 
934 				tmp_link_setting.link_rate = LINK_RATE_UNKNOWN;
935 				tmp_timing.flags.DSC = 0;
936 				orig_req_bw = dc_bandwidth_in_kbps_from_timing(&tmp_timing,
937 						dc_link_get_highest_encoding_format(link));
938 				edp_decide_link_settings(link, &tmp_link_setting, orig_req_bw);
939 				max_link_rate = tmp_link_setting.link_rate;
940 			}
941 			decide_edp_link_settings_with_dsc(link, link_setting, req_bw, max_link_rate);
942 		} else {
943 			edp_decide_link_settings(link, link_setting, req_bw);
944 		}
945 	} else {
946 		decide_dp_link_settings(link, link_setting, req_bw);
947 	}
948 
949 	return link_setting->lane_count != LANE_COUNT_UNKNOWN &&
950 			link_setting->link_rate != LINK_RATE_UNKNOWN;
951 }
952 
link_dp_get_encoding_format(const struct dc_link_settings * link_settings)953 enum dp_link_encoding link_dp_get_encoding_format(const struct dc_link_settings *link_settings)
954 {
955 	if ((link_settings->link_rate >= LINK_RATE_LOW) &&
956 			(link_settings->link_rate <= LINK_RATE_HIGH3))
957 		return DP_8b_10b_ENCODING;
958 	else if ((link_settings->link_rate >= LINK_RATE_UHBR10) &&
959 			(link_settings->link_rate <= LINK_RATE_UHBR20))
960 		return DP_128b_132b_ENCODING;
961 	return DP_UNKNOWN_ENCODING;
962 }
963 
mst_decide_link_encoding_format(const struct dc_link * link)964 enum dp_link_encoding mst_decide_link_encoding_format(const struct dc_link *link)
965 {
966 	struct dc_link_settings link_settings = {0};
967 
968 	if (!dc_is_dp_signal(link->connector_signal))
969 		return DP_UNKNOWN_ENCODING;
970 
971 	if (link->preferred_link_setting.lane_count !=
972 			LANE_COUNT_UNKNOWN &&
973 			link->preferred_link_setting.link_rate !=
974 					LINK_RATE_UNKNOWN) {
975 		link_settings = link->preferred_link_setting;
976 	} else {
977 		decide_mst_link_settings(link, &link_settings);
978 	}
979 
980 	return link_dp_get_encoding_format(&link_settings);
981 }
982 
read_dp_device_vendor_id(struct dc_link * link)983 static void read_dp_device_vendor_id(struct dc_link *link)
984 {
985 	struct dp_device_vendor_id dp_id;
986 
987 	/* read IEEE branch device id */
988 	core_link_read_dpcd(
989 		link,
990 		DP_BRANCH_OUI,
991 		(uint8_t *)&dp_id,
992 		sizeof(dp_id));
993 
994 	link->dpcd_caps.branch_dev_id =
995 		(dp_id.ieee_oui[0] << 16) +
996 		(dp_id.ieee_oui[1] << 8) +
997 		dp_id.ieee_oui[2];
998 
999 	memmove(
1000 		link->dpcd_caps.branch_dev_name,
1001 		dp_id.ieee_device_id,
1002 		sizeof(dp_id.ieee_device_id));
1003 }
1004 
wake_up_aux_channel(struct dc_link * link)1005 static enum dc_status wake_up_aux_channel(struct dc_link *link)
1006 {
1007 	enum dc_status status = DC_ERROR_UNEXPECTED;
1008 	uint32_t aux_channel_retry_cnt = 0;
1009 	uint8_t dpcd_power_state = '\0';
1010 
1011 	while (status != DC_OK && aux_channel_retry_cnt < 10) {
1012 		status = core_link_read_dpcd(link, DP_SET_POWER,
1013 				&dpcd_power_state, sizeof(dpcd_power_state));
1014 
1015 		/* Delay 1 ms if AUX CH is in power down state. Based on spec
1016 		 * section 2.3.1.2, if AUX CH may be powered down due to
1017 		 * write to DPCD 600h = 2. Sink AUX CH is monitoring differential
1018 		 * signal and may need up to 1 ms before being able to reply.
1019 		 */
1020 		if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3) {
1021 			fsleep(1000);
1022 			aux_channel_retry_cnt++;
1023 		}
1024 	}
1025 
1026 	if (status != DC_OK) {
1027 		dpcd_power_state = DP_SET_POWER_D0;
1028 		status = core_link_write_dpcd(
1029 				link,
1030 				DP_SET_POWER,
1031 				&dpcd_power_state,
1032 				sizeof(dpcd_power_state));
1033 
1034 		dpcd_power_state = DP_SET_POWER_D3;
1035 		status = core_link_write_dpcd(
1036 				link,
1037 				DP_SET_POWER,
1038 				&dpcd_power_state,
1039 				sizeof(dpcd_power_state));
1040 		DC_LOG_DC("%s: Failed to power up sink\n", __func__);
1041 		return DC_ERROR_UNEXPECTED;
1042 	}
1043 
1044 	return DC_OK;
1045 }
1046 
get_active_converter_info(uint8_t data,struct dc_link * link)1047 static void get_active_converter_info(
1048 	uint8_t data, struct dc_link *link)
1049 {
1050 	union dp_downstream_port_present ds_port = { .byte = data };
1051 	memset(&link->dpcd_caps.dongle_caps, 0, sizeof(link->dpcd_caps.dongle_caps));
1052 
1053 	/* decode converter info*/
1054 	if (!ds_port.fields.PORT_PRESENT) {
1055 		link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
1056 		set_dongle_type(link->ddc,
1057 				link->dpcd_caps.dongle_type);
1058 		link->dpcd_caps.is_branch_dev = false;
1059 		return;
1060 	}
1061 
1062 	/* DPCD 0x5 bit 0 = 1, it indicate it's branch device */
1063 	link->dpcd_caps.is_branch_dev = ds_port.fields.PORT_PRESENT;
1064 
1065 	switch (ds_port.fields.PORT_TYPE) {
1066 	case DOWNSTREAM_VGA:
1067 		link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER;
1068 		break;
1069 	case DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS:
1070 		/* At this point we don't know is it DVI or HDMI or DP++,
1071 		 * assume DVI.*/
1072 		link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER;
1073 		break;
1074 	default:
1075 		link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
1076 		break;
1077 	}
1078 
1079 	if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) {
1080 		uint8_t det_caps[16]; /* CTS 4.2.2.7 expects source to read Detailed Capabilities Info : 00080h-0008F.*/
1081 		union dwnstream_port_caps_byte0 *port_caps =
1082 			(union dwnstream_port_caps_byte0 *)det_caps;
1083 		if (core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0,
1084 				det_caps, sizeof(det_caps)) == DC_OK) {
1085 
1086 			switch (port_caps->bits.DWN_STRM_PORTX_TYPE) {
1087 			/*Handle DP case as DONGLE_NONE*/
1088 			case DOWN_STREAM_DETAILED_DP:
1089 				link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
1090 				break;
1091 			case DOWN_STREAM_DETAILED_VGA:
1092 				link->dpcd_caps.dongle_type =
1093 					DISPLAY_DONGLE_DP_VGA_CONVERTER;
1094 				break;
1095 			case DOWN_STREAM_DETAILED_DVI:
1096 				link->dpcd_caps.dongle_type =
1097 					DISPLAY_DONGLE_DP_DVI_CONVERTER;
1098 				break;
1099 			case DOWN_STREAM_DETAILED_HDMI:
1100 			case DOWN_STREAM_DETAILED_DP_PLUS_PLUS:
1101 				/*Handle DP++ active converter case, process DP++ case as HDMI case according DP1.4 spec*/
1102 				link->dpcd_caps.dongle_type =
1103 					DISPLAY_DONGLE_DP_HDMI_CONVERTER;
1104 
1105 				link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type;
1106 				if (ds_port.fields.DETAILED_CAPS) {
1107 
1108 					union dwnstream_port_caps_byte3_hdmi
1109 						hdmi_caps = {.raw = det_caps[3] };
1110 					union dwnstream_port_caps_byte2
1111 						hdmi_color_caps = {.raw = det_caps[2] };
1112 					link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz =
1113 						det_caps[1] * 2500;
1114 
1115 					link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter =
1116 						hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK;
1117 					/*YCBCR capability only for HDMI case*/
1118 					if (port_caps->bits.DWN_STRM_PORTX_TYPE
1119 							== DOWN_STREAM_DETAILED_HDMI) {
1120 						link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through =
1121 								hdmi_caps.bits.YCrCr422_PASS_THROUGH;
1122 						link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through =
1123 								hdmi_caps.bits.YCrCr420_PASS_THROUGH;
1124 						link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter =
1125 								hdmi_caps.bits.YCrCr422_CONVERSION;
1126 						link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter =
1127 								hdmi_caps.bits.YCrCr420_CONVERSION;
1128 					}
1129 
1130 					link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc =
1131 						translate_dpcd_max_bpc(
1132 							hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT);
1133 
1134 					if (link->dc->caps.dp_hdmi21_pcon_support) {
1135 						union hdmi_encoded_link_bw hdmi_encoded_link_bw;
1136 
1137 						link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps =
1138 								link_bw_kbps_from_raw_frl_link_rate_data(
1139 										hdmi_color_caps.bits.MAX_ENCODED_LINK_BW_SUPPORT);
1140 
1141 						// Intersect reported max link bw support with the supported link rate post FRL link training
1142 						if (core_link_read_dpcd(link, DP_PCON_HDMI_POST_FRL_STATUS,
1143 								&hdmi_encoded_link_bw.raw, sizeof(hdmi_encoded_link_bw)) == DC_OK) {
1144 							link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps = intersect_frl_link_bw_support(
1145 									link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps,
1146 									hdmi_encoded_link_bw);
1147 						}
1148 
1149 						if (link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps > 0)
1150 							link->dpcd_caps.dongle_caps.extendedCapValid = true;
1151 					}
1152 
1153 					if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz != 0)
1154 						link->dpcd_caps.dongle_caps.extendedCapValid = true;
1155 				}
1156 
1157 				break;
1158 			}
1159 		}
1160 	}
1161 
1162 	set_dongle_type(link->ddc, link->dpcd_caps.dongle_type);
1163 
1164 	{
1165 		struct dp_sink_hw_fw_revision dp_hw_fw_revision;
1166 
1167 		core_link_read_dpcd(
1168 			link,
1169 			DP_BRANCH_REVISION_START,
1170 			(uint8_t *)&dp_hw_fw_revision,
1171 			sizeof(dp_hw_fw_revision));
1172 
1173 		link->dpcd_caps.branch_hw_revision =
1174 			dp_hw_fw_revision.ieee_hw_rev;
1175 
1176 		memmove(
1177 			link->dpcd_caps.branch_fw_revision,
1178 			dp_hw_fw_revision.ieee_fw_rev,
1179 			sizeof(dp_hw_fw_revision.ieee_fw_rev));
1180 	}
1181 	if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
1182 			link->dpcd_caps.dongle_type != DISPLAY_DONGLE_NONE) {
1183 		union dp_dfp_cap_ext dfp_cap_ext;
1184 		memset(&dfp_cap_ext, '\0', sizeof (dfp_cap_ext));
1185 		core_link_read_dpcd(
1186 				link,
1187 				DP_DFP_CAPABILITY_EXTENSION_SUPPORT,
1188 				dfp_cap_ext.raw,
1189 				sizeof(dfp_cap_ext.raw));
1190 		link->dpcd_caps.dongle_caps.dfp_cap_ext.supported = dfp_cap_ext.fields.supported;
1191 		link->dpcd_caps.dongle_caps.dfp_cap_ext.max_pixel_rate_in_mps =
1192 				dfp_cap_ext.fields.max_pixel_rate_in_mps[0] +
1193 				(dfp_cap_ext.fields.max_pixel_rate_in_mps[1] << 8);
1194 		link->dpcd_caps.dongle_caps.dfp_cap_ext.max_video_h_active_width =
1195 				dfp_cap_ext.fields.max_video_h_active_width[0] +
1196 				(dfp_cap_ext.fields.max_video_h_active_width[1] << 8);
1197 		link->dpcd_caps.dongle_caps.dfp_cap_ext.max_video_v_active_height =
1198 				dfp_cap_ext.fields.max_video_v_active_height[0] +
1199 				(dfp_cap_ext.fields.max_video_v_active_height[1] << 8);
1200 		link->dpcd_caps.dongle_caps.dfp_cap_ext.encoding_format_caps =
1201 				dfp_cap_ext.fields.encoding_format_caps;
1202 		link->dpcd_caps.dongle_caps.dfp_cap_ext.rgb_color_depth_caps =
1203 				dfp_cap_ext.fields.rgb_color_depth_caps;
1204 		link->dpcd_caps.dongle_caps.dfp_cap_ext.ycbcr444_color_depth_caps =
1205 				dfp_cap_ext.fields.ycbcr444_color_depth_caps;
1206 		link->dpcd_caps.dongle_caps.dfp_cap_ext.ycbcr422_color_depth_caps =
1207 				dfp_cap_ext.fields.ycbcr422_color_depth_caps;
1208 		link->dpcd_caps.dongle_caps.dfp_cap_ext.ycbcr420_color_depth_caps =
1209 				dfp_cap_ext.fields.ycbcr420_color_depth_caps;
1210 		DC_LOG_DP2("DFP capability extension is read at link %d", link->link_index);
1211 		DC_LOG_DP2("\tdfp_cap_ext.supported = %s", link->dpcd_caps.dongle_caps.dfp_cap_ext.supported ? "true" : "false");
1212 		DC_LOG_DP2("\tdfp_cap_ext.max_pixel_rate_in_mps = %d", link->dpcd_caps.dongle_caps.dfp_cap_ext.max_pixel_rate_in_mps);
1213 		DC_LOG_DP2("\tdfp_cap_ext.max_video_h_active_width = %d", link->dpcd_caps.dongle_caps.dfp_cap_ext.max_video_h_active_width);
1214 		DC_LOG_DP2("\tdfp_cap_ext.max_video_v_active_height = %d", link->dpcd_caps.dongle_caps.dfp_cap_ext.max_video_v_active_height);
1215 	}
1216 }
1217 
apply_usbc_combo_phy_reset_wa(struct dc_link * link,struct dc_link_settings * link_settings)1218 static void apply_usbc_combo_phy_reset_wa(struct dc_link *link,
1219 		struct dc_link_settings *link_settings)
1220 {
1221 	/* Temporary Renoir-specific workaround PHY will sometimes be in bad
1222 	 * state on hotplugging display from certain USB-C dongle, so add extra
1223 	 * cycle of enabling and disabling the PHY before first link training.
1224 	 */
1225 	struct link_resource link_res = {0};
1226 	enum clock_source_id dp_cs_id = get_clock_source_id(link);
1227 
1228 	dp_enable_link_phy(link, &link_res, link->connector_signal,
1229 			dp_cs_id, link_settings);
1230 	dp_disable_link_phy(link, &link_res, link->connector_signal);
1231 }
1232 
dp_overwrite_extended_receiver_cap(struct dc_link * link)1233 bool dp_overwrite_extended_receiver_cap(struct dc_link *link)
1234 {
1235 	uint8_t dpcd_data[16];
1236 	uint32_t read_dpcd_retry_cnt = 3;
1237 	enum dc_status status = DC_ERROR_UNEXPECTED;
1238 	union dp_downstream_port_present ds_port = { 0 };
1239 	union down_stream_port_count down_strm_port_count;
1240 	union edp_configuration_cap edp_config_cap;
1241 
1242 	int i;
1243 
1244 	for (i = 0; i < read_dpcd_retry_cnt; i++) {
1245 		status = core_link_read_dpcd(
1246 				link,
1247 				DP_DPCD_REV,
1248 				dpcd_data,
1249 				sizeof(dpcd_data));
1250 		if (status == DC_OK)
1251 			break;
1252 	}
1253 
1254 	link->dpcd_caps.dpcd_rev.raw =
1255 		dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
1256 
1257 	if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
1258 		return false;
1259 
1260 	ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
1261 			DP_DPCD_REV];
1262 
1263 	get_active_converter_info(ds_port.byte, link);
1264 
1265 	down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
1266 			DP_DPCD_REV];
1267 
1268 	link->dpcd_caps.allow_invalid_MSA_timing_param =
1269 		down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
1270 
1271 	link->dpcd_caps.max_ln_count.raw = dpcd_data[
1272 		DP_MAX_LANE_COUNT - DP_DPCD_REV];
1273 
1274 	link->dpcd_caps.max_down_spread.raw = dpcd_data[
1275 		DP_MAX_DOWNSPREAD - DP_DPCD_REV];
1276 
1277 	link->reported_link_cap.lane_count =
1278 		link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
1279 	link->reported_link_cap.link_rate = dpcd_data[
1280 		DP_MAX_LINK_RATE - DP_DPCD_REV];
1281 	link->reported_link_cap.link_spread =
1282 		link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
1283 		LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
1284 
1285 	edp_config_cap.raw = dpcd_data[
1286 		DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
1287 	link->dpcd_caps.panel_mode_edp =
1288 		edp_config_cap.bits.ALT_SCRAMBLER_RESET;
1289 	link->dpcd_caps.dpcd_display_control_capable =
1290 		edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
1291 
1292 	return true;
1293 }
1294 
dpcd_set_source_specific_data(struct dc_link * link)1295 void dpcd_set_source_specific_data(struct dc_link *link)
1296 {
1297 	if (!link->dc->vendor_signature.is_valid) {
1298 		enum dc_status __maybe_unused result_write_min_hblank = DC_NOT_SUPPORTED;
1299 		struct dpcd_amd_signature amd_signature = {0};
1300 		struct dpcd_amd_device_id amd_device_id = {0};
1301 
1302 		amd_device_id.device_id_byte1 =
1303 				(uint8_t)(link->ctx->asic_id.chip_id);
1304 		amd_device_id.device_id_byte2 =
1305 				(uint8_t)(link->ctx->asic_id.chip_id >> 8);
1306 		amd_device_id.dce_version =
1307 				(uint8_t)(link->ctx->dce_version);
1308 		amd_device_id.dal_version_byte1 = 0x0; // needed? where to get?
1309 		amd_device_id.dal_version_byte2 = 0x0; // needed? where to get?
1310 
1311 		core_link_read_dpcd(link, DP_SOURCE_OUI,
1312 				(uint8_t *)(&amd_signature),
1313 				sizeof(amd_signature));
1314 
1315 		if (!((amd_signature.AMD_IEEE_TxSignature_byte1 == 0x0) &&
1316 			(amd_signature.AMD_IEEE_TxSignature_byte2 == 0x0) &&
1317 			(amd_signature.AMD_IEEE_TxSignature_byte3 == 0x1A))) {
1318 
1319 			amd_signature.AMD_IEEE_TxSignature_byte1 = 0x0;
1320 			amd_signature.AMD_IEEE_TxSignature_byte2 = 0x0;
1321 			amd_signature.AMD_IEEE_TxSignature_byte3 = 0x1A;
1322 
1323 			core_link_write_dpcd(link, DP_SOURCE_OUI,
1324 				(uint8_t *)(&amd_signature),
1325 				sizeof(amd_signature));
1326 		}
1327 
1328 		core_link_write_dpcd(link, DP_SOURCE_OUI+0x03,
1329 				(uint8_t *)(&amd_device_id),
1330 				sizeof(amd_device_id));
1331 
1332 		if (link->ctx->dce_version >= DCN_VERSION_2_0 &&
1333 			link->dc->caps.min_horizontal_blanking_period != 0) {
1334 
1335 			uint8_t hblank_size = (uint8_t)link->dc->caps.min_horizontal_blanking_period;
1336 
1337 			result_write_min_hblank = core_link_write_dpcd(link,
1338 				DP_SOURCE_MINIMUM_HBLANK_SUPPORTED, (uint8_t *)(&hblank_size),
1339 				sizeof(hblank_size));
1340 		}
1341 		DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
1342 							WPP_BIT_FLAG_DC_DETECTION_DP_CAPS,
1343 							"result=%u link_index=%u enum dce_version=%d DPCD=0x%04X min_hblank=%u branch_dev_id=0x%x branch_dev_name='%c%c%c%c%c%c'",
1344 							result_write_min_hblank,
1345 							link->link_index,
1346 							link->ctx->dce_version,
1347 							DP_SOURCE_MINIMUM_HBLANK_SUPPORTED,
1348 							link->dc->caps.min_horizontal_blanking_period,
1349 							link->dpcd_caps.branch_dev_id,
1350 							link->dpcd_caps.branch_dev_name[0],
1351 							link->dpcd_caps.branch_dev_name[1],
1352 							link->dpcd_caps.branch_dev_name[2],
1353 							link->dpcd_caps.branch_dev_name[3],
1354 							link->dpcd_caps.branch_dev_name[4],
1355 							link->dpcd_caps.branch_dev_name[5]);
1356 	} else {
1357 		core_link_write_dpcd(link, DP_SOURCE_OUI,
1358 				link->dc->vendor_signature.data.raw,
1359 				sizeof(link->dc->vendor_signature.data.raw));
1360 	}
1361 }
1362 
dpcd_write_cable_id_to_dprx(struct dc_link * link)1363 void dpcd_write_cable_id_to_dprx(struct dc_link *link)
1364 {
1365 	if (!link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED ||
1366 			link->dpcd_caps.cable_id.raw == 0 ||
1367 			link->dprx_states.cable_id_written)
1368 		return;
1369 
1370 	core_link_write_dpcd(link, DP_CABLE_ATTRIBUTES_UPDATED_BY_DPTX,
1371 			&link->dpcd_caps.cable_id.raw,
1372 			sizeof(link->dpcd_caps.cable_id.raw));
1373 
1374 	link->dprx_states.cable_id_written = 1;
1375 }
1376 
get_usbc_cable_id(struct dc_link * link,union dp_cable_id * cable_id)1377 static bool get_usbc_cable_id(struct dc_link *link, union dp_cable_id *cable_id)
1378 {
1379 	union dmub_rb_cmd cmd;
1380 
1381 	if (!link->ctx->dmub_srv ||
1382 			link->ep_type != DISPLAY_ENDPOINT_PHY ||
1383 			link->link_enc->features.flags.bits.DP_IS_USB_C == 0)
1384 		return false;
1385 
1386 	memset(&cmd, 0, sizeof(cmd));
1387 	cmd.cable_id.header.type = DMUB_CMD_GET_USBC_CABLE_ID;
1388 	cmd.cable_id.header.payload_bytes = sizeof(cmd.cable_id.data);
1389 	cmd.cable_id.data.input.phy_inst = resource_transmitter_to_phy_idx(
1390 			link->dc, link->link_enc->transmitter);
1391 	if (dm_execute_dmub_cmd(link->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) &&
1392 			cmd.cable_id.header.ret_status == 1) {
1393 		cable_id->raw = cmd.cable_id.data.output_raw;
1394 		DC_LOG_DC("usbc_cable_id = %d.\n", cable_id->raw);
1395 	}
1396 	return cmd.cable_id.header.ret_status == 1;
1397 }
1398 
retrieve_cable_id(struct dc_link * link)1399 static void retrieve_cable_id(struct dc_link *link)
1400 {
1401 	union dp_cable_id usbc_cable_id;
1402 
1403 	link->dpcd_caps.cable_id.raw = 0;
1404 	core_link_read_dpcd(link, DP_CABLE_ATTRIBUTES_UPDATED_BY_DPRX,
1405 			&link->dpcd_caps.cable_id.raw, sizeof(uint8_t));
1406 
1407 	if (get_usbc_cable_id(link, &usbc_cable_id))
1408 		link->dpcd_caps.cable_id = intersect_cable_id(
1409 				&link->dpcd_caps.cable_id, &usbc_cable_id);
1410 }
1411 
read_is_mst_supported(struct dc_link * link)1412 bool read_is_mst_supported(struct dc_link *link)
1413 {
1414 	bool mst          = false;
1415 	enum dc_status st = DC_OK;
1416 	union dpcd_rev rev;
1417 	union mstm_cap cap;
1418 
1419 	if (link->preferred_training_settings.mst_enable &&
1420 		*link->preferred_training_settings.mst_enable == false) {
1421 		return false;
1422 	}
1423 
1424 	rev.raw  = 0;
1425 	cap.raw  = 0;
1426 
1427 	st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw,
1428 			sizeof(rev));
1429 
1430 	if (st == DC_OK && rev.raw >= DPCD_REV_12) {
1431 
1432 		st = core_link_read_dpcd(link, DP_MSTM_CAP,
1433 				&cap.raw, sizeof(cap));
1434 		if (st == DC_OK && cap.bits.MST_CAP == 1)
1435 			mst = true;
1436 	}
1437 	return mst;
1438 
1439 }
1440 
1441 /* Read additional sink caps defined in source specific DPCD area
1442  * This function currently only reads from SinkCapability address (DP_SOURCE_SINK_CAP)
1443  * TODO: Add FS caps and read from DP_SOURCE_SINK_FS_CAP as well
1444  */
dpcd_read_sink_ext_caps(struct dc_link * link)1445 static bool dpcd_read_sink_ext_caps(struct dc_link *link)
1446 {
1447 	uint8_t dpcd_data = 0;
1448 	uint8_t edp_general_cap2 = 0;
1449 
1450 	if (!link)
1451 		return false;
1452 
1453 	if (core_link_read_dpcd(link, DP_SOURCE_SINK_CAP, &dpcd_data, 1) != DC_OK)
1454 		return false;
1455 
1456 	link->dpcd_sink_ext_caps.raw = dpcd_data;
1457 
1458 	if (core_link_read_dpcd(link, DP_EDP_GENERAL_CAP_2, &edp_general_cap2, 1) != DC_OK)
1459 		return false;
1460 
1461 	link->dpcd_caps.panel_luminance_control = (edp_general_cap2 & DP_EDP_PANEL_LUMINANCE_CONTROL_CAPABLE) != 0;
1462 
1463 	return true;
1464 }
1465 
dp_retrieve_lttpr_cap(struct dc_link * link)1466 enum dc_status dp_retrieve_lttpr_cap(struct dc_link *link)
1467 {
1468 	uint8_t lttpr_dpcd_data[8];
1469 	enum dc_status status;
1470 	bool is_lttpr_present;
1471 
1472 	/* Logic to determine LTTPR support*/
1473 	bool vbios_lttpr_interop = link->dc->caps.vbios_lttpr_aware;
1474 
1475 	if (!vbios_lttpr_interop || !link->dc->caps.extended_aux_timeout_support)
1476 		return DC_NOT_SUPPORTED;
1477 
1478 	/* By reading LTTPR capability, RX assumes that we will enable
1479 	 * LTTPR extended aux timeout if LTTPR is present.
1480 	 */
1481 	status = core_link_read_dpcd(
1482 			link,
1483 			DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
1484 			lttpr_dpcd_data,
1485 			sizeof(lttpr_dpcd_data));
1486 
1487 	link->dpcd_caps.lttpr_caps.revision.raw =
1488 			lttpr_dpcd_data[DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV -
1489 							DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1490 
1491 	link->dpcd_caps.lttpr_caps.max_link_rate =
1492 			lttpr_dpcd_data[DP_MAX_LINK_RATE_PHY_REPEATER -
1493 							DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1494 
1495 	link->dpcd_caps.lttpr_caps.phy_repeater_cnt =
1496 			lttpr_dpcd_data[DP_PHY_REPEATER_CNT -
1497 							DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1498 
1499 	link->dpcd_caps.lttpr_caps.max_lane_count =
1500 			lttpr_dpcd_data[DP_MAX_LANE_COUNT_PHY_REPEATER -
1501 							DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1502 
1503 	link->dpcd_caps.lttpr_caps.mode =
1504 			lttpr_dpcd_data[DP_PHY_REPEATER_MODE -
1505 							DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1506 
1507 	link->dpcd_caps.lttpr_caps.max_ext_timeout =
1508 			lttpr_dpcd_data[DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT -
1509 							DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1510 	link->dpcd_caps.lttpr_caps.main_link_channel_coding.raw =
1511 			lttpr_dpcd_data[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER -
1512 							DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1513 
1514 	link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.raw =
1515 			lttpr_dpcd_data[DP_PHY_REPEATER_128B132B_RATES -
1516 							DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1517 
1518 	/* If this chip cap is set, at least one retimer must exist in the chain
1519 	 * Override count to 1 if we receive a known bad count (0 or an invalid value) */
1520 	if ((link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
1521 			(dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) == 0)) {
1522 		ASSERT(0);
1523 		link->dpcd_caps.lttpr_caps.phy_repeater_cnt = 0x80;
1524 		DC_LOG_DC("lttpr_caps forced phy_repeater_cnt = %d\n", link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1525 	}
1526 
1527 	/* Attempt to train in LTTPR transparent mode if repeater count exceeds 8. */
1528 	is_lttpr_present = dp_is_lttpr_present(link);
1529 
1530 	if (is_lttpr_present)
1531 		CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: ");
1532 
1533 	DC_LOG_DC("is_lttpr_present = %d\n", is_lttpr_present);
1534 	return status;
1535 }
1536 
retrieve_link_cap(struct dc_link * link)1537 static bool retrieve_link_cap(struct dc_link *link)
1538 {
1539 	/* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16,
1540 	 * which means size 16 will be good for both of those DPCD register block reads
1541 	 */
1542 	uint8_t dpcd_data[16];
1543 	/*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST.
1544 	 */
1545 	uint8_t dpcd_dprx_data = '\0';
1546 
1547 	struct dp_device_vendor_id sink_id;
1548 	union down_stream_port_count down_strm_port_count;
1549 	union edp_configuration_cap edp_config_cap;
1550 	union dp_downstream_port_present ds_port = { 0 };
1551 	enum dc_status status = DC_ERROR_UNEXPECTED;
1552 	uint32_t read_dpcd_retry_cnt = 3;
1553 	int i;
1554 	struct dp_sink_hw_fw_revision dp_hw_fw_revision;
1555 	const uint32_t post_oui_delay = 30; // 30ms
1556 	bool is_fec_supported = false;
1557 	bool is_dsc_basic_supported = false;
1558 	bool is_dsc_passthrough_supported = false;
1559 
1560 	memset(dpcd_data, '\0', sizeof(dpcd_data));
1561 	memset(&down_strm_port_count,
1562 		'\0', sizeof(union down_stream_port_count));
1563 	memset(&edp_config_cap, '\0',
1564 		sizeof(union edp_configuration_cap));
1565 
1566 	/* if extended timeout is supported in hardware,
1567 	 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
1568 	 * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
1569 	 */
1570 	try_to_configure_aux_timeout(link->ddc,
1571 			LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
1572 
1573 	status = dp_retrieve_lttpr_cap(link);
1574 
1575 	if (status != DC_OK) {
1576 		status = wake_up_aux_channel(link);
1577 		if (status == DC_OK)
1578 			dp_retrieve_lttpr_cap(link);
1579 		else
1580 			return false;
1581 	}
1582 
1583 	if (dp_is_lttpr_present(link)) {
1584 		configure_lttpr_mode_transparent(link);
1585 
1586 		// Echo TOTAL_LTTPR_CNT back downstream
1587 		core_link_write_dpcd(
1588 				link,
1589 				DP_TOTAL_LTTPR_CNT,
1590 				&link->dpcd_caps.lttpr_caps.phy_repeater_cnt,
1591 				sizeof(link->dpcd_caps.lttpr_caps.phy_repeater_cnt));
1592 	}
1593 
1594 	/* Read DP tunneling information. */
1595 	status = dpcd_get_tunneling_device_data(link);
1596 
1597 	dpcd_set_source_specific_data(link);
1598 	/* Sink may need to configure internals based on vendor, so allow some
1599 	 * time before proceeding with possibly vendor specific transactions
1600 	 */
1601 	msleep(post_oui_delay);
1602 
1603 	for (i = 0; i < read_dpcd_retry_cnt; i++) {
1604 		status = core_link_read_dpcd(
1605 				link,
1606 				DP_DPCD_REV,
1607 				dpcd_data,
1608 				sizeof(dpcd_data));
1609 		if (status == DC_OK)
1610 			break;
1611 	}
1612 
1613 
1614 	if (status != DC_OK) {
1615 		dm_error("%s: Read receiver caps dpcd data failed.\n", __func__);
1616 		return false;
1617 	}
1618 
1619 	if (!dp_is_lttpr_present(link))
1620 		try_to_configure_aux_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
1621 
1622 
1623 	{
1624 		union training_aux_rd_interval aux_rd_interval;
1625 
1626 		aux_rd_interval.raw =
1627 			dpcd_data[DP_TRAINING_AUX_RD_INTERVAL];
1628 
1629 		link->dpcd_caps.ext_receiver_cap_field_present =
1630 				aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1;
1631 
1632 		if (aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1) {
1633 			uint8_t ext_cap_data[16];
1634 
1635 			memset(ext_cap_data, '\0', sizeof(ext_cap_data));
1636 			for (i = 0; i < read_dpcd_retry_cnt; i++) {
1637 				status = core_link_read_dpcd(
1638 				link,
1639 				DP_DP13_DPCD_REV,
1640 				ext_cap_data,
1641 				sizeof(ext_cap_data));
1642 				if (status == DC_OK) {
1643 					memcpy(dpcd_data, ext_cap_data, sizeof(dpcd_data));
1644 					break;
1645 				}
1646 			}
1647 			if (status != DC_OK)
1648 				dm_error("%s: Read extend caps data failed, use cap from dpcd 0.\n", __func__);
1649 		}
1650 	}
1651 
1652 	link->dpcd_caps.dpcd_rev.raw =
1653 			dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
1654 
1655 	if (link->dpcd_caps.ext_receiver_cap_field_present) {
1656 		for (i = 0; i < read_dpcd_retry_cnt; i++) {
1657 			status = core_link_read_dpcd(
1658 					link,
1659 					DP_DPRX_FEATURE_ENUMERATION_LIST,
1660 					&dpcd_dprx_data,
1661 					sizeof(dpcd_dprx_data));
1662 			if (status == DC_OK)
1663 				break;
1664 		}
1665 
1666 		link->dpcd_caps.dprx_feature.raw = dpcd_dprx_data;
1667 
1668 		if (status != DC_OK)
1669 			dm_error("%s: Read DPRX caps data failed.\n", __func__);
1670 
1671 		/* AdaptiveSyncCapability  */
1672 		dpcd_dprx_data = 0;
1673 		for (i = 0; i < read_dpcd_retry_cnt; i++) {
1674 			status = core_link_read_dpcd(
1675 					link, DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1,
1676 					&dpcd_dprx_data, sizeof(dpcd_dprx_data));
1677 			if (status == DC_OK)
1678 				break;
1679 		}
1680 
1681 		link->dpcd_caps.adaptive_sync_caps.dp_adap_sync_caps.raw = dpcd_dprx_data;
1682 
1683 		if (status != DC_OK)
1684 			dm_error("%s: Read DPRX caps data failed. Addr:%#x\n",
1685 					__func__, DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1);
1686 	}
1687 
1688 	else {
1689 		link->dpcd_caps.dprx_feature.raw = 0;
1690 	}
1691 
1692 
1693 	/* Error condition checking...
1694 	 * It is impossible for Sink to report Max Lane Count = 0.
1695 	 * It is possible for Sink to report Max Link Rate = 0, if it is
1696 	 * an eDP device that is reporting specialized link rates in the
1697 	 * SUPPORTED_LINK_RATE table.
1698 	 */
1699 	if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
1700 		return false;
1701 
1702 	ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
1703 				 DP_DPCD_REV];
1704 
1705 	read_dp_device_vendor_id(link);
1706 
1707 	/* TODO - decouple raw mst capability from policy decision */
1708 	link->dpcd_caps.is_mst_capable = read_is_mst_supported(link);
1709 	DC_LOG_DC("%s: MST_Support: %s\n", __func__, str_yes_no(link->dpcd_caps.is_mst_capable));
1710 
1711 	get_active_converter_info(ds_port.byte, link);
1712 
1713 	dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data));
1714 
1715 	down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
1716 				 DP_DPCD_REV];
1717 
1718 	link->dpcd_caps.allow_invalid_MSA_timing_param =
1719 		down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
1720 
1721 	link->dpcd_caps.max_ln_count.raw = dpcd_data[
1722 		DP_MAX_LANE_COUNT - DP_DPCD_REV];
1723 
1724 	link->dpcd_caps.max_down_spread.raw = dpcd_data[
1725 		DP_MAX_DOWNSPREAD - DP_DPCD_REV];
1726 
1727 	link->reported_link_cap.lane_count =
1728 		link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
1729 	link->reported_link_cap.link_rate = get_link_rate_from_max_link_bw(
1730 			dpcd_data[DP_MAX_LINK_RATE - DP_DPCD_REV]);
1731 	link->reported_link_cap.link_spread =
1732 		link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
1733 		LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
1734 
1735 	edp_config_cap.raw = dpcd_data[
1736 		DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
1737 	link->dpcd_caps.panel_mode_edp =
1738 		edp_config_cap.bits.ALT_SCRAMBLER_RESET;
1739 	link->dpcd_caps.dpcd_display_control_capable =
1740 		edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
1741 	link->dpcd_caps.channel_coding_cap.raw =
1742 			dpcd_data[DP_MAIN_LINK_CHANNEL_CODING - DP_DPCD_REV];
1743 	link->test_pattern_enabled = false;
1744 	link->compliance_test_state.raw = 0;
1745 
1746 	/* read sink count */
1747 	core_link_read_dpcd(link,
1748 			DP_SINK_COUNT,
1749 			&link->dpcd_caps.sink_count.raw,
1750 			sizeof(link->dpcd_caps.sink_count.raw));
1751 
1752 	/* read sink ieee oui */
1753 	core_link_read_dpcd(link,
1754 			DP_SINK_OUI,
1755 			(uint8_t *)(&sink_id),
1756 			sizeof(sink_id));
1757 
1758 	link->dpcd_caps.sink_dev_id =
1759 			(sink_id.ieee_oui[0] << 16) +
1760 			(sink_id.ieee_oui[1] << 8) +
1761 			(sink_id.ieee_oui[2]);
1762 
1763 	memmove(
1764 		link->dpcd_caps.sink_dev_id_str,
1765 		sink_id.ieee_device_id,
1766 		sizeof(sink_id.ieee_device_id));
1767 
1768 	core_link_read_dpcd(
1769 		link,
1770 		DP_SINK_HW_REVISION_START,
1771 		(uint8_t *)&dp_hw_fw_revision,
1772 		sizeof(dp_hw_fw_revision));
1773 
1774 	link->dpcd_caps.sink_hw_revision =
1775 		dp_hw_fw_revision.ieee_hw_rev;
1776 
1777 	memmove(
1778 		link->dpcd_caps.sink_fw_revision,
1779 		dp_hw_fw_revision.ieee_fw_rev,
1780 		sizeof(dp_hw_fw_revision.ieee_fw_rev));
1781 
1782 	/* Quirk for Retina panels: wrong DP_MAX_LINK_RATE */
1783 	{
1784 		uint8_t str_mbp_2018[] = { 101, 68, 21, 103, 98, 97 };
1785 		uint8_t fwrev_mbp_2018[] = { 7, 4 };
1786 		uint8_t fwrev_mbp_2018_vega[] = { 8, 4 };
1787 
1788 		/* We also check for the firmware revision as 16,1 models have an
1789 		 * identical device id and are incorrectly quirked otherwise.
1790 		 */
1791 		if ((link->dpcd_caps.sink_dev_id == 0x0010fa) &&
1792 		    !memcmp(link->dpcd_caps.sink_dev_id_str, str_mbp_2018,
1793 			     sizeof(str_mbp_2018)) &&
1794 		    (!memcmp(link->dpcd_caps.sink_fw_revision, fwrev_mbp_2018,
1795 			     sizeof(fwrev_mbp_2018)) ||
1796 		    !memcmp(link->dpcd_caps.sink_fw_revision, fwrev_mbp_2018_vega,
1797 			     sizeof(fwrev_mbp_2018_vega)))) {
1798 			link->reported_link_cap.link_rate = LINK_RATE_RBR2;
1799 		}
1800 	}
1801 
1802 	memset(&link->dpcd_caps.dsc_caps, '\0',
1803 			sizeof(link->dpcd_caps.dsc_caps));
1804 	memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap));
1805 	/* Read DSC and FEC sink capabilities if DP revision is 1.4 and up */
1806 	if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14) {
1807 		status = core_link_read_dpcd(
1808 				link,
1809 				DP_FEC_CAPABILITY,
1810 				&link->dpcd_caps.fec_cap.raw,
1811 				sizeof(link->dpcd_caps.fec_cap.raw));
1812 		status = core_link_read_dpcd(
1813 				link,
1814 				DP_DSC_SUPPORT,
1815 				link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
1816 				sizeof(link->dpcd_caps.dsc_caps.dsc_basic_caps.raw));
1817 		if (status == DC_OK) {
1818 			is_fec_supported = link->dpcd_caps.fec_cap.bits.FEC_CAPABLE;
1819 			is_dsc_basic_supported = link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT;
1820 			is_dsc_passthrough_supported = link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT;
1821 			DC_LOG_DC("%s: FEC_Sink_Support: %s\n", __func__,
1822 				  str_yes_no(is_fec_supported));
1823 			DC_LOG_DC("%s: DSC_Basic_Sink_Support: %s\n", __func__,
1824 				  str_yes_no(is_dsc_basic_supported));
1825 			DC_LOG_DC("%s: DSC_Passthrough_Sink_Support: %s\n", __func__,
1826 				  str_yes_no(is_dsc_passthrough_supported));
1827 		}
1828 		if (link->dpcd_caps.dongle_type != DISPLAY_DONGLE_NONE) {
1829 			status = core_link_read_dpcd(
1830 					link,
1831 					DP_DSC_BRANCH_OVERALL_THROUGHPUT_0,
1832 					link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
1833 					sizeof(link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw));
1834 			DC_LOG_DSC("DSC branch decoder capability is read at link %d", link->link_index);
1835 			DC_LOG_DSC("\tBRANCH_OVERALL_THROUGHPUT_0 = 0x%02x",
1836 					link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.fields.BRANCH_OVERALL_THROUGHPUT_0);
1837 			DC_LOG_DSC("\tBRANCH_OVERALL_THROUGHPUT_1 = 0x%02x",
1838 					link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.fields.BRANCH_OVERALL_THROUGHPUT_1);
1839 			DC_LOG_DSC("\tBRANCH_MAX_LINE_WIDTH 0x%02x",
1840 					link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.fields.BRANCH_MAX_LINE_WIDTH);
1841 		}
1842 
1843 		/* Apply work around to disable FEC and DSC for USB4 tunneling in TBT3 compatibility mode
1844 		 * only if required.
1845 		 */
1846 		if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
1847 				link->dc->debug.dpia_debug.bits.enable_force_tbt3_work_around &&
1848 				link->dpcd_caps.is_branch_dev &&
1849 				link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
1850 				link->dpcd_caps.branch_hw_revision == DP_BRANCH_HW_REV_10 &&
1851 				(link->dpcd_caps.fec_cap.bits.FEC_CAPABLE ||
1852 				link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT)) {
1853 			/* A TBT3 device is expected to report no support for FEC or DSC to a USB4 DPIA.
1854 			 * Clear FEC and DSC capabilities as a work around if that is not the case.
1855 			 */
1856 			link->wa_flags.dpia_forced_tbt3_mode = true;
1857 			memset(&link->dpcd_caps.dsc_caps, '\0', sizeof(link->dpcd_caps.dsc_caps));
1858 			memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap));
1859 			DC_LOG_DSC("Clear DSC SUPPORT for USB4 link(%d) in TBT3 compatibility mode", link->link_index);
1860 		} else
1861 			link->wa_flags.dpia_forced_tbt3_mode = false;
1862 	}
1863 
1864 	if (!dpcd_read_sink_ext_caps(link))
1865 		link->dpcd_sink_ext_caps.raw = 0;
1866 
1867 	if (link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED) {
1868 		DC_LOG_DP2("128b/132b encoding is supported at link %d", link->link_index);
1869 
1870 		core_link_read_dpcd(link,
1871 				DP_128B132B_SUPPORTED_LINK_RATES,
1872 				&link->dpcd_caps.dp_128b_132b_supported_link_rates.raw,
1873 				sizeof(link->dpcd_caps.dp_128b_132b_supported_link_rates.raw));
1874 		if (link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR20)
1875 			link->reported_link_cap.link_rate = LINK_RATE_UHBR20;
1876 		else if (link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR13_5)
1877 			link->reported_link_cap.link_rate = LINK_RATE_UHBR13_5;
1878 		else if (link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR10)
1879 			link->reported_link_cap.link_rate = LINK_RATE_UHBR10;
1880 		else
1881 			dm_error("%s: Invalid RX 128b_132b_supported_link_rates\n", __func__);
1882 		DC_LOG_DP2("128b/132b supported link rates is read at link %d", link->link_index);
1883 		DC_LOG_DP2("\tmax 128b/132b link rate support is %d.%d GHz",
1884 				link->reported_link_cap.link_rate / 100,
1885 				link->reported_link_cap.link_rate % 100);
1886 
1887 		core_link_read_dpcd(link,
1888 				DP_SINK_VIDEO_FALLBACK_FORMATS,
1889 				&link->dpcd_caps.fallback_formats.raw,
1890 				sizeof(link->dpcd_caps.fallback_formats.raw));
1891 		DC_LOG_DP2("sink video fallback format is read at link %d", link->link_index);
1892 		if (link->dpcd_caps.fallback_formats.bits.dp_1920x1080_60Hz_24bpp_support)
1893 			DC_LOG_DP2("\t1920x1080@60Hz 24bpp fallback format supported");
1894 		if (link->dpcd_caps.fallback_formats.bits.dp_1280x720_60Hz_24bpp_support)
1895 			DC_LOG_DP2("\t1280x720@60Hz 24bpp fallback format supported");
1896 		if (link->dpcd_caps.fallback_formats.bits.dp_1024x768_60Hz_24bpp_support)
1897 			DC_LOG_DP2("\t1024x768@60Hz 24bpp fallback format supported");
1898 		if (link->dpcd_caps.fallback_formats.raw == 0) {
1899 			DC_LOG_DP2("\tno supported fallback formats, assume 1920x1080@60Hz 24bpp is supported");
1900 			link->dpcd_caps.fallback_formats.bits.dp_1920x1080_60Hz_24bpp_support = 1;
1901 		}
1902 
1903 		core_link_read_dpcd(link,
1904 				DP_FEC_CAPABILITY_1,
1905 				&link->dpcd_caps.fec_cap1.raw,
1906 				sizeof(link->dpcd_caps.fec_cap1.raw));
1907 		DC_LOG_DP2("FEC CAPABILITY 1 is read at link %d", link->link_index);
1908 		if (link->dpcd_caps.fec_cap1.bits.AGGREGATED_ERROR_COUNTERS_CAPABLE)
1909 			DC_LOG_DP2("\tFEC aggregated error counters are supported");
1910 	}
1911 
1912 	retrieve_cable_id(link);
1913 	dpcd_write_cable_id_to_dprx(link);
1914 
1915 	/* Connectivity log: detection */
1916 	CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: ");
1917 
1918 	return true;
1919 }
1920 
detect_dp_sink_caps(struct dc_link * link)1921 bool detect_dp_sink_caps(struct dc_link *link)
1922 {
1923 	return retrieve_link_cap(link);
1924 }
1925 
detect_edp_sink_caps(struct dc_link * link)1926 void detect_edp_sink_caps(struct dc_link *link)
1927 {
1928 	uint8_t supported_link_rates[16];
1929 	uint32_t entry;
1930 	uint32_t link_rate_in_khz;
1931 	enum dc_link_rate link_rate = LINK_RATE_UNKNOWN;
1932 	uint8_t backlight_adj_cap;
1933 	uint8_t general_edp_cap;
1934 
1935 	retrieve_link_cap(link);
1936 	link->dpcd_caps.edp_supported_link_rates_count = 0;
1937 	memset(supported_link_rates, 0, sizeof(supported_link_rates));
1938 
1939 	/*
1940 	 * edp_supported_link_rates_count is only valid for eDP v1.4 or higher.
1941 	 * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
1942 	 */
1943 	if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_13) {
1944 		// Read DPCD 00010h - 0001Fh 16 bytes at one shot
1945 		core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
1946 							supported_link_rates, sizeof(supported_link_rates));
1947 
1948 		for (entry = 0; entry < 16; entry += 2) {
1949 			// DPCD register reports per-lane link rate = 16-bit link rate capability
1950 			// value X 200 kHz. Need multiplier to find link rate in kHz.
1951 			link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 +
1952 										supported_link_rates[entry]) * 200;
1953 
1954 			DC_LOG_DC("%s: eDP v1.4 supported sink rates: [%d] %d kHz\n", __func__,
1955 				  entry / 2, link_rate_in_khz);
1956 
1957 			if (link_rate_in_khz != 0) {
1958 				link_rate = linkRateInKHzToLinkRateMultiplier(link_rate_in_khz);
1959 				link->dpcd_caps.edp_supported_link_rates[link->dpcd_caps.edp_supported_link_rates_count] = link_rate;
1960 				link->dpcd_caps.edp_supported_link_rates_count++;
1961 			}
1962 		}
1963 	}
1964 
1965 	core_link_read_dpcd(link, DP_EDP_BACKLIGHT_ADJUSTMENT_CAP,
1966 						&backlight_adj_cap, sizeof(backlight_adj_cap));
1967 
1968 	link->dpcd_caps.dynamic_backlight_capable_edp =
1969 				(backlight_adj_cap & DP_EDP_DYNAMIC_BACKLIGHT_CAP) ? true:false;
1970 
1971 	core_link_read_dpcd(link, DP_EDP_GENERAL_CAP_1,
1972 						&general_edp_cap, sizeof(general_edp_cap));
1973 
1974 	link->dpcd_caps.set_power_state_capable_edp =
1975 				(general_edp_cap & DP_EDP_SET_POWER_CAP) ? true:false;
1976 
1977 	set_default_brightness_aux(link);
1978 
1979 	core_link_read_dpcd(link, DP_EDP_DPCD_REV,
1980 		&link->dpcd_caps.edp_rev,
1981 		sizeof(link->dpcd_caps.edp_rev));
1982 	/*
1983 	 * PSR is only valid for eDP v1.3 or higher.
1984 	 */
1985 	if (link->dpcd_caps.edp_rev >= DP_EDP_13) {
1986 		core_link_read_dpcd(link, DP_PSR_SUPPORT,
1987 			&link->dpcd_caps.psr_info.psr_version,
1988 			sizeof(link->dpcd_caps.psr_info.psr_version));
1989 		if (link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_001CF8)
1990 			core_link_read_dpcd(link, DP_FORCE_PSRSU_CAPABILITY,
1991 						&link->dpcd_caps.psr_info.force_psrsu_cap,
1992 						sizeof(link->dpcd_caps.psr_info.force_psrsu_cap));
1993 		core_link_read_dpcd(link, DP_PSR_CAPS,
1994 			&link->dpcd_caps.psr_info.psr_dpcd_caps.raw,
1995 			sizeof(link->dpcd_caps.psr_info.psr_dpcd_caps.raw));
1996 		if (link->dpcd_caps.psr_info.psr_dpcd_caps.bits.Y_COORDINATE_REQUIRED) {
1997 			core_link_read_dpcd(link, DP_PSR2_SU_Y_GRANULARITY,
1998 				&link->dpcd_caps.psr_info.psr2_su_y_granularity_cap,
1999 				sizeof(link->dpcd_caps.psr_info.psr2_su_y_granularity_cap));
2000 		}
2001 	}
2002 
2003 	/*
2004 	 * ALPM is only valid for eDP v1.4 or higher.
2005 	 */
2006 	if (link->dpcd_caps.dpcd_rev.raw >= DP_EDP_14)
2007 		core_link_read_dpcd(link, DP_RECEIVER_ALPM_CAP,
2008 			&link->dpcd_caps.alpm_caps.raw,
2009 			sizeof(link->dpcd_caps.alpm_caps.raw));
2010 
2011 	/*
2012 	 * Read REPLAY info
2013 	 */
2014 	core_link_read_dpcd(link, DP_SINK_PR_PIXEL_DEVIATION_PER_LINE,
2015 			&link->dpcd_caps.pr_info.pixel_deviation_per_line,
2016 			sizeof(link->dpcd_caps.pr_info.pixel_deviation_per_line));
2017 	core_link_read_dpcd(link, DP_SINK_PR_MAX_NUMBER_OF_DEVIATION_LINE,
2018 			&link->dpcd_caps.pr_info.max_deviation_line,
2019 			sizeof(link->dpcd_caps.pr_info.max_deviation_line));
2020 }
2021 
dp_get_max_link_enc_cap(const struct dc_link * link,struct dc_link_settings * max_link_enc_cap)2022 bool dp_get_max_link_enc_cap(const struct dc_link *link, struct dc_link_settings *max_link_enc_cap)
2023 {
2024 	struct link_encoder *link_enc = NULL;
2025 
2026 	if (!max_link_enc_cap) {
2027 		DC_LOG_ERROR("%s: Could not return max link encoder caps", __func__);
2028 		return false;
2029 	}
2030 
2031 	link_enc = link_enc_cfg_get_link_enc(link);
2032 	ASSERT(link_enc);
2033 
2034 	if (link_enc && link_enc->funcs->get_max_link_cap) {
2035 		link_enc->funcs->get_max_link_cap(link_enc, max_link_enc_cap);
2036 		return true;
2037 	}
2038 
2039 	DC_LOG_ERROR("%s: Max link encoder caps unknown", __func__);
2040 	max_link_enc_cap->lane_count = 1;
2041 	max_link_enc_cap->link_rate = 6;
2042 	return false;
2043 }
2044 
dp_get_verified_link_cap(const struct dc_link * link)2045 const struct dc_link_settings *dp_get_verified_link_cap(
2046 		const struct dc_link *link)
2047 {
2048 	if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN &&
2049 			link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
2050 		return &link->preferred_link_setting;
2051 	return &link->verified_link_cap;
2052 }
2053 
dp_get_max_link_cap(struct dc_link * link)2054 struct dc_link_settings dp_get_max_link_cap(struct dc_link *link)
2055 {
2056 	struct dc_link_settings max_link_cap = {0};
2057 	enum dc_link_rate lttpr_max_link_rate;
2058 	enum dc_link_rate cable_max_link_rate;
2059 	struct link_encoder *link_enc = NULL;
2060 
2061 
2062 	link_enc = link_enc_cfg_get_link_enc(link);
2063 	ASSERT(link_enc);
2064 
2065 	/* get max link encoder capability */
2066 	if (link_enc)
2067 		link_enc->funcs->get_max_link_cap(link_enc, &max_link_cap);
2068 
2069 	/* Lower link settings based on sink's link cap */
2070 	if (link->reported_link_cap.lane_count < max_link_cap.lane_count)
2071 		max_link_cap.lane_count =
2072 				link->reported_link_cap.lane_count;
2073 	if (link->reported_link_cap.link_rate < max_link_cap.link_rate)
2074 		max_link_cap.link_rate =
2075 				link->reported_link_cap.link_rate;
2076 	if (link->reported_link_cap.link_spread <
2077 			max_link_cap.link_spread)
2078 		max_link_cap.link_spread =
2079 				link->reported_link_cap.link_spread;
2080 
2081 	/* Lower link settings based on cable attributes
2082 	 * Cable ID is a DP2 feature to identify max certified link rate that
2083 	 * a cable can carry. The cable identification method requires both
2084 	 * cable and display hardware support. Since the specs comes late, it is
2085 	 * anticipated that the first round of DP2 cables and displays may not
2086 	 * be fully compatible to reliably return cable ID data. Therefore the
2087 	 * decision of our cable id policy is that if the cable can return non
2088 	 * zero cable id data, we will take cable's link rate capability into
2089 	 * account. However if we get zero data, the cable link rate capability
2090 	 * is considered inconclusive. In this case, we will not take cable's
2091 	 * capability into account to avoid of over limiting hardware capability
2092 	 * from users. The max overall link rate capability is still determined
2093 	 * after actual dp pre-training. Cable id is considered as an auxiliary
2094 	 * method of determining max link bandwidth capability.
2095 	 */
2096 	cable_max_link_rate = get_cable_max_link_rate(link);
2097 
2098 	if (!link->dc->debug.ignore_cable_id &&
2099 			cable_max_link_rate != LINK_RATE_UNKNOWN &&
2100 			cable_max_link_rate < max_link_cap.link_rate)
2101 		max_link_cap.link_rate = cable_max_link_rate;
2102 
2103 	/* account for lttpr repeaters cap
2104 	 * notes: repeaters do not snoop in the DPRX Capabilities addresses (3.6.3).
2105 	 */
2106 	if (dp_is_lttpr_present(link)) {
2107 		if (link->dpcd_caps.lttpr_caps.max_lane_count < max_link_cap.lane_count)
2108 			max_link_cap.lane_count = link->dpcd_caps.lttpr_caps.max_lane_count;
2109 		lttpr_max_link_rate = get_lttpr_max_link_rate(link);
2110 
2111 		if (lttpr_max_link_rate < max_link_cap.link_rate)
2112 			max_link_cap.link_rate = lttpr_max_link_rate;
2113 
2114 		DC_LOG_HW_LINK_TRAINING("%s\n Training with LTTPR,  max_lane count %d max_link rate %d \n",
2115 						__func__,
2116 						max_link_cap.lane_count,
2117 						max_link_cap.link_rate);
2118 	}
2119 
2120 	if (link_dp_get_encoding_format(&max_link_cap) == DP_128b_132b_ENCODING &&
2121 			link->dc->debug.disable_uhbr)
2122 		max_link_cap.link_rate = LINK_RATE_HIGH3;
2123 
2124 	return max_link_cap;
2125 }
2126 
dp_verify_link_cap(struct dc_link * link,struct dc_link_settings * known_limit_link_setting,int * fail_count)2127 static bool dp_verify_link_cap(
2128 	struct dc_link *link,
2129 	struct dc_link_settings *known_limit_link_setting,
2130 	int *fail_count)
2131 {
2132 	struct dc_link_settings cur_link_settings = {0};
2133 	struct dc_link_settings max_link_settings = *known_limit_link_setting;
2134 	bool success = false;
2135 	bool skip_video_pattern;
2136 	enum clock_source_id dp_cs_id = get_clock_source_id(link);
2137 	enum link_training_result status = LINK_TRAINING_SUCCESS;
2138 	union hpd_irq_data irq_data;
2139 	struct link_resource link_res;
2140 
2141 	memset(&irq_data, 0, sizeof(irq_data));
2142 	cur_link_settings = max_link_settings;
2143 
2144 	/* Grant extended timeout request */
2145 	if (dp_is_lttpr_present(link) && link->dpcd_caps.lttpr_caps.max_ext_timeout > 0) {
2146 		uint8_t grant = link->dpcd_caps.lttpr_caps.max_ext_timeout & 0x80;
2147 
2148 		core_link_write_dpcd(link, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT, &grant, sizeof(grant));
2149 	}
2150 
2151 	do {
2152 		if (!get_temp_dp_link_res(link, &link_res, &cur_link_settings))
2153 			continue;
2154 
2155 		skip_video_pattern = cur_link_settings.link_rate != LINK_RATE_LOW;
2156 		dp_enable_link_phy(
2157 				link,
2158 				&link_res,
2159 				link->connector_signal,
2160 				dp_cs_id,
2161 				&cur_link_settings);
2162 
2163 		status = dp_perform_link_training(
2164 				link,
2165 				&link_res,
2166 				&cur_link_settings,
2167 				skip_video_pattern);
2168 
2169 		if (status == LINK_TRAINING_SUCCESS) {
2170 			success = true;
2171 			fsleep(1000);
2172 			if (dp_read_hpd_rx_irq_data(link, &irq_data) == DC_OK &&
2173 					dp_parse_link_loss_status(
2174 							link,
2175 							&irq_data))
2176 				(*fail_count)++;
2177 		} else if (status == LINK_TRAINING_LINK_LOSS) {
2178 			success = true;
2179 			(*fail_count)++;
2180 		} else {
2181 			(*fail_count)++;
2182 		}
2183 		dp_trace_lt_total_count_increment(link, true);
2184 		dp_trace_lt_result_update(link, status, true);
2185 		dp_disable_link_phy(link, &link_res, link->connector_signal);
2186 	} while (!success && decide_fallback_link_setting(link,
2187 			&max_link_settings, &cur_link_settings, status));
2188 
2189 	link->verified_link_cap = success ?
2190 			cur_link_settings : fail_safe_link_settings;
2191 	return success;
2192 }
2193 
dp_verify_link_cap_with_retries(struct dc_link * link,struct dc_link_settings * known_limit_link_setting,int attempts)2194 bool dp_verify_link_cap_with_retries(
2195 	struct dc_link *link,
2196 	struct dc_link_settings *known_limit_link_setting,
2197 	int attempts)
2198 {
2199 	int i = 0;
2200 	bool success = false;
2201 	int fail_count = 0;
2202 	struct dc_link_settings last_verified_link_cap = fail_safe_link_settings;
2203 
2204 	dp_trace_detect_lt_init(link);
2205 
2206 	if (link->link_enc && link->link_enc->features.flags.bits.DP_IS_USB_C &&
2207 			link->dc->debug.usbc_combo_phy_reset_wa)
2208 		apply_usbc_combo_phy_reset_wa(link, known_limit_link_setting);
2209 
2210 	dp_trace_set_lt_start_timestamp(link, false);
2211 	for (i = 0; i < attempts; i++) {
2212 		enum dc_connection_type type = dc_connection_none;
2213 
2214 		memset(&link->verified_link_cap, 0,
2215 				sizeof(struct dc_link_settings));
2216 		if (!link_detect_connection_type(link, &type) || type == dc_connection_none) {
2217 			link->verified_link_cap = fail_safe_link_settings;
2218 			break;
2219 		} else if (dp_verify_link_cap(link, known_limit_link_setting, &fail_count)) {
2220 			last_verified_link_cap = link->verified_link_cap;
2221 			if (fail_count == 0) {
2222 				success = true;
2223 				break;
2224 			}
2225 		} else {
2226 			link->verified_link_cap = last_verified_link_cap;
2227 		}
2228 		fsleep(10 * 1000);
2229 	}
2230 
2231 	dp_trace_lt_fail_count_update(link, fail_count, true);
2232 	dp_trace_set_lt_end_timestamp(link, true);
2233 
2234 	return success;
2235 }
2236 
2237 /*
2238  * Check if there is a native DP or passive DP-HDMI dongle connected
2239  */
dp_is_sink_present(struct dc_link * link)2240 bool dp_is_sink_present(struct dc_link *link)
2241 {
2242 	enum gpio_result gpio_result;
2243 	uint32_t clock_pin = 0;
2244 	uint8_t retry = 0;
2245 	struct ddc *ddc;
2246 
2247 	enum connector_id connector_id =
2248 		dal_graphics_object_id_get_connector_id(link->link_id);
2249 
2250 	bool present =
2251 		((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
2252 		(connector_id == CONNECTOR_ID_EDP) ||
2253 		(connector_id == CONNECTOR_ID_USBC));
2254 
2255 	ddc = get_ddc_pin(link->ddc);
2256 
2257 	if (!ddc) {
2258 		BREAK_TO_DEBUGGER();
2259 		return present;
2260 	}
2261 
2262 	/* Open GPIO and set it to I2C mode */
2263 	/* Note: this GpioMode_Input will be converted
2264 	 * to GpioConfigType_I2cAuxDualMode in GPIO component,
2265 	 * which indicates we need additional delay
2266 	 */
2267 
2268 	if (dal_ddc_open(ddc, GPIO_MODE_INPUT,
2269 			 GPIO_DDC_CONFIG_TYPE_MODE_I2C) != GPIO_RESULT_OK) {
2270 		dal_ddc_close(ddc);
2271 
2272 		return present;
2273 	}
2274 
2275 	/*
2276 	 * Read GPIO: DP sink is present if both clock and data pins are zero
2277 	 *
2278 	 * [W/A] plug-unplug DP cable, sometimes customer board has
2279 	 * one short pulse on clk_pin(1V, < 1ms). DP will be config to HDMI/DVI
2280 	 * then monitor can't br light up. Add retry 3 times
2281 	 * But in real passive dongle, it need additional 3ms to detect
2282 	 */
2283 	do {
2284 		gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
2285 		ASSERT(gpio_result == GPIO_RESULT_OK);
2286 		if (clock_pin)
2287 			fsleep(1000);
2288 		else
2289 			break;
2290 	} while (retry++ < 3);
2291 
2292 	present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
2293 
2294 	dal_ddc_close(ddc);
2295 
2296 	return present;
2297 }
2298