xref: /openbmc/linux/drivers/pwm/pwm-rcar.c (revision d6a436c7)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * R-Car PWM Timer driver
4  *
5  * Copyright (C) 2015 Renesas Electronics Corporation
6  *
7  * Limitations:
8  * - The hardware cannot generate a 0% duty cycle.
9  */
10 
11 #include <linux/clk.h>
12 #include <linux/err.h>
13 #include <linux/io.h>
14 #include <linux/log2.h>
15 #include <linux/math64.h>
16 #include <linux/module.h>
17 #include <linux/of.h>
18 #include <linux/platform_device.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/pwm.h>
21 #include <linux/slab.h>
22 
23 #define RCAR_PWM_MAX_DIVISION	24
24 #define RCAR_PWM_MAX_CYCLE	1023
25 
26 #define RCAR_PWMCR		0x00
27 #define  RCAR_PWMCR_CC0_MASK	0x000f0000
28 #define  RCAR_PWMCR_CC0_SHIFT	16
29 #define  RCAR_PWMCR_CCMD	BIT(15)
30 #define  RCAR_PWMCR_SYNC	BIT(11)
31 #define  RCAR_PWMCR_SS0		BIT(4)
32 #define  RCAR_PWMCR_EN0		BIT(0)
33 
34 #define RCAR_PWMCNT		0x04
35 #define  RCAR_PWMCNT_CYC0_MASK	0x03ff0000
36 #define  RCAR_PWMCNT_CYC0_SHIFT	16
37 #define  RCAR_PWMCNT_PH0_MASK	0x000003ff
38 #define  RCAR_PWMCNT_PH0_SHIFT	0
39 
40 struct rcar_pwm_chip {
41 	struct pwm_chip chip;
42 	void __iomem *base;
43 	struct clk *clk;
44 };
45 
to_rcar_pwm_chip(struct pwm_chip * chip)46 static inline struct rcar_pwm_chip *to_rcar_pwm_chip(struct pwm_chip *chip)
47 {
48 	return container_of(chip, struct rcar_pwm_chip, chip);
49 }
50 
rcar_pwm_write(struct rcar_pwm_chip * rp,u32 data,unsigned int offset)51 static void rcar_pwm_write(struct rcar_pwm_chip *rp, u32 data,
52 			   unsigned int offset)
53 {
54 	writel(data, rp->base + offset);
55 }
56 
rcar_pwm_read(struct rcar_pwm_chip * rp,unsigned int offset)57 static u32 rcar_pwm_read(struct rcar_pwm_chip *rp, unsigned int offset)
58 {
59 	return readl(rp->base + offset);
60 }
61 
rcar_pwm_update(struct rcar_pwm_chip * rp,u32 mask,u32 data,unsigned int offset)62 static void rcar_pwm_update(struct rcar_pwm_chip *rp, u32 mask, u32 data,
63 			    unsigned int offset)
64 {
65 	u32 value;
66 
67 	value = rcar_pwm_read(rp, offset);
68 	value &= ~mask;
69 	value |= data & mask;
70 	rcar_pwm_write(rp, value, offset);
71 }
72 
rcar_pwm_get_clock_division(struct rcar_pwm_chip * rp,int period_ns)73 static int rcar_pwm_get_clock_division(struct rcar_pwm_chip *rp, int period_ns)
74 {
75 	unsigned long clk_rate = clk_get_rate(rp->clk);
76 	u64 div, tmp;
77 
78 	if (clk_rate == 0)
79 		return -EINVAL;
80 
81 	div = (u64)NSEC_PER_SEC * RCAR_PWM_MAX_CYCLE;
82 	tmp = (u64)period_ns * clk_rate + div - 1;
83 	tmp = div64_u64(tmp, div);
84 	div = ilog2(tmp - 1) + 1;
85 
86 	return (div <= RCAR_PWM_MAX_DIVISION) ? div : -ERANGE;
87 }
88 
rcar_pwm_set_clock_control(struct rcar_pwm_chip * rp,unsigned int div)89 static void rcar_pwm_set_clock_control(struct rcar_pwm_chip *rp,
90 				       unsigned int div)
91 {
92 	u32 value;
93 
94 	value = rcar_pwm_read(rp, RCAR_PWMCR);
95 	value &= ~(RCAR_PWMCR_CCMD | RCAR_PWMCR_CC0_MASK);
96 
97 	if (div & 1)
98 		value |= RCAR_PWMCR_CCMD;
99 
100 	div >>= 1;
101 
102 	value |= div << RCAR_PWMCR_CC0_SHIFT;
103 	rcar_pwm_write(rp, value, RCAR_PWMCR);
104 }
105 
rcar_pwm_set_counter(struct rcar_pwm_chip * rp,int div,int duty_ns,int period_ns)106 static int rcar_pwm_set_counter(struct rcar_pwm_chip *rp, int div, int duty_ns,
107 				int period_ns)
108 {
109 	unsigned long long one_cycle, tmp;	/* 0.01 nanoseconds */
110 	unsigned long clk_rate = clk_get_rate(rp->clk);
111 	u32 cyc, ph;
112 
113 	one_cycle = NSEC_PER_SEC * 100ULL << div;
114 	do_div(one_cycle, clk_rate);
115 
116 	tmp = period_ns * 100ULL;
117 	do_div(tmp, one_cycle);
118 	cyc = (tmp << RCAR_PWMCNT_CYC0_SHIFT) & RCAR_PWMCNT_CYC0_MASK;
119 
120 	tmp = duty_ns * 100ULL;
121 	do_div(tmp, one_cycle);
122 	ph = tmp & RCAR_PWMCNT_PH0_MASK;
123 
124 	/* Avoid prohibited setting */
125 	if (cyc == 0 || ph == 0)
126 		return -EINVAL;
127 
128 	rcar_pwm_write(rp, cyc | ph, RCAR_PWMCNT);
129 
130 	return 0;
131 }
132 
rcar_pwm_request(struct pwm_chip * chip,struct pwm_device * pwm)133 static int rcar_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
134 {
135 	return pm_runtime_get_sync(chip->dev);
136 }
137 
rcar_pwm_free(struct pwm_chip * chip,struct pwm_device * pwm)138 static void rcar_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
139 {
140 	pm_runtime_put(chip->dev);
141 }
142 
rcar_pwm_enable(struct rcar_pwm_chip * rp)143 static int rcar_pwm_enable(struct rcar_pwm_chip *rp)
144 {
145 	u32 value;
146 
147 	/* Don't enable the PWM device if CYC0 or PH0 is 0 */
148 	value = rcar_pwm_read(rp, RCAR_PWMCNT);
149 	if ((value & RCAR_PWMCNT_CYC0_MASK) == 0 ||
150 	    (value & RCAR_PWMCNT_PH0_MASK) == 0)
151 		return -EINVAL;
152 
153 	rcar_pwm_update(rp, RCAR_PWMCR_EN0, RCAR_PWMCR_EN0, RCAR_PWMCR);
154 
155 	return 0;
156 }
157 
rcar_pwm_disable(struct rcar_pwm_chip * rp)158 static void rcar_pwm_disable(struct rcar_pwm_chip *rp)
159 {
160 	rcar_pwm_update(rp, RCAR_PWMCR_EN0, 0, RCAR_PWMCR);
161 }
162 
rcar_pwm_apply(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)163 static int rcar_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
164 			  const struct pwm_state *state)
165 {
166 	struct rcar_pwm_chip *rp = to_rcar_pwm_chip(chip);
167 	int div, ret;
168 
169 	/* This HW/driver only supports normal polarity */
170 	if (state->polarity != PWM_POLARITY_NORMAL)
171 		return -EINVAL;
172 
173 	if (!state->enabled) {
174 		rcar_pwm_disable(rp);
175 		return 0;
176 	}
177 
178 	div = rcar_pwm_get_clock_division(rp, state->period);
179 	if (div < 0)
180 		return div;
181 
182 	rcar_pwm_update(rp, RCAR_PWMCR_SYNC, RCAR_PWMCR_SYNC, RCAR_PWMCR);
183 
184 	ret = rcar_pwm_set_counter(rp, div, state->duty_cycle, state->period);
185 	if (!ret)
186 		rcar_pwm_set_clock_control(rp, div);
187 
188 	/* The SYNC should be set to 0 even if rcar_pwm_set_counter failed */
189 	rcar_pwm_update(rp, RCAR_PWMCR_SYNC, 0, RCAR_PWMCR);
190 
191 	if (!ret)
192 		ret = rcar_pwm_enable(rp);
193 
194 	return ret;
195 }
196 
197 static const struct pwm_ops rcar_pwm_ops = {
198 	.request = rcar_pwm_request,
199 	.free = rcar_pwm_free,
200 	.apply = rcar_pwm_apply,
201 	.owner = THIS_MODULE,
202 };
203 
rcar_pwm_probe(struct platform_device * pdev)204 static int rcar_pwm_probe(struct platform_device *pdev)
205 {
206 	struct rcar_pwm_chip *rcar_pwm;
207 	int ret;
208 
209 	rcar_pwm = devm_kzalloc(&pdev->dev, sizeof(*rcar_pwm), GFP_KERNEL);
210 	if (rcar_pwm == NULL)
211 		return -ENOMEM;
212 
213 	rcar_pwm->base = devm_platform_ioremap_resource(pdev, 0);
214 	if (IS_ERR(rcar_pwm->base))
215 		return PTR_ERR(rcar_pwm->base);
216 
217 	rcar_pwm->clk = devm_clk_get(&pdev->dev, NULL);
218 	if (IS_ERR(rcar_pwm->clk)) {
219 		dev_err(&pdev->dev, "cannot get clock\n");
220 		return PTR_ERR(rcar_pwm->clk);
221 	}
222 
223 	platform_set_drvdata(pdev, rcar_pwm);
224 
225 	rcar_pwm->chip.dev = &pdev->dev;
226 	rcar_pwm->chip.ops = &rcar_pwm_ops;
227 	rcar_pwm->chip.npwm = 1;
228 
229 	pm_runtime_enable(&pdev->dev);
230 
231 	ret = pwmchip_add(&rcar_pwm->chip);
232 	if (ret < 0) {
233 		dev_err(&pdev->dev, "failed to register PWM chip: %d\n", ret);
234 		pm_runtime_disable(&pdev->dev);
235 		return ret;
236 	}
237 
238 	return 0;
239 }
240 
rcar_pwm_remove(struct platform_device * pdev)241 static void rcar_pwm_remove(struct platform_device *pdev)
242 {
243 	struct rcar_pwm_chip *rcar_pwm = platform_get_drvdata(pdev);
244 
245 	pwmchip_remove(&rcar_pwm->chip);
246 
247 	pm_runtime_disable(&pdev->dev);
248 }
249 
250 static const struct of_device_id rcar_pwm_of_table[] = {
251 	{ .compatible = "renesas,pwm-rcar", },
252 	{ },
253 };
254 MODULE_DEVICE_TABLE(of, rcar_pwm_of_table);
255 
256 static struct platform_driver rcar_pwm_driver = {
257 	.probe = rcar_pwm_probe,
258 	.remove_new = rcar_pwm_remove,
259 	.driver = {
260 		.name = "pwm-rcar",
261 		.of_match_table = rcar_pwm_of_table,
262 	}
263 };
264 module_platform_driver(rcar_pwm_driver);
265 
266 MODULE_AUTHOR("Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>");
267 MODULE_DESCRIPTION("Renesas PWM Timer Driver");
268 MODULE_LICENSE("GPL v2");
269 MODULE_ALIAS("platform:pwm-rcar");
270