xref: /openbmc/linux/arch/arm/mach-omap2/cm2xxx.c (revision 6aeb51c1)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * OMAP2xxx CM module functions
4  *
5  * Copyright (C) 2009 Nokia Corporation
6  * Copyright (C) 2008-2010, 2012 Texas Instruments, Inc.
7  * Paul Walmsley
8  * Rajendra Nayak <rnayak@ti.com>
9  */
10 
11 #include <linux/kernel.h>
12 #include <linux/types.h>
13 #include <linux/delay.h>
14 #include <linux/errno.h>
15 #include <linux/err.h>
16 #include <linux/io.h>
17 
18 #include "prm2xxx.h"
19 #include "cm.h"
20 #include "cm2xxx.h"
21 #include "cm-regbits-24xx.h"
22 #include "clockdomain.h"
23 
24 /* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */
25 #define DPLL_AUTOIDLE_DISABLE				0x0
26 #define OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP		0x3
27 
28 /* CM_AUTOIDLE_PLL.AUTO_* bit values for APLLs (OMAP2xxx only) */
29 #define OMAP2XXX_APLL_AUTOIDLE_DISABLE			0x0
30 #define OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP		0x3
31 
32 /* CM_IDLEST_PLL bit value offset for APLLs (OMAP2xxx only) */
33 #define EN_APLL_LOCKED					3
34 
35 static const u8 omap2xxx_cm_idlest_offs[] = {
36 	CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3, OMAP24XX_CM_IDLEST4
37 };
38 
39 /*
40  *
41  */
42 
_write_clktrctrl(u8 c,s16 module,u32 mask)43 static void _write_clktrctrl(u8 c, s16 module, u32 mask)
44 {
45 	u32 v;
46 
47 	v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
48 	v &= ~mask;
49 	v |= c << __ffs(mask);
50 	omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL);
51 }
52 
omap2xxx_cm_is_clkdm_in_hwsup(s16 module,u32 mask)53 static bool omap2xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
54 {
55 	u32 v;
56 
57 	v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
58 	v &= mask;
59 	v >>= __ffs(mask);
60 
61 	return (v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
62 }
63 
omap2xxx_cm_clkdm_enable_hwsup(s16 module,u32 mask)64 static void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
65 {
66 	_write_clktrctrl(OMAP24XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
67 }
68 
omap2xxx_cm_clkdm_disable_hwsup(s16 module,u32 mask)69 static void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
70 {
71 	_write_clktrctrl(OMAP24XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
72 }
73 
74 /*
75  * DPLL autoidle control
76  */
77 
_omap2xxx_set_dpll_autoidle(u8 m)78 static void _omap2xxx_set_dpll_autoidle(u8 m)
79 {
80 	u32 v;
81 
82 	v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
83 	v &= ~OMAP24XX_AUTO_DPLL_MASK;
84 	v |= m << OMAP24XX_AUTO_DPLL_SHIFT;
85 	omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
86 }
87 
omap2xxx_cm_set_dpll_disable_autoidle(void)88 void omap2xxx_cm_set_dpll_disable_autoidle(void)
89 {
90 	_omap2xxx_set_dpll_autoidle(OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP);
91 }
92 
omap2xxx_cm_set_dpll_auto_low_power_stop(void)93 void omap2xxx_cm_set_dpll_auto_low_power_stop(void)
94 {
95 	_omap2xxx_set_dpll_autoidle(DPLL_AUTOIDLE_DISABLE);
96 }
97 
98 /**
99  * omap2xxx_cm_split_idlest_reg - split CM_IDLEST reg addr into its components
100  * @idlest_reg: CM_IDLEST* virtual address
101  * @prcm_inst: pointer to an s16 to return the PRCM instance offset
102  * @idlest_reg_id: pointer to a u8 to return the CM_IDLESTx register ID
103  *
104  * XXX This function is only needed until absolute register addresses are
105  * removed from the OMAP struct clk records.
106  */
omap2xxx_cm_split_idlest_reg(struct clk_omap_reg * idlest_reg,s16 * prcm_inst,u8 * idlest_reg_id)107 static int omap2xxx_cm_split_idlest_reg(struct clk_omap_reg *idlest_reg,
108 					s16 *prcm_inst,
109 					u8 *idlest_reg_id)
110 {
111 	unsigned long offs;
112 	u8 idlest_offs;
113 	int i;
114 
115 	idlest_offs = idlest_reg->offset & 0xff;
116 	for (i = 0; i < ARRAY_SIZE(omap2xxx_cm_idlest_offs); i++) {
117 		if (idlest_offs == omap2xxx_cm_idlest_offs[i]) {
118 			*idlest_reg_id = i + 1;
119 			break;
120 		}
121 	}
122 
123 	if (i == ARRAY_SIZE(omap2xxx_cm_idlest_offs))
124 		return -EINVAL;
125 
126 	offs = idlest_reg->offset;
127 	offs &= 0xff00;
128 	*prcm_inst = offs;
129 
130 	return 0;
131 }
132 
133 /*
134  *
135  */
136 
137 /**
138  * omap2xxx_cm_wait_module_ready - wait for a module to leave idle or standby
139  * @part: PRCM partition, ignored for OMAP2
140  * @prcm_mod: PRCM module offset
141  * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
142  * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
143  *
144  * Wait for the PRCM to indicate that the module identified by
145  * (@prcm_mod, @idlest_id, @idlest_shift) is clocked.  Return 0 upon
146  * success or -EBUSY if the module doesn't enable in time.
147  */
omap2xxx_cm_wait_module_ready(u8 part,s16 prcm_mod,u16 idlest_id,u8 idlest_shift)148 static int omap2xxx_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_id,
149 					 u8 idlest_shift)
150 {
151 	int ena = 0, i = 0;
152 	u8 cm_idlest_reg;
153 	u32 mask;
154 
155 	if (!idlest_id || (idlest_id > ARRAY_SIZE(omap2xxx_cm_idlest_offs)))
156 		return -EINVAL;
157 
158 	cm_idlest_reg = omap2xxx_cm_idlest_offs[idlest_id - 1];
159 
160 	mask = 1 << idlest_shift;
161 	ena = mask;
162 
163 	omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) &
164 			    mask) == ena), MAX_MODULE_READY_TIME, i);
165 
166 	return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
167 }
168 
169 /* Clockdomain low-level functions */
170 
omap2xxx_clkdm_allow_idle(struct clockdomain * clkdm)171 static void omap2xxx_clkdm_allow_idle(struct clockdomain *clkdm)
172 {
173 	omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
174 				       clkdm->clktrctrl_mask);
175 }
176 
omap2xxx_clkdm_deny_idle(struct clockdomain * clkdm)177 static void omap2xxx_clkdm_deny_idle(struct clockdomain *clkdm)
178 {
179 	omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
180 					clkdm->clktrctrl_mask);
181 }
182 
omap2xxx_clkdm_clk_enable(struct clockdomain * clkdm)183 static int omap2xxx_clkdm_clk_enable(struct clockdomain *clkdm)
184 {
185 	bool hwsup = false;
186 
187 	if (!clkdm->clktrctrl_mask)
188 		return 0;
189 
190 	hwsup = omap2xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
191 					      clkdm->clktrctrl_mask);
192 	if (!hwsup && clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
193 		omap2xxx_clkdm_wakeup(clkdm);
194 
195 	return 0;
196 }
197 
omap2xxx_clkdm_clk_disable(struct clockdomain * clkdm)198 static int omap2xxx_clkdm_clk_disable(struct clockdomain *clkdm)
199 {
200 	bool hwsup = false;
201 
202 	if (!clkdm->clktrctrl_mask)
203 		return 0;
204 
205 	hwsup = omap2xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
206 					      clkdm->clktrctrl_mask);
207 
208 	if (!hwsup && clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
209 		omap2xxx_clkdm_sleep(clkdm);
210 
211 	return 0;
212 }
213 
214 struct clkdm_ops omap2_clkdm_operations = {
215 	.clkdm_add_wkdep	= omap2_clkdm_add_wkdep,
216 	.clkdm_del_wkdep	= omap2_clkdm_del_wkdep,
217 	.clkdm_read_wkdep	= omap2_clkdm_read_wkdep,
218 	.clkdm_clear_all_wkdeps	= omap2_clkdm_clear_all_wkdeps,
219 	.clkdm_sleep		= omap2xxx_clkdm_sleep,
220 	.clkdm_wakeup		= omap2xxx_clkdm_wakeup,
221 	.clkdm_allow_idle	= omap2xxx_clkdm_allow_idle,
222 	.clkdm_deny_idle	= omap2xxx_clkdm_deny_idle,
223 	.clkdm_clk_enable	= omap2xxx_clkdm_clk_enable,
224 	.clkdm_clk_disable	= omap2xxx_clkdm_clk_disable,
225 };
226 
omap2xxx_cm_fclks_active(void)227 int omap2xxx_cm_fclks_active(void)
228 {
229 	u32 f1, f2;
230 
231 	f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
232 	f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
233 
234 	return (f1 | f2) ? 1 : 0;
235 }
236 
omap2xxx_cm_mpu_retention_allowed(void)237 int omap2xxx_cm_mpu_retention_allowed(void)
238 {
239 	u32 l;
240 
241 	/* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
242 	l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
243 	if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
244 		 OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
245 		 OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
246 		return 0;
247 	/* Check for UART3. */
248 	l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
249 	if (l & OMAP24XX_EN_UART3_MASK)
250 		return 0;
251 
252 	return 1;
253 }
254 
omap2xxx_cm_get_core_clk_src(void)255 u32 omap2xxx_cm_get_core_clk_src(void)
256 {
257 	u32 v;
258 
259 	v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
260 	v &= OMAP24XX_CORE_CLK_SRC_MASK;
261 
262 	return v;
263 }
264 
omap2xxx_cm_get_core_pll_config(void)265 u32 omap2xxx_cm_get_core_pll_config(void)
266 {
267 	return omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
268 }
269 
omap2xxx_cm_set_mod_dividers(u32 mpu,u32 dsp,u32 gfx,u32 core,u32 mdm)270 void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core, u32 mdm)
271 {
272 	u32 tmp;
273 
274 	omap2_cm_write_mod_reg(mpu, MPU_MOD, CM_CLKSEL);
275 	omap2_cm_write_mod_reg(dsp, OMAP24XX_DSP_MOD, CM_CLKSEL);
276 	omap2_cm_write_mod_reg(gfx, GFX_MOD, CM_CLKSEL);
277 	tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) &
278 		OMAP24XX_CLKSEL_DSS2_MASK;
279 	omap2_cm_write_mod_reg(core | tmp, CORE_MOD, CM_CLKSEL1);
280 	if (mdm)
281 		omap2_cm_write_mod_reg(mdm, OMAP2430_MDM_MOD, CM_CLKSEL);
282 }
283 
284 /*
285  *
286  */
287 
288 static const struct cm_ll_data omap2xxx_cm_ll_data = {
289 	.split_idlest_reg	= &omap2xxx_cm_split_idlest_reg,
290 	.wait_module_ready	= &omap2xxx_cm_wait_module_ready,
291 };
292 
omap2xxx_cm_init(const struct omap_prcm_init_data * data)293 int __init omap2xxx_cm_init(const struct omap_prcm_init_data *data)
294 {
295 	return cm_register(&omap2xxx_cm_ll_data);
296 }
297 
omap2xxx_cm_exit(void)298 static void __exit omap2xxx_cm_exit(void)
299 {
300 	cm_unregister(&omap2xxx_cm_ll_data);
301 }
302 __exitcall(omap2xxx_cm_exit);
303