1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * KVM PMU support for Intel CPUs
4 *
5 * Copyright 2011 Red Hat, Inc. and/or its affiliates.
6 *
7 * Authors:
8 * Avi Kivity <avi@redhat.com>
9 * Gleb Natapov <gleb@redhat.com>
10 */
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12
13 #include <linux/types.h>
14 #include <linux/kvm_host.h>
15 #include <linux/perf_event.h>
16 #include <asm/perf_event.h>
17 #include "x86.h"
18 #include "cpuid.h"
19 #include "lapic.h"
20 #include "nested.h"
21 #include "pmu.h"
22
23 #define MSR_PMC_FULL_WIDTH_BIT (MSR_IA32_PMC0 - MSR_IA32_PERFCTR0)
24
25 enum intel_pmu_architectural_events {
26 /*
27 * The order of the architectural events matters as support for each
28 * event is enumerated via CPUID using the index of the event.
29 */
30 INTEL_ARCH_CPU_CYCLES,
31 INTEL_ARCH_INSTRUCTIONS_RETIRED,
32 INTEL_ARCH_REFERENCE_CYCLES,
33 INTEL_ARCH_LLC_REFERENCES,
34 INTEL_ARCH_LLC_MISSES,
35 INTEL_ARCH_BRANCHES_RETIRED,
36 INTEL_ARCH_BRANCHES_MISPREDICTED,
37
38 NR_REAL_INTEL_ARCH_EVENTS,
39
40 /*
41 * Pseudo-architectural event used to implement IA32_FIXED_CTR2, a.k.a.
42 * TSC reference cycles. The architectural reference cycles event may
43 * or may not actually use the TSC as the reference, e.g. might use the
44 * core crystal clock or the bus clock (yeah, "architectural").
45 */
46 PSEUDO_ARCH_REFERENCE_CYCLES = NR_REAL_INTEL_ARCH_EVENTS,
47 NR_INTEL_ARCH_EVENTS,
48 };
49
50 static struct {
51 u8 eventsel;
52 u8 unit_mask;
53 } const intel_arch_events[] = {
54 [INTEL_ARCH_CPU_CYCLES] = { 0x3c, 0x00 },
55 [INTEL_ARCH_INSTRUCTIONS_RETIRED] = { 0xc0, 0x00 },
56 [INTEL_ARCH_REFERENCE_CYCLES] = { 0x3c, 0x01 },
57 [INTEL_ARCH_LLC_REFERENCES] = { 0x2e, 0x4f },
58 [INTEL_ARCH_LLC_MISSES] = { 0x2e, 0x41 },
59 [INTEL_ARCH_BRANCHES_RETIRED] = { 0xc4, 0x00 },
60 [INTEL_ARCH_BRANCHES_MISPREDICTED] = { 0xc5, 0x00 },
61 [PSEUDO_ARCH_REFERENCE_CYCLES] = { 0x00, 0x03 },
62 };
63
64 /* mapping between fixed pmc index and intel_arch_events array */
65 static int fixed_pmc_events[] = {
66 [0] = INTEL_ARCH_INSTRUCTIONS_RETIRED,
67 [1] = INTEL_ARCH_CPU_CYCLES,
68 [2] = PSEUDO_ARCH_REFERENCE_CYCLES,
69 };
70
reprogram_fixed_counters(struct kvm_pmu * pmu,u64 data)71 static void reprogram_fixed_counters(struct kvm_pmu *pmu, u64 data)
72 {
73 struct kvm_pmc *pmc;
74 u64 old_fixed_ctr_ctrl = pmu->fixed_ctr_ctrl;
75 int i;
76
77 pmu->fixed_ctr_ctrl = data;
78 for (i = 0; i < pmu->nr_arch_fixed_counters; i++) {
79 u8 new_ctrl = fixed_ctrl_field(data, i);
80 u8 old_ctrl = fixed_ctrl_field(old_fixed_ctr_ctrl, i);
81
82 if (old_ctrl == new_ctrl)
83 continue;
84
85 pmc = get_fixed_pmc(pmu, MSR_CORE_PERF_FIXED_CTR0 + i);
86
87 __set_bit(INTEL_PMC_IDX_FIXED + i, pmu->pmc_in_use);
88 kvm_pmu_request_counter_reprogram(pmc);
89 }
90 }
91
intel_pmc_idx_to_pmc(struct kvm_pmu * pmu,int pmc_idx)92 static struct kvm_pmc *intel_pmc_idx_to_pmc(struct kvm_pmu *pmu, int pmc_idx)
93 {
94 if (pmc_idx < INTEL_PMC_IDX_FIXED) {
95 return get_gp_pmc(pmu, MSR_P6_EVNTSEL0 + pmc_idx,
96 MSR_P6_EVNTSEL0);
97 } else {
98 u32 idx = pmc_idx - INTEL_PMC_IDX_FIXED;
99
100 return get_fixed_pmc(pmu, idx + MSR_CORE_PERF_FIXED_CTR0);
101 }
102 }
103
intel_hw_event_available(struct kvm_pmc * pmc)104 static bool intel_hw_event_available(struct kvm_pmc *pmc)
105 {
106 struct kvm_pmu *pmu = pmc_to_pmu(pmc);
107 u8 event_select = pmc->eventsel & ARCH_PERFMON_EVENTSEL_EVENT;
108 u8 unit_mask = (pmc->eventsel & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
109 int i;
110
111 BUILD_BUG_ON(ARRAY_SIZE(intel_arch_events) != NR_INTEL_ARCH_EVENTS);
112
113 /*
114 * Disallow events reported as unavailable in guest CPUID. Note, this
115 * doesn't apply to pseudo-architectural events.
116 */
117 for (i = 0; i < NR_REAL_INTEL_ARCH_EVENTS; i++) {
118 if (intel_arch_events[i].eventsel != event_select ||
119 intel_arch_events[i].unit_mask != unit_mask)
120 continue;
121
122 return pmu->available_event_types & BIT(i);
123 }
124
125 return true;
126 }
127
intel_is_valid_rdpmc_ecx(struct kvm_vcpu * vcpu,unsigned int idx)128 static bool intel_is_valid_rdpmc_ecx(struct kvm_vcpu *vcpu, unsigned int idx)
129 {
130 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
131 bool fixed = idx & (1u << 30);
132
133 idx &= ~(3u << 30);
134
135 return fixed ? idx < pmu->nr_arch_fixed_counters
136 : idx < pmu->nr_arch_gp_counters;
137 }
138
intel_rdpmc_ecx_to_pmc(struct kvm_vcpu * vcpu,unsigned int idx,u64 * mask)139 static struct kvm_pmc *intel_rdpmc_ecx_to_pmc(struct kvm_vcpu *vcpu,
140 unsigned int idx, u64 *mask)
141 {
142 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
143 bool fixed = idx & (1u << 30);
144 struct kvm_pmc *counters;
145 unsigned int num_counters;
146
147 idx &= ~(3u << 30);
148 if (fixed) {
149 counters = pmu->fixed_counters;
150 num_counters = pmu->nr_arch_fixed_counters;
151 } else {
152 counters = pmu->gp_counters;
153 num_counters = pmu->nr_arch_gp_counters;
154 }
155 if (idx >= num_counters)
156 return NULL;
157 *mask &= pmu->counter_bitmask[fixed ? KVM_PMC_FIXED : KVM_PMC_GP];
158 return &counters[array_index_nospec(idx, num_counters)];
159 }
160
vcpu_get_perf_capabilities(struct kvm_vcpu * vcpu)161 static inline u64 vcpu_get_perf_capabilities(struct kvm_vcpu *vcpu)
162 {
163 if (!guest_cpuid_has(vcpu, X86_FEATURE_PDCM))
164 return 0;
165
166 return vcpu->arch.perf_capabilities;
167 }
168
fw_writes_is_enabled(struct kvm_vcpu * vcpu)169 static inline bool fw_writes_is_enabled(struct kvm_vcpu *vcpu)
170 {
171 return (vcpu_get_perf_capabilities(vcpu) & PMU_CAP_FW_WRITES) != 0;
172 }
173
get_fw_gp_pmc(struct kvm_pmu * pmu,u32 msr)174 static inline struct kvm_pmc *get_fw_gp_pmc(struct kvm_pmu *pmu, u32 msr)
175 {
176 if (!fw_writes_is_enabled(pmu_to_vcpu(pmu)))
177 return NULL;
178
179 return get_gp_pmc(pmu, msr, MSR_IA32_PMC0);
180 }
181
intel_pmu_is_valid_lbr_msr(struct kvm_vcpu * vcpu,u32 index)182 static bool intel_pmu_is_valid_lbr_msr(struct kvm_vcpu *vcpu, u32 index)
183 {
184 struct x86_pmu_lbr *records = vcpu_to_lbr_records(vcpu);
185 bool ret = false;
186
187 if (!intel_pmu_lbr_is_enabled(vcpu))
188 return ret;
189
190 ret = (index == MSR_LBR_SELECT) || (index == MSR_LBR_TOS) ||
191 (index >= records->from && index < records->from + records->nr) ||
192 (index >= records->to && index < records->to + records->nr);
193
194 if (!ret && records->info)
195 ret = (index >= records->info && index < records->info + records->nr);
196
197 return ret;
198 }
199
intel_is_valid_msr(struct kvm_vcpu * vcpu,u32 msr)200 static bool intel_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr)
201 {
202 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
203 u64 perf_capabilities;
204 int ret;
205
206 switch (msr) {
207 case MSR_CORE_PERF_FIXED_CTR_CTRL:
208 return kvm_pmu_has_perf_global_ctrl(pmu);
209 case MSR_IA32_PEBS_ENABLE:
210 ret = vcpu_get_perf_capabilities(vcpu) & PERF_CAP_PEBS_FORMAT;
211 break;
212 case MSR_IA32_DS_AREA:
213 ret = guest_cpuid_has(vcpu, X86_FEATURE_DS);
214 break;
215 case MSR_PEBS_DATA_CFG:
216 perf_capabilities = vcpu_get_perf_capabilities(vcpu);
217 ret = (perf_capabilities & PERF_CAP_PEBS_BASELINE) &&
218 ((perf_capabilities & PERF_CAP_PEBS_FORMAT) > 3);
219 break;
220 default:
221 ret = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0) ||
222 get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0) ||
223 get_fixed_pmc(pmu, msr) || get_fw_gp_pmc(pmu, msr) ||
224 intel_pmu_is_valid_lbr_msr(vcpu, msr);
225 break;
226 }
227
228 return ret;
229 }
230
intel_msr_idx_to_pmc(struct kvm_vcpu * vcpu,u32 msr)231 static struct kvm_pmc *intel_msr_idx_to_pmc(struct kvm_vcpu *vcpu, u32 msr)
232 {
233 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
234 struct kvm_pmc *pmc;
235
236 pmc = get_fixed_pmc(pmu, msr);
237 pmc = pmc ? pmc : get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0);
238 pmc = pmc ? pmc : get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0);
239
240 return pmc;
241 }
242
intel_pmu_release_guest_lbr_event(struct kvm_vcpu * vcpu)243 static inline void intel_pmu_release_guest_lbr_event(struct kvm_vcpu *vcpu)
244 {
245 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu);
246
247 if (lbr_desc->event) {
248 perf_event_release_kernel(lbr_desc->event);
249 lbr_desc->event = NULL;
250 vcpu_to_pmu(vcpu)->event_count--;
251 }
252 }
253
intel_pmu_create_guest_lbr_event(struct kvm_vcpu * vcpu)254 int intel_pmu_create_guest_lbr_event(struct kvm_vcpu *vcpu)
255 {
256 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu);
257 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
258 struct perf_event *event;
259
260 /*
261 * The perf_event_attr is constructed in the minimum efficient way:
262 * - set 'pinned = true' to make it task pinned so that if another
263 * cpu pinned event reclaims LBR, the event->oncpu will be set to -1;
264 * - set '.exclude_host = true' to record guest branches behavior;
265 *
266 * - set '.config = INTEL_FIXED_VLBR_EVENT' to indicates host perf
267 * schedule the event without a real HW counter but a fake one;
268 * check is_guest_lbr_event() and __intel_get_event_constraints();
269 *
270 * - set 'sample_type = PERF_SAMPLE_BRANCH_STACK' and
271 * 'branch_sample_type = PERF_SAMPLE_BRANCH_CALL_STACK |
272 * PERF_SAMPLE_BRANCH_USER' to configure it as a LBR callstack
273 * event, which helps KVM to save/restore guest LBR records
274 * during host context switches and reduces quite a lot overhead,
275 * check branch_user_callstack() and intel_pmu_lbr_sched_task();
276 */
277 struct perf_event_attr attr = {
278 .type = PERF_TYPE_RAW,
279 .size = sizeof(attr),
280 .config = INTEL_FIXED_VLBR_EVENT,
281 .sample_type = PERF_SAMPLE_BRANCH_STACK,
282 .pinned = true,
283 .exclude_host = true,
284 .branch_sample_type = PERF_SAMPLE_BRANCH_CALL_STACK |
285 PERF_SAMPLE_BRANCH_USER,
286 };
287
288 if (unlikely(lbr_desc->event)) {
289 __set_bit(INTEL_PMC_IDX_FIXED_VLBR, pmu->pmc_in_use);
290 return 0;
291 }
292
293 event = perf_event_create_kernel_counter(&attr, -1,
294 current, NULL, NULL);
295 if (IS_ERR(event)) {
296 pr_debug_ratelimited("%s: failed %ld\n",
297 __func__, PTR_ERR(event));
298 return PTR_ERR(event);
299 }
300 lbr_desc->event = event;
301 pmu->event_count++;
302 __set_bit(INTEL_PMC_IDX_FIXED_VLBR, pmu->pmc_in_use);
303 return 0;
304 }
305
306 /*
307 * It's safe to access LBR msrs from guest when they have not
308 * been passthrough since the host would help restore or reset
309 * the LBR msrs records when the guest LBR event is scheduled in.
310 */
intel_pmu_handle_lbr_msrs_access(struct kvm_vcpu * vcpu,struct msr_data * msr_info,bool read)311 static bool intel_pmu_handle_lbr_msrs_access(struct kvm_vcpu *vcpu,
312 struct msr_data *msr_info, bool read)
313 {
314 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu);
315 u32 index = msr_info->index;
316
317 if (!intel_pmu_is_valid_lbr_msr(vcpu, index))
318 return false;
319
320 if (!lbr_desc->event && intel_pmu_create_guest_lbr_event(vcpu) < 0)
321 goto dummy;
322
323 /*
324 * Disable irq to ensure the LBR feature doesn't get reclaimed by the
325 * host at the time the value is read from the msr, and this avoids the
326 * host LBR value to be leaked to the guest. If LBR has been reclaimed,
327 * return 0 on guest reads.
328 */
329 local_irq_disable();
330 if (lbr_desc->event->state == PERF_EVENT_STATE_ACTIVE) {
331 if (read)
332 rdmsrl(index, msr_info->data);
333 else
334 wrmsrl(index, msr_info->data);
335 __set_bit(INTEL_PMC_IDX_FIXED_VLBR, vcpu_to_pmu(vcpu)->pmc_in_use);
336 local_irq_enable();
337 return true;
338 }
339 clear_bit(INTEL_PMC_IDX_FIXED_VLBR, vcpu_to_pmu(vcpu)->pmc_in_use);
340 local_irq_enable();
341
342 dummy:
343 if (read)
344 msr_info->data = 0;
345 return true;
346 }
347
intel_pmu_get_msr(struct kvm_vcpu * vcpu,struct msr_data * msr_info)348 static int intel_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
349 {
350 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
351 struct kvm_pmc *pmc;
352 u32 msr = msr_info->index;
353
354 switch (msr) {
355 case MSR_CORE_PERF_FIXED_CTR_CTRL:
356 msr_info->data = pmu->fixed_ctr_ctrl;
357 break;
358 case MSR_IA32_PEBS_ENABLE:
359 msr_info->data = pmu->pebs_enable;
360 break;
361 case MSR_IA32_DS_AREA:
362 msr_info->data = pmu->ds_area;
363 break;
364 case MSR_PEBS_DATA_CFG:
365 msr_info->data = pmu->pebs_data_cfg;
366 break;
367 default:
368 if ((pmc = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)) ||
369 (pmc = get_gp_pmc(pmu, msr, MSR_IA32_PMC0))) {
370 u64 val = pmc_read_counter(pmc);
371 msr_info->data =
372 val & pmu->counter_bitmask[KVM_PMC_GP];
373 break;
374 } else if ((pmc = get_fixed_pmc(pmu, msr))) {
375 u64 val = pmc_read_counter(pmc);
376 msr_info->data =
377 val & pmu->counter_bitmask[KVM_PMC_FIXED];
378 break;
379 } else if ((pmc = get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0))) {
380 msr_info->data = pmc->eventsel;
381 break;
382 } else if (intel_pmu_handle_lbr_msrs_access(vcpu, msr_info, true)) {
383 break;
384 }
385 return 1;
386 }
387
388 return 0;
389 }
390
intel_pmu_set_msr(struct kvm_vcpu * vcpu,struct msr_data * msr_info)391 static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
392 {
393 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
394 struct kvm_pmc *pmc;
395 u32 msr = msr_info->index;
396 u64 data = msr_info->data;
397 u64 reserved_bits, diff;
398
399 switch (msr) {
400 case MSR_CORE_PERF_FIXED_CTR_CTRL:
401 if (data & pmu->fixed_ctr_ctrl_mask)
402 return 1;
403
404 if (pmu->fixed_ctr_ctrl != data)
405 reprogram_fixed_counters(pmu, data);
406 break;
407 case MSR_IA32_PEBS_ENABLE:
408 if (data & pmu->pebs_enable_mask)
409 return 1;
410
411 if (pmu->pebs_enable != data) {
412 diff = pmu->pebs_enable ^ data;
413 pmu->pebs_enable = data;
414 reprogram_counters(pmu, diff);
415 }
416 break;
417 case MSR_IA32_DS_AREA:
418 if (is_noncanonical_address(data, vcpu))
419 return 1;
420
421 pmu->ds_area = data;
422 break;
423 case MSR_PEBS_DATA_CFG:
424 if (data & pmu->pebs_data_cfg_mask)
425 return 1;
426
427 pmu->pebs_data_cfg = data;
428 break;
429 default:
430 if ((pmc = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)) ||
431 (pmc = get_gp_pmc(pmu, msr, MSR_IA32_PMC0))) {
432 if ((msr & MSR_PMC_FULL_WIDTH_BIT) &&
433 (data & ~pmu->counter_bitmask[KVM_PMC_GP]))
434 return 1;
435
436 if (!msr_info->host_initiated &&
437 !(msr & MSR_PMC_FULL_WIDTH_BIT))
438 data = (s64)(s32)data;
439 pmc_write_counter(pmc, data);
440 pmc_update_sample_period(pmc);
441 break;
442 } else if ((pmc = get_fixed_pmc(pmu, msr))) {
443 pmc_write_counter(pmc, data);
444 pmc_update_sample_period(pmc);
445 break;
446 } else if ((pmc = get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0))) {
447 reserved_bits = pmu->reserved_bits;
448 if ((pmc->idx == 2) &&
449 (pmu->raw_event_mask & HSW_IN_TX_CHECKPOINTED))
450 reserved_bits ^= HSW_IN_TX_CHECKPOINTED;
451 if (data & reserved_bits)
452 return 1;
453
454 if (data != pmc->eventsel) {
455 pmc->eventsel = data;
456 kvm_pmu_request_counter_reprogram(pmc);
457 }
458 break;
459 } else if (intel_pmu_handle_lbr_msrs_access(vcpu, msr_info, false)) {
460 break;
461 }
462 /* Not a known PMU MSR. */
463 return 1;
464 }
465
466 return 0;
467 }
468
setup_fixed_pmc_eventsel(struct kvm_pmu * pmu)469 static void setup_fixed_pmc_eventsel(struct kvm_pmu *pmu)
470 {
471 int i;
472
473 BUILD_BUG_ON(ARRAY_SIZE(fixed_pmc_events) != KVM_PMC_MAX_FIXED);
474
475 for (i = 0; i < pmu->nr_arch_fixed_counters; i++) {
476 int index = array_index_nospec(i, KVM_PMC_MAX_FIXED);
477 struct kvm_pmc *pmc = &pmu->fixed_counters[index];
478 u32 event = fixed_pmc_events[index];
479
480 pmc->eventsel = (intel_arch_events[event].unit_mask << 8) |
481 intel_arch_events[event].eventsel;
482 }
483 }
484
intel_pmu_refresh(struct kvm_vcpu * vcpu)485 static void intel_pmu_refresh(struct kvm_vcpu *vcpu)
486 {
487 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
488 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu);
489 struct kvm_cpuid_entry2 *entry;
490 union cpuid10_eax eax;
491 union cpuid10_edx edx;
492 u64 perf_capabilities;
493 u64 counter_mask;
494 int i;
495
496 memset(&lbr_desc->records, 0, sizeof(lbr_desc->records));
497
498 /*
499 * Setting passthrough of LBR MSRs is done only in the VM-Entry loop,
500 * and PMU refresh is disallowed after the vCPU has run, i.e. this code
501 * should never be reached while KVM is passing through MSRs.
502 */
503 if (KVM_BUG_ON(lbr_desc->msr_passthrough, vcpu->kvm))
504 return;
505
506 entry = kvm_find_cpuid_entry(vcpu, 0xa);
507 if (!entry)
508 return;
509
510 eax.full = entry->eax;
511 edx.full = entry->edx;
512
513 pmu->version = eax.split.version_id;
514 if (!pmu->version)
515 return;
516
517 pmu->nr_arch_gp_counters = min_t(int, eax.split.num_counters,
518 kvm_pmu_cap.num_counters_gp);
519 eax.split.bit_width = min_t(int, eax.split.bit_width,
520 kvm_pmu_cap.bit_width_gp);
521 pmu->counter_bitmask[KVM_PMC_GP] = ((u64)1 << eax.split.bit_width) - 1;
522 eax.split.mask_length = min_t(int, eax.split.mask_length,
523 kvm_pmu_cap.events_mask_len);
524 pmu->available_event_types = ~entry->ebx &
525 ((1ull << eax.split.mask_length) - 1);
526
527 if (pmu->version == 1) {
528 pmu->nr_arch_fixed_counters = 0;
529 } else {
530 pmu->nr_arch_fixed_counters = min_t(int, edx.split.num_counters_fixed,
531 kvm_pmu_cap.num_counters_fixed);
532 edx.split.bit_width_fixed = min_t(int, edx.split.bit_width_fixed,
533 kvm_pmu_cap.bit_width_fixed);
534 pmu->counter_bitmask[KVM_PMC_FIXED] =
535 ((u64)1 << edx.split.bit_width_fixed) - 1;
536 setup_fixed_pmc_eventsel(pmu);
537 }
538
539 for (i = 0; i < pmu->nr_arch_fixed_counters; i++)
540 pmu->fixed_ctr_ctrl_mask &= ~(0xbull << (i * 4));
541 counter_mask = ~(((1ull << pmu->nr_arch_gp_counters) - 1) |
542 (((1ull << pmu->nr_arch_fixed_counters) - 1) << INTEL_PMC_IDX_FIXED));
543 pmu->global_ctrl_mask = counter_mask;
544
545 /*
546 * GLOBAL_STATUS and GLOBAL_OVF_CONTROL (a.k.a. GLOBAL_STATUS_RESET)
547 * share reserved bit definitions. The kernel just happens to use
548 * OVF_CTRL for the names.
549 */
550 pmu->global_status_mask = pmu->global_ctrl_mask
551 & ~(MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF |
552 MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD);
553 if (vmx_pt_mode_is_host_guest())
554 pmu->global_status_mask &=
555 ~MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI;
556
557 entry = kvm_find_cpuid_entry_index(vcpu, 7, 0);
558 if (entry &&
559 (boot_cpu_has(X86_FEATURE_HLE) || boot_cpu_has(X86_FEATURE_RTM)) &&
560 (entry->ebx & (X86_FEATURE_HLE|X86_FEATURE_RTM))) {
561 pmu->reserved_bits ^= HSW_IN_TX;
562 pmu->raw_event_mask |= (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
563 }
564
565 bitmap_set(pmu->all_valid_pmc_idx,
566 0, pmu->nr_arch_gp_counters);
567 bitmap_set(pmu->all_valid_pmc_idx,
568 INTEL_PMC_MAX_GENERIC, pmu->nr_arch_fixed_counters);
569
570 perf_capabilities = vcpu_get_perf_capabilities(vcpu);
571 if (cpuid_model_is_consistent(vcpu) &&
572 (perf_capabilities & PMU_CAP_LBR_FMT))
573 x86_perf_get_lbr(&lbr_desc->records);
574 else
575 lbr_desc->records.nr = 0;
576
577 if (lbr_desc->records.nr)
578 bitmap_set(pmu->all_valid_pmc_idx, INTEL_PMC_IDX_FIXED_VLBR, 1);
579
580 if (perf_capabilities & PERF_CAP_PEBS_FORMAT) {
581 if (perf_capabilities & PERF_CAP_PEBS_BASELINE) {
582 pmu->pebs_enable_mask = counter_mask;
583 pmu->reserved_bits &= ~ICL_EVENTSEL_ADAPTIVE;
584 for (i = 0; i < pmu->nr_arch_fixed_counters; i++) {
585 pmu->fixed_ctr_ctrl_mask &=
586 ~(1ULL << (INTEL_PMC_IDX_FIXED + i * 4));
587 }
588 pmu->pebs_data_cfg_mask = ~0xff00000full;
589 } else {
590 pmu->pebs_enable_mask =
591 ~((1ull << pmu->nr_arch_gp_counters) - 1);
592 }
593 }
594 }
595
intel_pmu_init(struct kvm_vcpu * vcpu)596 static void intel_pmu_init(struct kvm_vcpu *vcpu)
597 {
598 int i;
599 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
600 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu);
601
602 for (i = 0; i < KVM_INTEL_PMC_MAX_GENERIC; i++) {
603 pmu->gp_counters[i].type = KVM_PMC_GP;
604 pmu->gp_counters[i].vcpu = vcpu;
605 pmu->gp_counters[i].idx = i;
606 pmu->gp_counters[i].current_config = 0;
607 }
608
609 for (i = 0; i < KVM_PMC_MAX_FIXED; i++) {
610 pmu->fixed_counters[i].type = KVM_PMC_FIXED;
611 pmu->fixed_counters[i].vcpu = vcpu;
612 pmu->fixed_counters[i].idx = i + INTEL_PMC_IDX_FIXED;
613 pmu->fixed_counters[i].current_config = 0;
614 }
615
616 lbr_desc->records.nr = 0;
617 lbr_desc->event = NULL;
618 lbr_desc->msr_passthrough = false;
619 }
620
intel_pmu_reset(struct kvm_vcpu * vcpu)621 static void intel_pmu_reset(struct kvm_vcpu *vcpu)
622 {
623 intel_pmu_release_guest_lbr_event(vcpu);
624 }
625
626 /*
627 * Emulate LBR_On_PMI behavior for 1 < pmu.version < 4.
628 *
629 * If Freeze_LBR_On_PMI = 1, the LBR is frozen on PMI and
630 * the KVM emulates to clear the LBR bit (bit 0) in IA32_DEBUGCTL.
631 *
632 * Guest needs to re-enable LBR to resume branches recording.
633 */
intel_pmu_legacy_freezing_lbrs_on_pmi(struct kvm_vcpu * vcpu)634 static void intel_pmu_legacy_freezing_lbrs_on_pmi(struct kvm_vcpu *vcpu)
635 {
636 u64 data = vmcs_read64(GUEST_IA32_DEBUGCTL);
637
638 if (data & DEBUGCTLMSR_FREEZE_LBRS_ON_PMI) {
639 data &= ~DEBUGCTLMSR_LBR;
640 vmcs_write64(GUEST_IA32_DEBUGCTL, data);
641 }
642 }
643
intel_pmu_deliver_pmi(struct kvm_vcpu * vcpu)644 static void intel_pmu_deliver_pmi(struct kvm_vcpu *vcpu)
645 {
646 u8 version = vcpu_to_pmu(vcpu)->version;
647
648 if (!intel_pmu_lbr_is_enabled(vcpu))
649 return;
650
651 if (version > 1 && version < 4)
652 intel_pmu_legacy_freezing_lbrs_on_pmi(vcpu);
653 }
654
vmx_update_intercept_for_lbr_msrs(struct kvm_vcpu * vcpu,bool set)655 static void vmx_update_intercept_for_lbr_msrs(struct kvm_vcpu *vcpu, bool set)
656 {
657 struct x86_pmu_lbr *lbr = vcpu_to_lbr_records(vcpu);
658 int i;
659
660 for (i = 0; i < lbr->nr; i++) {
661 vmx_set_intercept_for_msr(vcpu, lbr->from + i, MSR_TYPE_RW, set);
662 vmx_set_intercept_for_msr(vcpu, lbr->to + i, MSR_TYPE_RW, set);
663 if (lbr->info)
664 vmx_set_intercept_for_msr(vcpu, lbr->info + i, MSR_TYPE_RW, set);
665 }
666
667 vmx_set_intercept_for_msr(vcpu, MSR_LBR_SELECT, MSR_TYPE_RW, set);
668 vmx_set_intercept_for_msr(vcpu, MSR_LBR_TOS, MSR_TYPE_RW, set);
669 }
670
vmx_disable_lbr_msrs_passthrough(struct kvm_vcpu * vcpu)671 static inline void vmx_disable_lbr_msrs_passthrough(struct kvm_vcpu *vcpu)
672 {
673 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu);
674
675 if (!lbr_desc->msr_passthrough)
676 return;
677
678 vmx_update_intercept_for_lbr_msrs(vcpu, true);
679 lbr_desc->msr_passthrough = false;
680 }
681
vmx_enable_lbr_msrs_passthrough(struct kvm_vcpu * vcpu)682 static inline void vmx_enable_lbr_msrs_passthrough(struct kvm_vcpu *vcpu)
683 {
684 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu);
685
686 if (lbr_desc->msr_passthrough)
687 return;
688
689 vmx_update_intercept_for_lbr_msrs(vcpu, false);
690 lbr_desc->msr_passthrough = true;
691 }
692
693 /*
694 * Higher priority host perf events (e.g. cpu pinned) could reclaim the
695 * pmu resources (e.g. LBR) that were assigned to the guest. This is
696 * usually done via ipi calls (more details in perf_install_in_context).
697 *
698 * Before entering the non-root mode (with irq disabled here), double
699 * confirm that the pmu features enabled to the guest are not reclaimed
700 * by higher priority host events. Otherwise, disallow vcpu's access to
701 * the reclaimed features.
702 */
vmx_passthrough_lbr_msrs(struct kvm_vcpu * vcpu)703 void vmx_passthrough_lbr_msrs(struct kvm_vcpu *vcpu)
704 {
705 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
706 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu);
707
708 if (!lbr_desc->event) {
709 vmx_disable_lbr_msrs_passthrough(vcpu);
710 if (vmcs_read64(GUEST_IA32_DEBUGCTL) & DEBUGCTLMSR_LBR)
711 goto warn;
712 if (test_bit(INTEL_PMC_IDX_FIXED_VLBR, pmu->pmc_in_use))
713 goto warn;
714 return;
715 }
716
717 if (lbr_desc->event->state < PERF_EVENT_STATE_ACTIVE) {
718 vmx_disable_lbr_msrs_passthrough(vcpu);
719 __clear_bit(INTEL_PMC_IDX_FIXED_VLBR, pmu->pmc_in_use);
720 goto warn;
721 } else
722 vmx_enable_lbr_msrs_passthrough(vcpu);
723
724 return;
725
726 warn:
727 pr_warn_ratelimited("vcpu-%d: fail to passthrough LBR.\n", vcpu->vcpu_id);
728 }
729
intel_pmu_cleanup(struct kvm_vcpu * vcpu)730 static void intel_pmu_cleanup(struct kvm_vcpu *vcpu)
731 {
732 if (!(vmcs_read64(GUEST_IA32_DEBUGCTL) & DEBUGCTLMSR_LBR))
733 intel_pmu_release_guest_lbr_event(vcpu);
734 }
735
intel_pmu_cross_mapped_check(struct kvm_pmu * pmu)736 void intel_pmu_cross_mapped_check(struct kvm_pmu *pmu)
737 {
738 struct kvm_pmc *pmc = NULL;
739 int bit, hw_idx;
740
741 for_each_set_bit(bit, (unsigned long *)&pmu->global_ctrl,
742 X86_PMC_IDX_MAX) {
743 pmc = intel_pmc_idx_to_pmc(pmu, bit);
744
745 if (!pmc || !pmc_speculative_in_use(pmc) ||
746 !pmc_is_globally_enabled(pmc) || !pmc->perf_event)
747 continue;
748
749 /*
750 * A negative index indicates the event isn't mapped to a
751 * physical counter in the host, e.g. due to contention.
752 */
753 hw_idx = pmc->perf_event->hw.idx;
754 if (hw_idx != pmc->idx && hw_idx > -1)
755 pmu->host_cross_mapped_mask |= BIT_ULL(hw_idx);
756 }
757 }
758
759 struct kvm_pmu_ops intel_pmu_ops __initdata = {
760 .hw_event_available = intel_hw_event_available,
761 .pmc_idx_to_pmc = intel_pmc_idx_to_pmc,
762 .rdpmc_ecx_to_pmc = intel_rdpmc_ecx_to_pmc,
763 .msr_idx_to_pmc = intel_msr_idx_to_pmc,
764 .is_valid_rdpmc_ecx = intel_is_valid_rdpmc_ecx,
765 .is_valid_msr = intel_is_valid_msr,
766 .get_msr = intel_pmu_get_msr,
767 .set_msr = intel_pmu_set_msr,
768 .refresh = intel_pmu_refresh,
769 .init = intel_pmu_init,
770 .reset = intel_pmu_reset,
771 .deliver_pmi = intel_pmu_deliver_pmi,
772 .cleanup = intel_pmu_cleanup,
773 .EVENTSEL_EVENT = ARCH_PERFMON_EVENTSEL_EVENT,
774 .MAX_NR_GP_COUNTERS = KVM_INTEL_PMC_MAX_GENERIC,
775 .MIN_NR_GP_COUNTERS = 1,
776 };
777