1 /* 2 * Intel 82975X Memory Controller kernel module 3 * (C) 2007 aCarLab (India) Pvt. Ltd. (http://acarlab.com) 4 * (C) 2007 jetzbroadband (http://jetzbroadband.com) 5 * This file may be distributed under the terms of the 6 * GNU General Public License. 7 * 8 * Written by Arvind R. 9 * Copied from i82875p_edac.c source: 10 */ 11 12 #include <linux/module.h> 13 #include <linux/init.h> 14 #include <linux/pci.h> 15 #include <linux/pci_ids.h> 16 #include <linux/edac.h> 17 #include "edac_module.h" 18 19 #define EDAC_MOD_STR "i82975x_edac" 20 21 #define i82975x_printk(level, fmt, arg...) \ 22 edac_printk(level, "i82975x", fmt, ##arg) 23 24 #define i82975x_mc_printk(mci, level, fmt, arg...) \ 25 edac_mc_chipset_printk(mci, level, "i82975x", fmt, ##arg) 26 27 #ifndef PCI_DEVICE_ID_INTEL_82975_0 28 #define PCI_DEVICE_ID_INTEL_82975_0 0x277c 29 #endif /* PCI_DEVICE_ID_INTEL_82975_0 */ 30 31 #define I82975X_NR_DIMMS 8 32 #define I82975X_NR_CSROWS(nr_chans) (I82975X_NR_DIMMS / (nr_chans)) 33 34 /* Intel 82975X register addresses - device 0 function 0 - DRAM Controller */ 35 #define I82975X_EAP 0x58 /* Dram Error Address Pointer (32b) 36 * 37 * 31:7 128 byte cache-line address 38 * 6:1 reserved 39 * 0 0: CH0; 1: CH1 40 */ 41 42 #define I82975X_DERRSYN 0x5c /* Dram Error SYNdrome (8b) 43 * 44 * 7:0 DRAM ECC Syndrome 45 */ 46 47 #define I82975X_DES 0x5d /* Dram ERRor DeSTination (8b) 48 * 0h: Processor Memory Reads 49 * 1h:7h reserved 50 * More - See Page 65 of Intel DocSheet. 51 */ 52 53 #define I82975X_ERRSTS 0xc8 /* Error Status Register (16b) 54 * 55 * 15:12 reserved 56 * 11 Thermal Sensor Event 57 * 10 reserved 58 * 9 non-DRAM lock error (ndlock) 59 * 8 Refresh Timeout 60 * 7:2 reserved 61 * 1 ECC UE (multibit DRAM error) 62 * 0 ECC CE (singlebit DRAM error) 63 */ 64 65 /* Error Reporting is supported by 3 mechanisms: 66 1. DMI SERR generation ( ERRCMD ) 67 2. SMI DMI generation ( SMICMD ) 68 3. SCI DMI generation ( SCICMD ) 69 NOTE: Only ONE of the three must be enabled 70 */ 71 #define I82975X_ERRCMD 0xca /* Error Command (16b) 72 * 73 * 15:12 reserved 74 * 11 Thermal Sensor Event 75 * 10 reserved 76 * 9 non-DRAM lock error (ndlock) 77 * 8 Refresh Timeout 78 * 7:2 reserved 79 * 1 ECC UE (multibit DRAM error) 80 * 0 ECC CE (singlebit DRAM error) 81 */ 82 83 #define I82975X_SMICMD 0xcc /* Error Command (16b) 84 * 85 * 15:2 reserved 86 * 1 ECC UE (multibit DRAM error) 87 * 0 ECC CE (singlebit DRAM error) 88 */ 89 90 #define I82975X_SCICMD 0xce /* Error Command (16b) 91 * 92 * 15:2 reserved 93 * 1 ECC UE (multibit DRAM error) 94 * 0 ECC CE (singlebit DRAM error) 95 */ 96 97 #define I82975X_XEAP 0xfc /* Extended Dram Error Address Pointer (8b) 98 * 99 * 7:1 reserved 100 * 0 Bit32 of the Dram Error Address 101 */ 102 103 #define I82975X_MCHBAR 0x44 /* 104 * 105 * 31:14 Base Addr of 16K memory-mapped 106 * configuration space 107 * 13:1 reserved 108 * 0 mem-mapped config space enable 109 */ 110 111 /* NOTE: Following addresses have to indexed using MCHBAR offset (44h, 32b) */ 112 /* Intel 82975x memory mapped register space */ 113 114 #define I82975X_DRB_SHIFT 25 /* fixed 32MiB grain */ 115 116 #define I82975X_DRB 0x100 /* DRAM Row Boundary (8b x 8) 117 * 118 * 7 set to 1 in highest DRB of 119 * channel if 4GB in ch. 120 * 6:2 upper boundary of rank in 121 * 32MB grains 122 * 1:0 set to 0 123 */ 124 #define I82975X_DRB_CH0R0 0x100 125 #define I82975X_DRB_CH0R1 0x101 126 #define I82975X_DRB_CH0R2 0x102 127 #define I82975X_DRB_CH0R3 0x103 128 #define I82975X_DRB_CH1R0 0x180 129 #define I82975X_DRB_CH1R1 0x181 130 #define I82975X_DRB_CH1R2 0x182 131 #define I82975X_DRB_CH1R3 0x183 132 133 134 #define I82975X_DRA 0x108 /* DRAM Row Attribute (4b x 8) 135 * defines the PAGE SIZE to be used 136 * for the rank 137 * 7 reserved 138 * 6:4 row attr of odd rank, i.e. 1 139 * 3 reserved 140 * 2:0 row attr of even rank, i.e. 0 141 * 142 * 000 = unpopulated 143 * 001 = reserved 144 * 010 = 4KiB 145 * 011 = 8KiB 146 * 100 = 16KiB 147 * others = reserved 148 */ 149 #define I82975X_DRA_CH0R01 0x108 150 #define I82975X_DRA_CH0R23 0x109 151 #define I82975X_DRA_CH1R01 0x188 152 #define I82975X_DRA_CH1R23 0x189 153 154 155 #define I82975X_BNKARC 0x10e /* Type of device in each rank - Bank Arch (16b) 156 * 157 * 15:8 reserved 158 * 7:6 Rank 3 architecture 159 * 5:4 Rank 2 architecture 160 * 3:2 Rank 1 architecture 161 * 1:0 Rank 0 architecture 162 * 163 * 00 => 4 banks 164 * 01 => 8 banks 165 */ 166 #define I82975X_C0BNKARC 0x10e 167 #define I82975X_C1BNKARC 0x18e 168 169 170 171 #define I82975X_DRC 0x120 /* DRAM Controller Mode0 (32b) 172 * 173 * 31:30 reserved 174 * 29 init complete 175 * 28:11 reserved, according to Intel 176 * 22:21 number of channels 177 * 00=1 01=2 in 82875 178 * seems to be ECC mode 179 * bits in 82975 in Asus 180 * P5W 181 * 19:18 Data Integ Mode 182 * 00=none 01=ECC in 82875 183 * 10:8 refresh mode 184 * 7 reserved 185 * 6:4 mode select 186 * 3:2 reserved 187 * 1:0 DRAM type 10=Second Revision 188 * DDR2 SDRAM 189 * 00, 01, 11 reserved 190 */ 191 #define I82975X_DRC_CH0M0 0x120 192 #define I82975X_DRC_CH1M0 0x1A0 193 194 195 #define I82975X_DRC_M1 0x124 /* DRAM Controller Mode1 (32b) 196 * 31 0=Standard Address Map 197 * 1=Enhanced Address Map 198 * 30:0 reserved 199 */ 200 201 #define I82975X_DRC_CH0M1 0x124 202 #define I82975X_DRC_CH1M1 0x1A4 203 204 enum i82975x_chips { 205 I82975X = 0, 206 }; 207 208 struct i82975x_pvt { 209 void __iomem *mch_window; 210 }; 211 212 struct i82975x_dev_info { 213 const char *ctl_name; 214 }; 215 216 struct i82975x_error_info { 217 u16 errsts; 218 u32 eap; 219 u8 des; 220 u8 derrsyn; 221 u16 errsts2; 222 u8 chan; /* the channel is bit 0 of EAP */ 223 u8 xeap; /* extended eap bit */ 224 }; 225 226 static const struct i82975x_dev_info i82975x_devs[] = { 227 [I82975X] = { 228 .ctl_name = "i82975x" 229 }, 230 }; 231 232 static struct pci_dev *mci_pdev; /* init dev: in case that AGP code has 233 * already registered driver 234 */ 235 236 static int i82975x_registered = 1; 237 i82975x_get_error_info(struct mem_ctl_info * mci,struct i82975x_error_info * info)238 static void i82975x_get_error_info(struct mem_ctl_info *mci, 239 struct i82975x_error_info *info) 240 { 241 struct pci_dev *pdev; 242 243 pdev = to_pci_dev(mci->pdev); 244 245 /* 246 * This is a mess because there is no atomic way to read all the 247 * registers at once and the registers can transition from CE being 248 * overwritten by UE. 249 */ 250 pci_read_config_word(pdev, I82975X_ERRSTS, &info->errsts); 251 pci_read_config_dword(pdev, I82975X_EAP, &info->eap); 252 pci_read_config_byte(pdev, I82975X_XEAP, &info->xeap); 253 pci_read_config_byte(pdev, I82975X_DES, &info->des); 254 pci_read_config_byte(pdev, I82975X_DERRSYN, &info->derrsyn); 255 pci_read_config_word(pdev, I82975X_ERRSTS, &info->errsts2); 256 257 pci_write_bits16(pdev, I82975X_ERRSTS, 0x0003, 0x0003); 258 259 /* 260 * If the error is the same then we can for both reads then 261 * the first set of reads is valid. If there is a change then 262 * there is a CE no info and the second set of reads is valid 263 * and should be UE info. 264 */ 265 if (!(info->errsts2 & 0x0003)) 266 return; 267 268 if ((info->errsts ^ info->errsts2) & 0x0003) { 269 pci_read_config_dword(pdev, I82975X_EAP, &info->eap); 270 pci_read_config_byte(pdev, I82975X_XEAP, &info->xeap); 271 pci_read_config_byte(pdev, I82975X_DES, &info->des); 272 pci_read_config_byte(pdev, I82975X_DERRSYN, 273 &info->derrsyn); 274 } 275 } 276 i82975x_process_error_info(struct mem_ctl_info * mci,struct i82975x_error_info * info,int handle_errors)277 static int i82975x_process_error_info(struct mem_ctl_info *mci, 278 struct i82975x_error_info *info, int handle_errors) 279 { 280 int row, chan; 281 unsigned long offst, page; 282 283 if (!(info->errsts2 & 0x0003)) 284 return 0; 285 286 if (!handle_errors) 287 return 1; 288 289 if ((info->errsts ^ info->errsts2) & 0x0003) { 290 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0, 291 -1, -1, -1, "UE overwrote CE", ""); 292 info->errsts = info->errsts2; 293 } 294 295 page = (unsigned long) info->eap; 296 page >>= 1; 297 if (info->xeap & 1) 298 page |= 0x80000000; 299 page >>= (PAGE_SHIFT - 1); 300 row = edac_mc_find_csrow_by_page(mci, page); 301 302 if (row == -1) { 303 i82975x_mc_printk(mci, KERN_ERR, "error processing EAP:\n" 304 "\tXEAP=%u\n" 305 "\t EAP=0x%08x\n" 306 "\tPAGE=0x%08x\n", 307 (info->xeap & 1) ? 1 : 0, info->eap, (unsigned int) page); 308 return 0; 309 } 310 chan = (mci->csrows[row]->nr_channels == 1) ? 0 : info->eap & 1; 311 offst = info->eap 312 & ((1 << PAGE_SHIFT) - 313 (1 << mci->csrows[row]->channels[chan]->dimm->grain)); 314 315 if (info->errsts & 0x0002) 316 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 317 page, offst, 0, 318 row, -1, -1, 319 "i82975x UE", ""); 320 else 321 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 322 page, offst, info->derrsyn, 323 row, chan ? chan : 0, -1, 324 "i82975x CE", ""); 325 326 return 1; 327 } 328 i82975x_check(struct mem_ctl_info * mci)329 static void i82975x_check(struct mem_ctl_info *mci) 330 { 331 struct i82975x_error_info info; 332 333 i82975x_get_error_info(mci, &info); 334 i82975x_process_error_info(mci, &info, 1); 335 } 336 337 /* Return 1 if dual channel mode is active. Else return 0. */ dual_channel_active(void __iomem * mch_window)338 static int dual_channel_active(void __iomem *mch_window) 339 { 340 /* 341 * We treat interleaved-symmetric configuration as dual-channel - EAP's 342 * bit-0 giving the channel of the error location. 343 * 344 * All other configurations are treated as single channel - the EAP's 345 * bit-0 will resolve ok in symmetric area of mixed 346 * (symmetric/asymmetric) configurations 347 */ 348 u8 drb[4][2]; 349 int row; 350 int dualch; 351 352 for (dualch = 1, row = 0; dualch && (row < 4); row++) { 353 drb[row][0] = readb(mch_window + I82975X_DRB + row); 354 drb[row][1] = readb(mch_window + I82975X_DRB + row + 0x80); 355 dualch = dualch && (drb[row][0] == drb[row][1]); 356 } 357 return dualch; 358 } 359 i82975x_init_csrows(struct mem_ctl_info * mci,struct pci_dev * pdev,void __iomem * mch_window)360 static void i82975x_init_csrows(struct mem_ctl_info *mci, 361 struct pci_dev *pdev, void __iomem *mch_window) 362 { 363 struct csrow_info *csrow; 364 unsigned long last_cumul_size; 365 u8 value; 366 u32 cumul_size, nr_pages; 367 int index, chan; 368 struct dimm_info *dimm; 369 370 last_cumul_size = 0; 371 372 /* 373 * 82875 comment: 374 * The dram row boundary (DRB) reg values are boundary address 375 * for each DRAM row with a granularity of 32 or 64MB (single/dual 376 * channel operation). DRB regs are cumulative; therefore DRB7 will 377 * contain the total memory contained in all rows. 378 * 379 */ 380 381 for (index = 0; index < mci->nr_csrows; index++) { 382 csrow = mci->csrows[index]; 383 384 value = readb(mch_window + I82975X_DRB + index + 385 ((index >= 4) ? 0x80 : 0)); 386 cumul_size = value; 387 cumul_size <<= (I82975X_DRB_SHIFT - PAGE_SHIFT); 388 /* 389 * Adjust cumul_size w.r.t number of channels 390 * 391 */ 392 if (csrow->nr_channels > 1) 393 cumul_size <<= 1; 394 edac_dbg(3, "(%d) cumul_size 0x%x\n", index, cumul_size); 395 396 nr_pages = cumul_size - last_cumul_size; 397 if (!nr_pages) 398 continue; 399 400 /* 401 * Initialise dram labels 402 * index values: 403 * [0-7] for single-channel; i.e. csrow->nr_channels = 1 404 * [0-3] for dual-channel; i.e. csrow->nr_channels = 2 405 */ 406 for (chan = 0; chan < csrow->nr_channels; chan++) { 407 dimm = mci->csrows[index]->channels[chan]->dimm; 408 409 dimm->nr_pages = nr_pages / csrow->nr_channels; 410 411 snprintf(csrow->channels[chan]->dimm->label, EDAC_MC_LABEL_LEN, "DIMM %c%d", 412 (chan == 0) ? 'A' : 'B', 413 index); 414 dimm->grain = 1 << 7; /* 128Byte cache-line resolution */ 415 416 /* ECC is possible on i92975x ONLY with DEV_X8. */ 417 dimm->dtype = DEV_X8; 418 419 dimm->mtype = MEM_DDR2; /* I82975x supports only DDR2 */ 420 dimm->edac_mode = EDAC_SECDED; /* only supported */ 421 } 422 423 csrow->first_page = last_cumul_size; 424 csrow->last_page = cumul_size - 1; 425 last_cumul_size = cumul_size; 426 } 427 } 428 429 /* #define i82975x_DEBUG_IOMEM */ 430 431 #ifdef i82975x_DEBUG_IOMEM i82975x_print_dram_timings(void __iomem * mch_window)432 static void i82975x_print_dram_timings(void __iomem *mch_window) 433 { 434 /* 435 * The register meanings are from Intel specs; 436 * (shows 13-5-5-5 for 800-DDR2) 437 * Asus P5W Bios reports 15-5-4-4 438 * What's your religion? 439 */ 440 static const int caslats[4] = { 5, 4, 3, 6 }; 441 u32 dtreg[2]; 442 443 dtreg[0] = readl(mch_window + 0x114); 444 dtreg[1] = readl(mch_window + 0x194); 445 i82975x_printk(KERN_INFO, "DRAM Timings : Ch0 Ch1\n" 446 " RAS Active Min = %d %d\n" 447 " CAS latency = %d %d\n" 448 " RAS to CAS = %d %d\n" 449 " RAS precharge = %d %d\n", 450 (dtreg[0] >> 19 ) & 0x0f, 451 (dtreg[1] >> 19) & 0x0f, 452 caslats[(dtreg[0] >> 8) & 0x03], 453 caslats[(dtreg[1] >> 8) & 0x03], 454 ((dtreg[0] >> 4) & 0x07) + 2, 455 ((dtreg[1] >> 4) & 0x07) + 2, 456 (dtreg[0] & 0x07) + 2, 457 (dtreg[1] & 0x07) + 2 458 ); 459 460 } 461 #endif 462 i82975x_probe1(struct pci_dev * pdev,int dev_idx)463 static int i82975x_probe1(struct pci_dev *pdev, int dev_idx) 464 { 465 int rc = -ENODEV; 466 struct mem_ctl_info *mci; 467 struct edac_mc_layer layers[2]; 468 struct i82975x_pvt *pvt; 469 void __iomem *mch_window; 470 u32 mchbar; 471 u32 drc[2]; 472 struct i82975x_error_info discard; 473 int chans; 474 #ifdef i82975x_DEBUG_IOMEM 475 u8 c0drb[4]; 476 u8 c1drb[4]; 477 #endif 478 479 edac_dbg(0, "\n"); 480 481 pci_read_config_dword(pdev, I82975X_MCHBAR, &mchbar); 482 if (!(mchbar & 1)) { 483 edac_dbg(3, "failed, MCHBAR disabled!\n"); 484 goto fail0; 485 } 486 mchbar &= 0xffffc000; /* bits 31:14 used for 16K window */ 487 mch_window = ioremap(mchbar, 0x1000); 488 if (!mch_window) { 489 edac_dbg(3, "error ioremapping MCHBAR!\n"); 490 goto fail0; 491 } 492 493 #ifdef i82975x_DEBUG_IOMEM 494 i82975x_printk(KERN_INFO, "MCHBAR real = %0x, remapped = %p\n", 495 mchbar, mch_window); 496 497 c0drb[0] = readb(mch_window + I82975X_DRB_CH0R0); 498 c0drb[1] = readb(mch_window + I82975X_DRB_CH0R1); 499 c0drb[2] = readb(mch_window + I82975X_DRB_CH0R2); 500 c0drb[3] = readb(mch_window + I82975X_DRB_CH0R3); 501 c1drb[0] = readb(mch_window + I82975X_DRB_CH1R0); 502 c1drb[1] = readb(mch_window + I82975X_DRB_CH1R1); 503 c1drb[2] = readb(mch_window + I82975X_DRB_CH1R2); 504 c1drb[3] = readb(mch_window + I82975X_DRB_CH1R3); 505 i82975x_printk(KERN_INFO, "DRBCH0R0 = 0x%02x\n", c0drb[0]); 506 i82975x_printk(KERN_INFO, "DRBCH0R1 = 0x%02x\n", c0drb[1]); 507 i82975x_printk(KERN_INFO, "DRBCH0R2 = 0x%02x\n", c0drb[2]); 508 i82975x_printk(KERN_INFO, "DRBCH0R3 = 0x%02x\n", c0drb[3]); 509 i82975x_printk(KERN_INFO, "DRBCH1R0 = 0x%02x\n", c1drb[0]); 510 i82975x_printk(KERN_INFO, "DRBCH1R1 = 0x%02x\n", c1drb[1]); 511 i82975x_printk(KERN_INFO, "DRBCH1R2 = 0x%02x\n", c1drb[2]); 512 i82975x_printk(KERN_INFO, "DRBCH1R3 = 0x%02x\n", c1drb[3]); 513 #endif 514 515 drc[0] = readl(mch_window + I82975X_DRC_CH0M0); 516 drc[1] = readl(mch_window + I82975X_DRC_CH1M0); 517 #ifdef i82975x_DEBUG_IOMEM 518 i82975x_printk(KERN_INFO, "DRC_CH0 = %0x, %s\n", drc[0], 519 ((drc[0] >> 21) & 3) == 1 ? 520 "ECC enabled" : "ECC disabled"); 521 i82975x_printk(KERN_INFO, "DRC_CH1 = %0x, %s\n", drc[1], 522 ((drc[1] >> 21) & 3) == 1 ? 523 "ECC enabled" : "ECC disabled"); 524 525 i82975x_printk(KERN_INFO, "C0 BNKARC = %0x\n", 526 readw(mch_window + I82975X_C0BNKARC)); 527 i82975x_printk(KERN_INFO, "C1 BNKARC = %0x\n", 528 readw(mch_window + I82975X_C1BNKARC)); 529 i82975x_print_dram_timings(mch_window); 530 goto fail1; 531 #endif 532 if (!(((drc[0] >> 21) & 3) == 1 || ((drc[1] >> 21) & 3) == 1)) { 533 i82975x_printk(KERN_INFO, "ECC disabled on both channels.\n"); 534 goto fail1; 535 } 536 537 chans = dual_channel_active(mch_window) + 1; 538 539 /* assuming only one controller, index thus is 0 */ 540 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; 541 layers[0].size = I82975X_NR_DIMMS; 542 layers[0].is_virt_csrow = true; 543 layers[1].type = EDAC_MC_LAYER_CHANNEL; 544 layers[1].size = I82975X_NR_CSROWS(chans); 545 layers[1].is_virt_csrow = false; 546 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt)); 547 if (!mci) { 548 rc = -ENOMEM; 549 goto fail1; 550 } 551 552 edac_dbg(3, "init mci\n"); 553 mci->pdev = &pdev->dev; 554 mci->mtype_cap = MEM_FLAG_DDR2; 555 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; 556 mci->edac_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; 557 mci->mod_name = EDAC_MOD_STR; 558 mci->ctl_name = i82975x_devs[dev_idx].ctl_name; 559 mci->dev_name = pci_name(pdev); 560 mci->edac_check = i82975x_check; 561 mci->ctl_page_to_phys = NULL; 562 edac_dbg(3, "init pvt\n"); 563 pvt = (struct i82975x_pvt *) mci->pvt_info; 564 pvt->mch_window = mch_window; 565 i82975x_init_csrows(mci, pdev, mch_window); 566 mci->scrub_mode = SCRUB_HW_SRC; 567 i82975x_get_error_info(mci, &discard); /* clear counters */ 568 569 /* finalize this instance of memory controller with edac core */ 570 if (edac_mc_add_mc(mci)) { 571 edac_dbg(3, "failed edac_mc_add_mc()\n"); 572 goto fail2; 573 } 574 575 /* get this far and it's successful */ 576 edac_dbg(3, "success\n"); 577 return 0; 578 579 fail2: 580 edac_mc_free(mci); 581 582 fail1: 583 iounmap(mch_window); 584 fail0: 585 return rc; 586 } 587 588 /* returns count (>= 0), or negative on error */ i82975x_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)589 static int i82975x_init_one(struct pci_dev *pdev, 590 const struct pci_device_id *ent) 591 { 592 int rc; 593 594 edac_dbg(0, "\n"); 595 596 if (pci_enable_device(pdev) < 0) 597 return -EIO; 598 599 rc = i82975x_probe1(pdev, ent->driver_data); 600 601 if (mci_pdev == NULL) 602 mci_pdev = pci_dev_get(pdev); 603 604 return rc; 605 } 606 i82975x_remove_one(struct pci_dev * pdev)607 static void i82975x_remove_one(struct pci_dev *pdev) 608 { 609 struct mem_ctl_info *mci; 610 struct i82975x_pvt *pvt; 611 612 edac_dbg(0, "\n"); 613 614 mci = edac_mc_del_mc(&pdev->dev); 615 if (mci == NULL) 616 return; 617 618 pvt = mci->pvt_info; 619 if (pvt->mch_window) 620 iounmap( pvt->mch_window ); 621 622 edac_mc_free(mci); 623 } 624 625 static const struct pci_device_id i82975x_pci_tbl[] = { 626 { 627 PCI_VEND_DEV(INTEL, 82975_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, 628 I82975X 629 }, 630 { 631 0, 632 } /* 0 terminated list. */ 633 }; 634 635 MODULE_DEVICE_TABLE(pci, i82975x_pci_tbl); 636 637 static struct pci_driver i82975x_driver = { 638 .name = EDAC_MOD_STR, 639 .probe = i82975x_init_one, 640 .remove = i82975x_remove_one, 641 .id_table = i82975x_pci_tbl, 642 }; 643 i82975x_init(void)644 static int __init i82975x_init(void) 645 { 646 int pci_rc; 647 648 edac_dbg(3, "\n"); 649 650 /* Ensure that the OPSTATE is set correctly for POLL or NMI */ 651 opstate_init(); 652 653 pci_rc = pci_register_driver(&i82975x_driver); 654 if (pci_rc < 0) 655 goto fail0; 656 657 if (mci_pdev == NULL) { 658 mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 659 PCI_DEVICE_ID_INTEL_82975_0, NULL); 660 661 if (!mci_pdev) { 662 edac_dbg(0, "i82975x pci_get_device fail\n"); 663 pci_rc = -ENODEV; 664 goto fail1; 665 } 666 667 pci_rc = i82975x_init_one(mci_pdev, i82975x_pci_tbl); 668 669 if (pci_rc < 0) { 670 edac_dbg(0, "i82975x init fail\n"); 671 pci_rc = -ENODEV; 672 goto fail1; 673 } 674 } 675 676 return 0; 677 678 fail1: 679 pci_unregister_driver(&i82975x_driver); 680 681 fail0: 682 pci_dev_put(mci_pdev); 683 return pci_rc; 684 } 685 i82975x_exit(void)686 static void __exit i82975x_exit(void) 687 { 688 edac_dbg(3, "\n"); 689 690 pci_unregister_driver(&i82975x_driver); 691 692 if (!i82975x_registered) { 693 i82975x_remove_one(mci_pdev); 694 pci_dev_put(mci_pdev); 695 } 696 } 697 698 module_init(i82975x_init); 699 module_exit(i82975x_exit); 700 701 MODULE_LICENSE("GPL"); 702 MODULE_AUTHOR("Arvind R. <arvino55@gmail.com>"); 703 MODULE_DESCRIPTION("MC support for Intel 82975 memory hub controllers"); 704 705 module_param(edac_op_state, int, 0444); 706 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); 707