1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Helper routines to scan the device tree for PCI devices and busses
4  *
5  * Migrated out of PowerPC architecture pci_64.c file by Grant Likely
6  * <grant.likely@secretlab.ca> so that these routines are available for
7  * 32 bit also.
8  *
9  * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
10  *   Rework, based on alpha PCI code.
11  * Copyright (c) 2009 Secret Lab Technologies Ltd.
12  */
13 
14 #include <linux/pci.h>
15 #include <linux/export.h>
16 #include <linux/of.h>
17 #include <asm/pci-bridge.h>
18 
19 /**
20  * get_int_prop - Decode a u32 from a device tree property
21  */
get_int_prop(struct device_node * np,const char * name,u32 def)22 static u32 get_int_prop(struct device_node *np, const char *name, u32 def)
23 {
24 	const __be32 *prop;
25 	int len;
26 
27 	prop = of_get_property(np, name, &len);
28 	if (prop && len >= 4)
29 		return of_read_number(prop, 1);
30 	return def;
31 }
32 
33 /**
34  * pci_parse_of_flags - Parse the flags cell of a device tree PCI address
35  * @addr0: value of 1st cell of a device tree PCI address.
36  * @bridge: Set this flag if the address is from a bridge 'ranges' property
37  *
38  * PCI Bus Binding to IEEE Std 1275-1994
39  *
40  * Bit#            33222222 22221111 11111100 00000000
41  *                 10987654 32109876 54321098 76543210
42  * phys.hi cell:   npt000ss bbbbbbbb dddddfff rrrrrrrr
43  * phys.mid cell:  hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh
44  * phys.lo cell:   llllllll llllllll llllllll llllllll
45  *
46  * where:
47  * n        is 0 if the address is relocatable, 1 otherwise
48  * p        is 1 if the addressable region is "prefetchable", 0 otherwise
49  * t        is 1 if the address is aliased (for non-relocatable I/O),
50  *          below 1 MB (for Memory),or below 64 KB (for relocatable I/O).
51  * ss       is the space code, denoting the address space:
52  *              00 denotes Configuration Space
53  *              01 denotes I/O Space
54  *              10 denotes 32-bit-address Memory Space
55  *              11 denotes 64-bit-address Memory Space
56  * bbbbbbbb is the 8-bit Bus Number
57  * ddddd    is the 5-bit Device Number
58  * fff      is the 3-bit Function Number
59  * rrrrrrrr is the 8-bit Register Number
60  */
61 #define OF_PCI_ADDR0_SPACE(ss)		(((ss)&3)<<24)
62 #define OF_PCI_ADDR0_SPACE_CFG		OF_PCI_ADDR0_SPACE(0)
63 #define OF_PCI_ADDR0_SPACE_IO		OF_PCI_ADDR0_SPACE(1)
64 #define OF_PCI_ADDR0_SPACE_MMIO32	OF_PCI_ADDR0_SPACE(2)
65 #define OF_PCI_ADDR0_SPACE_MMIO64	OF_PCI_ADDR0_SPACE(3)
66 #define OF_PCI_ADDR0_SPACE_MASK		OF_PCI_ADDR0_SPACE(3)
67 #define OF_PCI_ADDR0_RELOC		(1UL<<31)
68 #define OF_PCI_ADDR0_PREFETCH		(1UL<<30)
69 #define OF_PCI_ADDR0_ALIAS		(1UL<<29)
70 #define OF_PCI_ADDR0_BUS		0x00FF0000UL
71 #define OF_PCI_ADDR0_DEV		0x0000F800UL
72 #define OF_PCI_ADDR0_FN			0x00000700UL
73 #define OF_PCI_ADDR0_BARREG		0x000000FFUL
74 
pci_parse_of_flags(u32 addr0,int bridge)75 unsigned int pci_parse_of_flags(u32 addr0, int bridge)
76 {
77 	unsigned int flags = 0, as = addr0 & OF_PCI_ADDR0_SPACE_MASK;
78 
79 	if (as == OF_PCI_ADDR0_SPACE_MMIO32 || as == OF_PCI_ADDR0_SPACE_MMIO64) {
80 		flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
81 
82 		if (as == OF_PCI_ADDR0_SPACE_MMIO64)
83 			flags |= PCI_BASE_ADDRESS_MEM_TYPE_64 | IORESOURCE_MEM_64;
84 
85 		if (addr0 & OF_PCI_ADDR0_ALIAS)
86 			flags |= PCI_BASE_ADDRESS_MEM_TYPE_1M;
87 
88 		if (addr0 & OF_PCI_ADDR0_PREFETCH)
89 			flags |= IORESOURCE_PREFETCH |
90 				 PCI_BASE_ADDRESS_MEM_PREFETCH;
91 
92 		/* Note: We don't know whether the ROM has been left enabled
93 		 * by the firmware or not. We mark it as disabled (ie, we do
94 		 * not set the IORESOURCE_ROM_ENABLE flag) for now rather than
95 		 * do a config space read, it will be force-enabled if needed
96 		 */
97 		if (!bridge && (addr0 & OF_PCI_ADDR0_BARREG) == PCI_ROM_ADDRESS)
98 			flags |= IORESOURCE_READONLY;
99 
100 	} else if (as == OF_PCI_ADDR0_SPACE_IO)
101 		flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
102 
103 	if (flags)
104 		flags |= IORESOURCE_SIZEALIGN;
105 
106 	return flags;
107 }
108 
109 /**
110  * of_pci_parse_addrs - Parse PCI addresses assigned in the device tree node
111  * @node: device tree node for the PCI device
112  * @dev: pci_dev structure for the device
113  *
114  * This function parses the 'assigned-addresses' property of a PCI devices'
115  * device tree node and writes them into the associated pci_dev structure.
116  */
of_pci_parse_addrs(struct device_node * node,struct pci_dev * dev)117 static void of_pci_parse_addrs(struct device_node *node, struct pci_dev *dev)
118 {
119 	u64 base, size;
120 	unsigned int flags;
121 	struct pci_bus_region region;
122 	struct resource *res;
123 	const __be32 *addrs;
124 	u32 i;
125 	int proplen;
126 	bool mark_unset = false;
127 
128 	addrs = of_get_property(node, "assigned-addresses", &proplen);
129 	if (!addrs || !proplen) {
130 		addrs = of_get_property(node, "reg", &proplen);
131 		if (!addrs || !proplen)
132 			return;
133 		mark_unset = true;
134 	}
135 
136 	pr_debug("    parse addresses (%d bytes) @ %p\n", proplen, addrs);
137 	for (; proplen >= 20; proplen -= 20, addrs += 5) {
138 		flags = pci_parse_of_flags(of_read_number(addrs, 1), 0);
139 		if (!flags)
140 			continue;
141 		base = of_read_number(&addrs[1], 2);
142 		size = of_read_number(&addrs[3], 2);
143 		if (!size)
144 			continue;
145 		i = of_read_number(addrs, 1) & 0xff;
146 		pr_debug("  base: %llx, size: %llx, i: %x\n",
147 			 (unsigned long long)base,
148 			 (unsigned long long)size, i);
149 
150 		if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
151 			res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
152 		} else if (i == dev->rom_base_reg) {
153 			res = &dev->resource[PCI_ROM_RESOURCE];
154 			flags |= IORESOURCE_READONLY;
155 		} else {
156 			printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
157 			continue;
158 		}
159 		res->flags = flags;
160 		if (mark_unset)
161 			res->flags |= IORESOURCE_UNSET;
162 		res->name = pci_name(dev);
163 		region.start = base;
164 		region.end = base + size - 1;
165 		pcibios_bus_to_resource(dev->bus, res, &region);
166 	}
167 }
168 
169 /**
170  * of_create_pci_dev - Given a device tree node on a pci bus, create a pci_dev
171  * @node: device tree node pointer
172  * @bus: bus the device is sitting on
173  * @devfn: PCI function number, extracted from device tree by caller.
174  */
of_create_pci_dev(struct device_node * node,struct pci_bus * bus,int devfn)175 struct pci_dev *of_create_pci_dev(struct device_node *node,
176 				 struct pci_bus *bus, int devfn)
177 {
178 	struct pci_dev *dev;
179 
180 	dev = pci_alloc_dev(bus);
181 	if (!dev)
182 		return NULL;
183 
184 	pr_debug("    create device, devfn: %x, type: %s\n", devfn,
185 		 of_node_get_device_type(node));
186 
187 	dev->dev.of_node = of_node_get(node);
188 	dev->dev.parent = bus->bridge;
189 	dev->dev.bus = &pci_bus_type;
190 	dev->devfn = devfn;
191 	dev->multifunction = 0;		/* maybe a lie? */
192 	dev->needs_freset = 0;		/* pcie fundamental reset required */
193 	set_pcie_port_type(dev);
194 
195 	pci_dev_assign_slot(dev);
196 	dev->vendor = get_int_prop(node, "vendor-id", 0xffff);
197 	dev->device = get_int_prop(node, "device-id", 0xffff);
198 	dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0);
199 	dev->subsystem_device = get_int_prop(node, "subsystem-id", 0);
200 
201 	dev->cfg_size = pci_cfg_space_size(dev);
202 
203 	dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus),
204 		dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
205 	dev->class = get_int_prop(node, "class-code", 0);
206 	dev->revision = get_int_prop(node, "revision-id", 0);
207 
208 	pr_debug("    class: 0x%x\n", dev->class);
209 	pr_debug("    revision: 0x%x\n", dev->revision);
210 
211 	dev->current_state = PCI_UNKNOWN;	/* unknown power state */
212 	dev->error_state = pci_channel_io_normal;
213 	dev->dma_mask = 0xffffffff;
214 
215 	/* Early fixups, before probing the BARs */
216 	pci_fixup_device(pci_fixup_early, dev);
217 
218 	if (of_node_is_type(node, "pci") || of_node_is_type(node, "pciex")) {
219 		/* a PCI-PCI bridge */
220 		dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
221 		dev->rom_base_reg = PCI_ROM_ADDRESS1;
222 		set_pcie_hotplug_bridge(dev);
223 	} else if (of_node_is_type(node, "cardbus")) {
224 		dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
225 	} else {
226 		dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
227 		dev->rom_base_reg = PCI_ROM_ADDRESS;
228 		/* Maybe do a default OF mapping here */
229 		dev->irq = 0;
230 	}
231 
232 	of_pci_parse_addrs(node, dev);
233 
234 	pr_debug("    adding to system ...\n");
235 
236 	pci_device_add(dev, bus);
237 
238 	return dev;
239 }
240 EXPORT_SYMBOL(of_create_pci_dev);
241 
242 /**
243  * of_scan_pci_bridge - Set up a PCI bridge and scan for child nodes
244  * @dev: pci_dev structure for the bridge
245  *
246  * of_scan_bus() calls this routine for each PCI bridge that it finds, and
247  * this routine in turn call of_scan_bus() recursively to scan for more child
248  * devices.
249  */
of_scan_pci_bridge(struct pci_dev * dev)250 void of_scan_pci_bridge(struct pci_dev *dev)
251 {
252 	struct device_node *node = dev->dev.of_node;
253 	struct pci_bus *bus;
254 	struct pci_controller *phb;
255 	const __be32 *busrange, *ranges;
256 	int len, i, mode;
257 	struct pci_bus_region region;
258 	struct resource *res;
259 	unsigned int flags;
260 	u64 size;
261 
262 	pr_debug("of_scan_pci_bridge(%pOF)\n", node);
263 
264 	/* parse bus-range property */
265 	busrange = of_get_property(node, "bus-range", &len);
266 	if (busrange == NULL || len != 8) {
267 		printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %pOF\n",
268 		       node);
269 		return;
270 	}
271 	ranges = of_get_property(node, "ranges", &len);
272 	if (ranges == NULL) {
273 		printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %pOF\n",
274 		       node);
275 		return;
276 	}
277 
278 	bus = pci_find_bus(pci_domain_nr(dev->bus),
279 			   of_read_number(busrange, 1));
280 	if (!bus) {
281 		bus = pci_add_new_bus(dev->bus, dev,
282 				      of_read_number(busrange, 1));
283 		if (!bus) {
284 			printk(KERN_ERR "Failed to create pci bus for %pOF\n",
285 			       node);
286 			return;
287 		}
288 	}
289 
290 	bus->primary = dev->bus->number;
291 	pci_bus_insert_busn_res(bus, of_read_number(busrange, 1),
292 				of_read_number(busrange+1, 1));
293 	bus->bridge_ctl = 0;
294 
295 	/* parse ranges property */
296 	/* PCI #address-cells == 3 and #size-cells == 2 always */
297 	res = &dev->resource[PCI_BRIDGE_RESOURCES];
298 	for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
299 		res->flags = 0;
300 		bus->resource[i] = res;
301 		++res;
302 	}
303 	i = 1;
304 	for (; len >= 32; len -= 32, ranges += 8) {
305 		flags = pci_parse_of_flags(of_read_number(ranges, 1), 1);
306 		size = of_read_number(&ranges[6], 2);
307 		if (flags == 0 || size == 0)
308 			continue;
309 		if (flags & IORESOURCE_IO) {
310 			res = bus->resource[0];
311 			if (res->flags) {
312 				printk(KERN_ERR "PCI: ignoring extra I/O range"
313 				       " for bridge %pOF\n", node);
314 				continue;
315 			}
316 		} else {
317 			if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
318 				printk(KERN_ERR "PCI: too many memory ranges"
319 				       " for bridge %pOF\n", node);
320 				continue;
321 			}
322 			res = bus->resource[i];
323 			++i;
324 		}
325 		res->flags = flags;
326 		region.start = of_read_number(&ranges[1], 2);
327 		region.end = region.start + size - 1;
328 		pcibios_bus_to_resource(dev->bus, res, &region);
329 	}
330 	sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
331 		bus->number);
332 	pr_debug("    bus name: %s\n", bus->name);
333 
334 	phb = pci_bus_to_host(bus);
335 
336 	mode = PCI_PROBE_NORMAL;
337 	if (phb->controller_ops.probe_mode)
338 		mode = phb->controller_ops.probe_mode(bus);
339 	pr_debug("    probe mode: %d\n", mode);
340 
341 	if (mode == PCI_PROBE_DEVTREE)
342 		of_scan_bus(node, bus);
343 	else if (mode == PCI_PROBE_NORMAL)
344 		pci_scan_child_bus(bus);
345 }
346 EXPORT_SYMBOL(of_scan_pci_bridge);
347 
of_scan_pci_dev(struct pci_bus * bus,struct device_node * dn)348 static struct pci_dev *of_scan_pci_dev(struct pci_bus *bus,
349 			    struct device_node *dn)
350 {
351 	struct pci_dev *dev = NULL;
352 	const __be32 *reg;
353 	int reglen, devfn;
354 #ifdef CONFIG_EEH
355 	struct eeh_dev *edev = pdn_to_eeh_dev(PCI_DN(dn));
356 #endif
357 
358 	pr_debug("  * %pOF\n", dn);
359 	if (!of_device_is_available(dn))
360 		return NULL;
361 
362 	reg = of_get_property(dn, "reg", &reglen);
363 	if (reg == NULL || reglen < 20)
364 		return NULL;
365 	devfn = (of_read_number(reg, 1) >> 8) & 0xff;
366 
367 	/* Check if the PCI device is already there */
368 	dev = pci_get_slot(bus, devfn);
369 	if (dev) {
370 		pci_dev_put(dev);
371 		return dev;
372 	}
373 
374 	/* Device removed permanently ? */
375 #ifdef CONFIG_EEH
376 	if (edev && (edev->mode & EEH_DEV_REMOVED))
377 		return NULL;
378 #endif
379 
380 	/* create a new pci_dev for this device */
381 	dev = of_create_pci_dev(dn, bus, devfn);
382 	if (!dev)
383 		return NULL;
384 
385 	pr_debug("  dev header type: %x\n", dev->hdr_type);
386 	return dev;
387 }
388 
389 /**
390  * __of_scan_bus - given a PCI bus node, setup bus and scan for child devices
391  * @node: device tree node for the PCI bus
392  * @bus: pci_bus structure for the PCI bus
393  * @rescan_existing: Flag indicating bus has already been set up
394  */
__of_scan_bus(struct device_node * node,struct pci_bus * bus,int rescan_existing)395 static void __of_scan_bus(struct device_node *node, struct pci_bus *bus,
396 			  int rescan_existing)
397 {
398 	struct device_node *child;
399 	struct pci_dev *dev;
400 
401 	pr_debug("of_scan_bus(%pOF) bus no %d...\n",
402 		 node, bus->number);
403 
404 	/* Scan direct children */
405 	for_each_child_of_node(node, child) {
406 		dev = of_scan_pci_dev(bus, child);
407 		if (!dev)
408 			continue;
409 		pr_debug("    dev header type: %x\n", dev->hdr_type);
410 	}
411 
412 	/* Apply all fixups necessary. We don't fixup the bus "self"
413 	 * for an existing bridge that is being rescanned
414 	 */
415 	if (!rescan_existing)
416 		pcibios_setup_bus_self(bus);
417 
418 	/* Now scan child busses */
419 	for_each_pci_bridge(dev, bus)
420 		of_scan_pci_bridge(dev);
421 }
422 
423 /**
424  * of_scan_bus - given a PCI bus node, setup bus and scan for child devices
425  * @node: device tree node for the PCI bus
426  * @bus: pci_bus structure for the PCI bus
427  */
of_scan_bus(struct device_node * node,struct pci_bus * bus)428 void of_scan_bus(struct device_node *node, struct pci_bus *bus)
429 {
430 	__of_scan_bus(node, bus, 0);
431 }
432 EXPORT_SYMBOL_GPL(of_scan_bus);
433 
434 /**
435  * of_rescan_bus - given a PCI bus node, scan for child devices
436  * @node: device tree node for the PCI bus
437  * @bus: pci_bus structure for the PCI bus
438  *
439  * Same as of_scan_bus, but for a pci_bus structure that has already been
440  * setup.
441  */
of_rescan_bus(struct device_node * node,struct pci_bus * bus)442 void of_rescan_bus(struct device_node *node, struct pci_bus *bus)
443 {
444 	__of_scan_bus(node, bus, 1);
445 }
446 EXPORT_SYMBOL_GPL(of_rescan_bus);
447 
448