1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2021 MediaTek Inc.
4  * Author: Sam Shih <sam.shih@mediatek.com>
5  * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
6  * Author: Jianhui Zhao <zhaojh329@gmail.com>
7  * Author: Daniel Golle <daniel@makrotopia.org>
8  */
9 
10 #include <linux/clk-provider.h>
11 #include <linux/mod_devicetable.h>
12 #include <linux/platform_device.h>
13 
14 #include "clk-mtk.h"
15 #include "clk-gate.h"
16 
17 #include <dt-bindings/clock/mediatek,mt7981-clk.h>
18 
19 static const struct mtk_gate_regs sgmii0_cg_regs = {
20 	.set_ofs = 0xE4,
21 	.clr_ofs = 0xE4,
22 	.sta_ofs = 0xE4,
23 };
24 
25 #define GATE_SGMII0(_id, _name, _parent, _shift) {	\
26 		.id = _id,				\
27 		.name = _name,				\
28 		.parent_name = _parent,			\
29 		.regs = &sgmii0_cg_regs,			\
30 		.shift = _shift,			\
31 		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
32 	}
33 
34 static const struct mtk_gate sgmii0_clks[] __initconst = {
35 	GATE_SGMII0(CLK_SGM0_TX_EN, "sgm0_tx_en", "usb_tx250m", 2),
36 	GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", "usb_eq_rx250m", 3),
37 	GATE_SGMII0(CLK_SGM0_CK0_EN, "sgm0_ck0_en", "usb_ln0", 4),
38 	GATE_SGMII0(CLK_SGM0_CDR_CK0_EN, "sgm0_cdr_ck0_en", "usb_cdr", 5),
39 };
40 
41 static const struct mtk_gate_regs sgmii1_cg_regs = {
42 	.set_ofs = 0xE4,
43 	.clr_ofs = 0xE4,
44 	.sta_ofs = 0xE4,
45 };
46 
47 #define GATE_SGMII1(_id, _name, _parent, _shift) {	\
48 		.id = _id,				\
49 		.name = _name,				\
50 		.parent_name = _parent,			\
51 		.regs = &sgmii1_cg_regs,			\
52 		.shift = _shift,			\
53 		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
54 	}
55 
56 static const struct mtk_gate sgmii1_clks[] __initconst = {
57 	GATE_SGMII1(CLK_SGM1_TX_EN, "sgm1_tx_en", "usb_tx250m", 2),
58 	GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", "usb_eq_rx250m", 3),
59 	GATE_SGMII1(CLK_SGM1_CK1_EN, "sgm1_ck1_en", "usb_ln0", 4),
60 	GATE_SGMII1(CLK_SGM1_CDR_CK1_EN, "sgm1_cdr_ck1_en", "usb_cdr", 5),
61 };
62 
63 static const struct mtk_gate_regs eth_cg_regs = {
64 	.set_ofs = 0x30,
65 	.clr_ofs = 0x30,
66 	.sta_ofs = 0x30,
67 };
68 
69 #define GATE_ETH(_id, _name, _parent, _shift) {	\
70 		.id = _id,				\
71 		.name = _name,				\
72 		.parent_name = _parent,			\
73 		.regs = &eth_cg_regs,			\
74 		.shift = _shift,			\
75 		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
76 	}
77 
78 static const struct mtk_gate eth_clks[] __initconst = {
79 	GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x", 6),
80 	GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m", 7),
81 	GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m", 8),
82 	GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", "netsys_wed_mcu", 15),
83 };
84 
85 static const struct mtk_clk_desc eth_desc = {
86 	.clks = eth_clks,
87 	.num_clks = ARRAY_SIZE(eth_clks),
88 };
89 
90 static const struct mtk_clk_desc sgmii0_desc = {
91 	.clks = sgmii0_clks,
92 	.num_clks = ARRAY_SIZE(sgmii0_clks),
93 };
94 
95 static const struct mtk_clk_desc sgmii1_desc = {
96 	.clks = sgmii1_clks,
97 	.num_clks = ARRAY_SIZE(sgmii1_clks),
98 };
99 
100 static const struct of_device_id of_match_clk_mt7981_eth[] = {
101 	{ .compatible = "mediatek,mt7981-ethsys", .data = &eth_desc },
102 	{ .compatible = "mediatek,mt7981-sgmiisys_0", .data = &sgmii0_desc },
103 	{ .compatible = "mediatek,mt7981-sgmiisys_1", .data = &sgmii1_desc },
104 	{ /* sentinel */ }
105 };
106 MODULE_DEVICE_TABLE(of, of_match_clk_mt7981_eth);
107 
108 static struct platform_driver clk_mt7981_eth_drv = {
109 	.probe = mtk_clk_simple_probe,
110 	.remove_new = mtk_clk_simple_remove,
111 	.driver = {
112 		.name = "clk-mt7981-eth",
113 		.of_match_table = of_match_clk_mt7981_eth,
114 	},
115 };
116 module_platform_driver(clk_mt7981_eth_drv);
117 MODULE_LICENSE("GPL");
118