1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * PCIe host controller driver for NWL PCIe Bridge
4 * Based on pcie-xilinx.c, pci-tegra.c
5 *
6 * (C) Copyright 2014 - 2015, Xilinx, Inc.
7 */
8
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/interrupt.h>
12 #include <linux/irq.h>
13 #include <linux/irqdomain.h>
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/msi.h>
17 #include <linux/of_address.h>
18 #include <linux/of_pci.h>
19 #include <linux/of_platform.h>
20 #include <linux/pci.h>
21 #include <linux/pci-ecam.h>
22 #include <linux/platform_device.h>
23 #include <linux/irqchip/chained_irq.h>
24
25 #include "../pci.h"
26
27 /* Bridge core config registers */
28 #define BRCFG_PCIE_RX0 0x00000000
29 #define BRCFG_PCIE_RX1 0x00000004
30 #define BRCFG_INTERRUPT 0x00000010
31 #define BRCFG_PCIE_RX_MSG_FILTER 0x00000020
32
33 /* Egress - Bridge translation registers */
34 #define E_BREG_CAPABILITIES 0x00000200
35 #define E_BREG_CONTROL 0x00000208
36 #define E_BREG_BASE_LO 0x00000210
37 #define E_BREG_BASE_HI 0x00000214
38 #define E_ECAM_CAPABILITIES 0x00000220
39 #define E_ECAM_CONTROL 0x00000228
40 #define E_ECAM_BASE_LO 0x00000230
41 #define E_ECAM_BASE_HI 0x00000234
42
43 /* Ingress - address translations */
44 #define I_MSII_CAPABILITIES 0x00000300
45 #define I_MSII_CONTROL 0x00000308
46 #define I_MSII_BASE_LO 0x00000310
47 #define I_MSII_BASE_HI 0x00000314
48
49 #define I_ISUB_CONTROL 0x000003E8
50 #define SET_ISUB_CONTROL BIT(0)
51 /* Rxed msg fifo - Interrupt status registers */
52 #define MSGF_MISC_STATUS 0x00000400
53 #define MSGF_MISC_MASK 0x00000404
54 #define MSGF_LEG_STATUS 0x00000420
55 #define MSGF_LEG_MASK 0x00000424
56 #define MSGF_MSI_STATUS_LO 0x00000440
57 #define MSGF_MSI_STATUS_HI 0x00000444
58 #define MSGF_MSI_MASK_LO 0x00000448
59 #define MSGF_MSI_MASK_HI 0x0000044C
60
61 /* Msg filter mask bits */
62 #define CFG_ENABLE_PM_MSG_FWD BIT(1)
63 #define CFG_ENABLE_INT_MSG_FWD BIT(2)
64 #define CFG_ENABLE_ERR_MSG_FWD BIT(3)
65 #define CFG_ENABLE_MSG_FILTER_MASK (CFG_ENABLE_PM_MSG_FWD | \
66 CFG_ENABLE_INT_MSG_FWD | \
67 CFG_ENABLE_ERR_MSG_FWD)
68
69 /* Misc interrupt status mask bits */
70 #define MSGF_MISC_SR_RXMSG_AVAIL BIT(0)
71 #define MSGF_MISC_SR_RXMSG_OVER BIT(1)
72 #define MSGF_MISC_SR_SLAVE_ERR BIT(4)
73 #define MSGF_MISC_SR_MASTER_ERR BIT(5)
74 #define MSGF_MISC_SR_I_ADDR_ERR BIT(6)
75 #define MSGF_MISC_SR_E_ADDR_ERR BIT(7)
76 #define MSGF_MISC_SR_FATAL_AER BIT(16)
77 #define MSGF_MISC_SR_NON_FATAL_AER BIT(17)
78 #define MSGF_MISC_SR_CORR_AER BIT(18)
79 #define MSGF_MISC_SR_UR_DETECT BIT(20)
80 #define MSGF_MISC_SR_NON_FATAL_DEV BIT(22)
81 #define MSGF_MISC_SR_FATAL_DEV BIT(23)
82 #define MSGF_MISC_SR_LINK_DOWN BIT(24)
83 #define MSGF_MISC_SR_LINK_AUTO_BWIDTH BIT(25)
84 #define MSGF_MISC_SR_LINK_BWIDTH BIT(26)
85
86 #define MSGF_MISC_SR_MASKALL (MSGF_MISC_SR_RXMSG_AVAIL | \
87 MSGF_MISC_SR_RXMSG_OVER | \
88 MSGF_MISC_SR_SLAVE_ERR | \
89 MSGF_MISC_SR_MASTER_ERR | \
90 MSGF_MISC_SR_I_ADDR_ERR | \
91 MSGF_MISC_SR_E_ADDR_ERR | \
92 MSGF_MISC_SR_FATAL_AER | \
93 MSGF_MISC_SR_NON_FATAL_AER | \
94 MSGF_MISC_SR_CORR_AER | \
95 MSGF_MISC_SR_UR_DETECT | \
96 MSGF_MISC_SR_NON_FATAL_DEV | \
97 MSGF_MISC_SR_FATAL_DEV | \
98 MSGF_MISC_SR_LINK_DOWN | \
99 MSGF_MISC_SR_LINK_AUTO_BWIDTH | \
100 MSGF_MISC_SR_LINK_BWIDTH)
101
102 /* Legacy interrupt status mask bits */
103 #define MSGF_LEG_SR_INTA BIT(0)
104 #define MSGF_LEG_SR_INTB BIT(1)
105 #define MSGF_LEG_SR_INTC BIT(2)
106 #define MSGF_LEG_SR_INTD BIT(3)
107 #define MSGF_LEG_SR_MASKALL (MSGF_LEG_SR_INTA | MSGF_LEG_SR_INTB | \
108 MSGF_LEG_SR_INTC | MSGF_LEG_SR_INTD)
109
110 /* MSI interrupt status mask bits */
111 #define MSGF_MSI_SR_LO_MASK GENMASK(31, 0)
112 #define MSGF_MSI_SR_HI_MASK GENMASK(31, 0)
113
114 #define MSII_PRESENT BIT(0)
115 #define MSII_ENABLE BIT(0)
116 #define MSII_STATUS_ENABLE BIT(15)
117
118 /* Bridge config interrupt mask */
119 #define BRCFG_INTERRUPT_MASK BIT(0)
120 #define BREG_PRESENT BIT(0)
121 #define BREG_ENABLE BIT(0)
122 #define BREG_ENABLE_FORCE BIT(1)
123
124 /* E_ECAM status mask bits */
125 #define E_ECAM_PRESENT BIT(0)
126 #define E_ECAM_CR_ENABLE BIT(0)
127 #define E_ECAM_SIZE_LOC GENMASK(20, 16)
128 #define E_ECAM_SIZE_SHIFT 16
129 #define NWL_ECAM_VALUE_DEFAULT 12
130
131 #define CFG_DMA_REG_BAR GENMASK(2, 0)
132 #define CFG_PCIE_CACHE GENMASK(7, 0)
133
134 #define INT_PCI_MSI_NR (2 * 32)
135
136 /* Readin the PS_LINKUP */
137 #define PS_LINKUP_OFFSET 0x00000238
138 #define PCIE_PHY_LINKUP_BIT BIT(0)
139 #define PHY_RDY_LINKUP_BIT BIT(1)
140
141 /* Parameters for the waiting for link up routine */
142 #define LINK_WAIT_MAX_RETRIES 10
143 #define LINK_WAIT_USLEEP_MIN 90000
144 #define LINK_WAIT_USLEEP_MAX 100000
145
146 struct nwl_msi { /* MSI information */
147 struct irq_domain *msi_domain;
148 DECLARE_BITMAP(bitmap, INT_PCI_MSI_NR);
149 struct irq_domain *dev_domain;
150 struct mutex lock; /* protect bitmap variable */
151 int irq_msi0;
152 int irq_msi1;
153 };
154
155 struct nwl_pcie {
156 struct device *dev;
157 void __iomem *breg_base;
158 void __iomem *pcireg_base;
159 void __iomem *ecam_base;
160 phys_addr_t phys_breg_base; /* Physical Bridge Register Base */
161 phys_addr_t phys_pcie_reg_base; /* Physical PCIe Controller Base */
162 phys_addr_t phys_ecam_base; /* Physical Configuration Base */
163 u32 breg_size;
164 u32 pcie_reg_size;
165 u32 ecam_size;
166 int irq_intx;
167 int irq_misc;
168 u32 ecam_value;
169 u8 last_busno;
170 struct nwl_msi msi;
171 struct irq_domain *legacy_irq_domain;
172 struct clk *clk;
173 raw_spinlock_t leg_mask_lock;
174 };
175
nwl_bridge_readl(struct nwl_pcie * pcie,u32 off)176 static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off)
177 {
178 return readl(pcie->breg_base + off);
179 }
180
nwl_bridge_writel(struct nwl_pcie * pcie,u32 val,u32 off)181 static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off)
182 {
183 writel(val, pcie->breg_base + off);
184 }
185
nwl_pcie_link_up(struct nwl_pcie * pcie)186 static bool nwl_pcie_link_up(struct nwl_pcie *pcie)
187 {
188 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT)
189 return true;
190 return false;
191 }
192
nwl_phy_link_up(struct nwl_pcie * pcie)193 static bool nwl_phy_link_up(struct nwl_pcie *pcie)
194 {
195 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT)
196 return true;
197 return false;
198 }
199
nwl_wait_for_link(struct nwl_pcie * pcie)200 static int nwl_wait_for_link(struct nwl_pcie *pcie)
201 {
202 struct device *dev = pcie->dev;
203 int retries;
204
205 /* check if the link is up or not */
206 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
207 if (nwl_phy_link_up(pcie))
208 return 0;
209 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
210 }
211
212 dev_err(dev, "PHY link never came up\n");
213 return -ETIMEDOUT;
214 }
215
nwl_pcie_valid_device(struct pci_bus * bus,unsigned int devfn)216 static bool nwl_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
217 {
218 struct nwl_pcie *pcie = bus->sysdata;
219
220 /* Check link before accessing downstream ports */
221 if (!pci_is_root_bus(bus)) {
222 if (!nwl_pcie_link_up(pcie))
223 return false;
224 } else if (devfn > 0)
225 /* Only one device down on each root port */
226 return false;
227
228 return true;
229 }
230
231 /**
232 * nwl_pcie_map_bus - Get configuration base
233 *
234 * @bus: Bus structure of current bus
235 * @devfn: Device/function
236 * @where: Offset from base
237 *
238 * Return: Base address of the configuration space needed to be
239 * accessed.
240 */
nwl_pcie_map_bus(struct pci_bus * bus,unsigned int devfn,int where)241 static void __iomem *nwl_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
242 int where)
243 {
244 struct nwl_pcie *pcie = bus->sysdata;
245
246 if (!nwl_pcie_valid_device(bus, devfn))
247 return NULL;
248
249 return pcie->ecam_base + PCIE_ECAM_OFFSET(bus->number, devfn, where);
250 }
251
252 /* PCIe operations */
253 static struct pci_ops nwl_pcie_ops = {
254 .map_bus = nwl_pcie_map_bus,
255 .read = pci_generic_config_read,
256 .write = pci_generic_config_write,
257 };
258
nwl_pcie_misc_handler(int irq,void * data)259 static irqreturn_t nwl_pcie_misc_handler(int irq, void *data)
260 {
261 struct nwl_pcie *pcie = data;
262 struct device *dev = pcie->dev;
263 u32 misc_stat;
264
265 /* Checking for misc interrupts */
266 misc_stat = nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &
267 MSGF_MISC_SR_MASKALL;
268 if (!misc_stat)
269 return IRQ_NONE;
270
271 if (misc_stat & MSGF_MISC_SR_RXMSG_OVER)
272 dev_err(dev, "Received Message FIFO Overflow\n");
273
274 if (misc_stat & MSGF_MISC_SR_SLAVE_ERR)
275 dev_err(dev, "Slave error\n");
276
277 if (misc_stat & MSGF_MISC_SR_MASTER_ERR)
278 dev_err(dev, "Master error\n");
279
280 if (misc_stat & MSGF_MISC_SR_I_ADDR_ERR)
281 dev_err(dev, "In Misc Ingress address translation error\n");
282
283 if (misc_stat & MSGF_MISC_SR_E_ADDR_ERR)
284 dev_err(dev, "In Misc Egress address translation error\n");
285
286 if (misc_stat & MSGF_MISC_SR_FATAL_AER)
287 dev_err(dev, "Fatal Error in AER Capability\n");
288
289 if (misc_stat & MSGF_MISC_SR_NON_FATAL_AER)
290 dev_err(dev, "Non-Fatal Error in AER Capability\n");
291
292 if (misc_stat & MSGF_MISC_SR_CORR_AER)
293 dev_err(dev, "Correctable Error in AER Capability\n");
294
295 if (misc_stat & MSGF_MISC_SR_UR_DETECT)
296 dev_err(dev, "Unsupported request Detected\n");
297
298 if (misc_stat & MSGF_MISC_SR_NON_FATAL_DEV)
299 dev_err(dev, "Non-Fatal Error Detected\n");
300
301 if (misc_stat & MSGF_MISC_SR_FATAL_DEV)
302 dev_err(dev, "Fatal Error Detected\n");
303
304 if (misc_stat & MSGF_MISC_SR_LINK_AUTO_BWIDTH)
305 dev_info(dev, "Link Autonomous Bandwidth Management Status bit set\n");
306
307 if (misc_stat & MSGF_MISC_SR_LINK_BWIDTH)
308 dev_info(dev, "Link Bandwidth Management Status bit set\n");
309
310 /* Clear misc interrupt status */
311 nwl_bridge_writel(pcie, misc_stat, MSGF_MISC_STATUS);
312
313 return IRQ_HANDLED;
314 }
315
nwl_pcie_leg_handler(struct irq_desc * desc)316 static void nwl_pcie_leg_handler(struct irq_desc *desc)
317 {
318 struct irq_chip *chip = irq_desc_get_chip(desc);
319 struct nwl_pcie *pcie;
320 unsigned long status;
321 u32 bit;
322
323 chained_irq_enter(chip, desc);
324 pcie = irq_desc_get_handler_data(desc);
325
326 while ((status = nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
327 MSGF_LEG_SR_MASKALL) != 0) {
328 for_each_set_bit(bit, &status, PCI_NUM_INTX)
329 generic_handle_domain_irq(pcie->legacy_irq_domain, bit);
330 }
331
332 chained_irq_exit(chip, desc);
333 }
334
nwl_pcie_handle_msi_irq(struct nwl_pcie * pcie,u32 status_reg)335 static void nwl_pcie_handle_msi_irq(struct nwl_pcie *pcie, u32 status_reg)
336 {
337 struct nwl_msi *msi = &pcie->msi;
338 unsigned long status;
339 u32 bit;
340
341 while ((status = nwl_bridge_readl(pcie, status_reg)) != 0) {
342 for_each_set_bit(bit, &status, 32) {
343 nwl_bridge_writel(pcie, 1 << bit, status_reg);
344 generic_handle_domain_irq(msi->dev_domain, bit);
345 }
346 }
347 }
348
nwl_pcie_msi_handler_high(struct irq_desc * desc)349 static void nwl_pcie_msi_handler_high(struct irq_desc *desc)
350 {
351 struct irq_chip *chip = irq_desc_get_chip(desc);
352 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);
353
354 chained_irq_enter(chip, desc);
355 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_HI);
356 chained_irq_exit(chip, desc);
357 }
358
nwl_pcie_msi_handler_low(struct irq_desc * desc)359 static void nwl_pcie_msi_handler_low(struct irq_desc *desc)
360 {
361 struct irq_chip *chip = irq_desc_get_chip(desc);
362 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);
363
364 chained_irq_enter(chip, desc);
365 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_LO);
366 chained_irq_exit(chip, desc);
367 }
368
nwl_mask_leg_irq(struct irq_data * data)369 static void nwl_mask_leg_irq(struct irq_data *data)
370 {
371 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
372 unsigned long flags;
373 u32 mask;
374 u32 val;
375
376 mask = 1 << data->hwirq;
377 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags);
378 val = nwl_bridge_readl(pcie, MSGF_LEG_MASK);
379 nwl_bridge_writel(pcie, (val & (~mask)), MSGF_LEG_MASK);
380 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags);
381 }
382
nwl_unmask_leg_irq(struct irq_data * data)383 static void nwl_unmask_leg_irq(struct irq_data *data)
384 {
385 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
386 unsigned long flags;
387 u32 mask;
388 u32 val;
389
390 mask = 1 << data->hwirq;
391 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags);
392 val = nwl_bridge_readl(pcie, MSGF_LEG_MASK);
393 nwl_bridge_writel(pcie, (val | mask), MSGF_LEG_MASK);
394 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags);
395 }
396
397 static struct irq_chip nwl_leg_irq_chip = {
398 .name = "nwl_pcie:legacy",
399 .irq_enable = nwl_unmask_leg_irq,
400 .irq_disable = nwl_mask_leg_irq,
401 .irq_mask = nwl_mask_leg_irq,
402 .irq_unmask = nwl_unmask_leg_irq,
403 };
404
nwl_legacy_map(struct irq_domain * domain,unsigned int irq,irq_hw_number_t hwirq)405 static int nwl_legacy_map(struct irq_domain *domain, unsigned int irq,
406 irq_hw_number_t hwirq)
407 {
408 irq_set_chip_and_handler(irq, &nwl_leg_irq_chip, handle_level_irq);
409 irq_set_chip_data(irq, domain->host_data);
410 irq_set_status_flags(irq, IRQ_LEVEL);
411
412 return 0;
413 }
414
415 static const struct irq_domain_ops legacy_domain_ops = {
416 .map = nwl_legacy_map,
417 .xlate = pci_irqd_intx_xlate,
418 };
419
420 #ifdef CONFIG_PCI_MSI
421 static struct irq_chip nwl_msi_irq_chip = {
422 .name = "nwl_pcie:msi",
423 .irq_enable = pci_msi_unmask_irq,
424 .irq_disable = pci_msi_mask_irq,
425 .irq_mask = pci_msi_mask_irq,
426 .irq_unmask = pci_msi_unmask_irq,
427 };
428
429 static struct msi_domain_info nwl_msi_domain_info = {
430 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
431 MSI_FLAG_MULTI_PCI_MSI),
432 .chip = &nwl_msi_irq_chip,
433 };
434 #endif
435
nwl_compose_msi_msg(struct irq_data * data,struct msi_msg * msg)436 static void nwl_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
437 {
438 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
439 phys_addr_t msi_addr = pcie->phys_pcie_reg_base;
440
441 msg->address_lo = lower_32_bits(msi_addr);
442 msg->address_hi = upper_32_bits(msi_addr);
443 msg->data = data->hwirq;
444 }
445
nwl_msi_set_affinity(struct irq_data * irq_data,const struct cpumask * mask,bool force)446 static int nwl_msi_set_affinity(struct irq_data *irq_data,
447 const struct cpumask *mask, bool force)
448 {
449 return -EINVAL;
450 }
451
452 static struct irq_chip nwl_irq_chip = {
453 .name = "Xilinx MSI",
454 .irq_compose_msi_msg = nwl_compose_msi_msg,
455 .irq_set_affinity = nwl_msi_set_affinity,
456 };
457
nwl_irq_domain_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * args)458 static int nwl_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
459 unsigned int nr_irqs, void *args)
460 {
461 struct nwl_pcie *pcie = domain->host_data;
462 struct nwl_msi *msi = &pcie->msi;
463 int bit;
464 int i;
465
466 mutex_lock(&msi->lock);
467 bit = bitmap_find_free_region(msi->bitmap, INT_PCI_MSI_NR,
468 get_count_order(nr_irqs));
469 if (bit < 0) {
470 mutex_unlock(&msi->lock);
471 return -ENOSPC;
472 }
473
474 for (i = 0; i < nr_irqs; i++) {
475 irq_domain_set_info(domain, virq + i, bit + i, &nwl_irq_chip,
476 domain->host_data, handle_simple_irq,
477 NULL, NULL);
478 }
479 mutex_unlock(&msi->lock);
480 return 0;
481 }
482
nwl_irq_domain_free(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs)483 static void nwl_irq_domain_free(struct irq_domain *domain, unsigned int virq,
484 unsigned int nr_irqs)
485 {
486 struct irq_data *data = irq_domain_get_irq_data(domain, virq);
487 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
488 struct nwl_msi *msi = &pcie->msi;
489
490 mutex_lock(&msi->lock);
491 bitmap_release_region(msi->bitmap, data->hwirq,
492 get_count_order(nr_irqs));
493 mutex_unlock(&msi->lock);
494 }
495
496 static const struct irq_domain_ops dev_msi_domain_ops = {
497 .alloc = nwl_irq_domain_alloc,
498 .free = nwl_irq_domain_free,
499 };
500
nwl_pcie_init_msi_irq_domain(struct nwl_pcie * pcie)501 static int nwl_pcie_init_msi_irq_domain(struct nwl_pcie *pcie)
502 {
503 #ifdef CONFIG_PCI_MSI
504 struct device *dev = pcie->dev;
505 struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node);
506 struct nwl_msi *msi = &pcie->msi;
507
508 msi->dev_domain = irq_domain_add_linear(NULL, INT_PCI_MSI_NR,
509 &dev_msi_domain_ops, pcie);
510 if (!msi->dev_domain) {
511 dev_err(dev, "failed to create dev IRQ domain\n");
512 return -ENOMEM;
513 }
514 msi->msi_domain = pci_msi_create_irq_domain(fwnode,
515 &nwl_msi_domain_info,
516 msi->dev_domain);
517 if (!msi->msi_domain) {
518 dev_err(dev, "failed to create msi IRQ domain\n");
519 irq_domain_remove(msi->dev_domain);
520 return -ENOMEM;
521 }
522 #endif
523 return 0;
524 }
525
nwl_pcie_init_irq_domain(struct nwl_pcie * pcie)526 static int nwl_pcie_init_irq_domain(struct nwl_pcie *pcie)
527 {
528 struct device *dev = pcie->dev;
529 struct device_node *node = dev->of_node;
530 struct device_node *legacy_intc_node;
531
532 legacy_intc_node = of_get_next_child(node, NULL);
533 if (!legacy_intc_node) {
534 dev_err(dev, "No legacy intc node found\n");
535 return -EINVAL;
536 }
537
538 pcie->legacy_irq_domain = irq_domain_add_linear(legacy_intc_node,
539 PCI_NUM_INTX,
540 &legacy_domain_ops,
541 pcie);
542 of_node_put(legacy_intc_node);
543 if (!pcie->legacy_irq_domain) {
544 dev_err(dev, "failed to create IRQ domain\n");
545 return -ENOMEM;
546 }
547
548 raw_spin_lock_init(&pcie->leg_mask_lock);
549 nwl_pcie_init_msi_irq_domain(pcie);
550 return 0;
551 }
552
nwl_pcie_enable_msi(struct nwl_pcie * pcie)553 static int nwl_pcie_enable_msi(struct nwl_pcie *pcie)
554 {
555 struct device *dev = pcie->dev;
556 struct platform_device *pdev = to_platform_device(dev);
557 struct nwl_msi *msi = &pcie->msi;
558 unsigned long base;
559 int ret;
560
561 mutex_init(&msi->lock);
562
563 /* Get msi_1 IRQ number */
564 msi->irq_msi1 = platform_get_irq_byname(pdev, "msi1");
565 if (msi->irq_msi1 < 0)
566 return -EINVAL;
567
568 irq_set_chained_handler_and_data(msi->irq_msi1,
569 nwl_pcie_msi_handler_high, pcie);
570
571 /* Get msi_0 IRQ number */
572 msi->irq_msi0 = platform_get_irq_byname(pdev, "msi0");
573 if (msi->irq_msi0 < 0)
574 return -EINVAL;
575
576 irq_set_chained_handler_and_data(msi->irq_msi0,
577 nwl_pcie_msi_handler_low, pcie);
578
579 /* Check for msii_present bit */
580 ret = nwl_bridge_readl(pcie, I_MSII_CAPABILITIES) & MSII_PRESENT;
581 if (!ret) {
582 dev_err(dev, "MSI not present\n");
583 return -EIO;
584 }
585
586 /* Enable MSII */
587 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
588 MSII_ENABLE, I_MSII_CONTROL);
589
590 /* Enable MSII status */
591 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
592 MSII_STATUS_ENABLE, I_MSII_CONTROL);
593
594 /* setup AFI/FPCI range */
595 base = pcie->phys_pcie_reg_base;
596 nwl_bridge_writel(pcie, lower_32_bits(base), I_MSII_BASE_LO);
597 nwl_bridge_writel(pcie, upper_32_bits(base), I_MSII_BASE_HI);
598
599 /*
600 * For high range MSI interrupts: disable, clear any pending,
601 * and enable
602 */
603 nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_HI);
604
605 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_HI) &
606 MSGF_MSI_SR_HI_MASK, MSGF_MSI_STATUS_HI);
607
608 nwl_bridge_writel(pcie, MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI);
609
610 /*
611 * For low range MSI interrupts: disable, clear any pending,
612 * and enable
613 */
614 nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_LO);
615
616 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_LO) &
617 MSGF_MSI_SR_LO_MASK, MSGF_MSI_STATUS_LO);
618
619 nwl_bridge_writel(pcie, MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO);
620
621 return 0;
622 }
623
nwl_pcie_bridge_init(struct nwl_pcie * pcie)624 static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)
625 {
626 struct device *dev = pcie->dev;
627 struct platform_device *pdev = to_platform_device(dev);
628 u32 breg_val, ecam_val, first_busno = 0;
629 int err;
630
631 breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT;
632 if (!breg_val) {
633 dev_err(dev, "BREG is not present\n");
634 return breg_val;
635 }
636
637 /* Write bridge_off to breg base */
638 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base),
639 E_BREG_BASE_LO);
640 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base),
641 E_BREG_BASE_HI);
642
643 /* Enable BREG */
644 nwl_bridge_writel(pcie, ~BREG_ENABLE_FORCE & BREG_ENABLE,
645 E_BREG_CONTROL);
646
647 /* Disable DMA channel registers */
648 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX0) |
649 CFG_DMA_REG_BAR, BRCFG_PCIE_RX0);
650
651 /* Enable Ingress subtractive decode translation */
652 nwl_bridge_writel(pcie, SET_ISUB_CONTROL, I_ISUB_CONTROL);
653
654 /* Enable msg filtering details */
655 nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK,
656 BRCFG_PCIE_RX_MSG_FILTER);
657
658 /* This routes the PCIe DMA traffic to go through CCI path */
659 if (of_dma_is_coherent(dev->of_node))
660 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX1) |
661 CFG_PCIE_CACHE, BRCFG_PCIE_RX1);
662
663 err = nwl_wait_for_link(pcie);
664 if (err)
665 return err;
666
667 ecam_val = nwl_bridge_readl(pcie, E_ECAM_CAPABILITIES) & E_ECAM_PRESENT;
668 if (!ecam_val) {
669 dev_err(dev, "ECAM is not present\n");
670 return ecam_val;
671 }
672
673 /* Enable ECAM */
674 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
675 E_ECAM_CR_ENABLE, E_ECAM_CONTROL);
676
677 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
678 (pcie->ecam_value << E_ECAM_SIZE_SHIFT),
679 E_ECAM_CONTROL);
680
681 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base),
682 E_ECAM_BASE_LO);
683 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base),
684 E_ECAM_BASE_HI);
685
686 /* Get bus range */
687 ecam_val = nwl_bridge_readl(pcie, E_ECAM_CONTROL);
688 pcie->last_busno = (ecam_val & E_ECAM_SIZE_LOC) >> E_ECAM_SIZE_SHIFT;
689 /* Write primary, secondary and subordinate bus numbers */
690 ecam_val = first_busno;
691 ecam_val |= (first_busno + 1) << 8;
692 ecam_val |= (pcie->last_busno << E_ECAM_SIZE_SHIFT);
693 writel(ecam_val, (pcie->ecam_base + PCI_PRIMARY_BUS));
694
695 if (nwl_pcie_link_up(pcie))
696 dev_info(dev, "Link is UP\n");
697 else
698 dev_info(dev, "Link is DOWN\n");
699
700 /* Get misc IRQ number */
701 pcie->irq_misc = platform_get_irq_byname(pdev, "misc");
702 if (pcie->irq_misc < 0)
703 return -EINVAL;
704
705 err = devm_request_irq(dev, pcie->irq_misc,
706 nwl_pcie_misc_handler, IRQF_SHARED,
707 "nwl_pcie:misc", pcie);
708 if (err) {
709 dev_err(dev, "fail to register misc IRQ#%d\n",
710 pcie->irq_misc);
711 return err;
712 }
713
714 /* Disable all misc interrupts */
715 nwl_bridge_writel(pcie, (u32)~MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
716
717 /* Clear pending misc interrupts */
718 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &
719 MSGF_MISC_SR_MASKALL, MSGF_MISC_STATUS);
720
721 /* Enable all misc interrupts */
722 nwl_bridge_writel(pcie, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
723
724 /* Disable all legacy interrupts */
725 nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
726
727 /* Clear pending legacy interrupts */
728 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
729 MSGF_LEG_SR_MASKALL, MSGF_LEG_STATUS);
730
731 /* Enable all legacy interrupts */
732 nwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
733
734 /* Enable the bridge config interrupt */
735 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_INTERRUPT) |
736 BRCFG_INTERRUPT_MASK, BRCFG_INTERRUPT);
737
738 return 0;
739 }
740
nwl_pcie_parse_dt(struct nwl_pcie * pcie,struct platform_device * pdev)741 static int nwl_pcie_parse_dt(struct nwl_pcie *pcie,
742 struct platform_device *pdev)
743 {
744 struct device *dev = pcie->dev;
745 struct resource *res;
746
747 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "breg");
748 pcie->breg_base = devm_ioremap_resource(dev, res);
749 if (IS_ERR(pcie->breg_base))
750 return PTR_ERR(pcie->breg_base);
751 pcie->phys_breg_base = res->start;
752
753 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcireg");
754 pcie->pcireg_base = devm_ioremap_resource(dev, res);
755 if (IS_ERR(pcie->pcireg_base))
756 return PTR_ERR(pcie->pcireg_base);
757 pcie->phys_pcie_reg_base = res->start;
758
759 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
760 pcie->ecam_base = devm_pci_remap_cfg_resource(dev, res);
761 if (IS_ERR(pcie->ecam_base))
762 return PTR_ERR(pcie->ecam_base);
763 pcie->phys_ecam_base = res->start;
764
765 /* Get intx IRQ number */
766 pcie->irq_intx = platform_get_irq_byname(pdev, "intx");
767 if (pcie->irq_intx < 0)
768 return pcie->irq_intx;
769
770 irq_set_chained_handler_and_data(pcie->irq_intx,
771 nwl_pcie_leg_handler, pcie);
772
773 return 0;
774 }
775
776 static const struct of_device_id nwl_pcie_of_match[] = {
777 { .compatible = "xlnx,nwl-pcie-2.11", },
778 {}
779 };
780
nwl_pcie_probe(struct platform_device * pdev)781 static int nwl_pcie_probe(struct platform_device *pdev)
782 {
783 struct device *dev = &pdev->dev;
784 struct nwl_pcie *pcie;
785 struct pci_host_bridge *bridge;
786 int err;
787
788 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
789 if (!bridge)
790 return -ENODEV;
791
792 pcie = pci_host_bridge_priv(bridge);
793 platform_set_drvdata(pdev, pcie);
794
795 pcie->dev = dev;
796 pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT;
797
798 err = nwl_pcie_parse_dt(pcie, pdev);
799 if (err) {
800 dev_err(dev, "Parsing DT failed\n");
801 return err;
802 }
803
804 pcie->clk = devm_clk_get(dev, NULL);
805 if (IS_ERR(pcie->clk))
806 return PTR_ERR(pcie->clk);
807
808 err = clk_prepare_enable(pcie->clk);
809 if (err) {
810 dev_err(dev, "can't enable PCIe ref clock\n");
811 return err;
812 }
813
814 err = nwl_pcie_bridge_init(pcie);
815 if (err) {
816 dev_err(dev, "HW Initialization failed\n");
817 goto err_clk;
818 }
819
820 err = nwl_pcie_init_irq_domain(pcie);
821 if (err) {
822 dev_err(dev, "Failed creating IRQ Domain\n");
823 goto err_clk;
824 }
825
826 bridge->sysdata = pcie;
827 bridge->ops = &nwl_pcie_ops;
828
829 if (IS_ENABLED(CONFIG_PCI_MSI)) {
830 err = nwl_pcie_enable_msi(pcie);
831 if (err < 0) {
832 dev_err(dev, "failed to enable MSI support: %d\n", err);
833 goto err_clk;
834 }
835 }
836
837 err = pci_host_probe(bridge);
838 if (!err)
839 return 0;
840
841 err_clk:
842 clk_disable_unprepare(pcie->clk);
843 return err;
844 }
845
nwl_pcie_remove(struct platform_device * pdev)846 static void nwl_pcie_remove(struct platform_device *pdev)
847 {
848 struct nwl_pcie *pcie = platform_get_drvdata(pdev);
849
850 clk_disable_unprepare(pcie->clk);
851 }
852
853 static struct platform_driver nwl_pcie_driver = {
854 .driver = {
855 .name = "nwl-pcie",
856 .suppress_bind_attrs = true,
857 .of_match_table = nwl_pcie_of_match,
858 },
859 .probe = nwl_pcie_probe,
860 .remove_new = nwl_pcie_remove,
861 };
862 builtin_platform_driver(nwl_pcie_driver);
863