1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * NVM Express device driver
4 * Copyright (c) 2011-2014, Intel Corporation.
5 */
6
7 #include <linux/acpi.h>
8 #include <linux/async.h>
9 #include <linux/blkdev.h>
10 #include <linux/blk-mq.h>
11 #include <linux/blk-mq-pci.h>
12 #include <linux/blk-integrity.h>
13 #include <linux/dmi.h>
14 #include <linux/init.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/kstrtox.h>
18 #include <linux/memremap.h>
19 #include <linux/mm.h>
20 #include <linux/module.h>
21 #include <linux/mutex.h>
22 #include <linux/once.h>
23 #include <linux/pci.h>
24 #include <linux/suspend.h>
25 #include <linux/t10-pi.h>
26 #include <linux/types.h>
27 #include <linux/io-64-nonatomic-lo-hi.h>
28 #include <linux/io-64-nonatomic-hi-lo.h>
29 #include <linux/sed-opal.h>
30 #include <linux/pci-p2pdma.h>
31
32 #include "trace.h"
33 #include "nvme.h"
34
35 #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
36 #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
37
38 #define SGES_PER_PAGE (NVME_CTRL_PAGE_SIZE / sizeof(struct nvme_sgl_desc))
39
40 /*
41 * These can be higher, but we need to ensure that any command doesn't
42 * require an sg allocation that needs more than a page of data.
43 */
44 #define NVME_MAX_KB_SZ 8192
45 #define NVME_MAX_SEGS 128
46 #define NVME_MAX_NR_ALLOCATIONS 5
47
48 static int use_threaded_interrupts;
49 module_param(use_threaded_interrupts, int, 0444);
50
51 static bool use_cmb_sqes = true;
52 module_param(use_cmb_sqes, bool, 0444);
53 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
54
55 static unsigned int max_host_mem_size_mb = 128;
56 module_param(max_host_mem_size_mb, uint, 0444);
57 MODULE_PARM_DESC(max_host_mem_size_mb,
58 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
59
60 static unsigned int sgl_threshold = SZ_32K;
61 module_param(sgl_threshold, uint, 0644);
62 MODULE_PARM_DESC(sgl_threshold,
63 "Use SGLs when average request segment size is larger or equal to "
64 "this size. Use 0 to disable SGLs.");
65
66 #define NVME_PCI_MIN_QUEUE_SIZE 2
67 #define NVME_PCI_MAX_QUEUE_SIZE 4095
68 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
69 static const struct kernel_param_ops io_queue_depth_ops = {
70 .set = io_queue_depth_set,
71 .get = param_get_uint,
72 };
73
74 static unsigned int io_queue_depth = 1024;
75 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
76 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096");
77
io_queue_count_set(const char * val,const struct kernel_param * kp)78 static int io_queue_count_set(const char *val, const struct kernel_param *kp)
79 {
80 unsigned int n;
81 int ret;
82
83 ret = kstrtouint(val, 10, &n);
84 if (ret != 0 || n > num_possible_cpus())
85 return -EINVAL;
86 return param_set_uint(val, kp);
87 }
88
89 static const struct kernel_param_ops io_queue_count_ops = {
90 .set = io_queue_count_set,
91 .get = param_get_uint,
92 };
93
94 static unsigned int write_queues;
95 module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
96 MODULE_PARM_DESC(write_queues,
97 "Number of queues to use for writes. If not set, reads and writes "
98 "will share a queue set.");
99
100 static unsigned int poll_queues;
101 module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
102 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
103
104 static bool noacpi;
105 module_param(noacpi, bool, 0444);
106 MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
107
108 struct nvme_dev;
109 struct nvme_queue;
110
111 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
112 static void nvme_delete_io_queues(struct nvme_dev *dev);
113 static void nvme_update_attrs(struct nvme_dev *dev);
114
115 /*
116 * Represents an NVM Express device. Each nvme_dev is a PCI function.
117 */
118 struct nvme_dev {
119 struct nvme_queue *queues;
120 struct blk_mq_tag_set tagset;
121 struct blk_mq_tag_set admin_tagset;
122 u32 __iomem *dbs;
123 struct device *dev;
124 struct dma_pool *prp_page_pool;
125 struct dma_pool *prp_small_pool;
126 unsigned online_queues;
127 unsigned max_qid;
128 unsigned io_queues[HCTX_MAX_TYPES];
129 unsigned int num_vecs;
130 u32 q_depth;
131 int io_sqes;
132 u32 db_stride;
133 void __iomem *bar;
134 unsigned long bar_mapped_size;
135 struct mutex shutdown_lock;
136 bool subsystem;
137 u64 cmb_size;
138 bool cmb_use_sqes;
139 u32 cmbsz;
140 u32 cmbloc;
141 struct nvme_ctrl ctrl;
142 u32 last_ps;
143 bool hmb;
144
145 mempool_t *iod_mempool;
146
147 /* shadow doorbell buffer support: */
148 __le32 *dbbuf_dbs;
149 dma_addr_t dbbuf_dbs_dma_addr;
150 __le32 *dbbuf_eis;
151 dma_addr_t dbbuf_eis_dma_addr;
152
153 /* host memory buffer support: */
154 u64 host_mem_size;
155 u32 nr_host_mem_descs;
156 dma_addr_t host_mem_descs_dma;
157 struct nvme_host_mem_buf_desc *host_mem_descs;
158 void **host_mem_desc_bufs;
159 unsigned int nr_allocated_queues;
160 unsigned int nr_write_queues;
161 unsigned int nr_poll_queues;
162 };
163
io_queue_depth_set(const char * val,const struct kernel_param * kp)164 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
165 {
166 return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE,
167 NVME_PCI_MAX_QUEUE_SIZE);
168 }
169
sq_idx(unsigned int qid,u32 stride)170 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
171 {
172 return qid * 2 * stride;
173 }
174
cq_idx(unsigned int qid,u32 stride)175 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
176 {
177 return (qid * 2 + 1) * stride;
178 }
179
to_nvme_dev(struct nvme_ctrl * ctrl)180 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
181 {
182 return container_of(ctrl, struct nvme_dev, ctrl);
183 }
184
185 /*
186 * An NVM Express queue. Each device has at least two (one for admin
187 * commands and one for I/O commands).
188 */
189 struct nvme_queue {
190 struct nvme_dev *dev;
191 spinlock_t sq_lock;
192 void *sq_cmds;
193 /* only used for poll queues: */
194 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
195 struct nvme_completion *cqes;
196 dma_addr_t sq_dma_addr;
197 dma_addr_t cq_dma_addr;
198 u32 __iomem *q_db;
199 u32 q_depth;
200 u16 cq_vector;
201 u16 sq_tail;
202 u16 last_sq_tail;
203 u16 cq_head;
204 u16 qid;
205 u8 cq_phase;
206 u8 sqes;
207 unsigned long flags;
208 #define NVMEQ_ENABLED 0
209 #define NVMEQ_SQ_CMB 1
210 #define NVMEQ_DELETE_ERROR 2
211 #define NVMEQ_POLLED 3
212 __le32 *dbbuf_sq_db;
213 __le32 *dbbuf_cq_db;
214 __le32 *dbbuf_sq_ei;
215 __le32 *dbbuf_cq_ei;
216 struct completion delete_done;
217 };
218
219 union nvme_descriptor {
220 struct nvme_sgl_desc *sg_list;
221 __le64 *prp_list;
222 };
223
224 /*
225 * The nvme_iod describes the data in an I/O.
226 *
227 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
228 * to the actual struct scatterlist.
229 */
230 struct nvme_iod {
231 struct nvme_request req;
232 struct nvme_command cmd;
233 bool aborted;
234 s8 nr_allocations; /* PRP list pool allocations. 0 means small
235 pool in use */
236 unsigned int dma_len; /* length of single DMA segment mapping */
237 dma_addr_t first_dma;
238 dma_addr_t meta_dma;
239 struct sg_table sgt;
240 union nvme_descriptor list[NVME_MAX_NR_ALLOCATIONS];
241 };
242
nvme_dbbuf_size(struct nvme_dev * dev)243 static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
244 {
245 return dev->nr_allocated_queues * 8 * dev->db_stride;
246 }
247
nvme_dbbuf_dma_alloc(struct nvme_dev * dev)248 static void nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
249 {
250 unsigned int mem_size = nvme_dbbuf_size(dev);
251
252 if (!(dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP))
253 return;
254
255 if (dev->dbbuf_dbs) {
256 /*
257 * Clear the dbbuf memory so the driver doesn't observe stale
258 * values from the previous instantiation.
259 */
260 memset(dev->dbbuf_dbs, 0, mem_size);
261 memset(dev->dbbuf_eis, 0, mem_size);
262 return;
263 }
264
265 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
266 &dev->dbbuf_dbs_dma_addr,
267 GFP_KERNEL);
268 if (!dev->dbbuf_dbs)
269 goto fail;
270 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
271 &dev->dbbuf_eis_dma_addr,
272 GFP_KERNEL);
273 if (!dev->dbbuf_eis)
274 goto fail_free_dbbuf_dbs;
275 return;
276
277 fail_free_dbbuf_dbs:
278 dma_free_coherent(dev->dev, mem_size, dev->dbbuf_dbs,
279 dev->dbbuf_dbs_dma_addr);
280 dev->dbbuf_dbs = NULL;
281 fail:
282 dev_warn(dev->dev, "unable to allocate dma for dbbuf\n");
283 }
284
nvme_dbbuf_dma_free(struct nvme_dev * dev)285 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
286 {
287 unsigned int mem_size = nvme_dbbuf_size(dev);
288
289 if (dev->dbbuf_dbs) {
290 dma_free_coherent(dev->dev, mem_size,
291 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
292 dev->dbbuf_dbs = NULL;
293 }
294 if (dev->dbbuf_eis) {
295 dma_free_coherent(dev->dev, mem_size,
296 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
297 dev->dbbuf_eis = NULL;
298 }
299 }
300
nvme_dbbuf_init(struct nvme_dev * dev,struct nvme_queue * nvmeq,int qid)301 static void nvme_dbbuf_init(struct nvme_dev *dev,
302 struct nvme_queue *nvmeq, int qid)
303 {
304 if (!dev->dbbuf_dbs || !qid)
305 return;
306
307 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
308 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
309 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
310 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
311 }
312
nvme_dbbuf_free(struct nvme_queue * nvmeq)313 static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
314 {
315 if (!nvmeq->qid)
316 return;
317
318 nvmeq->dbbuf_sq_db = NULL;
319 nvmeq->dbbuf_cq_db = NULL;
320 nvmeq->dbbuf_sq_ei = NULL;
321 nvmeq->dbbuf_cq_ei = NULL;
322 }
323
nvme_dbbuf_set(struct nvme_dev * dev)324 static void nvme_dbbuf_set(struct nvme_dev *dev)
325 {
326 struct nvme_command c = { };
327 unsigned int i;
328
329 if (!dev->dbbuf_dbs)
330 return;
331
332 c.dbbuf.opcode = nvme_admin_dbbuf;
333 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
334 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
335
336 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
337 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
338 /* Free memory and continue on */
339 nvme_dbbuf_dma_free(dev);
340
341 for (i = 1; i <= dev->online_queues; i++)
342 nvme_dbbuf_free(&dev->queues[i]);
343 }
344 }
345
nvme_dbbuf_need_event(u16 event_idx,u16 new_idx,u16 old)346 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
347 {
348 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
349 }
350
351 /* Update dbbuf and return true if an MMIO is required */
nvme_dbbuf_update_and_check_event(u16 value,__le32 * dbbuf_db,volatile __le32 * dbbuf_ei)352 static bool nvme_dbbuf_update_and_check_event(u16 value, __le32 *dbbuf_db,
353 volatile __le32 *dbbuf_ei)
354 {
355 if (dbbuf_db) {
356 u16 old_value, event_idx;
357
358 /*
359 * Ensure that the queue is written before updating
360 * the doorbell in memory
361 */
362 wmb();
363
364 old_value = le32_to_cpu(*dbbuf_db);
365 *dbbuf_db = cpu_to_le32(value);
366
367 /*
368 * Ensure that the doorbell is updated before reading the event
369 * index from memory. The controller needs to provide similar
370 * ordering to ensure the envent index is updated before reading
371 * the doorbell.
372 */
373 mb();
374
375 event_idx = le32_to_cpu(*dbbuf_ei);
376 if (!nvme_dbbuf_need_event(event_idx, value, old_value))
377 return false;
378 }
379
380 return true;
381 }
382
383 /*
384 * Will slightly overestimate the number of pages needed. This is OK
385 * as it only leads to a small amount of wasted memory for the lifetime of
386 * the I/O.
387 */
nvme_pci_npages_prp(void)388 static int nvme_pci_npages_prp(void)
389 {
390 unsigned max_bytes = (NVME_MAX_KB_SZ * 1024) + NVME_CTRL_PAGE_SIZE;
391 unsigned nprps = DIV_ROUND_UP(max_bytes, NVME_CTRL_PAGE_SIZE);
392 return DIV_ROUND_UP(8 * nprps, NVME_CTRL_PAGE_SIZE - 8);
393 }
394
nvme_admin_init_hctx(struct blk_mq_hw_ctx * hctx,void * data,unsigned int hctx_idx)395 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
396 unsigned int hctx_idx)
397 {
398 struct nvme_dev *dev = to_nvme_dev(data);
399 struct nvme_queue *nvmeq = &dev->queues[0];
400
401 WARN_ON(hctx_idx != 0);
402 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
403
404 hctx->driver_data = nvmeq;
405 return 0;
406 }
407
nvme_init_hctx(struct blk_mq_hw_ctx * hctx,void * data,unsigned int hctx_idx)408 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
409 unsigned int hctx_idx)
410 {
411 struct nvme_dev *dev = to_nvme_dev(data);
412 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
413
414 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
415 hctx->driver_data = nvmeq;
416 return 0;
417 }
418
nvme_pci_init_request(struct blk_mq_tag_set * set,struct request * req,unsigned int hctx_idx,unsigned int numa_node)419 static int nvme_pci_init_request(struct blk_mq_tag_set *set,
420 struct request *req, unsigned int hctx_idx,
421 unsigned int numa_node)
422 {
423 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
424
425 nvme_req(req)->ctrl = set->driver_data;
426 nvme_req(req)->cmd = &iod->cmd;
427 return 0;
428 }
429
queue_irq_offset(struct nvme_dev * dev)430 static int queue_irq_offset(struct nvme_dev *dev)
431 {
432 /* if we have more than 1 vec, admin queue offsets us by 1 */
433 if (dev->num_vecs > 1)
434 return 1;
435
436 return 0;
437 }
438
nvme_pci_map_queues(struct blk_mq_tag_set * set)439 static void nvme_pci_map_queues(struct blk_mq_tag_set *set)
440 {
441 struct nvme_dev *dev = to_nvme_dev(set->driver_data);
442 int i, qoff, offset;
443
444 offset = queue_irq_offset(dev);
445 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
446 struct blk_mq_queue_map *map = &set->map[i];
447
448 map->nr_queues = dev->io_queues[i];
449 if (!map->nr_queues) {
450 BUG_ON(i == HCTX_TYPE_DEFAULT);
451 continue;
452 }
453
454 /*
455 * The poll queue(s) doesn't have an IRQ (and hence IRQ
456 * affinity), so use the regular blk-mq cpu mapping
457 */
458 map->queue_offset = qoff;
459 if (i != HCTX_TYPE_POLL && offset)
460 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
461 else
462 blk_mq_map_queues(map);
463 qoff += map->nr_queues;
464 offset += map->nr_queues;
465 }
466 }
467
468 /*
469 * Write sq tail if we are asked to, or if the next command would wrap.
470 */
nvme_write_sq_db(struct nvme_queue * nvmeq,bool write_sq)471 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
472 {
473 if (!write_sq) {
474 u16 next_tail = nvmeq->sq_tail + 1;
475
476 if (next_tail == nvmeq->q_depth)
477 next_tail = 0;
478 if (next_tail != nvmeq->last_sq_tail)
479 return;
480 }
481
482 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
483 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
484 writel(nvmeq->sq_tail, nvmeq->q_db);
485 nvmeq->last_sq_tail = nvmeq->sq_tail;
486 }
487
nvme_sq_copy_cmd(struct nvme_queue * nvmeq,struct nvme_command * cmd)488 static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq,
489 struct nvme_command *cmd)
490 {
491 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
492 absolute_pointer(cmd), sizeof(*cmd));
493 if (++nvmeq->sq_tail == nvmeq->q_depth)
494 nvmeq->sq_tail = 0;
495 }
496
nvme_commit_rqs(struct blk_mq_hw_ctx * hctx)497 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
498 {
499 struct nvme_queue *nvmeq = hctx->driver_data;
500
501 spin_lock(&nvmeq->sq_lock);
502 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
503 nvme_write_sq_db(nvmeq, true);
504 spin_unlock(&nvmeq->sq_lock);
505 }
506
nvme_pci_use_sgls(struct nvme_dev * dev,struct request * req,int nseg)507 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req,
508 int nseg)
509 {
510 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
511 unsigned int avg_seg_size;
512
513 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
514
515 if (!nvme_ctrl_sgl_supported(&dev->ctrl))
516 return false;
517 if (!nvmeq->qid)
518 return false;
519 if (!sgl_threshold || avg_seg_size < sgl_threshold)
520 return false;
521 return true;
522 }
523
nvme_free_prps(struct nvme_dev * dev,struct request * req)524 static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
525 {
526 const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
527 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
528 dma_addr_t dma_addr = iod->first_dma;
529 int i;
530
531 for (i = 0; i < iod->nr_allocations; i++) {
532 __le64 *prp_list = iod->list[i].prp_list;
533 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
534
535 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
536 dma_addr = next_dma_addr;
537 }
538 }
539
nvme_unmap_data(struct nvme_dev * dev,struct request * req)540 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
541 {
542 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
543
544 if (iod->dma_len) {
545 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
546 rq_dma_dir(req));
547 return;
548 }
549
550 WARN_ON_ONCE(!iod->sgt.nents);
551
552 dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0);
553
554 if (iod->nr_allocations == 0)
555 dma_pool_free(dev->prp_small_pool, iod->list[0].sg_list,
556 iod->first_dma);
557 else if (iod->nr_allocations == 1)
558 dma_pool_free(dev->prp_page_pool, iod->list[0].sg_list,
559 iod->first_dma);
560 else
561 nvme_free_prps(dev, req);
562 mempool_free(iod->sgt.sgl, dev->iod_mempool);
563 }
564
nvme_print_sgl(struct scatterlist * sgl,int nents)565 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
566 {
567 int i;
568 struct scatterlist *sg;
569
570 for_each_sg(sgl, sg, nents, i) {
571 dma_addr_t phys = sg_phys(sg);
572 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
573 "dma_address:%pad dma_length:%d\n",
574 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
575 sg_dma_len(sg));
576 }
577 }
578
nvme_pci_setup_prps(struct nvme_dev * dev,struct request * req,struct nvme_rw_command * cmnd)579 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
580 struct request *req, struct nvme_rw_command *cmnd)
581 {
582 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
583 struct dma_pool *pool;
584 int length = blk_rq_payload_bytes(req);
585 struct scatterlist *sg = iod->sgt.sgl;
586 int dma_len = sg_dma_len(sg);
587 u64 dma_addr = sg_dma_address(sg);
588 int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
589 __le64 *prp_list;
590 dma_addr_t prp_dma;
591 int nprps, i;
592
593 length -= (NVME_CTRL_PAGE_SIZE - offset);
594 if (length <= 0) {
595 iod->first_dma = 0;
596 goto done;
597 }
598
599 dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
600 if (dma_len) {
601 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
602 } else {
603 sg = sg_next(sg);
604 dma_addr = sg_dma_address(sg);
605 dma_len = sg_dma_len(sg);
606 }
607
608 if (length <= NVME_CTRL_PAGE_SIZE) {
609 iod->first_dma = dma_addr;
610 goto done;
611 }
612
613 nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
614 if (nprps <= (256 / 8)) {
615 pool = dev->prp_small_pool;
616 iod->nr_allocations = 0;
617 } else {
618 pool = dev->prp_page_pool;
619 iod->nr_allocations = 1;
620 }
621
622 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
623 if (!prp_list) {
624 iod->nr_allocations = -1;
625 return BLK_STS_RESOURCE;
626 }
627 iod->list[0].prp_list = prp_list;
628 iod->first_dma = prp_dma;
629 i = 0;
630 for (;;) {
631 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
632 __le64 *old_prp_list = prp_list;
633 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
634 if (!prp_list)
635 goto free_prps;
636 iod->list[iod->nr_allocations++].prp_list = prp_list;
637 prp_list[0] = old_prp_list[i - 1];
638 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
639 i = 1;
640 }
641 prp_list[i++] = cpu_to_le64(dma_addr);
642 dma_len -= NVME_CTRL_PAGE_SIZE;
643 dma_addr += NVME_CTRL_PAGE_SIZE;
644 length -= NVME_CTRL_PAGE_SIZE;
645 if (length <= 0)
646 break;
647 if (dma_len > 0)
648 continue;
649 if (unlikely(dma_len < 0))
650 goto bad_sgl;
651 sg = sg_next(sg);
652 dma_addr = sg_dma_address(sg);
653 dma_len = sg_dma_len(sg);
654 }
655 done:
656 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sgt.sgl));
657 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
658 return BLK_STS_OK;
659 free_prps:
660 nvme_free_prps(dev, req);
661 return BLK_STS_RESOURCE;
662 bad_sgl:
663 WARN(DO_ONCE(nvme_print_sgl, iod->sgt.sgl, iod->sgt.nents),
664 "Invalid SGL for payload:%d nents:%d\n",
665 blk_rq_payload_bytes(req), iod->sgt.nents);
666 return BLK_STS_IOERR;
667 }
668
nvme_pci_sgl_set_data(struct nvme_sgl_desc * sge,struct scatterlist * sg)669 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
670 struct scatterlist *sg)
671 {
672 sge->addr = cpu_to_le64(sg_dma_address(sg));
673 sge->length = cpu_to_le32(sg_dma_len(sg));
674 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
675 }
676
nvme_pci_sgl_set_seg(struct nvme_sgl_desc * sge,dma_addr_t dma_addr,int entries)677 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
678 dma_addr_t dma_addr, int entries)
679 {
680 sge->addr = cpu_to_le64(dma_addr);
681 sge->length = cpu_to_le32(entries * sizeof(*sge));
682 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
683 }
684
nvme_pci_setup_sgls(struct nvme_dev * dev,struct request * req,struct nvme_rw_command * cmd)685 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
686 struct request *req, struct nvme_rw_command *cmd)
687 {
688 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
689 struct dma_pool *pool;
690 struct nvme_sgl_desc *sg_list;
691 struct scatterlist *sg = iod->sgt.sgl;
692 unsigned int entries = iod->sgt.nents;
693 dma_addr_t sgl_dma;
694 int i = 0;
695
696 /* setting the transfer type as SGL */
697 cmd->flags = NVME_CMD_SGL_METABUF;
698
699 if (entries == 1) {
700 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
701 return BLK_STS_OK;
702 }
703
704 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
705 pool = dev->prp_small_pool;
706 iod->nr_allocations = 0;
707 } else {
708 pool = dev->prp_page_pool;
709 iod->nr_allocations = 1;
710 }
711
712 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
713 if (!sg_list) {
714 iod->nr_allocations = -1;
715 return BLK_STS_RESOURCE;
716 }
717
718 iod->list[0].sg_list = sg_list;
719 iod->first_dma = sgl_dma;
720
721 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
722 do {
723 nvme_pci_sgl_set_data(&sg_list[i++], sg);
724 sg = sg_next(sg);
725 } while (--entries > 0);
726
727 return BLK_STS_OK;
728 }
729
nvme_setup_prp_simple(struct nvme_dev * dev,struct request * req,struct nvme_rw_command * cmnd,struct bio_vec * bv)730 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
731 struct request *req, struct nvme_rw_command *cmnd,
732 struct bio_vec *bv)
733 {
734 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
735 unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
736 unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
737
738 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
739 if (dma_mapping_error(dev->dev, iod->first_dma))
740 return BLK_STS_RESOURCE;
741 iod->dma_len = bv->bv_len;
742
743 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
744 if (bv->bv_len > first_prp_len)
745 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
746 else
747 cmnd->dptr.prp2 = 0;
748 return BLK_STS_OK;
749 }
750
nvme_setup_sgl_simple(struct nvme_dev * dev,struct request * req,struct nvme_rw_command * cmnd,struct bio_vec * bv)751 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
752 struct request *req, struct nvme_rw_command *cmnd,
753 struct bio_vec *bv)
754 {
755 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
756
757 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
758 if (dma_mapping_error(dev->dev, iod->first_dma))
759 return BLK_STS_RESOURCE;
760 iod->dma_len = bv->bv_len;
761
762 cmnd->flags = NVME_CMD_SGL_METABUF;
763 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
764 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
765 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
766 return BLK_STS_OK;
767 }
768
nvme_map_data(struct nvme_dev * dev,struct request * req,struct nvme_command * cmnd)769 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
770 struct nvme_command *cmnd)
771 {
772 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
773 blk_status_t ret = BLK_STS_RESOURCE;
774 int rc;
775
776 if (blk_rq_nr_phys_segments(req) == 1) {
777 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
778 struct bio_vec bv = req_bvec(req);
779
780 if (!is_pci_p2pdma_page(bv.bv_page)) {
781 if ((bv.bv_offset & (NVME_CTRL_PAGE_SIZE - 1)) +
782 bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
783 return nvme_setup_prp_simple(dev, req,
784 &cmnd->rw, &bv);
785
786 if (nvmeq->qid && sgl_threshold &&
787 nvme_ctrl_sgl_supported(&dev->ctrl))
788 return nvme_setup_sgl_simple(dev, req,
789 &cmnd->rw, &bv);
790 }
791 }
792
793 iod->dma_len = 0;
794 iod->sgt.sgl = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
795 if (!iod->sgt.sgl)
796 return BLK_STS_RESOURCE;
797 sg_init_table(iod->sgt.sgl, blk_rq_nr_phys_segments(req));
798 iod->sgt.orig_nents = blk_rq_map_sg(req->q, req, iod->sgt.sgl);
799 if (!iod->sgt.orig_nents)
800 goto out_free_sg;
801
802 rc = dma_map_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req),
803 DMA_ATTR_NO_WARN);
804 if (rc) {
805 if (rc == -EREMOTEIO)
806 ret = BLK_STS_TARGET;
807 goto out_free_sg;
808 }
809
810 if (nvme_pci_use_sgls(dev, req, iod->sgt.nents))
811 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw);
812 else
813 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
814 if (ret != BLK_STS_OK)
815 goto out_unmap_sg;
816 return BLK_STS_OK;
817
818 out_unmap_sg:
819 dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0);
820 out_free_sg:
821 mempool_free(iod->sgt.sgl, dev->iod_mempool);
822 return ret;
823 }
824
nvme_map_metadata(struct nvme_dev * dev,struct request * req,struct nvme_command * cmnd)825 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
826 struct nvme_command *cmnd)
827 {
828 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
829 struct bio_vec bv = rq_integrity_vec(req);
830
831 iod->meta_dma = dma_map_bvec(dev->dev, &bv, rq_dma_dir(req), 0);
832 if (dma_mapping_error(dev->dev, iod->meta_dma))
833 return BLK_STS_IOERR;
834 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
835 return BLK_STS_OK;
836 }
837
nvme_prep_rq(struct nvme_dev * dev,struct request * req)838 static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req)
839 {
840 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
841 blk_status_t ret;
842
843 iod->aborted = false;
844 iod->nr_allocations = -1;
845 iod->sgt.nents = 0;
846
847 ret = nvme_setup_cmd(req->q->queuedata, req);
848 if (ret)
849 return ret;
850
851 if (blk_rq_nr_phys_segments(req)) {
852 ret = nvme_map_data(dev, req, &iod->cmd);
853 if (ret)
854 goto out_free_cmd;
855 }
856
857 if (blk_integrity_rq(req)) {
858 ret = nvme_map_metadata(dev, req, &iod->cmd);
859 if (ret)
860 goto out_unmap_data;
861 }
862
863 nvme_start_request(req);
864 return BLK_STS_OK;
865 out_unmap_data:
866 if (blk_rq_nr_phys_segments(req))
867 nvme_unmap_data(dev, req);
868 out_free_cmd:
869 nvme_cleanup_cmd(req);
870 return ret;
871 }
872
873 /*
874 * NOTE: ns is NULL when called on the admin queue.
875 */
nvme_queue_rq(struct blk_mq_hw_ctx * hctx,const struct blk_mq_queue_data * bd)876 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
877 const struct blk_mq_queue_data *bd)
878 {
879 struct nvme_queue *nvmeq = hctx->driver_data;
880 struct nvme_dev *dev = nvmeq->dev;
881 struct request *req = bd->rq;
882 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
883 blk_status_t ret;
884
885 /*
886 * We should not need to do this, but we're still using this to
887 * ensure we can drain requests on a dying queue.
888 */
889 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
890 return BLK_STS_IOERR;
891
892 if (unlikely(!nvme_check_ready(&dev->ctrl, req, true)))
893 return nvme_fail_nonready_command(&dev->ctrl, req);
894
895 ret = nvme_prep_rq(dev, req);
896 if (unlikely(ret))
897 return ret;
898 spin_lock(&nvmeq->sq_lock);
899 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
900 nvme_write_sq_db(nvmeq, bd->last);
901 spin_unlock(&nvmeq->sq_lock);
902 return BLK_STS_OK;
903 }
904
nvme_submit_cmds(struct nvme_queue * nvmeq,struct request ** rqlist)905 static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist)
906 {
907 spin_lock(&nvmeq->sq_lock);
908 while (!rq_list_empty(*rqlist)) {
909 struct request *req = rq_list_pop(rqlist);
910 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
911
912 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
913 }
914 nvme_write_sq_db(nvmeq, true);
915 spin_unlock(&nvmeq->sq_lock);
916 }
917
nvme_prep_rq_batch(struct nvme_queue * nvmeq,struct request * req)918 static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req)
919 {
920 /*
921 * We should not need to do this, but we're still using this to
922 * ensure we can drain requests on a dying queue.
923 */
924 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
925 return false;
926 if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true)))
927 return false;
928
929 req->mq_hctx->tags->rqs[req->tag] = req;
930 return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK;
931 }
932
nvme_queue_rqs(struct request ** rqlist)933 static void nvme_queue_rqs(struct request **rqlist)
934 {
935 struct request *req, *next, *prev = NULL;
936 struct request *requeue_list = NULL;
937
938 rq_list_for_each_safe(rqlist, req, next) {
939 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
940
941 if (!nvme_prep_rq_batch(nvmeq, req)) {
942 /* detach 'req' and add to remainder list */
943 rq_list_move(rqlist, &requeue_list, req, prev);
944
945 req = prev;
946 if (!req)
947 continue;
948 }
949
950 if (!next || req->mq_hctx != next->mq_hctx) {
951 /* detach rest of list, and submit */
952 req->rq_next = NULL;
953 nvme_submit_cmds(nvmeq, rqlist);
954 *rqlist = next;
955 prev = NULL;
956 } else
957 prev = req;
958 }
959
960 *rqlist = requeue_list;
961 }
962
nvme_pci_unmap_rq(struct request * req)963 static __always_inline void nvme_pci_unmap_rq(struct request *req)
964 {
965 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
966 struct nvme_dev *dev = nvmeq->dev;
967
968 if (blk_integrity_rq(req)) {
969 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
970
971 dma_unmap_page(dev->dev, iod->meta_dma,
972 rq_integrity_vec(req).bv_len, rq_dma_dir(req));
973 }
974
975 if (blk_rq_nr_phys_segments(req))
976 nvme_unmap_data(dev, req);
977 }
978
nvme_pci_complete_rq(struct request * req)979 static void nvme_pci_complete_rq(struct request *req)
980 {
981 nvme_pci_unmap_rq(req);
982 nvme_complete_rq(req);
983 }
984
nvme_pci_complete_batch(struct io_comp_batch * iob)985 static void nvme_pci_complete_batch(struct io_comp_batch *iob)
986 {
987 nvme_complete_batch(iob, nvme_pci_unmap_rq);
988 }
989
990 /* We read the CQE phase first to check if the rest of the entry is valid */
nvme_cqe_pending(struct nvme_queue * nvmeq)991 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
992 {
993 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
994
995 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
996 }
997
nvme_ring_cq_doorbell(struct nvme_queue * nvmeq)998 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
999 {
1000 u16 head = nvmeq->cq_head;
1001
1002 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
1003 nvmeq->dbbuf_cq_ei))
1004 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
1005 }
1006
nvme_queue_tagset(struct nvme_queue * nvmeq)1007 static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
1008 {
1009 if (!nvmeq->qid)
1010 return nvmeq->dev->admin_tagset.tags[0];
1011 return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
1012 }
1013
nvme_handle_cqe(struct nvme_queue * nvmeq,struct io_comp_batch * iob,u16 idx)1014 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
1015 struct io_comp_batch *iob, u16 idx)
1016 {
1017 struct nvme_completion *cqe = &nvmeq->cqes[idx];
1018 __u16 command_id = READ_ONCE(cqe->command_id);
1019 struct request *req;
1020
1021 /*
1022 * AEN requests are special as they don't time out and can
1023 * survive any kind of queue freeze and often don't respond to
1024 * aborts. We don't even bother to allocate a struct request
1025 * for them but rather special case them here.
1026 */
1027 if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
1028 nvme_complete_async_event(&nvmeq->dev->ctrl,
1029 cqe->status, &cqe->result);
1030 return;
1031 }
1032
1033 req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id);
1034 if (unlikely(!req)) {
1035 dev_warn(nvmeq->dev->ctrl.device,
1036 "invalid id %d completed on queue %d\n",
1037 command_id, le16_to_cpu(cqe->sq_id));
1038 return;
1039 }
1040
1041 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
1042 if (!nvme_try_complete_req(req, cqe->status, cqe->result) &&
1043 !blk_mq_add_to_batch(req, iob, nvme_req(req)->status,
1044 nvme_pci_complete_batch))
1045 nvme_pci_complete_rq(req);
1046 }
1047
nvme_update_cq_head(struct nvme_queue * nvmeq)1048 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1049 {
1050 u32 tmp = nvmeq->cq_head + 1;
1051
1052 if (tmp == nvmeq->q_depth) {
1053 nvmeq->cq_head = 0;
1054 nvmeq->cq_phase ^= 1;
1055 } else {
1056 nvmeq->cq_head = tmp;
1057 }
1058 }
1059
nvme_poll_cq(struct nvme_queue * nvmeq,struct io_comp_batch * iob)1060 static inline int nvme_poll_cq(struct nvme_queue *nvmeq,
1061 struct io_comp_batch *iob)
1062 {
1063 int found = 0;
1064
1065 while (nvme_cqe_pending(nvmeq)) {
1066 found++;
1067 /*
1068 * load-load control dependency between phase and the rest of
1069 * the cqe requires a full read memory barrier
1070 */
1071 dma_rmb();
1072 nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head);
1073 nvme_update_cq_head(nvmeq);
1074 }
1075
1076 if (found)
1077 nvme_ring_cq_doorbell(nvmeq);
1078 return found;
1079 }
1080
nvme_irq(int irq,void * data)1081 static irqreturn_t nvme_irq(int irq, void *data)
1082 {
1083 struct nvme_queue *nvmeq = data;
1084 DEFINE_IO_COMP_BATCH(iob);
1085
1086 if (nvme_poll_cq(nvmeq, &iob)) {
1087 if (!rq_list_empty(iob.req_list))
1088 nvme_pci_complete_batch(&iob);
1089 return IRQ_HANDLED;
1090 }
1091 return IRQ_NONE;
1092 }
1093
nvme_irq_check(int irq,void * data)1094 static irqreturn_t nvme_irq_check(int irq, void *data)
1095 {
1096 struct nvme_queue *nvmeq = data;
1097
1098 if (nvme_cqe_pending(nvmeq))
1099 return IRQ_WAKE_THREAD;
1100 return IRQ_NONE;
1101 }
1102
1103 /*
1104 * Poll for completions for any interrupt driven queue
1105 * Can be called from any context.
1106 */
nvme_poll_irqdisable(struct nvme_queue * nvmeq)1107 static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
1108 {
1109 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1110
1111 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
1112
1113 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1114 nvme_poll_cq(nvmeq, NULL);
1115 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1116 }
1117
nvme_poll(struct blk_mq_hw_ctx * hctx,struct io_comp_batch * iob)1118 static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob)
1119 {
1120 struct nvme_queue *nvmeq = hctx->driver_data;
1121 bool found;
1122
1123 if (!nvme_cqe_pending(nvmeq))
1124 return 0;
1125
1126 spin_lock(&nvmeq->cq_poll_lock);
1127 found = nvme_poll_cq(nvmeq, iob);
1128 spin_unlock(&nvmeq->cq_poll_lock);
1129
1130 return found;
1131 }
1132
nvme_pci_submit_async_event(struct nvme_ctrl * ctrl)1133 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1134 {
1135 struct nvme_dev *dev = to_nvme_dev(ctrl);
1136 struct nvme_queue *nvmeq = &dev->queues[0];
1137 struct nvme_command c = { };
1138
1139 c.common.opcode = nvme_admin_async_event;
1140 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1141
1142 spin_lock(&nvmeq->sq_lock);
1143 nvme_sq_copy_cmd(nvmeq, &c);
1144 nvme_write_sq_db(nvmeq, true);
1145 spin_unlock(&nvmeq->sq_lock);
1146 }
1147
adapter_delete_queue(struct nvme_dev * dev,u8 opcode,u16 id)1148 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1149 {
1150 struct nvme_command c = { };
1151
1152 c.delete_queue.opcode = opcode;
1153 c.delete_queue.qid = cpu_to_le16(id);
1154
1155 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1156 }
1157
adapter_alloc_cq(struct nvme_dev * dev,u16 qid,struct nvme_queue * nvmeq,s16 vector)1158 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1159 struct nvme_queue *nvmeq, s16 vector)
1160 {
1161 struct nvme_command c = { };
1162 int flags = NVME_QUEUE_PHYS_CONTIG;
1163
1164 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
1165 flags |= NVME_CQ_IRQ_ENABLED;
1166
1167 /*
1168 * Note: we (ab)use the fact that the prp fields survive if no data
1169 * is attached to the request.
1170 */
1171 c.create_cq.opcode = nvme_admin_create_cq;
1172 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1173 c.create_cq.cqid = cpu_to_le16(qid);
1174 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1175 c.create_cq.cq_flags = cpu_to_le16(flags);
1176 c.create_cq.irq_vector = cpu_to_le16(vector);
1177
1178 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1179 }
1180
adapter_alloc_sq(struct nvme_dev * dev,u16 qid,struct nvme_queue * nvmeq)1181 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1182 struct nvme_queue *nvmeq)
1183 {
1184 struct nvme_ctrl *ctrl = &dev->ctrl;
1185 struct nvme_command c = { };
1186 int flags = NVME_QUEUE_PHYS_CONTIG;
1187
1188 /*
1189 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1190 * set. Since URGENT priority is zeroes, it makes all queues
1191 * URGENT.
1192 */
1193 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1194 flags |= NVME_SQ_PRIO_MEDIUM;
1195
1196 /*
1197 * Note: we (ab)use the fact that the prp fields survive if no data
1198 * is attached to the request.
1199 */
1200 c.create_sq.opcode = nvme_admin_create_sq;
1201 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1202 c.create_sq.sqid = cpu_to_le16(qid);
1203 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1204 c.create_sq.sq_flags = cpu_to_le16(flags);
1205 c.create_sq.cqid = cpu_to_le16(qid);
1206
1207 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1208 }
1209
adapter_delete_cq(struct nvme_dev * dev,u16 cqid)1210 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1211 {
1212 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1213 }
1214
adapter_delete_sq(struct nvme_dev * dev,u16 sqid)1215 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1216 {
1217 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1218 }
1219
abort_endio(struct request * req,blk_status_t error)1220 static enum rq_end_io_ret abort_endio(struct request *req, blk_status_t error)
1221 {
1222 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1223
1224 dev_warn(nvmeq->dev->ctrl.device,
1225 "Abort status: 0x%x", nvme_req(req)->status);
1226 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1227 blk_mq_free_request(req);
1228 return RQ_END_IO_NONE;
1229 }
1230
nvme_should_reset(struct nvme_dev * dev,u32 csts)1231 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1232 {
1233 /* If true, indicates loss of adapter communication, possibly by a
1234 * NVMe Subsystem reset.
1235 */
1236 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1237
1238 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1239 switch (nvme_ctrl_state(&dev->ctrl)) {
1240 case NVME_CTRL_RESETTING:
1241 case NVME_CTRL_CONNECTING:
1242 return false;
1243 default:
1244 break;
1245 }
1246
1247 /* We shouldn't reset unless the controller is on fatal error state
1248 * _or_ if we lost the communication with it.
1249 */
1250 if (!(csts & NVME_CSTS_CFS) && !nssro)
1251 return false;
1252
1253 return true;
1254 }
1255
nvme_warn_reset(struct nvme_dev * dev,u32 csts)1256 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1257 {
1258 /* Read a config register to help see what died. */
1259 u16 pci_status;
1260 int result;
1261
1262 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1263 &pci_status);
1264 if (result == PCIBIOS_SUCCESSFUL)
1265 dev_warn(dev->ctrl.device,
1266 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1267 csts, pci_status);
1268 else
1269 dev_warn(dev->ctrl.device,
1270 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1271 csts, result);
1272
1273 if (csts != ~0)
1274 return;
1275
1276 dev_warn(dev->ctrl.device,
1277 "Does your device have a faulty power saving mode enabled?\n");
1278 dev_warn(dev->ctrl.device,
1279 "Try \"nvme_core.default_ps_max_latency_us=0 pcie_aspm=off pcie_port_pm=off\" and report a bug\n");
1280 }
1281
nvme_timeout(struct request * req)1282 static enum blk_eh_timer_return nvme_timeout(struct request *req)
1283 {
1284 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1285 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1286 struct nvme_dev *dev = nvmeq->dev;
1287 struct request *abort_req;
1288 struct nvme_command cmd = { };
1289 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1290
1291 if (nvme_state_terminal(&dev->ctrl))
1292 goto disable;
1293
1294 /* If PCI error recovery process is happening, we cannot reset or
1295 * the recovery mechanism will surely fail.
1296 */
1297 mb();
1298 if (pci_channel_offline(to_pci_dev(dev->dev)))
1299 return BLK_EH_RESET_TIMER;
1300
1301 /*
1302 * Reset immediately if the controller is failed
1303 */
1304 if (nvme_should_reset(dev, csts)) {
1305 nvme_warn_reset(dev, csts);
1306 goto disable;
1307 }
1308
1309 /*
1310 * Did we miss an interrupt?
1311 */
1312 if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1313 nvme_poll(req->mq_hctx, NULL);
1314 else
1315 nvme_poll_irqdisable(nvmeq);
1316
1317 if (blk_mq_rq_state(req) != MQ_RQ_IN_FLIGHT) {
1318 dev_warn(dev->ctrl.device,
1319 "I/O %d QID %d timeout, completion polled\n",
1320 req->tag, nvmeq->qid);
1321 return BLK_EH_DONE;
1322 }
1323
1324 /*
1325 * Shutdown immediately if controller times out while starting. The
1326 * reset work will see the pci device disabled when it gets the forced
1327 * cancellation error. All outstanding requests are completed on
1328 * shutdown, so we return BLK_EH_DONE.
1329 */
1330 switch (nvme_ctrl_state(&dev->ctrl)) {
1331 case NVME_CTRL_CONNECTING:
1332 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1333 fallthrough;
1334 case NVME_CTRL_DELETING:
1335 dev_warn_ratelimited(dev->ctrl.device,
1336 "I/O %d QID %d timeout, disable controller\n",
1337 req->tag, nvmeq->qid);
1338 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1339 nvme_dev_disable(dev, true);
1340 return BLK_EH_DONE;
1341 case NVME_CTRL_RESETTING:
1342 return BLK_EH_RESET_TIMER;
1343 default:
1344 break;
1345 }
1346
1347 /*
1348 * Shutdown the controller immediately and schedule a reset if the
1349 * command was already aborted once before and still hasn't been
1350 * returned to the driver, or if this is the admin queue.
1351 */
1352 if (!nvmeq->qid || iod->aborted) {
1353 dev_warn(dev->ctrl.device,
1354 "I/O %d QID %d timeout, reset controller\n",
1355 req->tag, nvmeq->qid);
1356 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1357 goto disable;
1358 }
1359
1360 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1361 atomic_inc(&dev->ctrl.abort_limit);
1362 return BLK_EH_RESET_TIMER;
1363 }
1364 iod->aborted = true;
1365
1366 cmd.abort.opcode = nvme_admin_abort_cmd;
1367 cmd.abort.cid = nvme_cid(req);
1368 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1369
1370 dev_warn(nvmeq->dev->ctrl.device,
1371 "I/O %d (%s) QID %d timeout, aborting\n",
1372 req->tag,
1373 nvme_get_opcode_str(nvme_req(req)->cmd->common.opcode),
1374 nvmeq->qid);
1375
1376 abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd),
1377 BLK_MQ_REQ_NOWAIT);
1378 if (IS_ERR(abort_req)) {
1379 atomic_inc(&dev->ctrl.abort_limit);
1380 return BLK_EH_RESET_TIMER;
1381 }
1382 nvme_init_request(abort_req, &cmd);
1383
1384 abort_req->end_io = abort_endio;
1385 abort_req->end_io_data = NULL;
1386 blk_execute_rq_nowait(abort_req, false);
1387
1388 /*
1389 * The aborted req will be completed on receiving the abort req.
1390 * We enable the timer again. If hit twice, it'll cause a device reset,
1391 * as the device then is in a faulty state.
1392 */
1393 return BLK_EH_RESET_TIMER;
1394
1395 disable:
1396 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING)) {
1397 if (nvme_state_terminal(&dev->ctrl))
1398 nvme_dev_disable(dev, true);
1399 return BLK_EH_DONE;
1400 }
1401
1402 nvme_dev_disable(dev, false);
1403 if (nvme_try_sched_reset(&dev->ctrl))
1404 nvme_unquiesce_io_queues(&dev->ctrl);
1405 return BLK_EH_DONE;
1406 }
1407
nvme_free_queue(struct nvme_queue * nvmeq)1408 static void nvme_free_queue(struct nvme_queue *nvmeq)
1409 {
1410 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
1411 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1412 if (!nvmeq->sq_cmds)
1413 return;
1414
1415 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1416 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
1417 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1418 } else {
1419 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
1420 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1421 }
1422 }
1423
nvme_free_queues(struct nvme_dev * dev,int lowest)1424 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1425 {
1426 int i;
1427
1428 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1429 dev->ctrl.queue_count--;
1430 nvme_free_queue(&dev->queues[i]);
1431 }
1432 }
1433
nvme_suspend_queue(struct nvme_dev * dev,unsigned int qid)1434 static void nvme_suspend_queue(struct nvme_dev *dev, unsigned int qid)
1435 {
1436 struct nvme_queue *nvmeq = &dev->queues[qid];
1437
1438 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
1439 return;
1440
1441 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
1442 mb();
1443
1444 nvmeq->dev->online_queues--;
1445 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1446 nvme_quiesce_admin_queue(&nvmeq->dev->ctrl);
1447 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1448 pci_free_irq(to_pci_dev(dev->dev), nvmeq->cq_vector, nvmeq);
1449 }
1450
nvme_suspend_io_queues(struct nvme_dev * dev)1451 static void nvme_suspend_io_queues(struct nvme_dev *dev)
1452 {
1453 int i;
1454
1455 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1456 nvme_suspend_queue(dev, i);
1457 }
1458
1459 /*
1460 * Called only on a device that has been disabled and after all other threads
1461 * that can check this device's completion queues have synced, except
1462 * nvme_poll(). This is the last chance for the driver to see a natural
1463 * completion before nvme_cancel_request() terminates all incomplete requests.
1464 */
nvme_reap_pending_cqes(struct nvme_dev * dev)1465 static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1466 {
1467 int i;
1468
1469 for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1470 spin_lock(&dev->queues[i].cq_poll_lock);
1471 nvme_poll_cq(&dev->queues[i], NULL);
1472 spin_unlock(&dev->queues[i].cq_poll_lock);
1473 }
1474 }
1475
nvme_cmb_qdepth(struct nvme_dev * dev,int nr_io_queues,int entry_size)1476 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1477 int entry_size)
1478 {
1479 int q_depth = dev->q_depth;
1480 unsigned q_size_aligned = roundup(q_depth * entry_size,
1481 NVME_CTRL_PAGE_SIZE);
1482
1483 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1484 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1485
1486 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
1487 q_depth = div_u64(mem_per_q, entry_size);
1488
1489 /*
1490 * Ensure the reduced q_depth is above some threshold where it
1491 * would be better to map queues in system memory with the
1492 * original depth
1493 */
1494 if (q_depth < 64)
1495 return -ENOMEM;
1496 }
1497
1498 return q_depth;
1499 }
1500
nvme_alloc_sq_cmds(struct nvme_dev * dev,struct nvme_queue * nvmeq,int qid)1501 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1502 int qid)
1503 {
1504 struct pci_dev *pdev = to_pci_dev(dev->dev);
1505
1506 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1507 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
1508 if (nvmeq->sq_cmds) {
1509 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1510 nvmeq->sq_cmds);
1511 if (nvmeq->sq_dma_addr) {
1512 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1513 return 0;
1514 }
1515
1516 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1517 }
1518 }
1519
1520 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
1521 &nvmeq->sq_dma_addr, GFP_KERNEL);
1522 if (!nvmeq->sq_cmds)
1523 return -ENOMEM;
1524 return 0;
1525 }
1526
nvme_alloc_queue(struct nvme_dev * dev,int qid,int depth)1527 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1528 {
1529 struct nvme_queue *nvmeq = &dev->queues[qid];
1530
1531 if (dev->ctrl.queue_count > qid)
1532 return 0;
1533
1534 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
1535 nvmeq->q_depth = depth;
1536 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
1537 &nvmeq->cq_dma_addr, GFP_KERNEL);
1538 if (!nvmeq->cqes)
1539 goto free_nvmeq;
1540
1541 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
1542 goto free_cqdma;
1543
1544 nvmeq->dev = dev;
1545 spin_lock_init(&nvmeq->sq_lock);
1546 spin_lock_init(&nvmeq->cq_poll_lock);
1547 nvmeq->cq_head = 0;
1548 nvmeq->cq_phase = 1;
1549 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1550 nvmeq->qid = qid;
1551 dev->ctrl.queue_count++;
1552
1553 return 0;
1554
1555 free_cqdma:
1556 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1557 nvmeq->cq_dma_addr);
1558 free_nvmeq:
1559 return -ENOMEM;
1560 }
1561
queue_request_irq(struct nvme_queue * nvmeq)1562 static int queue_request_irq(struct nvme_queue *nvmeq)
1563 {
1564 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1565 int nr = nvmeq->dev->ctrl.instance;
1566
1567 if (use_threaded_interrupts) {
1568 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1569 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1570 } else {
1571 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1572 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1573 }
1574 }
1575
nvme_init_queue(struct nvme_queue * nvmeq,u16 qid)1576 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1577 {
1578 struct nvme_dev *dev = nvmeq->dev;
1579
1580 nvmeq->sq_tail = 0;
1581 nvmeq->last_sq_tail = 0;
1582 nvmeq->cq_head = 0;
1583 nvmeq->cq_phase = 1;
1584 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1585 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
1586 nvme_dbbuf_init(dev, nvmeq, qid);
1587 dev->online_queues++;
1588 wmb(); /* ensure the first interrupt sees the initialization */
1589 }
1590
1591 /*
1592 * Try getting shutdown_lock while setting up IO queues.
1593 */
nvme_setup_io_queues_trylock(struct nvme_dev * dev)1594 static int nvme_setup_io_queues_trylock(struct nvme_dev *dev)
1595 {
1596 /*
1597 * Give up if the lock is being held by nvme_dev_disable.
1598 */
1599 if (!mutex_trylock(&dev->shutdown_lock))
1600 return -ENODEV;
1601
1602 /*
1603 * Controller is in wrong state, fail early.
1604 */
1605 if (nvme_ctrl_state(&dev->ctrl) != NVME_CTRL_CONNECTING) {
1606 mutex_unlock(&dev->shutdown_lock);
1607 return -ENODEV;
1608 }
1609
1610 return 0;
1611 }
1612
nvme_create_queue(struct nvme_queue * nvmeq,int qid,bool polled)1613 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
1614 {
1615 struct nvme_dev *dev = nvmeq->dev;
1616 int result;
1617 u16 vector = 0;
1618
1619 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1620
1621 /*
1622 * A queue's vector matches the queue identifier unless the controller
1623 * has only one vector available.
1624 */
1625 if (!polled)
1626 vector = dev->num_vecs == 1 ? 0 : qid;
1627 else
1628 set_bit(NVMEQ_POLLED, &nvmeq->flags);
1629
1630 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1631 if (result)
1632 return result;
1633
1634 result = adapter_alloc_sq(dev, qid, nvmeq);
1635 if (result < 0)
1636 return result;
1637 if (result)
1638 goto release_cq;
1639
1640 nvmeq->cq_vector = vector;
1641
1642 result = nvme_setup_io_queues_trylock(dev);
1643 if (result)
1644 return result;
1645 nvme_init_queue(nvmeq, qid);
1646 if (!polled) {
1647 result = queue_request_irq(nvmeq);
1648 if (result < 0)
1649 goto release_sq;
1650 }
1651
1652 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1653 mutex_unlock(&dev->shutdown_lock);
1654 return result;
1655
1656 release_sq:
1657 dev->online_queues--;
1658 mutex_unlock(&dev->shutdown_lock);
1659 adapter_delete_sq(dev, qid);
1660 release_cq:
1661 adapter_delete_cq(dev, qid);
1662 return result;
1663 }
1664
1665 static const struct blk_mq_ops nvme_mq_admin_ops = {
1666 .queue_rq = nvme_queue_rq,
1667 .complete = nvme_pci_complete_rq,
1668 .init_hctx = nvme_admin_init_hctx,
1669 .init_request = nvme_pci_init_request,
1670 .timeout = nvme_timeout,
1671 };
1672
1673 static const struct blk_mq_ops nvme_mq_ops = {
1674 .queue_rq = nvme_queue_rq,
1675 .queue_rqs = nvme_queue_rqs,
1676 .complete = nvme_pci_complete_rq,
1677 .commit_rqs = nvme_commit_rqs,
1678 .init_hctx = nvme_init_hctx,
1679 .init_request = nvme_pci_init_request,
1680 .map_queues = nvme_pci_map_queues,
1681 .timeout = nvme_timeout,
1682 .poll = nvme_poll,
1683 };
1684
nvme_dev_remove_admin(struct nvme_dev * dev)1685 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1686 {
1687 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1688 /*
1689 * If the controller was reset during removal, it's possible
1690 * user requests may be waiting on a stopped queue. Start the
1691 * queue to flush these to completion.
1692 */
1693 nvme_unquiesce_admin_queue(&dev->ctrl);
1694 nvme_remove_admin_tag_set(&dev->ctrl);
1695 }
1696 }
1697
db_bar_size(struct nvme_dev * dev,unsigned nr_io_queues)1698 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1699 {
1700 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1701 }
1702
nvme_remap_bar(struct nvme_dev * dev,unsigned long size)1703 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1704 {
1705 struct pci_dev *pdev = to_pci_dev(dev->dev);
1706
1707 if (size <= dev->bar_mapped_size)
1708 return 0;
1709 if (size > pci_resource_len(pdev, 0))
1710 return -ENOMEM;
1711 if (dev->bar)
1712 iounmap(dev->bar);
1713 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1714 if (!dev->bar) {
1715 dev->bar_mapped_size = 0;
1716 return -ENOMEM;
1717 }
1718 dev->bar_mapped_size = size;
1719 dev->dbs = dev->bar + NVME_REG_DBS;
1720
1721 return 0;
1722 }
1723
nvme_pci_configure_admin_queue(struct nvme_dev * dev)1724 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1725 {
1726 int result;
1727 u32 aqa;
1728 struct nvme_queue *nvmeq;
1729
1730 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1731 if (result < 0)
1732 return result;
1733
1734 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1735 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1736
1737 if (dev->subsystem &&
1738 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1739 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1740
1741 /*
1742 * If the device has been passed off to us in an enabled state, just
1743 * clear the enabled bit. The spec says we should set the 'shutdown
1744 * notification bits', but doing so may cause the device to complete
1745 * commands to the admin queue ... and we don't know what memory that
1746 * might be pointing at!
1747 */
1748 result = nvme_disable_ctrl(&dev->ctrl, false);
1749 if (result < 0)
1750 return result;
1751
1752 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1753 if (result)
1754 return result;
1755
1756 dev->ctrl.numa_node = dev_to_node(dev->dev);
1757
1758 nvmeq = &dev->queues[0];
1759 aqa = nvmeq->q_depth - 1;
1760 aqa |= aqa << 16;
1761
1762 writel(aqa, dev->bar + NVME_REG_AQA);
1763 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1764 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1765
1766 result = nvme_enable_ctrl(&dev->ctrl);
1767 if (result)
1768 return result;
1769
1770 nvmeq->cq_vector = 0;
1771 nvme_init_queue(nvmeq, 0);
1772 result = queue_request_irq(nvmeq);
1773 if (result) {
1774 dev->online_queues--;
1775 return result;
1776 }
1777
1778 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1779 return result;
1780 }
1781
nvme_create_io_queues(struct nvme_dev * dev)1782 static int nvme_create_io_queues(struct nvme_dev *dev)
1783 {
1784 unsigned i, max, rw_queues;
1785 int ret = 0;
1786
1787 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1788 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1789 ret = -ENOMEM;
1790 break;
1791 }
1792 }
1793
1794 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1795 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1796 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1797 dev->io_queues[HCTX_TYPE_READ];
1798 } else {
1799 rw_queues = max;
1800 }
1801
1802 for (i = dev->online_queues; i <= max; i++) {
1803 bool polled = i > rw_queues;
1804
1805 ret = nvme_create_queue(&dev->queues[i], i, polled);
1806 if (ret)
1807 break;
1808 }
1809
1810 /*
1811 * Ignore failing Create SQ/CQ commands, we can continue with less
1812 * than the desired amount of queues, and even a controller without
1813 * I/O queues can still be used to issue admin commands. This might
1814 * be useful to upgrade a buggy firmware for example.
1815 */
1816 return ret >= 0 ? 0 : ret;
1817 }
1818
nvme_cmb_size_unit(struct nvme_dev * dev)1819 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1820 {
1821 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1822
1823 return 1ULL << (12 + 4 * szu);
1824 }
1825
nvme_cmb_size(struct nvme_dev * dev)1826 static u32 nvme_cmb_size(struct nvme_dev *dev)
1827 {
1828 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1829 }
1830
nvme_map_cmb(struct nvme_dev * dev)1831 static void nvme_map_cmb(struct nvme_dev *dev)
1832 {
1833 u64 size, offset;
1834 resource_size_t bar_size;
1835 struct pci_dev *pdev = to_pci_dev(dev->dev);
1836 int bar;
1837
1838 if (dev->cmb_size)
1839 return;
1840
1841 if (NVME_CAP_CMBS(dev->ctrl.cap))
1842 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1843
1844 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1845 if (!dev->cmbsz)
1846 return;
1847 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1848
1849 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1850 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1851 bar = NVME_CMB_BIR(dev->cmbloc);
1852 bar_size = pci_resource_len(pdev, bar);
1853
1854 if (offset > bar_size)
1855 return;
1856
1857 /*
1858 * Tell the controller about the host side address mapping the CMB,
1859 * and enable CMB decoding for the NVMe 1.4+ scheme:
1860 */
1861 if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1862 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1863 (pci_bus_address(pdev, bar) + offset),
1864 dev->bar + NVME_REG_CMBMSC);
1865 }
1866
1867 /*
1868 * Controllers may support a CMB size larger than their BAR,
1869 * for example, due to being behind a bridge. Reduce the CMB to
1870 * the reported size of the BAR
1871 */
1872 if (size > bar_size - offset)
1873 size = bar_size - offset;
1874
1875 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1876 dev_warn(dev->ctrl.device,
1877 "failed to register the CMB\n");
1878 return;
1879 }
1880
1881 dev->cmb_size = size;
1882 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1883
1884 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1885 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1886 pci_p2pmem_publish(pdev, true);
1887
1888 nvme_update_attrs(dev);
1889 }
1890
nvme_set_host_mem(struct nvme_dev * dev,u32 bits)1891 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1892 {
1893 u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
1894 u64 dma_addr = dev->host_mem_descs_dma;
1895 struct nvme_command c = { };
1896 int ret;
1897
1898 c.features.opcode = nvme_admin_set_features;
1899 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1900 c.features.dword11 = cpu_to_le32(bits);
1901 c.features.dword12 = cpu_to_le32(host_mem_size);
1902 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1903 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1904 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1905
1906 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1907 if (ret) {
1908 dev_warn(dev->ctrl.device,
1909 "failed to set host mem (err %d, flags %#x).\n",
1910 ret, bits);
1911 } else
1912 dev->hmb = bits & NVME_HOST_MEM_ENABLE;
1913
1914 return ret;
1915 }
1916
nvme_free_host_mem(struct nvme_dev * dev)1917 static void nvme_free_host_mem(struct nvme_dev *dev)
1918 {
1919 int i;
1920
1921 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1922 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1923 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
1924
1925 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1926 le64_to_cpu(desc->addr),
1927 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1928 }
1929
1930 kfree(dev->host_mem_desc_bufs);
1931 dev->host_mem_desc_bufs = NULL;
1932 dma_free_coherent(dev->dev,
1933 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1934 dev->host_mem_descs, dev->host_mem_descs_dma);
1935 dev->host_mem_descs = NULL;
1936 dev->nr_host_mem_descs = 0;
1937 }
1938
__nvme_alloc_host_mem(struct nvme_dev * dev,u64 preferred,u32 chunk_size)1939 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1940 u32 chunk_size)
1941 {
1942 struct nvme_host_mem_buf_desc *descs;
1943 u32 max_entries, len;
1944 dma_addr_t descs_dma;
1945 int i = 0;
1946 void **bufs;
1947 u64 size, tmp;
1948
1949 tmp = (preferred + chunk_size - 1);
1950 do_div(tmp, chunk_size);
1951 max_entries = tmp;
1952
1953 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1954 max_entries = dev->ctrl.hmmaxd;
1955
1956 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1957 &descs_dma, GFP_KERNEL);
1958 if (!descs)
1959 goto out;
1960
1961 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1962 if (!bufs)
1963 goto out_free_descs;
1964
1965 for (size = 0; size < preferred && i < max_entries; size += len) {
1966 dma_addr_t dma_addr;
1967
1968 len = min_t(u64, chunk_size, preferred - size);
1969 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1970 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1971 if (!bufs[i])
1972 break;
1973
1974 descs[i].addr = cpu_to_le64(dma_addr);
1975 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
1976 i++;
1977 }
1978
1979 if (!size)
1980 goto out_free_bufs;
1981
1982 dev->nr_host_mem_descs = i;
1983 dev->host_mem_size = size;
1984 dev->host_mem_descs = descs;
1985 dev->host_mem_descs_dma = descs_dma;
1986 dev->host_mem_desc_bufs = bufs;
1987 return 0;
1988
1989 out_free_bufs:
1990 while (--i >= 0) {
1991 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
1992
1993 dma_free_attrs(dev->dev, size, bufs[i],
1994 le64_to_cpu(descs[i].addr),
1995 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1996 }
1997
1998 kfree(bufs);
1999 out_free_descs:
2000 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
2001 descs_dma);
2002 out:
2003 dev->host_mem_descs = NULL;
2004 return -ENOMEM;
2005 }
2006
nvme_alloc_host_mem(struct nvme_dev * dev,u64 min,u64 preferred)2007 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
2008 {
2009 u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
2010 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2011 u64 chunk_size;
2012
2013 /* start big and work our way down */
2014 for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
2015 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2016 if (!min || dev->host_mem_size >= min)
2017 return 0;
2018 nvme_free_host_mem(dev);
2019 }
2020 }
2021
2022 return -ENOMEM;
2023 }
2024
nvme_setup_host_mem(struct nvme_dev * dev)2025 static int nvme_setup_host_mem(struct nvme_dev *dev)
2026 {
2027 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2028 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2029 u64 min = (u64)dev->ctrl.hmmin * 4096;
2030 u32 enable_bits = NVME_HOST_MEM_ENABLE;
2031 int ret;
2032
2033 if (!dev->ctrl.hmpre)
2034 return 0;
2035
2036 preferred = min(preferred, max);
2037 if (min > max) {
2038 dev_warn(dev->ctrl.device,
2039 "min host memory (%lld MiB) above limit (%d MiB).\n",
2040 min >> ilog2(SZ_1M), max_host_mem_size_mb);
2041 nvme_free_host_mem(dev);
2042 return 0;
2043 }
2044
2045 /*
2046 * If we already have a buffer allocated check if we can reuse it.
2047 */
2048 if (dev->host_mem_descs) {
2049 if (dev->host_mem_size >= min)
2050 enable_bits |= NVME_HOST_MEM_RETURN;
2051 else
2052 nvme_free_host_mem(dev);
2053 }
2054
2055 if (!dev->host_mem_descs) {
2056 if (nvme_alloc_host_mem(dev, min, preferred)) {
2057 dev_warn(dev->ctrl.device,
2058 "failed to allocate host memory buffer.\n");
2059 return 0; /* controller must work without HMB */
2060 }
2061
2062 dev_info(dev->ctrl.device,
2063 "allocated %lld MiB host memory buffer.\n",
2064 dev->host_mem_size >> ilog2(SZ_1M));
2065 }
2066
2067 ret = nvme_set_host_mem(dev, enable_bits);
2068 if (ret)
2069 nvme_free_host_mem(dev);
2070 return ret;
2071 }
2072
cmb_show(struct device * dev,struct device_attribute * attr,char * buf)2073 static ssize_t cmb_show(struct device *dev, struct device_attribute *attr,
2074 char *buf)
2075 {
2076 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2077
2078 return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n",
2079 ndev->cmbloc, ndev->cmbsz);
2080 }
2081 static DEVICE_ATTR_RO(cmb);
2082
cmbloc_show(struct device * dev,struct device_attribute * attr,char * buf)2083 static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr,
2084 char *buf)
2085 {
2086 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2087
2088 return sysfs_emit(buf, "%u\n", ndev->cmbloc);
2089 }
2090 static DEVICE_ATTR_RO(cmbloc);
2091
cmbsz_show(struct device * dev,struct device_attribute * attr,char * buf)2092 static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr,
2093 char *buf)
2094 {
2095 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2096
2097 return sysfs_emit(buf, "%u\n", ndev->cmbsz);
2098 }
2099 static DEVICE_ATTR_RO(cmbsz);
2100
hmb_show(struct device * dev,struct device_attribute * attr,char * buf)2101 static ssize_t hmb_show(struct device *dev, struct device_attribute *attr,
2102 char *buf)
2103 {
2104 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2105
2106 return sysfs_emit(buf, "%d\n", ndev->hmb);
2107 }
2108
hmb_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)2109 static ssize_t hmb_store(struct device *dev, struct device_attribute *attr,
2110 const char *buf, size_t count)
2111 {
2112 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2113 bool new;
2114 int ret;
2115
2116 if (kstrtobool(buf, &new) < 0)
2117 return -EINVAL;
2118
2119 if (new == ndev->hmb)
2120 return count;
2121
2122 if (new) {
2123 ret = nvme_setup_host_mem(ndev);
2124 } else {
2125 ret = nvme_set_host_mem(ndev, 0);
2126 if (!ret)
2127 nvme_free_host_mem(ndev);
2128 }
2129
2130 if (ret < 0)
2131 return ret;
2132
2133 return count;
2134 }
2135 static DEVICE_ATTR_RW(hmb);
2136
nvme_pci_attrs_are_visible(struct kobject * kobj,struct attribute * a,int n)2137 static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj,
2138 struct attribute *a, int n)
2139 {
2140 struct nvme_ctrl *ctrl =
2141 dev_get_drvdata(container_of(kobj, struct device, kobj));
2142 struct nvme_dev *dev = to_nvme_dev(ctrl);
2143
2144 if (a == &dev_attr_cmb.attr ||
2145 a == &dev_attr_cmbloc.attr ||
2146 a == &dev_attr_cmbsz.attr) {
2147 if (!dev->cmbsz)
2148 return 0;
2149 }
2150 if (a == &dev_attr_hmb.attr && !ctrl->hmpre)
2151 return 0;
2152
2153 return a->mode;
2154 }
2155
2156 static struct attribute *nvme_pci_attrs[] = {
2157 &dev_attr_cmb.attr,
2158 &dev_attr_cmbloc.attr,
2159 &dev_attr_cmbsz.attr,
2160 &dev_attr_hmb.attr,
2161 NULL,
2162 };
2163
2164 static const struct attribute_group nvme_pci_dev_attrs_group = {
2165 .attrs = nvme_pci_attrs,
2166 .is_visible = nvme_pci_attrs_are_visible,
2167 };
2168
2169 static const struct attribute_group *nvme_pci_dev_attr_groups[] = {
2170 &nvme_dev_attrs_group,
2171 &nvme_pci_dev_attrs_group,
2172 NULL,
2173 };
2174
nvme_update_attrs(struct nvme_dev * dev)2175 static void nvme_update_attrs(struct nvme_dev *dev)
2176 {
2177 sysfs_update_group(&dev->ctrl.device->kobj, &nvme_pci_dev_attrs_group);
2178 }
2179
2180 /*
2181 * nirqs is the number of interrupts available for write and read
2182 * queues. The core already reserved an interrupt for the admin queue.
2183 */
nvme_calc_irq_sets(struct irq_affinity * affd,unsigned int nrirqs)2184 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
2185 {
2186 struct nvme_dev *dev = affd->priv;
2187 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
2188
2189 /*
2190 * If there is no interrupt available for queues, ensure that
2191 * the default queue is set to 1. The affinity set size is
2192 * also set to one, but the irq core ignores it for this case.
2193 *
2194 * If only one interrupt is available or 'write_queue' == 0, combine
2195 * write and read queues.
2196 *
2197 * If 'write_queues' > 0, ensure it leaves room for at least one read
2198 * queue.
2199 */
2200 if (!nrirqs) {
2201 nrirqs = 1;
2202 nr_read_queues = 0;
2203 } else if (nrirqs == 1 || !nr_write_queues) {
2204 nr_read_queues = 0;
2205 } else if (nr_write_queues >= nrirqs) {
2206 nr_read_queues = 1;
2207 } else {
2208 nr_read_queues = nrirqs - nr_write_queues;
2209 }
2210
2211 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2212 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2213 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2214 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2215 affd->nr_sets = nr_read_queues ? 2 : 1;
2216 }
2217
nvme_setup_irqs(struct nvme_dev * dev,unsigned int nr_io_queues)2218 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
2219 {
2220 struct pci_dev *pdev = to_pci_dev(dev->dev);
2221 struct irq_affinity affd = {
2222 .pre_vectors = 1,
2223 .calc_sets = nvme_calc_irq_sets,
2224 .priv = dev,
2225 };
2226 unsigned int irq_queues, poll_queues;
2227 unsigned int flags = PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY;
2228
2229 /*
2230 * Poll queues don't need interrupts, but we need at least one I/O queue
2231 * left over for non-polled I/O.
2232 */
2233 poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2234 dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
2235
2236 /*
2237 * Initialize for the single interrupt case, will be updated in
2238 * nvme_calc_irq_sets().
2239 */
2240 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2241 dev->io_queues[HCTX_TYPE_READ] = 0;
2242
2243 /*
2244 * We need interrupts for the admin queue and each non-polled I/O queue,
2245 * but some Apple controllers require all queues to use the first
2246 * vector.
2247 */
2248 irq_queues = 1;
2249 if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2250 irq_queues += (nr_io_queues - poll_queues);
2251 if (dev->ctrl.quirks & NVME_QUIRK_BROKEN_MSI)
2252 flags &= ~PCI_IRQ_MSI;
2253 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, flags,
2254 &affd);
2255 }
2256
nvme_max_io_queues(struct nvme_dev * dev)2257 static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2258 {
2259 /*
2260 * If tags are shared with admin queue (Apple bug), then
2261 * make sure we only use one IO queue.
2262 */
2263 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2264 return 1;
2265 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2266 }
2267
nvme_setup_io_queues(struct nvme_dev * dev)2268 static int nvme_setup_io_queues(struct nvme_dev *dev)
2269 {
2270 struct nvme_queue *adminq = &dev->queues[0];
2271 struct pci_dev *pdev = to_pci_dev(dev->dev);
2272 unsigned int nr_io_queues;
2273 unsigned long size;
2274 int result;
2275
2276 /*
2277 * Sample the module parameters once at reset time so that we have
2278 * stable values to work with.
2279 */
2280 dev->nr_write_queues = write_queues;
2281 dev->nr_poll_queues = poll_queues;
2282
2283 nr_io_queues = dev->nr_allocated_queues - 1;
2284 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2285 if (result < 0)
2286 return result;
2287
2288 if (nr_io_queues == 0)
2289 return 0;
2290
2291 /*
2292 * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions
2293 * from set to unset. If there is a window to it is truely freed,
2294 * pci_free_irq_vectors() jumping into this window will crash.
2295 * And take lock to avoid racing with pci_free_irq_vectors() in
2296 * nvme_dev_disable() path.
2297 */
2298 result = nvme_setup_io_queues_trylock(dev);
2299 if (result)
2300 return result;
2301 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2302 pci_free_irq(pdev, 0, adminq);
2303
2304 if (dev->cmb_use_sqes) {
2305 result = nvme_cmb_qdepth(dev, nr_io_queues,
2306 sizeof(struct nvme_command));
2307 if (result > 0) {
2308 dev->q_depth = result;
2309 dev->ctrl.sqsize = result - 1;
2310 } else {
2311 dev->cmb_use_sqes = false;
2312 }
2313 }
2314
2315 do {
2316 size = db_bar_size(dev, nr_io_queues);
2317 result = nvme_remap_bar(dev, size);
2318 if (!result)
2319 break;
2320 if (!--nr_io_queues) {
2321 result = -ENOMEM;
2322 goto out_unlock;
2323 }
2324 } while (1);
2325 adminq->q_db = dev->dbs;
2326
2327 retry:
2328 /* Deregister the admin queue's interrupt */
2329 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2330 pci_free_irq(pdev, 0, adminq);
2331
2332 /*
2333 * If we enable msix early due to not intx, disable it again before
2334 * setting up the full range we need.
2335 */
2336 pci_free_irq_vectors(pdev);
2337
2338 result = nvme_setup_irqs(dev, nr_io_queues);
2339 if (result <= 0) {
2340 result = -EIO;
2341 goto out_unlock;
2342 }
2343
2344 dev->num_vecs = result;
2345 result = max(result - 1, 1);
2346 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
2347
2348 /*
2349 * Should investigate if there's a performance win from allocating
2350 * more queues than interrupt vectors; it might allow the submission
2351 * path to scale better, even if the receive path is limited by the
2352 * number of interrupts.
2353 */
2354 result = queue_request_irq(adminq);
2355 if (result)
2356 goto out_unlock;
2357 set_bit(NVMEQ_ENABLED, &adminq->flags);
2358 mutex_unlock(&dev->shutdown_lock);
2359
2360 result = nvme_create_io_queues(dev);
2361 if (result || dev->online_queues < 2)
2362 return result;
2363
2364 if (dev->online_queues - 1 < dev->max_qid) {
2365 nr_io_queues = dev->online_queues - 1;
2366 nvme_delete_io_queues(dev);
2367 result = nvme_setup_io_queues_trylock(dev);
2368 if (result)
2369 return result;
2370 nvme_suspend_io_queues(dev);
2371 goto retry;
2372 }
2373 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2374 dev->io_queues[HCTX_TYPE_DEFAULT],
2375 dev->io_queues[HCTX_TYPE_READ],
2376 dev->io_queues[HCTX_TYPE_POLL]);
2377 return 0;
2378 out_unlock:
2379 mutex_unlock(&dev->shutdown_lock);
2380 return result;
2381 }
2382
nvme_del_queue_end(struct request * req,blk_status_t error)2383 static enum rq_end_io_ret nvme_del_queue_end(struct request *req,
2384 blk_status_t error)
2385 {
2386 struct nvme_queue *nvmeq = req->end_io_data;
2387
2388 blk_mq_free_request(req);
2389 complete(&nvmeq->delete_done);
2390 return RQ_END_IO_NONE;
2391 }
2392
nvme_del_cq_end(struct request * req,blk_status_t error)2393 static enum rq_end_io_ret nvme_del_cq_end(struct request *req,
2394 blk_status_t error)
2395 {
2396 struct nvme_queue *nvmeq = req->end_io_data;
2397
2398 if (error)
2399 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
2400
2401 return nvme_del_queue_end(req, error);
2402 }
2403
nvme_delete_queue(struct nvme_queue * nvmeq,u8 opcode)2404 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2405 {
2406 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2407 struct request *req;
2408 struct nvme_command cmd = { };
2409
2410 cmd.delete_queue.opcode = opcode;
2411 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2412
2413 req = blk_mq_alloc_request(q, nvme_req_op(&cmd), BLK_MQ_REQ_NOWAIT);
2414 if (IS_ERR(req))
2415 return PTR_ERR(req);
2416 nvme_init_request(req, &cmd);
2417
2418 if (opcode == nvme_admin_delete_cq)
2419 req->end_io = nvme_del_cq_end;
2420 else
2421 req->end_io = nvme_del_queue_end;
2422 req->end_io_data = nvmeq;
2423
2424 init_completion(&nvmeq->delete_done);
2425 blk_execute_rq_nowait(req, false);
2426 return 0;
2427 }
2428
__nvme_delete_io_queues(struct nvme_dev * dev,u8 opcode)2429 static bool __nvme_delete_io_queues(struct nvme_dev *dev, u8 opcode)
2430 {
2431 int nr_queues = dev->online_queues - 1, sent = 0;
2432 unsigned long timeout;
2433
2434 retry:
2435 timeout = NVME_ADMIN_TIMEOUT;
2436 while (nr_queues > 0) {
2437 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2438 break;
2439 nr_queues--;
2440 sent++;
2441 }
2442 while (sent) {
2443 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2444
2445 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
2446 timeout);
2447 if (timeout == 0)
2448 return false;
2449
2450 sent--;
2451 if (nr_queues)
2452 goto retry;
2453 }
2454 return true;
2455 }
2456
nvme_delete_io_queues(struct nvme_dev * dev)2457 static void nvme_delete_io_queues(struct nvme_dev *dev)
2458 {
2459 if (__nvme_delete_io_queues(dev, nvme_admin_delete_sq))
2460 __nvme_delete_io_queues(dev, nvme_admin_delete_cq);
2461 }
2462
nvme_pci_nr_maps(struct nvme_dev * dev)2463 static unsigned int nvme_pci_nr_maps(struct nvme_dev *dev)
2464 {
2465 if (dev->io_queues[HCTX_TYPE_POLL])
2466 return 3;
2467 if (dev->io_queues[HCTX_TYPE_READ])
2468 return 2;
2469 return 1;
2470 }
2471
nvme_pci_update_nr_queues(struct nvme_dev * dev)2472 static bool nvme_pci_update_nr_queues(struct nvme_dev *dev)
2473 {
2474 if (!dev->ctrl.tagset) {
2475 nvme_alloc_io_tag_set(&dev->ctrl, &dev->tagset, &nvme_mq_ops,
2476 nvme_pci_nr_maps(dev), sizeof(struct nvme_iod));
2477 return true;
2478 }
2479
2480 /* Give up if we are racing with nvme_dev_disable() */
2481 if (!mutex_trylock(&dev->shutdown_lock))
2482 return false;
2483
2484 /* Check if nvme_dev_disable() has been executed already */
2485 if (!dev->online_queues) {
2486 mutex_unlock(&dev->shutdown_lock);
2487 return false;
2488 }
2489
2490 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2491 /* free previously allocated queues that are no longer usable */
2492 nvme_free_queues(dev, dev->online_queues);
2493 mutex_unlock(&dev->shutdown_lock);
2494 return true;
2495 }
2496
nvme_pci_enable(struct nvme_dev * dev)2497 static int nvme_pci_enable(struct nvme_dev *dev)
2498 {
2499 int result = -ENOMEM;
2500 struct pci_dev *pdev = to_pci_dev(dev->dev);
2501 unsigned int flags = PCI_IRQ_ALL_TYPES;
2502
2503 if (pci_enable_device_mem(pdev))
2504 return result;
2505
2506 pci_set_master(pdev);
2507
2508 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2509 result = -ENODEV;
2510 goto disable;
2511 }
2512
2513 /*
2514 * Some devices and/or platforms don't advertise or work with INTx
2515 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2516 * adjust this later.
2517 */
2518 if (dev->ctrl.quirks & NVME_QUIRK_BROKEN_MSI)
2519 flags &= ~PCI_IRQ_MSI;
2520 result = pci_alloc_irq_vectors(pdev, 1, 1, flags);
2521 if (result < 0)
2522 goto disable;
2523
2524 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2525
2526 dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2527 io_queue_depth);
2528 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2529 dev->dbs = dev->bar + 4096;
2530
2531 /*
2532 * Some Apple controllers require a non-standard SQE size.
2533 * Interestingly they also seem to ignore the CC:IOSQES register
2534 * so we don't bother updating it here.
2535 */
2536 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2537 dev->io_sqes = 7;
2538 else
2539 dev->io_sqes = NVME_NVM_IOSQES;
2540
2541 if (dev->ctrl.quirks & NVME_QUIRK_QDEPTH_ONE) {
2542 dev->q_depth = 2;
2543 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2544 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2545 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2546 dev->q_depth = 64;
2547 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2548 "set queue depth=%u\n", dev->q_depth);
2549 }
2550
2551 /*
2552 * Controllers with the shared tags quirk need the IO queue to be
2553 * big enough so that we get 32 tags for the admin queue
2554 */
2555 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2556 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2557 dev->q_depth = NVME_AQ_DEPTH + 2;
2558 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2559 dev->q_depth);
2560 }
2561 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
2562
2563 nvme_map_cmb(dev);
2564
2565 pci_save_state(pdev);
2566
2567 result = nvme_pci_configure_admin_queue(dev);
2568 if (result)
2569 goto free_irq;
2570 return result;
2571
2572 free_irq:
2573 pci_free_irq_vectors(pdev);
2574 disable:
2575 pci_disable_device(pdev);
2576 return result;
2577 }
2578
nvme_dev_unmap(struct nvme_dev * dev)2579 static void nvme_dev_unmap(struct nvme_dev *dev)
2580 {
2581 if (dev->bar)
2582 iounmap(dev->bar);
2583 pci_release_mem_regions(to_pci_dev(dev->dev));
2584 }
2585
nvme_pci_ctrl_is_dead(struct nvme_dev * dev)2586 static bool nvme_pci_ctrl_is_dead(struct nvme_dev *dev)
2587 {
2588 struct pci_dev *pdev = to_pci_dev(dev->dev);
2589 u32 csts;
2590
2591 if (!pci_is_enabled(pdev) || !pci_device_is_present(pdev))
2592 return true;
2593 if (pdev->error_state != pci_channel_io_normal)
2594 return true;
2595
2596 csts = readl(dev->bar + NVME_REG_CSTS);
2597 return (csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY);
2598 }
2599
nvme_dev_disable(struct nvme_dev * dev,bool shutdown)2600 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2601 {
2602 enum nvme_ctrl_state state = nvme_ctrl_state(&dev->ctrl);
2603 struct pci_dev *pdev = to_pci_dev(dev->dev);
2604 bool dead;
2605
2606 mutex_lock(&dev->shutdown_lock);
2607 dead = nvme_pci_ctrl_is_dead(dev);
2608 if (state == NVME_CTRL_LIVE || state == NVME_CTRL_RESETTING) {
2609 if (pci_is_enabled(pdev))
2610 nvme_start_freeze(&dev->ctrl);
2611 /*
2612 * Give the controller a chance to complete all entered requests
2613 * if doing a safe shutdown.
2614 */
2615 if (!dead && shutdown)
2616 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2617 }
2618
2619 nvme_quiesce_io_queues(&dev->ctrl);
2620
2621 if (!dead && dev->ctrl.queue_count > 0) {
2622 nvme_delete_io_queues(dev);
2623 nvme_disable_ctrl(&dev->ctrl, shutdown);
2624 nvme_poll_irqdisable(&dev->queues[0]);
2625 }
2626 nvme_suspend_io_queues(dev);
2627 nvme_suspend_queue(dev, 0);
2628 pci_free_irq_vectors(pdev);
2629 if (pci_is_enabled(pdev))
2630 pci_disable_device(pdev);
2631 nvme_reap_pending_cqes(dev);
2632
2633 nvme_cancel_tagset(&dev->ctrl);
2634 nvme_cancel_admin_tagset(&dev->ctrl);
2635
2636 /*
2637 * The driver will not be starting up queues again if shutting down so
2638 * must flush all entered requests to their failed completion to avoid
2639 * deadlocking blk-mq hot-cpu notifier.
2640 */
2641 if (shutdown) {
2642 nvme_unquiesce_io_queues(&dev->ctrl);
2643 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2644 nvme_unquiesce_admin_queue(&dev->ctrl);
2645 }
2646 mutex_unlock(&dev->shutdown_lock);
2647 }
2648
nvme_disable_prepare_reset(struct nvme_dev * dev,bool shutdown)2649 static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2650 {
2651 if (!nvme_wait_reset(&dev->ctrl))
2652 return -EBUSY;
2653 nvme_dev_disable(dev, shutdown);
2654 return 0;
2655 }
2656
nvme_setup_prp_pools(struct nvme_dev * dev)2657 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2658 {
2659 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2660 NVME_CTRL_PAGE_SIZE,
2661 NVME_CTRL_PAGE_SIZE, 0);
2662 if (!dev->prp_page_pool)
2663 return -ENOMEM;
2664
2665 /* Optimisation for I/Os between 4k and 128k */
2666 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2667 256, 256, 0);
2668 if (!dev->prp_small_pool) {
2669 dma_pool_destroy(dev->prp_page_pool);
2670 return -ENOMEM;
2671 }
2672 return 0;
2673 }
2674
nvme_release_prp_pools(struct nvme_dev * dev)2675 static void nvme_release_prp_pools(struct nvme_dev *dev)
2676 {
2677 dma_pool_destroy(dev->prp_page_pool);
2678 dma_pool_destroy(dev->prp_small_pool);
2679 }
2680
nvme_pci_alloc_iod_mempool(struct nvme_dev * dev)2681 static int nvme_pci_alloc_iod_mempool(struct nvme_dev *dev)
2682 {
2683 size_t alloc_size = sizeof(struct scatterlist) * NVME_MAX_SEGS;
2684
2685 dev->iod_mempool = mempool_create_node(1,
2686 mempool_kmalloc, mempool_kfree,
2687 (void *)alloc_size, GFP_KERNEL,
2688 dev_to_node(dev->dev));
2689 if (!dev->iod_mempool)
2690 return -ENOMEM;
2691 return 0;
2692 }
2693
nvme_free_tagset(struct nvme_dev * dev)2694 static void nvme_free_tagset(struct nvme_dev *dev)
2695 {
2696 if (dev->tagset.tags)
2697 nvme_remove_io_tag_set(&dev->ctrl);
2698 dev->ctrl.tagset = NULL;
2699 }
2700
2701 /* pairs with nvme_pci_alloc_dev */
nvme_pci_free_ctrl(struct nvme_ctrl * ctrl)2702 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2703 {
2704 struct nvme_dev *dev = to_nvme_dev(ctrl);
2705
2706 nvme_free_tagset(dev);
2707 put_device(dev->dev);
2708 kfree(dev->queues);
2709 kfree(dev);
2710 }
2711
nvme_reset_work(struct work_struct * work)2712 static void nvme_reset_work(struct work_struct *work)
2713 {
2714 struct nvme_dev *dev =
2715 container_of(work, struct nvme_dev, ctrl.reset_work);
2716 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2717 int result;
2718
2719 if (nvme_ctrl_state(&dev->ctrl) != NVME_CTRL_RESETTING) {
2720 dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n",
2721 dev->ctrl.state);
2722 result = -ENODEV;
2723 goto out;
2724 }
2725
2726 /*
2727 * If we're called to reset a live controller first shut it down before
2728 * moving on.
2729 */
2730 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2731 nvme_dev_disable(dev, false);
2732 nvme_sync_queues(&dev->ctrl);
2733
2734 mutex_lock(&dev->shutdown_lock);
2735 result = nvme_pci_enable(dev);
2736 if (result)
2737 goto out_unlock;
2738 nvme_unquiesce_admin_queue(&dev->ctrl);
2739 mutex_unlock(&dev->shutdown_lock);
2740
2741 /*
2742 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2743 * initializing procedure here.
2744 */
2745 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2746 dev_warn(dev->ctrl.device,
2747 "failed to mark controller CONNECTING\n");
2748 result = -EBUSY;
2749 goto out;
2750 }
2751
2752 result = nvme_init_ctrl_finish(&dev->ctrl, was_suspend);
2753 if (result)
2754 goto out;
2755
2756 nvme_dbbuf_dma_alloc(dev);
2757
2758 result = nvme_setup_host_mem(dev);
2759 if (result < 0)
2760 goto out;
2761
2762 result = nvme_setup_io_queues(dev);
2763 if (result)
2764 goto out;
2765
2766 /*
2767 * Freeze and update the number of I/O queues as thos might have
2768 * changed. If there are no I/O queues left after this reset, keep the
2769 * controller around but remove all namespaces.
2770 */
2771 if (dev->online_queues > 1) {
2772 nvme_dbbuf_set(dev);
2773 nvme_unquiesce_io_queues(&dev->ctrl);
2774 nvme_wait_freeze(&dev->ctrl);
2775 if (!nvme_pci_update_nr_queues(dev))
2776 goto out;
2777 nvme_unfreeze(&dev->ctrl);
2778 } else {
2779 dev_warn(dev->ctrl.device, "IO queues lost\n");
2780 nvme_mark_namespaces_dead(&dev->ctrl);
2781 nvme_unquiesce_io_queues(&dev->ctrl);
2782 nvme_remove_namespaces(&dev->ctrl);
2783 nvme_free_tagset(dev);
2784 }
2785
2786 /*
2787 * If only admin queue live, keep it to do further investigation or
2788 * recovery.
2789 */
2790 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2791 dev_warn(dev->ctrl.device,
2792 "failed to mark controller live state\n");
2793 result = -ENODEV;
2794 goto out;
2795 }
2796
2797 nvme_start_ctrl(&dev->ctrl);
2798 return;
2799
2800 out_unlock:
2801 mutex_unlock(&dev->shutdown_lock);
2802 out:
2803 /*
2804 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2805 * may be holding this pci_dev's device lock.
2806 */
2807 dev_warn(dev->ctrl.device, "Disabling device after reset failure: %d\n",
2808 result);
2809 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2810 nvme_dev_disable(dev, true);
2811 nvme_sync_queues(&dev->ctrl);
2812 nvme_mark_namespaces_dead(&dev->ctrl);
2813 nvme_unquiesce_io_queues(&dev->ctrl);
2814 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2815 }
2816
nvme_pci_reg_read32(struct nvme_ctrl * ctrl,u32 off,u32 * val)2817 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2818 {
2819 *val = readl(to_nvme_dev(ctrl)->bar + off);
2820 return 0;
2821 }
2822
nvme_pci_reg_write32(struct nvme_ctrl * ctrl,u32 off,u32 val)2823 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2824 {
2825 writel(val, to_nvme_dev(ctrl)->bar + off);
2826 return 0;
2827 }
2828
nvme_pci_reg_read64(struct nvme_ctrl * ctrl,u32 off,u64 * val)2829 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2830 {
2831 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
2832 return 0;
2833 }
2834
nvme_pci_get_address(struct nvme_ctrl * ctrl,char * buf,int size)2835 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2836 {
2837 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2838
2839 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
2840 }
2841
nvme_pci_print_device_info(struct nvme_ctrl * ctrl)2842 static void nvme_pci_print_device_info(struct nvme_ctrl *ctrl)
2843 {
2844 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2845 struct nvme_subsystem *subsys = ctrl->subsys;
2846
2847 dev_err(ctrl->device,
2848 "VID:DID %04x:%04x model:%.*s firmware:%.*s\n",
2849 pdev->vendor, pdev->device,
2850 nvme_strlen(subsys->model, sizeof(subsys->model)),
2851 subsys->model, nvme_strlen(subsys->firmware_rev,
2852 sizeof(subsys->firmware_rev)),
2853 subsys->firmware_rev);
2854 }
2855
nvme_pci_supports_pci_p2pdma(struct nvme_ctrl * ctrl)2856 static bool nvme_pci_supports_pci_p2pdma(struct nvme_ctrl *ctrl)
2857 {
2858 struct nvme_dev *dev = to_nvme_dev(ctrl);
2859
2860 return dma_pci_p2pdma_supported(dev->dev);
2861 }
2862
2863 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2864 .name = "pcie",
2865 .module = THIS_MODULE,
2866 .flags = NVME_F_METADATA_SUPPORTED,
2867 .dev_attr_groups = nvme_pci_dev_attr_groups,
2868 .reg_read32 = nvme_pci_reg_read32,
2869 .reg_write32 = nvme_pci_reg_write32,
2870 .reg_read64 = nvme_pci_reg_read64,
2871 .free_ctrl = nvme_pci_free_ctrl,
2872 .submit_async_event = nvme_pci_submit_async_event,
2873 .get_address = nvme_pci_get_address,
2874 .print_device_info = nvme_pci_print_device_info,
2875 .supports_pci_p2pdma = nvme_pci_supports_pci_p2pdma,
2876 };
2877
nvme_dev_map(struct nvme_dev * dev)2878 static int nvme_dev_map(struct nvme_dev *dev)
2879 {
2880 struct pci_dev *pdev = to_pci_dev(dev->dev);
2881
2882 if (pci_request_mem_regions(pdev, "nvme"))
2883 return -ENODEV;
2884
2885 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2886 goto release;
2887
2888 return 0;
2889 release:
2890 pci_release_mem_regions(pdev);
2891 return -ENODEV;
2892 }
2893
check_vendor_combination_bug(struct pci_dev * pdev)2894 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2895 {
2896 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2897 /*
2898 * Several Samsung devices seem to drop off the PCIe bus
2899 * randomly when APST is on and uses the deepest sleep state.
2900 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2901 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2902 * 950 PRO 256GB", but it seems to be restricted to two Dell
2903 * laptops.
2904 */
2905 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2906 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2907 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2908 return NVME_QUIRK_NO_DEEPEST_PS;
2909 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2910 /*
2911 * Samsung SSD 960 EVO drops off the PCIe bus after system
2912 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2913 * within few minutes after bootup on a Coffee Lake board -
2914 * ASUS PRIME Z370-A
2915 */
2916 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2917 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2918 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
2919 return NVME_QUIRK_NO_APST;
2920 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2921 pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2922 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2923 /*
2924 * Forcing to use host managed nvme power settings for
2925 * lowest idle power with quick resume latency on
2926 * Samsung and Toshiba SSDs based on suspend behavior
2927 * on Coffee Lake board for LENOVO C640
2928 */
2929 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2930 dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2931 return NVME_QUIRK_SIMPLE_SUSPEND;
2932 } else if (pdev->vendor == 0x2646 && (pdev->device == 0x2263 ||
2933 pdev->device == 0x500f)) {
2934 /*
2935 * Exclude some Kingston NV1 and A2000 devices from
2936 * NVME_QUIRK_SIMPLE_SUSPEND. Do a full suspend to save a
2937 * lot fo energy with s2idle sleep on some TUXEDO platforms.
2938 */
2939 if (dmi_match(DMI_BOARD_NAME, "NS5X_NS7XAU") ||
2940 dmi_match(DMI_BOARD_NAME, "NS5x_7xAU") ||
2941 dmi_match(DMI_BOARD_NAME, "NS5x_7xPU") ||
2942 dmi_match(DMI_BOARD_NAME, "PH4PRX1_PH6PRX1"))
2943 return NVME_QUIRK_FORCE_NO_SIMPLE_SUSPEND;
2944 } else if (pdev->vendor == 0x144d && pdev->device == 0xa80d) {
2945 /*
2946 * Exclude Samsung 990 Evo from NVME_QUIRK_SIMPLE_SUSPEND
2947 * because of high power consumption (> 2 Watt) in s2idle
2948 * sleep. Only some boards with Intel CPU are affected.
2949 */
2950 if (dmi_match(DMI_BOARD_NAME, "GMxPXxx") ||
2951 dmi_match(DMI_BOARD_NAME, "PH4PG31") ||
2952 dmi_match(DMI_BOARD_NAME, "PH4PRX1_PH6PRX1") ||
2953 dmi_match(DMI_BOARD_NAME, "PH6PG01_PH6PG71"))
2954 return NVME_QUIRK_FORCE_NO_SIMPLE_SUSPEND;
2955 }
2956
2957 /*
2958 * NVMe SSD drops off the PCIe bus after system idle
2959 * for 10 hours on a Lenovo N60z board.
2960 */
2961 if (dmi_match(DMI_BOARD_NAME, "LXKT-ZXEG-N6"))
2962 return NVME_QUIRK_NO_APST;
2963
2964 return 0;
2965 }
2966
nvme_pci_alloc_dev(struct pci_dev * pdev,const struct pci_device_id * id)2967 static struct nvme_dev *nvme_pci_alloc_dev(struct pci_dev *pdev,
2968 const struct pci_device_id *id)
2969 {
2970 unsigned long quirks = id->driver_data;
2971 int node = dev_to_node(&pdev->dev);
2972 struct nvme_dev *dev;
2973 int ret = -ENOMEM;
2974
2975 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2976 if (!dev)
2977 return ERR_PTR(-ENOMEM);
2978 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2979 mutex_init(&dev->shutdown_lock);
2980
2981 dev->nr_write_queues = write_queues;
2982 dev->nr_poll_queues = poll_queues;
2983 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
2984 dev->queues = kcalloc_node(dev->nr_allocated_queues,
2985 sizeof(struct nvme_queue), GFP_KERNEL, node);
2986 if (!dev->queues)
2987 goto out_free_dev;
2988
2989 dev->dev = get_device(&pdev->dev);
2990
2991 quirks |= check_vendor_combination_bug(pdev);
2992 if (!noacpi &&
2993 !(quirks & NVME_QUIRK_FORCE_NO_SIMPLE_SUSPEND) &&
2994 acpi_storage_d3(&pdev->dev)) {
2995 /*
2996 * Some systems use a bios work around to ask for D3 on
2997 * platforms that support kernel managed suspend.
2998 */
2999 dev_info(&pdev->dev,
3000 "platform quirk: setting simple suspend\n");
3001 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
3002 }
3003 ret = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
3004 quirks);
3005 if (ret)
3006 goto out_put_device;
3007
3008 if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
3009 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(48));
3010 else
3011 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
3012 dma_set_min_align_mask(&pdev->dev, NVME_CTRL_PAGE_SIZE - 1);
3013 dma_set_max_seg_size(&pdev->dev, 0xffffffff);
3014
3015 /*
3016 * Limit the max command size to prevent iod->sg allocations going
3017 * over a single page.
3018 */
3019 dev->ctrl.max_hw_sectors = min_t(u32,
3020 NVME_MAX_KB_SZ << 1, dma_opt_mapping_size(&pdev->dev) >> 9);
3021 dev->ctrl.max_segments = NVME_MAX_SEGS;
3022
3023 /*
3024 * There is no support for SGLs for metadata (yet), so we are limited to
3025 * a single integrity segment for the separate metadata pointer.
3026 */
3027 dev->ctrl.max_integrity_segments = 1;
3028 return dev;
3029
3030 out_put_device:
3031 put_device(dev->dev);
3032 kfree(dev->queues);
3033 out_free_dev:
3034 kfree(dev);
3035 return ERR_PTR(ret);
3036 }
3037
nvme_probe(struct pci_dev * pdev,const struct pci_device_id * id)3038 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3039 {
3040 struct nvme_dev *dev;
3041 int result = -ENOMEM;
3042
3043 dev = nvme_pci_alloc_dev(pdev, id);
3044 if (IS_ERR(dev))
3045 return PTR_ERR(dev);
3046
3047 result = nvme_dev_map(dev);
3048 if (result)
3049 goto out_uninit_ctrl;
3050
3051 result = nvme_setup_prp_pools(dev);
3052 if (result)
3053 goto out_dev_unmap;
3054
3055 result = nvme_pci_alloc_iod_mempool(dev);
3056 if (result)
3057 goto out_release_prp_pools;
3058
3059 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
3060
3061 result = nvme_pci_enable(dev);
3062 if (result)
3063 goto out_release_iod_mempool;
3064
3065 result = nvme_alloc_admin_tag_set(&dev->ctrl, &dev->admin_tagset,
3066 &nvme_mq_admin_ops, sizeof(struct nvme_iod));
3067 if (result)
3068 goto out_disable;
3069
3070 /*
3071 * Mark the controller as connecting before sending admin commands to
3072 * allow the timeout handler to do the right thing.
3073 */
3074 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
3075 dev_warn(dev->ctrl.device,
3076 "failed to mark controller CONNECTING\n");
3077 result = -EBUSY;
3078 goto out_disable;
3079 }
3080
3081 result = nvme_init_ctrl_finish(&dev->ctrl, false);
3082 if (result)
3083 goto out_disable;
3084
3085 nvme_dbbuf_dma_alloc(dev);
3086
3087 result = nvme_setup_host_mem(dev);
3088 if (result < 0)
3089 goto out_disable;
3090
3091 result = nvme_setup_io_queues(dev);
3092 if (result)
3093 goto out_disable;
3094
3095 if (dev->online_queues > 1) {
3096 nvme_alloc_io_tag_set(&dev->ctrl, &dev->tagset, &nvme_mq_ops,
3097 nvme_pci_nr_maps(dev), sizeof(struct nvme_iod));
3098 nvme_dbbuf_set(dev);
3099 }
3100
3101 if (!dev->ctrl.tagset)
3102 dev_warn(dev->ctrl.device, "IO queues not created\n");
3103
3104 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
3105 dev_warn(dev->ctrl.device,
3106 "failed to mark controller live state\n");
3107 result = -ENODEV;
3108 goto out_disable;
3109 }
3110
3111 pci_set_drvdata(pdev, dev);
3112
3113 nvme_start_ctrl(&dev->ctrl);
3114 nvme_put_ctrl(&dev->ctrl);
3115 flush_work(&dev->ctrl.scan_work);
3116 return 0;
3117
3118 out_disable:
3119 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
3120 nvme_dev_disable(dev, true);
3121 nvme_free_host_mem(dev);
3122 nvme_dev_remove_admin(dev);
3123 nvme_dbbuf_dma_free(dev);
3124 nvme_free_queues(dev, 0);
3125 out_release_iod_mempool:
3126 mempool_destroy(dev->iod_mempool);
3127 out_release_prp_pools:
3128 nvme_release_prp_pools(dev);
3129 out_dev_unmap:
3130 nvme_dev_unmap(dev);
3131 out_uninit_ctrl:
3132 nvme_uninit_ctrl(&dev->ctrl);
3133 nvme_put_ctrl(&dev->ctrl);
3134 return result;
3135 }
3136
nvme_reset_prepare(struct pci_dev * pdev)3137 static void nvme_reset_prepare(struct pci_dev *pdev)
3138 {
3139 struct nvme_dev *dev = pci_get_drvdata(pdev);
3140
3141 /*
3142 * We don't need to check the return value from waiting for the reset
3143 * state as pci_dev device lock is held, making it impossible to race
3144 * with ->remove().
3145 */
3146 nvme_disable_prepare_reset(dev, false);
3147 nvme_sync_queues(&dev->ctrl);
3148 }
3149
nvme_reset_done(struct pci_dev * pdev)3150 static void nvme_reset_done(struct pci_dev *pdev)
3151 {
3152 struct nvme_dev *dev = pci_get_drvdata(pdev);
3153
3154 if (!nvme_try_sched_reset(&dev->ctrl))
3155 flush_work(&dev->ctrl.reset_work);
3156 }
3157
nvme_shutdown(struct pci_dev * pdev)3158 static void nvme_shutdown(struct pci_dev *pdev)
3159 {
3160 struct nvme_dev *dev = pci_get_drvdata(pdev);
3161
3162 nvme_disable_prepare_reset(dev, true);
3163 }
3164
3165 /*
3166 * The driver's remove may be called on a device in a partially initialized
3167 * state. This function must not have any dependencies on the device state in
3168 * order to proceed.
3169 */
nvme_remove(struct pci_dev * pdev)3170 static void nvme_remove(struct pci_dev *pdev)
3171 {
3172 struct nvme_dev *dev = pci_get_drvdata(pdev);
3173
3174 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
3175 pci_set_drvdata(pdev, NULL);
3176
3177 if (!pci_device_is_present(pdev)) {
3178 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
3179 nvme_dev_disable(dev, true);
3180 }
3181
3182 flush_work(&dev->ctrl.reset_work);
3183 nvme_stop_ctrl(&dev->ctrl);
3184 nvme_remove_namespaces(&dev->ctrl);
3185 nvme_dev_disable(dev, true);
3186 nvme_free_host_mem(dev);
3187 nvme_dev_remove_admin(dev);
3188 nvme_dbbuf_dma_free(dev);
3189 nvme_free_queues(dev, 0);
3190 mempool_destroy(dev->iod_mempool);
3191 nvme_release_prp_pools(dev);
3192 nvme_dev_unmap(dev);
3193 nvme_uninit_ctrl(&dev->ctrl);
3194 }
3195
3196 #ifdef CONFIG_PM_SLEEP
nvme_get_power_state(struct nvme_ctrl * ctrl,u32 * ps)3197 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3198 {
3199 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3200 }
3201
nvme_set_power_state(struct nvme_ctrl * ctrl,u32 ps)3202 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3203 {
3204 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3205 }
3206
nvme_resume(struct device * dev)3207 static int nvme_resume(struct device *dev)
3208 {
3209 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3210 struct nvme_ctrl *ctrl = &ndev->ctrl;
3211
3212 if (ndev->last_ps == U32_MAX ||
3213 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
3214 goto reset;
3215 if (ctrl->hmpre && nvme_setup_host_mem(ndev))
3216 goto reset;
3217
3218 return 0;
3219 reset:
3220 return nvme_try_sched_reset(ctrl);
3221 }
3222
nvme_suspend(struct device * dev)3223 static int nvme_suspend(struct device *dev)
3224 {
3225 struct pci_dev *pdev = to_pci_dev(dev);
3226 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3227 struct nvme_ctrl *ctrl = &ndev->ctrl;
3228 int ret = -EBUSY;
3229
3230 ndev->last_ps = U32_MAX;
3231
3232 /*
3233 * The platform does not remove power for a kernel managed suspend so
3234 * use host managed nvme power settings for lowest idle power if
3235 * possible. This should have quicker resume latency than a full device
3236 * shutdown. But if the firmware is involved after the suspend or the
3237 * device does not support any non-default power states, shut down the
3238 * device fully.
3239 *
3240 * If ASPM is not enabled for the device, shut down the device and allow
3241 * the PCI bus layer to put it into D3 in order to take the PCIe link
3242 * down, so as to allow the platform to achieve its minimum low-power
3243 * state (which may not be possible if the link is up).
3244 */
3245 if (pm_suspend_via_firmware() || !ctrl->npss ||
3246 !pcie_aspm_enabled(pdev) ||
3247 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3248 return nvme_disable_prepare_reset(ndev, true);
3249
3250 nvme_start_freeze(ctrl);
3251 nvme_wait_freeze(ctrl);
3252 nvme_sync_queues(ctrl);
3253
3254 if (nvme_ctrl_state(ctrl) != NVME_CTRL_LIVE)
3255 goto unfreeze;
3256
3257 /*
3258 * Host memory access may not be successful in a system suspend state,
3259 * but the specification allows the controller to access memory in a
3260 * non-operational power state.
3261 */
3262 if (ndev->hmb) {
3263 ret = nvme_set_host_mem(ndev, 0);
3264 if (ret < 0)
3265 goto unfreeze;
3266 }
3267
3268 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3269 if (ret < 0)
3270 goto unfreeze;
3271
3272 /*
3273 * A saved state prevents pci pm from generically controlling the
3274 * device's power. If we're using protocol specific settings, we don't
3275 * want pci interfering.
3276 */
3277 pci_save_state(pdev);
3278
3279 ret = nvme_set_power_state(ctrl, ctrl->npss);
3280 if (ret < 0)
3281 goto unfreeze;
3282
3283 if (ret) {
3284 /* discard the saved state */
3285 pci_load_saved_state(pdev, NULL);
3286
3287 /*
3288 * Clearing npss forces a controller reset on resume. The
3289 * correct value will be rediscovered then.
3290 */
3291 ret = nvme_disable_prepare_reset(ndev, true);
3292 ctrl->npss = 0;
3293 }
3294 unfreeze:
3295 nvme_unfreeze(ctrl);
3296 return ret;
3297 }
3298
nvme_simple_suspend(struct device * dev)3299 static int nvme_simple_suspend(struct device *dev)
3300 {
3301 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3302
3303 return nvme_disable_prepare_reset(ndev, true);
3304 }
3305
nvme_simple_resume(struct device * dev)3306 static int nvme_simple_resume(struct device *dev)
3307 {
3308 struct pci_dev *pdev = to_pci_dev(dev);
3309 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3310
3311 return nvme_try_sched_reset(&ndev->ctrl);
3312 }
3313
3314 static const struct dev_pm_ops nvme_dev_pm_ops = {
3315 .suspend = nvme_suspend,
3316 .resume = nvme_resume,
3317 .freeze = nvme_simple_suspend,
3318 .thaw = nvme_simple_resume,
3319 .poweroff = nvme_simple_suspend,
3320 .restore = nvme_simple_resume,
3321 };
3322 #endif /* CONFIG_PM_SLEEP */
3323
nvme_error_detected(struct pci_dev * pdev,pci_channel_state_t state)3324 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3325 pci_channel_state_t state)
3326 {
3327 struct nvme_dev *dev = pci_get_drvdata(pdev);
3328
3329 /*
3330 * A frozen channel requires a reset. When detected, this method will
3331 * shutdown the controller to quiesce. The controller will be restarted
3332 * after the slot reset through driver's slot_reset callback.
3333 */
3334 switch (state) {
3335 case pci_channel_io_normal:
3336 return PCI_ERS_RESULT_CAN_RECOVER;
3337 case pci_channel_io_frozen:
3338 dev_warn(dev->ctrl.device,
3339 "frozen state error detected, reset controller\n");
3340 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING)) {
3341 nvme_dev_disable(dev, true);
3342 return PCI_ERS_RESULT_DISCONNECT;
3343 }
3344 nvme_dev_disable(dev, false);
3345 return PCI_ERS_RESULT_NEED_RESET;
3346 case pci_channel_io_perm_failure:
3347 dev_warn(dev->ctrl.device,
3348 "failure state error detected, request disconnect\n");
3349 return PCI_ERS_RESULT_DISCONNECT;
3350 }
3351 return PCI_ERS_RESULT_NEED_RESET;
3352 }
3353
nvme_slot_reset(struct pci_dev * pdev)3354 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3355 {
3356 struct nvme_dev *dev = pci_get_drvdata(pdev);
3357
3358 dev_info(dev->ctrl.device, "restart after slot reset\n");
3359 pci_restore_state(pdev);
3360 if (!nvme_try_sched_reset(&dev->ctrl))
3361 nvme_unquiesce_io_queues(&dev->ctrl);
3362 return PCI_ERS_RESULT_RECOVERED;
3363 }
3364
nvme_error_resume(struct pci_dev * pdev)3365 static void nvme_error_resume(struct pci_dev *pdev)
3366 {
3367 struct nvme_dev *dev = pci_get_drvdata(pdev);
3368
3369 flush_work(&dev->ctrl.reset_work);
3370 }
3371
3372 static const struct pci_error_handlers nvme_err_handler = {
3373 .error_detected = nvme_error_detected,
3374 .slot_reset = nvme_slot_reset,
3375 .resume = nvme_error_resume,
3376 .reset_prepare = nvme_reset_prepare,
3377 .reset_done = nvme_reset_done,
3378 };
3379
3380 static const struct pci_device_id nvme_id_table[] = {
3381 { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */
3382 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3383 NVME_QUIRK_DEALLOCATE_ZEROES, },
3384 { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */
3385 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3386 NVME_QUIRK_DEALLOCATE_ZEROES, },
3387 { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */
3388 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3389 NVME_QUIRK_DEALLOCATE_ZEROES |
3390 NVME_QUIRK_IGNORE_DEV_SUBNQN |
3391 NVME_QUIRK_BOGUS_NID, },
3392 { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */
3393 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3394 NVME_QUIRK_DEALLOCATE_ZEROES, },
3395 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
3396 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3397 NVME_QUIRK_MEDIUM_PRIO_SQ |
3398 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3399 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3400 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3401 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3402 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
3403 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3404 NVME_QUIRK_DISABLE_WRITE_ZEROES |
3405 NVME_QUIRK_BOGUS_NID, },
3406 { PCI_VDEVICE(REDHAT, 0x0010), /* Qemu emulated controller */
3407 .driver_data = NVME_QUIRK_BOGUS_NID, },
3408 { PCI_DEVICE(0x1217, 0x8760), /* O2 Micro 64GB Steam Deck */
3409 .driver_data = NVME_QUIRK_QDEPTH_ONE },
3410 { PCI_DEVICE(0x126f, 0x2262), /* Silicon Motion generic */
3411 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3412 NVME_QUIRK_BOGUS_NID, },
3413 { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */
3414 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3415 NVME_QUIRK_BOGUS_NID, },
3416 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
3417 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3418 NVME_QUIRK_NO_NS_DESC_LIST, },
3419 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3420 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3421 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3422 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3423 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3424 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3425 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3426 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3427 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
3428 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3429 NVME_QUIRK_DISABLE_WRITE_ZEROES|
3430 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3431 { PCI_DEVICE(0x15b7, 0x5008), /* Sandisk SN530 */
3432 .driver_data = NVME_QUIRK_BROKEN_MSI },
3433 { PCI_DEVICE(0x1987, 0x5012), /* Phison E12 */
3434 .driver_data = NVME_QUIRK_BOGUS_NID, },
3435 { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */
3436 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3437 NVME_QUIRK_BOGUS_NID, },
3438 { PCI_DEVICE(0x1987, 0x5019), /* phison E19 */
3439 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3440 { PCI_DEVICE(0x1987, 0x5021), /* Phison E21 */
3441 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3442 { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */
3443 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3444 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3445 { PCI_DEVICE(0x1cc1, 0x33f8), /* ADATA IM2P33F8ABR1 1 TB */
3446 .driver_data = NVME_QUIRK_BOGUS_NID, },
3447 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
3448 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3449 NVME_QUIRK_BOGUS_NID, },
3450 { PCI_DEVICE(0x10ec, 0x5763), /* ADATA SX6000PNP */
3451 .driver_data = NVME_QUIRK_BOGUS_NID, },
3452 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3453 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3454 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3455 { PCI_DEVICE(0x1344, 0x5407), /* Micron Technology Inc NVMe SSD */
3456 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN },
3457 { PCI_DEVICE(0x1344, 0x6001), /* Micron Nitro NVMe */
3458 .driver_data = NVME_QUIRK_BOGUS_NID, },
3459 { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */
3460 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3461 { PCI_DEVICE(0x1c5c, 0x174a), /* SK Hynix P31 SSD */
3462 .driver_data = NVME_QUIRK_BOGUS_NID, },
3463 { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */
3464 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3465 { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */
3466 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3467 { PCI_DEVICE(0x144d, 0xa80b), /* Samsung PM9B1 256G and 512G */
3468 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES |
3469 NVME_QUIRK_BOGUS_NID, },
3470 { PCI_DEVICE(0x144d, 0xa809), /* Samsung MZALQ256HBJD 256G */
3471 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3472 { PCI_DEVICE(0x144d, 0xa802), /* Samsung SM953 */
3473 .driver_data = NVME_QUIRK_BOGUS_NID, },
3474 { PCI_DEVICE(0x1cc4, 0x6303), /* UMIS RPJTJ512MGE1QDY 512G */
3475 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3476 { PCI_DEVICE(0x1cc4, 0x6302), /* UMIS RPJTJ256MGE1QDY 256G */
3477 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3478 { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */
3479 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3480 { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */
3481 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3482 { PCI_DEVICE(0x2646, 0x5013), /* Kingston KC3000, Kingston FURY Renegade */
3483 .driver_data = NVME_QUIRK_NO_SECONDARY_TEMP_THRESH, },
3484 { PCI_DEVICE(0x2646, 0x5018), /* KINGSTON OM8SFP4xxxxP OS21012 NVMe SSD */
3485 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3486 { PCI_DEVICE(0x2646, 0x5016), /* KINGSTON OM3PGP4xxxxP OS21011 NVMe SSD */
3487 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3488 { PCI_DEVICE(0x2646, 0x501A), /* KINGSTON OM8PGP4xxxxP OS21005 NVMe SSD */
3489 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3490 { PCI_DEVICE(0x2646, 0x501B), /* KINGSTON OM8PGP4xxxxQ OS21005 NVMe SSD */
3491 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3492 { PCI_DEVICE(0x2646, 0x501E), /* KINGSTON OM3PGP4xxxxQ OS21011 NVMe SSD */
3493 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3494 { PCI_DEVICE(0x1f40, 0x1202), /* Netac Technologies Co. NV3000 NVMe SSD */
3495 .driver_data = NVME_QUIRK_BOGUS_NID, },
3496 { PCI_DEVICE(0x1f40, 0x5236), /* Netac Technologies Co. NV7000 NVMe SSD */
3497 .driver_data = NVME_QUIRK_BOGUS_NID, },
3498 { PCI_DEVICE(0x1e4B, 0x1001), /* MAXIO MAP1001 */
3499 .driver_data = NVME_QUIRK_BOGUS_NID, },
3500 { PCI_DEVICE(0x1e4B, 0x1002), /* MAXIO MAP1002 */
3501 .driver_data = NVME_QUIRK_BOGUS_NID, },
3502 { PCI_DEVICE(0x1e4B, 0x1202), /* MAXIO MAP1202 */
3503 .driver_data = NVME_QUIRK_BOGUS_NID, },
3504 { PCI_DEVICE(0x1e4B, 0x1602), /* MAXIO MAP1602 */
3505 .driver_data = NVME_QUIRK_BOGUS_NID, },
3506 { PCI_DEVICE(0x1cc1, 0x5350), /* ADATA XPG GAMMIX S50 */
3507 .driver_data = NVME_QUIRK_BOGUS_NID, },
3508 { PCI_DEVICE(0x1dbe, 0x5236), /* ADATA XPG GAMMIX S70 */
3509 .driver_data = NVME_QUIRK_BOGUS_NID, },
3510 { PCI_DEVICE(0x1e49, 0x0021), /* ZHITAI TiPro5000 NVMe SSD */
3511 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3512 { PCI_DEVICE(0x1e49, 0x0041), /* ZHITAI TiPro7000 NVMe SSD */
3513 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3514 { PCI_DEVICE(0xc0a9, 0x540a), /* Crucial P2 */
3515 .driver_data = NVME_QUIRK_BOGUS_NID, },
3516 { PCI_DEVICE(0x1d97, 0x2263), /* Lexar NM610 */
3517 .driver_data = NVME_QUIRK_BOGUS_NID, },
3518 { PCI_DEVICE(0x1d97, 0x1d97), /* Lexar NM620 */
3519 .driver_data = NVME_QUIRK_BOGUS_NID, },
3520 { PCI_DEVICE(0x1d97, 0x2269), /* Lexar NM760 */
3521 .driver_data = NVME_QUIRK_BOGUS_NID |
3522 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3523 { PCI_DEVICE(0x10ec, 0x5763), /* TEAMGROUP T-FORCE CARDEA ZERO Z330 SSD */
3524 .driver_data = NVME_QUIRK_BOGUS_NID, },
3525 { PCI_DEVICE(0x1e4b, 0x1602), /* HS-SSD-FUTURE 2048G */
3526 .driver_data = NVME_QUIRK_BOGUS_NID, },
3527 { PCI_DEVICE(0x10ec, 0x5765), /* TEAMGROUP MP33 2TB SSD */
3528 .driver_data = NVME_QUIRK_BOGUS_NID, },
3529 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
3530 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3531 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
3532 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3533 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
3534 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3535 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
3536 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3537 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
3538 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3539 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
3540 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3541 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3542 /*
3543 * Fix for the Apple controller found in the MacBook8,1 and
3544 * some MacBook7,1 to avoid controller resets and data loss.
3545 */
3546 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
3547 NVME_QUIRK_QDEPTH_ONE },
3548 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
3549 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3550 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
3551 NVME_QUIRK_128_BYTES_SQES |
3552 NVME_QUIRK_SHARED_TAGS |
3553 NVME_QUIRK_SKIP_CID_GEN |
3554 NVME_QUIRK_IDENTIFY_CNS },
3555 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3556 { 0, }
3557 };
3558 MODULE_DEVICE_TABLE(pci, nvme_id_table);
3559
3560 static struct pci_driver nvme_driver = {
3561 .name = "nvme",
3562 .id_table = nvme_id_table,
3563 .probe = nvme_probe,
3564 .remove = nvme_remove,
3565 .shutdown = nvme_shutdown,
3566 .driver = {
3567 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
3568 #ifdef CONFIG_PM_SLEEP
3569 .pm = &nvme_dev_pm_ops,
3570 #endif
3571 },
3572 .sriov_configure = pci_sriov_configure_simple,
3573 .err_handler = &nvme_err_handler,
3574 };
3575
nvme_init(void)3576 static int __init nvme_init(void)
3577 {
3578 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3579 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3580 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
3581 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
3582 BUILD_BUG_ON(NVME_MAX_SEGS > SGES_PER_PAGE);
3583 BUILD_BUG_ON(sizeof(struct scatterlist) * NVME_MAX_SEGS > PAGE_SIZE);
3584 BUILD_BUG_ON(nvme_pci_npages_prp() > NVME_MAX_NR_ALLOCATIONS);
3585
3586 return pci_register_driver(&nvme_driver);
3587 }
3588
nvme_exit(void)3589 static void __exit nvme_exit(void)
3590 {
3591 pci_unregister_driver(&nvme_driver);
3592 flush_workqueue(nvme_wq);
3593 }
3594
3595 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3596 MODULE_LICENSE("GPL");
3597 MODULE_VERSION("1.0");
3598 module_init(nvme_init);
3599 module_exit(nvme_exit);
3600