1 /*
2 * NVMe block driver based on vfio
3 *
4 * Copyright 2016 - 2018 Red Hat, Inc.
5 *
6 * Authors:
7 * Fam Zheng <famz@redhat.com>
8 * Paolo Bonzini <pbonzini@redhat.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 */
13
14 #include "qemu/osdep.h"
15 #include <linux/vfio.h>
16 #include "qapi/error.h"
17 #include "qobject/qdict.h"
18 #include "qobject/qstring.h"
19 #include "qemu/defer-call.h"
20 #include "qemu/error-report.h"
21 #include "qemu/host-pci-mmio.h"
22 #include "qemu/main-loop.h"
23 #include "qemu/module.h"
24 #include "qemu/cutils.h"
25 #include "qemu/option.h"
26 #include "qemu/memalign.h"
27 #include "qemu/vfio-helpers.h"
28 #include "block/block-io.h"
29 #include "block/block_int.h"
30 #include "system/block-backend.h"
31 #include "system/replay.h"
32 #include "trace.h"
33
34 #include "block/nvme.h"
35
36 #define NVME_SQ_ENTRY_BYTES 64
37 #define NVME_CQ_ENTRY_BYTES 16
38 #define NVME_QUEUE_SIZE 128
39 #define NVME_DOORBELL_SIZE 4096
40
41 /*
42 * We have to leave one slot empty as that is the full queue case where
43 * head == tail + 1.
44 */
45 #define NVME_NUM_REQS (NVME_QUEUE_SIZE - 1)
46
47 typedef struct BDRVNVMeState BDRVNVMeState;
48
49 /* Same index is used for queues and IRQs */
50 #define INDEX_ADMIN 0
51 #define INDEX_IO(n) (1 + n)
52
53 /* This driver shares a single MSIX IRQ for the admin and I/O queues */
54 enum {
55 MSIX_SHARED_IRQ_IDX = 0,
56 MSIX_IRQ_COUNT = 1
57 };
58
59 typedef struct {
60 int32_t head, tail;
61 uint8_t *queue;
62 uint64_t iova;
63 /* Hardware MMIO register */
64 uint32_t *doorbell;
65 } NVMeQueue;
66
67 typedef struct {
68 BlockCompletionFunc *cb;
69 void *opaque;
70 int cid;
71 void *prp_list_page;
72 uint64_t prp_list_iova;
73 int free_req_next; /* q->reqs[] index of next free req */
74 } NVMeRequest;
75
76 typedef struct {
77 QemuMutex lock;
78
79 /* Read from I/O code path, initialized under BQL */
80 BDRVNVMeState *s;
81 int index;
82
83 /* Fields protected by BQL */
84 uint8_t *prp_list_pages;
85
86 /* Fields protected by @lock */
87 CoQueue free_req_queue;
88 NVMeQueue sq, cq;
89 int cq_phase;
90 int free_req_head;
91 NVMeRequest reqs[NVME_NUM_REQS];
92 int need_kick;
93 int inflight;
94
95 /* Thread-safe, no lock necessary */
96 QEMUBH *completion_bh;
97 } NVMeQueuePair;
98
99 struct BDRVNVMeState {
100 AioContext *aio_context;
101 QEMUVFIOState *vfio;
102 void *bar0_wo_map;
103 /* Memory mapped registers */
104 struct {
105 uint32_t sq_tail;
106 uint32_t cq_head;
107 } *doorbells;
108 /* The submission/completion queue pairs.
109 * [0]: admin queue.
110 * [1..]: io queues.
111 */
112 NVMeQueuePair **queues;
113 unsigned queue_count;
114 size_t page_size;
115 /* How many uint32_t elements does each doorbell entry take. */
116 size_t doorbell_scale;
117 bool write_cache_supported;
118 EventNotifier irq_notifier[MSIX_IRQ_COUNT];
119
120 uint64_t nsze; /* Namespace size reported by identify command */
121 int nsid; /* The namespace id to read/write data. */
122 int blkshift;
123
124 uint64_t max_transfer;
125
126 bool supports_write_zeroes;
127 bool supports_discard;
128
129 CoMutex dma_map_lock;
130 CoQueue dma_flush_queue;
131
132 /* Total size of mapped qiov, accessed under dma_map_lock */
133 int dma_map_count;
134
135 /* PCI address (required for nvme_refresh_filename()) */
136 char *device;
137
138 struct {
139 uint64_t completion_errors;
140 uint64_t aligned_accesses;
141 uint64_t unaligned_accesses;
142 } stats;
143 };
144
145 #define NVME_BLOCK_OPT_DEVICE "device"
146 #define NVME_BLOCK_OPT_NAMESPACE "namespace"
147
148 static void nvme_process_completion_bh(void *opaque);
149
150 static QemuOptsList runtime_opts = {
151 .name = "nvme",
152 .head = QTAILQ_HEAD_INITIALIZER(runtime_opts.head),
153 .desc = {
154 {
155 .name = NVME_BLOCK_OPT_DEVICE,
156 .type = QEMU_OPT_STRING,
157 .help = "NVMe PCI device address",
158 },
159 {
160 .name = NVME_BLOCK_OPT_NAMESPACE,
161 .type = QEMU_OPT_NUMBER,
162 .help = "NVMe namespace",
163 },
164 { /* end of list */ }
165 },
166 };
167
168 /* Returns true on success, false on failure. */
nvme_init_queue(BDRVNVMeState * s,NVMeQueue * q,unsigned nentries,size_t entry_bytes,Error ** errp)169 static bool nvme_init_queue(BDRVNVMeState *s, NVMeQueue *q,
170 unsigned nentries, size_t entry_bytes, Error **errp)
171 {
172 ERRP_GUARD();
173 size_t bytes;
174 int r;
175
176 bytes = ROUND_UP(nentries * entry_bytes, qemu_real_host_page_size());
177 q->head = q->tail = 0;
178 q->queue = qemu_try_memalign(qemu_real_host_page_size(), bytes);
179 if (!q->queue) {
180 error_setg(errp, "Cannot allocate queue");
181 return false;
182 }
183 memset(q->queue, 0, bytes);
184 r = qemu_vfio_dma_map(s->vfio, q->queue, bytes, false, &q->iova, errp);
185 if (r) {
186 error_prepend(errp, "Cannot map queue: ");
187 }
188 return r == 0;
189 }
190
nvme_free_queue(NVMeQueue * q)191 static void nvme_free_queue(NVMeQueue *q)
192 {
193 qemu_vfree(q->queue);
194 }
195
nvme_free_queue_pair(NVMeQueuePair * q)196 static void nvme_free_queue_pair(NVMeQueuePair *q)
197 {
198 trace_nvme_free_queue_pair(q->index, q, &q->cq, &q->sq);
199 if (q->completion_bh) {
200 qemu_bh_delete(q->completion_bh);
201 }
202 nvme_free_queue(&q->sq);
203 nvme_free_queue(&q->cq);
204 qemu_vfree(q->prp_list_pages);
205 qemu_mutex_destroy(&q->lock);
206 g_free(q);
207 }
208
nvme_free_req_queue_cb(void * opaque)209 static void nvme_free_req_queue_cb(void *opaque)
210 {
211 NVMeQueuePair *q = opaque;
212
213 qemu_mutex_lock(&q->lock);
214 while (q->free_req_head != -1 &&
215 qemu_co_enter_next(&q->free_req_queue, &q->lock)) {
216 /* Retry waiting requests */
217 }
218 qemu_mutex_unlock(&q->lock);
219 }
220
nvme_create_queue_pair(BDRVNVMeState * s,AioContext * aio_context,unsigned idx,size_t size,Error ** errp)221 static NVMeQueuePair *nvme_create_queue_pair(BDRVNVMeState *s,
222 AioContext *aio_context,
223 unsigned idx, size_t size,
224 Error **errp)
225 {
226 ERRP_GUARD();
227 int i, r;
228 NVMeQueuePair *q;
229 uint64_t prp_list_iova;
230 size_t bytes;
231
232 q = g_try_new0(NVMeQueuePair, 1);
233 if (!q) {
234 error_setg(errp, "Cannot allocate queue pair");
235 return NULL;
236 }
237 trace_nvme_create_queue_pair(idx, q, size, aio_context,
238 event_notifier_get_fd(s->irq_notifier));
239 bytes = QEMU_ALIGN_UP(s->page_size * NVME_NUM_REQS,
240 qemu_real_host_page_size());
241 q->prp_list_pages = qemu_try_memalign(qemu_real_host_page_size(), bytes);
242 if (!q->prp_list_pages) {
243 error_setg(errp, "Cannot allocate PRP page list");
244 goto fail;
245 }
246 memset(q->prp_list_pages, 0, bytes);
247 qemu_mutex_init(&q->lock);
248 q->s = s;
249 q->index = idx;
250 qemu_co_queue_init(&q->free_req_queue);
251 q->completion_bh = aio_bh_new(aio_context, nvme_process_completion_bh, q);
252 r = qemu_vfio_dma_map(s->vfio, q->prp_list_pages, bytes,
253 false, &prp_list_iova, errp);
254 if (r) {
255 error_prepend(errp, "Cannot map buffer for DMA: ");
256 goto fail;
257 }
258 q->free_req_head = -1;
259 for (i = 0; i < NVME_NUM_REQS; i++) {
260 NVMeRequest *req = &q->reqs[i];
261 req->cid = i + 1;
262 req->free_req_next = q->free_req_head;
263 q->free_req_head = i;
264 req->prp_list_page = q->prp_list_pages + i * s->page_size;
265 req->prp_list_iova = prp_list_iova + i * s->page_size;
266 }
267
268 if (!nvme_init_queue(s, &q->sq, size, NVME_SQ_ENTRY_BYTES, errp)) {
269 goto fail;
270 }
271 q->sq.doorbell = &s->doorbells[idx * s->doorbell_scale].sq_tail;
272
273 if (!nvme_init_queue(s, &q->cq, size, NVME_CQ_ENTRY_BYTES, errp)) {
274 goto fail;
275 }
276 q->cq.doorbell = &s->doorbells[idx * s->doorbell_scale].cq_head;
277
278 return q;
279 fail:
280 nvme_free_queue_pair(q);
281 return NULL;
282 }
283
284 /* With q->lock */
nvme_kick(NVMeQueuePair * q)285 static void nvme_kick(NVMeQueuePair *q)
286 {
287 BDRVNVMeState *s = q->s;
288
289 if (!q->need_kick) {
290 return;
291 }
292 trace_nvme_kick(s, q->index);
293 assert(!(q->sq.tail & 0xFF00));
294 /* Fence the write to submission queue entry before notifying the device. */
295 smp_wmb();
296 host_pci_stl_le_p(q->sq.doorbell, q->sq.tail);
297 q->inflight += q->need_kick;
298 q->need_kick = 0;
299 }
300
nvme_get_free_req_nofail_locked(NVMeQueuePair * q)301 static NVMeRequest *nvme_get_free_req_nofail_locked(NVMeQueuePair *q)
302 {
303 NVMeRequest *req;
304
305 req = &q->reqs[q->free_req_head];
306 q->free_req_head = req->free_req_next;
307 req->free_req_next = -1;
308 return req;
309 }
310
311 /* Return a free request element if any, otherwise return NULL. */
nvme_get_free_req_nowait(NVMeQueuePair * q)312 static NVMeRequest *nvme_get_free_req_nowait(NVMeQueuePair *q)
313 {
314 QEMU_LOCK_GUARD(&q->lock);
315 if (q->free_req_head == -1) {
316 return NULL;
317 }
318 return nvme_get_free_req_nofail_locked(q);
319 }
320
321 /*
322 * Wait for a free request to become available if necessary, then
323 * return it.
324 */
nvme_get_free_req(NVMeQueuePair * q)325 static coroutine_fn NVMeRequest *nvme_get_free_req(NVMeQueuePair *q)
326 {
327 QEMU_LOCK_GUARD(&q->lock);
328
329 while (q->free_req_head == -1) {
330 trace_nvme_free_req_queue_wait(q->s, q->index);
331 qemu_co_queue_wait(&q->free_req_queue, &q->lock);
332 }
333
334 return nvme_get_free_req_nofail_locked(q);
335 }
336
337 /* With q->lock */
nvme_put_free_req_locked(NVMeQueuePair * q,NVMeRequest * req)338 static void nvme_put_free_req_locked(NVMeQueuePair *q, NVMeRequest *req)
339 {
340 req->free_req_next = q->free_req_head;
341 q->free_req_head = req - q->reqs;
342 }
343
344 /* With q->lock */
nvme_wake_free_req_locked(NVMeQueuePair * q)345 static void nvme_wake_free_req_locked(NVMeQueuePair *q)
346 {
347 if (!qemu_co_queue_empty(&q->free_req_queue)) {
348 replay_bh_schedule_oneshot_event(q->s->aio_context,
349 nvme_free_req_queue_cb, q);
350 }
351 }
352
353 /* Insert a request in the freelist and wake waiters */
nvme_put_free_req_and_wake(NVMeQueuePair * q,NVMeRequest * req)354 static void nvme_put_free_req_and_wake(NVMeQueuePair *q, NVMeRequest *req)
355 {
356 qemu_mutex_lock(&q->lock);
357 nvme_put_free_req_locked(q, req);
358 nvme_wake_free_req_locked(q);
359 qemu_mutex_unlock(&q->lock);
360 }
361
nvme_translate_error(const NvmeCqe * c)362 static inline int nvme_translate_error(const NvmeCqe *c)
363 {
364 uint16_t status = (le16_to_cpu(c->status) >> 1) & 0xFF;
365 if (status) {
366 trace_nvme_error(le32_to_cpu(c->result),
367 le16_to_cpu(c->sq_head),
368 le16_to_cpu(c->sq_id),
369 le16_to_cpu(c->cid),
370 le16_to_cpu(status));
371 }
372 switch (status) {
373 case 0:
374 return 0;
375 case 1:
376 return -ENOSYS;
377 case 2:
378 return -EINVAL;
379 default:
380 return -EIO;
381 }
382 }
383
384 /* With q->lock */
nvme_process_completion(NVMeQueuePair * q)385 static bool nvme_process_completion(NVMeQueuePair *q)
386 {
387 BDRVNVMeState *s = q->s;
388 bool progress = false;
389 NVMeRequest *preq;
390 NVMeRequest req;
391 NvmeCqe *c;
392
393 trace_nvme_process_completion(s, q->index, q->inflight);
394
395 /*
396 * Support re-entrancy when a request cb() function invokes aio_poll().
397 * Pending completions must be visible to aio_poll() so that a cb()
398 * function can wait for the completion of another request.
399 *
400 * The aio_poll() loop will execute our BH and we'll resume completion
401 * processing there.
402 */
403 qemu_bh_schedule(q->completion_bh);
404
405 assert(q->inflight >= 0);
406 while (q->inflight) {
407 int ret;
408 int16_t cid;
409
410 c = (NvmeCqe *)&q->cq.queue[q->cq.head * NVME_CQ_ENTRY_BYTES];
411 if ((le16_to_cpu(c->status) & 0x1) == q->cq_phase) {
412 break;
413 }
414 ret = nvme_translate_error(c);
415 if (ret) {
416 s->stats.completion_errors++;
417 }
418 q->cq.head = (q->cq.head + 1) % NVME_QUEUE_SIZE;
419 if (!q->cq.head) {
420 q->cq_phase = !q->cq_phase;
421 }
422 cid = le16_to_cpu(c->cid);
423 if (cid == 0 || cid > NVME_NUM_REQS) {
424 warn_report("NVMe: Unexpected CID in completion queue: %" PRIu32
425 ", should be within: 1..%u inclusively", cid,
426 NVME_NUM_REQS);
427 continue;
428 }
429 trace_nvme_complete_command(s, q->index, cid);
430 preq = &q->reqs[cid - 1];
431 req = *preq;
432 assert(req.cid == cid);
433 assert(req.cb);
434 nvme_put_free_req_locked(q, preq);
435 preq->cb = preq->opaque = NULL;
436 q->inflight--;
437 qemu_mutex_unlock(&q->lock);
438 req.cb(req.opaque, ret);
439 qemu_mutex_lock(&q->lock);
440 progress = true;
441 }
442 if (progress) {
443 /* Notify the device so it can post more completions. */
444 smp_mb_release();
445 host_pci_stl_le_p(q->cq.doorbell, q->cq.head);
446 nvme_wake_free_req_locked(q);
447 }
448
449 qemu_bh_cancel(q->completion_bh);
450
451 return progress;
452 }
453
nvme_process_completion_bh(void * opaque)454 static void nvme_process_completion_bh(void *opaque)
455 {
456 NVMeQueuePair *q = opaque;
457
458 /*
459 * We're being invoked because a nvme_process_completion() cb() function
460 * called aio_poll(). The callback may be waiting for further completions
461 * so notify the device that it has space to fill in more completions now.
462 */
463 smp_mb_release();
464 host_pci_stl_le_p(q->cq.doorbell, q->cq.head);
465 nvme_wake_free_req_locked(q);
466
467 nvme_process_completion(q);
468 }
469
nvme_trace_command(const NvmeCmd * cmd)470 static void nvme_trace_command(const NvmeCmd *cmd)
471 {
472 int i;
473
474 if (!trace_event_get_state_backends(TRACE_NVME_SUBMIT_COMMAND_RAW)) {
475 return;
476 }
477 for (i = 0; i < 8; ++i) {
478 uint8_t *cmdp = (uint8_t *)cmd + i * 8;
479 trace_nvme_submit_command_raw(cmdp[0], cmdp[1], cmdp[2], cmdp[3],
480 cmdp[4], cmdp[5], cmdp[6], cmdp[7]);
481 }
482 }
483
nvme_kick_and_check_completions(void * opaque)484 static void nvme_kick_and_check_completions(void *opaque)
485 {
486 NVMeQueuePair *q = opaque;
487
488 QEMU_LOCK_GUARD(&q->lock);
489 nvme_kick(q);
490 nvme_process_completion(q);
491 }
492
nvme_deferred_fn(void * opaque)493 static void nvme_deferred_fn(void *opaque)
494 {
495 NVMeQueuePair *q = opaque;
496
497 if (qemu_get_current_aio_context() == q->s->aio_context) {
498 nvme_kick_and_check_completions(q);
499 } else {
500 aio_bh_schedule_oneshot(q->s->aio_context,
501 nvme_kick_and_check_completions, q);
502 }
503 }
504
nvme_submit_command(NVMeQueuePair * q,NVMeRequest * req,NvmeCmd * cmd,BlockCompletionFunc cb,void * opaque)505 static void nvme_submit_command(NVMeQueuePair *q, NVMeRequest *req,
506 NvmeCmd *cmd, BlockCompletionFunc cb,
507 void *opaque)
508 {
509 assert(!req->cb);
510 req->cb = cb;
511 req->opaque = opaque;
512 cmd->cid = cpu_to_le16(req->cid);
513
514 trace_nvme_submit_command(q->s, q->index, req->cid);
515 nvme_trace_command(cmd);
516 qemu_mutex_lock(&q->lock);
517 memcpy((uint8_t *)q->sq.queue +
518 q->sq.tail * NVME_SQ_ENTRY_BYTES, cmd, sizeof(*cmd));
519 q->sq.tail = (q->sq.tail + 1) % NVME_QUEUE_SIZE;
520 q->need_kick++;
521 qemu_mutex_unlock(&q->lock);
522
523 defer_call(nvme_deferred_fn, q);
524 }
525
nvme_admin_cmd_sync_cb(void * opaque,int ret)526 static void nvme_admin_cmd_sync_cb(void *opaque, int ret)
527 {
528 int *pret = opaque;
529 *pret = ret;
530 aio_wait_kick();
531 }
532
nvme_admin_cmd_sync(BlockDriverState * bs,NvmeCmd * cmd)533 static int nvme_admin_cmd_sync(BlockDriverState *bs, NvmeCmd *cmd)
534 {
535 BDRVNVMeState *s = bs->opaque;
536 NVMeQueuePair *q = s->queues[INDEX_ADMIN];
537 AioContext *aio_context = bdrv_get_aio_context(bs);
538 NVMeRequest *req;
539 int ret = -EINPROGRESS;
540 req = nvme_get_free_req_nowait(q);
541 if (!req) {
542 return -EBUSY;
543 }
544 nvme_submit_command(q, req, cmd, nvme_admin_cmd_sync_cb, &ret);
545
546 AIO_WAIT_WHILE(aio_context, ret == -EINPROGRESS);
547 return ret;
548 }
549
550 /* Returns true on success, false on failure. */
nvme_identify(BlockDriverState * bs,int namespace,Error ** errp)551 static bool nvme_identify(BlockDriverState *bs, int namespace, Error **errp)
552 {
553 ERRP_GUARD();
554 BDRVNVMeState *s = bs->opaque;
555 bool ret = false;
556 QEMU_AUTO_VFREE union {
557 NvmeIdCtrl ctrl;
558 NvmeIdNs ns;
559 } *id = NULL;
560 NvmeLBAF *lbaf;
561 uint16_t oncs;
562 int r;
563 uint64_t iova;
564 NvmeCmd cmd = {
565 .opcode = NVME_ADM_CMD_IDENTIFY,
566 .cdw10 = cpu_to_le32(0x1),
567 };
568 size_t id_size = QEMU_ALIGN_UP(sizeof(*id), qemu_real_host_page_size());
569
570 id = qemu_try_memalign(qemu_real_host_page_size(), id_size);
571 if (!id) {
572 error_setg(errp, "Cannot allocate buffer for identify response");
573 goto out;
574 }
575 r = qemu_vfio_dma_map(s->vfio, id, id_size, true, &iova, errp);
576 if (r) {
577 error_prepend(errp, "Cannot map buffer for DMA: ");
578 goto out;
579 }
580
581 memset(id, 0, id_size);
582 cmd.dptr.prp1 = cpu_to_le64(iova);
583 if (nvme_admin_cmd_sync(bs, &cmd)) {
584 error_setg(errp, "Failed to identify controller");
585 goto out;
586 }
587
588 if (le32_to_cpu(id->ctrl.nn) < namespace) {
589 error_setg(errp, "Invalid namespace");
590 goto out;
591 }
592 s->write_cache_supported = le32_to_cpu(id->ctrl.vwc) & 0x1;
593 s->max_transfer = (id->ctrl.mdts ? 1 << id->ctrl.mdts : 0) * s->page_size;
594 /* For now the page list buffer per command is one page, to hold at most
595 * s->page_size / sizeof(uint64_t) entries. */
596 s->max_transfer = MIN_NON_ZERO(s->max_transfer,
597 s->page_size / sizeof(uint64_t) * s->page_size);
598
599 oncs = le16_to_cpu(id->ctrl.oncs);
600 s->supports_write_zeroes = !!(oncs & NVME_ONCS_WRITE_ZEROES);
601 s->supports_discard = !!(oncs & NVME_ONCS_DSM);
602
603 memset(id, 0, id_size);
604 cmd.cdw10 = 0;
605 cmd.nsid = cpu_to_le32(namespace);
606 if (nvme_admin_cmd_sync(bs, &cmd)) {
607 error_setg(errp, "Failed to identify namespace");
608 goto out;
609 }
610
611 s->nsze = le64_to_cpu(id->ns.nsze);
612 lbaf = &id->ns.lbaf[NVME_ID_NS_FLBAS_INDEX(id->ns.flbas)];
613
614 if (NVME_ID_NS_DLFEAT_WRITE_ZEROES(id->ns.dlfeat) &&
615 NVME_ID_NS_DLFEAT_READ_BEHAVIOR(id->ns.dlfeat) ==
616 NVME_ID_NS_DLFEAT_READ_BEHAVIOR_ZEROES) {
617 bs->supported_write_flags |= BDRV_REQ_MAY_UNMAP;
618 }
619
620 if (lbaf->ms) {
621 error_setg(errp, "Namespaces with metadata are not yet supported");
622 goto out;
623 }
624
625 if (lbaf->ds < BDRV_SECTOR_BITS || lbaf->ds > 12 ||
626 (1 << lbaf->ds) > s->page_size)
627 {
628 error_setg(errp, "Namespace has unsupported block size (2^%d)",
629 lbaf->ds);
630 goto out;
631 }
632
633 ret = true;
634 s->blkshift = lbaf->ds;
635 out:
636 qemu_vfio_dma_unmap(s->vfio, id);
637
638 return ret;
639 }
640
nvme_poll_queue(NVMeQueuePair * q)641 static void nvme_poll_queue(NVMeQueuePair *q)
642 {
643 const size_t cqe_offset = q->cq.head * NVME_CQ_ENTRY_BYTES;
644 NvmeCqe *cqe = (NvmeCqe *)&q->cq.queue[cqe_offset];
645
646 trace_nvme_poll_queue(q->s, q->index);
647 /*
648 * Do an early check for completions. q->lock isn't needed because
649 * nvme_process_completion() only runs in the event loop thread and
650 * cannot race with itself.
651 */
652 if ((le16_to_cpu(cqe->status) & 0x1) == q->cq_phase) {
653 return;
654 }
655
656 qemu_mutex_lock(&q->lock);
657 while (nvme_process_completion(q)) {
658 /* Keep polling */
659 }
660 qemu_mutex_unlock(&q->lock);
661 }
662
nvme_poll_queues(BDRVNVMeState * s)663 static void nvme_poll_queues(BDRVNVMeState *s)
664 {
665 int i;
666
667 for (i = 0; i < s->queue_count; i++) {
668 nvme_poll_queue(s->queues[i]);
669 }
670 }
671
nvme_handle_event(EventNotifier * n)672 static void nvme_handle_event(EventNotifier *n)
673 {
674 BDRVNVMeState *s = container_of(n, BDRVNVMeState,
675 irq_notifier[MSIX_SHARED_IRQ_IDX]);
676
677 trace_nvme_handle_event(s);
678 event_notifier_test_and_clear(n);
679 nvme_poll_queues(s);
680 }
681
nvme_add_io_queue(BlockDriverState * bs,Error ** errp)682 static bool nvme_add_io_queue(BlockDriverState *bs, Error **errp)
683 {
684 BDRVNVMeState *s = bs->opaque;
685 unsigned n = s->queue_count;
686 NVMeQueuePair *q;
687 NvmeCmd cmd;
688 unsigned queue_size = NVME_QUEUE_SIZE;
689
690 assert(n <= UINT16_MAX);
691 q = nvme_create_queue_pair(s, bdrv_get_aio_context(bs),
692 n, queue_size, errp);
693 if (!q) {
694 return false;
695 }
696 cmd = (NvmeCmd) {
697 .opcode = NVME_ADM_CMD_CREATE_CQ,
698 .dptr.prp1 = cpu_to_le64(q->cq.iova),
699 .cdw10 = cpu_to_le32(((queue_size - 1) << 16) | n),
700 .cdw11 = cpu_to_le32(NVME_CQ_IEN | NVME_CQ_PC),
701 };
702 if (nvme_admin_cmd_sync(bs, &cmd)) {
703 error_setg(errp, "Failed to create CQ io queue [%u]", n);
704 goto out_error;
705 }
706 cmd = (NvmeCmd) {
707 .opcode = NVME_ADM_CMD_CREATE_SQ,
708 .dptr.prp1 = cpu_to_le64(q->sq.iova),
709 .cdw10 = cpu_to_le32(((queue_size - 1) << 16) | n),
710 .cdw11 = cpu_to_le32(NVME_SQ_PC | (n << 16)),
711 };
712 if (nvme_admin_cmd_sync(bs, &cmd)) {
713 error_setg(errp, "Failed to create SQ io queue [%u]", n);
714 goto out_error;
715 }
716 s->queues = g_renew(NVMeQueuePair *, s->queues, n + 1);
717 s->queues[n] = q;
718 s->queue_count++;
719 return true;
720 out_error:
721 nvme_free_queue_pair(q);
722 return false;
723 }
724
nvme_poll_cb(void * opaque)725 static bool nvme_poll_cb(void *opaque)
726 {
727 EventNotifier *e = opaque;
728 BDRVNVMeState *s = container_of(e, BDRVNVMeState,
729 irq_notifier[MSIX_SHARED_IRQ_IDX]);
730 int i;
731
732 for (i = 0; i < s->queue_count; i++) {
733 NVMeQueuePair *q = s->queues[i];
734 const size_t cqe_offset = q->cq.head * NVME_CQ_ENTRY_BYTES;
735 NvmeCqe *cqe = (NvmeCqe *)&q->cq.queue[cqe_offset];
736
737 /*
738 * q->lock isn't needed because nvme_process_completion() only runs in
739 * the event loop thread and cannot race with itself.
740 */
741 if ((le16_to_cpu(cqe->status) & 0x1) != q->cq_phase) {
742 return true;
743 }
744 }
745 return false;
746 }
747
nvme_poll_ready(EventNotifier * e)748 static void nvme_poll_ready(EventNotifier *e)
749 {
750 BDRVNVMeState *s = container_of(e, BDRVNVMeState,
751 irq_notifier[MSIX_SHARED_IRQ_IDX]);
752
753 nvme_poll_queues(s);
754 }
755
nvme_init(BlockDriverState * bs,const char * device,int namespace,Error ** errp)756 static int nvme_init(BlockDriverState *bs, const char *device, int namespace,
757 Error **errp)
758 {
759 BDRVNVMeState *s = bs->opaque;
760 NVMeQueuePair *q;
761 AioContext *aio_context = bdrv_get_aio_context(bs);
762 int ret;
763 uint64_t cap;
764 uint32_t ver;
765 uint32_t cc;
766 uint64_t timeout_ms;
767 uint64_t deadline, now;
768 NvmeBar *regs = NULL;
769
770 qemu_co_mutex_init(&s->dma_map_lock);
771 qemu_co_queue_init(&s->dma_flush_queue);
772 s->device = g_strdup(device);
773 s->nsid = namespace;
774 s->aio_context = bdrv_get_aio_context(bs);
775 ret = event_notifier_init(&s->irq_notifier[MSIX_SHARED_IRQ_IDX], 0);
776 if (ret) {
777 error_setg(errp, "Failed to init event notifier");
778 return ret;
779 }
780
781 s->vfio = qemu_vfio_open_pci(device, errp);
782 if (!s->vfio) {
783 ret = -EINVAL;
784 goto out;
785 }
786
787 regs = qemu_vfio_pci_map_bar(s->vfio, 0, 0, sizeof(NvmeBar),
788 PROT_READ | PROT_WRITE, errp);
789 if (!regs) {
790 ret = -EINVAL;
791 goto out;
792 }
793 /* Perform initialize sequence as described in NVMe spec "7.6.1
794 * Initialization". */
795
796 cap = host_pci_ldq_le_p(®s->cap);
797 trace_nvme_controller_capability_raw(cap);
798 trace_nvme_controller_capability("Maximum Queue Entries Supported",
799 1 + NVME_CAP_MQES(cap));
800 trace_nvme_controller_capability("Contiguous Queues Required",
801 NVME_CAP_CQR(cap));
802 trace_nvme_controller_capability("Doorbell Stride",
803 1 << (2 + NVME_CAP_DSTRD(cap)));
804 trace_nvme_controller_capability("Subsystem Reset Supported",
805 NVME_CAP_NSSRS(cap));
806 trace_nvme_controller_capability("Memory Page Size Minimum",
807 1 << (12 + NVME_CAP_MPSMIN(cap)));
808 trace_nvme_controller_capability("Memory Page Size Maximum",
809 1 << (12 + NVME_CAP_MPSMAX(cap)));
810 if (!NVME_CAP_CSS(cap)) {
811 error_setg(errp, "Device doesn't support NVMe command set");
812 ret = -EINVAL;
813 goto out;
814 }
815
816 s->page_size = 1u << (12 + NVME_CAP_MPSMIN(cap));
817 s->doorbell_scale = (4 << NVME_CAP_DSTRD(cap)) / sizeof(uint32_t);
818 bs->bl.opt_mem_alignment = s->page_size;
819 bs->bl.request_alignment = s->page_size;
820 timeout_ms = MIN(500 * NVME_CAP_TO(cap), 30000);
821
822 ver = host_pci_ldl_le_p(®s->vs);
823 trace_nvme_controller_spec_version(extract32(ver, 16, 16),
824 extract32(ver, 8, 8),
825 extract32(ver, 0, 8));
826
827 /* Reset device to get a clean state. */
828 cc = host_pci_ldl_le_p(®s->cc);
829 host_pci_stl_le_p(®s->cc, cc & 0xFE);
830 /* Wait for CSTS.RDY = 0. */
831 deadline = qemu_clock_get_ns(QEMU_CLOCK_REALTIME) + timeout_ms * SCALE_MS;
832 while (NVME_CSTS_RDY(host_pci_ldl_le_p(®s->csts))) {
833 if (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) > deadline) {
834 error_setg(errp, "Timeout while waiting for device to reset (%"
835 PRId64 " ms)",
836 timeout_ms);
837 ret = -ETIMEDOUT;
838 goto out;
839 }
840 }
841
842 s->bar0_wo_map = qemu_vfio_pci_map_bar(s->vfio, 0, 0,
843 sizeof(NvmeBar) + NVME_DOORBELL_SIZE,
844 PROT_WRITE, errp);
845 s->doorbells = (void *)((uintptr_t)s->bar0_wo_map + sizeof(NvmeBar));
846 if (!s->doorbells) {
847 ret = -EINVAL;
848 goto out;
849 }
850
851 /* Set up admin queue. */
852 s->queues = g_new(NVMeQueuePair *, 1);
853 q = nvme_create_queue_pair(s, aio_context, 0, NVME_QUEUE_SIZE, errp);
854 if (!q) {
855 ret = -EINVAL;
856 goto out;
857 }
858 s->queues[INDEX_ADMIN] = q;
859 s->queue_count = 1;
860 QEMU_BUILD_BUG_ON((NVME_QUEUE_SIZE - 1) & 0xF000);
861 host_pci_stl_le_p(®s->aqa,
862 ((NVME_QUEUE_SIZE - 1) << AQA_ACQS_SHIFT) |
863 ((NVME_QUEUE_SIZE - 1) << AQA_ASQS_SHIFT));
864 host_pci_stq_le_p(®s->asq, q->sq.iova);
865 host_pci_stq_le_p(®s->acq, q->cq.iova);
866
867 /* After setting up all control registers we can enable device now. */
868 host_pci_stl_le_p(®s->cc,
869 (ctz32(NVME_CQ_ENTRY_BYTES) << CC_IOCQES_SHIFT) |
870 (ctz32(NVME_SQ_ENTRY_BYTES) << CC_IOSQES_SHIFT) |
871 CC_EN_MASK);
872 /* Wait for CSTS.RDY = 1. */
873 now = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
874 deadline = now + timeout_ms * SCALE_MS;
875 while (!NVME_CSTS_RDY(host_pci_ldl_le_p(®s->csts))) {
876 if (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) > deadline) {
877 error_setg(errp, "Timeout while waiting for device to start (%"
878 PRId64 " ms)",
879 timeout_ms);
880 ret = -ETIMEDOUT;
881 goto out;
882 }
883 }
884
885 ret = qemu_vfio_pci_init_irq(s->vfio, s->irq_notifier,
886 VFIO_PCI_MSIX_IRQ_INDEX, errp);
887 if (ret) {
888 goto out;
889 }
890 aio_set_event_notifier(bdrv_get_aio_context(bs),
891 &s->irq_notifier[MSIX_SHARED_IRQ_IDX],
892 nvme_handle_event, nvme_poll_cb,
893 nvme_poll_ready);
894
895 if (!nvme_identify(bs, namespace, errp)) {
896 ret = -EIO;
897 goto out;
898 }
899
900 /* Set up command queues. */
901 if (!nvme_add_io_queue(bs, errp)) {
902 ret = -EIO;
903 }
904 out:
905 if (regs) {
906 qemu_vfio_pci_unmap_bar(s->vfio, 0, (void *)regs, 0, sizeof(NvmeBar));
907 }
908
909 /* Cleaning up is done in nvme_open() upon error. */
910 return ret;
911 }
912
913 /* Parse a filename in the format of nvme://XXXX:XX:XX.X/X. Example:
914 *
915 * nvme://0000:44:00.0/1
916 *
917 * where the "nvme://" is a fixed form of the protocol prefix, the middle part
918 * is the PCI address, and the last part is the namespace number starting from
919 * 1 according to the NVMe spec. */
nvme_parse_filename(const char * filename,QDict * options,Error ** errp)920 static void nvme_parse_filename(const char *filename, QDict *options,
921 Error **errp)
922 {
923 int pref = strlen("nvme://");
924
925 if (strlen(filename) > pref && !strncmp(filename, "nvme://", pref)) {
926 const char *tmp = filename + pref;
927 char *device;
928 const char *namespace;
929 unsigned long ns;
930 const char *slash = strchr(tmp, '/');
931 if (!slash) {
932 qdict_put_str(options, NVME_BLOCK_OPT_DEVICE, tmp);
933 return;
934 }
935 device = g_strndup(tmp, slash - tmp);
936 qdict_put_str(options, NVME_BLOCK_OPT_DEVICE, device);
937 g_free(device);
938 namespace = slash + 1;
939 if (*namespace && qemu_strtoul(namespace, NULL, 10, &ns)) {
940 error_setg(errp, "Invalid namespace '%s', positive number expected",
941 namespace);
942 return;
943 }
944 qdict_put_str(options, NVME_BLOCK_OPT_NAMESPACE,
945 *namespace ? namespace : "1");
946 }
947 }
948
nvme_enable_disable_write_cache(BlockDriverState * bs,bool enable,Error ** errp)949 static int nvme_enable_disable_write_cache(BlockDriverState *bs, bool enable,
950 Error **errp)
951 {
952 int ret;
953 BDRVNVMeState *s = bs->opaque;
954 NvmeCmd cmd = {
955 .opcode = NVME_ADM_CMD_SET_FEATURES,
956 .nsid = cpu_to_le32(s->nsid),
957 .cdw10 = cpu_to_le32(0x06),
958 .cdw11 = cpu_to_le32(enable ? 0x01 : 0x00),
959 };
960
961 ret = nvme_admin_cmd_sync(bs, &cmd);
962 if (ret) {
963 error_setg(errp, "Failed to configure NVMe write cache");
964 }
965 return ret;
966 }
967
nvme_close(BlockDriverState * bs)968 static void nvme_close(BlockDriverState *bs)
969 {
970 BDRVNVMeState *s = bs->opaque;
971
972 for (unsigned i = 0; i < s->queue_count; ++i) {
973 nvme_free_queue_pair(s->queues[i]);
974 }
975 g_free(s->queues);
976 aio_set_event_notifier(bdrv_get_aio_context(bs),
977 &s->irq_notifier[MSIX_SHARED_IRQ_IDX],
978 NULL, NULL, NULL);
979 event_notifier_cleanup(&s->irq_notifier[MSIX_SHARED_IRQ_IDX]);
980 qemu_vfio_pci_unmap_bar(s->vfio, 0, s->bar0_wo_map,
981 0, sizeof(NvmeBar) + NVME_DOORBELL_SIZE);
982 qemu_vfio_close(s->vfio);
983
984 g_free(s->device);
985 }
986
nvme_open(BlockDriverState * bs,QDict * options,int flags,Error ** errp)987 static int nvme_open(BlockDriverState *bs, QDict *options, int flags,
988 Error **errp)
989 {
990 const char *device;
991 QemuOpts *opts;
992 int namespace;
993 int ret;
994 BDRVNVMeState *s = bs->opaque;
995
996 bs->supported_write_flags = BDRV_REQ_FUA;
997
998 opts = qemu_opts_create(&runtime_opts, NULL, 0, &error_abort);
999 qemu_opts_absorb_qdict(opts, options, &error_abort);
1000 device = qemu_opt_get(opts, NVME_BLOCK_OPT_DEVICE);
1001 if (!device) {
1002 error_setg(errp, "'" NVME_BLOCK_OPT_DEVICE "' option is required");
1003 qemu_opts_del(opts);
1004 return -EINVAL;
1005 }
1006
1007 namespace = qemu_opt_get_number(opts, NVME_BLOCK_OPT_NAMESPACE, 1);
1008 ret = nvme_init(bs, device, namespace, errp);
1009 qemu_opts_del(opts);
1010 if (ret) {
1011 goto fail;
1012 }
1013 if (flags & BDRV_O_NOCACHE) {
1014 if (!s->write_cache_supported) {
1015 error_setg(errp,
1016 "NVMe controller doesn't support write cache configuration");
1017 ret = -EINVAL;
1018 } else {
1019 ret = nvme_enable_disable_write_cache(bs, !(flags & BDRV_O_NOCACHE),
1020 errp);
1021 }
1022 if (ret) {
1023 goto fail;
1024 }
1025 }
1026 return 0;
1027 fail:
1028 nvme_close(bs);
1029 return ret;
1030 }
1031
nvme_co_getlength(BlockDriverState * bs)1032 static int64_t coroutine_fn nvme_co_getlength(BlockDriverState *bs)
1033 {
1034 BDRVNVMeState *s = bs->opaque;
1035 return s->nsze << s->blkshift;
1036 }
1037
nvme_get_blocksize(BlockDriverState * bs)1038 static uint32_t nvme_get_blocksize(BlockDriverState *bs)
1039 {
1040 BDRVNVMeState *s = bs->opaque;
1041 assert(s->blkshift >= BDRV_SECTOR_BITS && s->blkshift <= 12);
1042 return UINT32_C(1) << s->blkshift;
1043 }
1044
nvme_probe_blocksizes(BlockDriverState * bs,BlockSizes * bsz)1045 static int nvme_probe_blocksizes(BlockDriverState *bs, BlockSizes *bsz)
1046 {
1047 uint32_t blocksize = nvme_get_blocksize(bs);
1048 bsz->phys = blocksize;
1049 bsz->log = blocksize;
1050 return 0;
1051 }
1052
1053 /* Called with s->dma_map_lock */
nvme_cmd_unmap_qiov(BlockDriverState * bs,QEMUIOVector * qiov)1054 static coroutine_fn int nvme_cmd_unmap_qiov(BlockDriverState *bs,
1055 QEMUIOVector *qiov)
1056 {
1057 int r = 0;
1058 BDRVNVMeState *s = bs->opaque;
1059
1060 s->dma_map_count -= qiov->size;
1061 if (!s->dma_map_count && !qemu_co_queue_empty(&s->dma_flush_queue)) {
1062 r = qemu_vfio_dma_reset_temporary(s->vfio);
1063 if (!r) {
1064 qemu_co_queue_restart_all(&s->dma_flush_queue);
1065 }
1066 }
1067 return r;
1068 }
1069
1070 /* Called with s->dma_map_lock */
nvme_cmd_map_qiov(BlockDriverState * bs,NvmeCmd * cmd,NVMeRequest * req,QEMUIOVector * qiov)1071 static coroutine_fn int nvme_cmd_map_qiov(BlockDriverState *bs, NvmeCmd *cmd,
1072 NVMeRequest *req, QEMUIOVector *qiov)
1073 {
1074 BDRVNVMeState *s = bs->opaque;
1075 uint64_t *pagelist = req->prp_list_page;
1076 int i, j, r;
1077 int entries = 0;
1078 Error *local_err = NULL, **errp = NULL;
1079
1080 assert(qiov->size);
1081 assert(QEMU_IS_ALIGNED(qiov->size, s->page_size));
1082 assert(qiov->size / s->page_size <= s->page_size / sizeof(uint64_t));
1083 for (i = 0; i < qiov->niov; ++i) {
1084 bool retry = true;
1085 uint64_t iova;
1086 size_t len = QEMU_ALIGN_UP(qiov->iov[i].iov_len,
1087 qemu_real_host_page_size());
1088 try_map:
1089 r = qemu_vfio_dma_map(s->vfio,
1090 qiov->iov[i].iov_base,
1091 len, true, &iova, errp);
1092 if (r == -ENOSPC) {
1093 /*
1094 * In addition to the -ENOMEM error, the VFIO_IOMMU_MAP_DMA
1095 * ioctl returns -ENOSPC to signal the user exhausted the DMA
1096 * mappings available for a container since Linux kernel commit
1097 * 492855939bdb ("vfio/type1: Limit DMA mappings per container",
1098 * April 2019, see CVE-2019-3882).
1099 *
1100 * This block driver already handles this error path by checking
1101 * for the -ENOMEM error, so we directly replace -ENOSPC by
1102 * -ENOMEM. Beside, -ENOSPC has a specific meaning for blockdev
1103 * coroutines: it triggers BLOCKDEV_ON_ERROR_ENOSPC and
1104 * BLOCK_ERROR_ACTION_STOP which stops the VM, asking the operator
1105 * to add more storage to the blockdev. Not something we can do
1106 * easily with an IOMMU :)
1107 */
1108 r = -ENOMEM;
1109 }
1110 if (r == -ENOMEM && retry) {
1111 /*
1112 * We exhausted the DMA mappings available for our container:
1113 * recycle the volatile IOVA mappings.
1114 */
1115 retry = false;
1116 trace_nvme_dma_flush_queue_wait(s);
1117 if (s->dma_map_count) {
1118 trace_nvme_dma_map_flush(s);
1119 qemu_co_queue_wait(&s->dma_flush_queue, &s->dma_map_lock);
1120 } else {
1121 r = qemu_vfio_dma_reset_temporary(s->vfio);
1122 if (r) {
1123 goto fail;
1124 }
1125 }
1126 errp = &local_err;
1127
1128 goto try_map;
1129 }
1130 if (r) {
1131 goto fail;
1132 }
1133
1134 for (j = 0; j < qiov->iov[i].iov_len / s->page_size; j++) {
1135 pagelist[entries++] = cpu_to_le64(iova + j * s->page_size);
1136 }
1137 trace_nvme_cmd_map_qiov_iov(s, i, qiov->iov[i].iov_base,
1138 qiov->iov[i].iov_len / s->page_size);
1139 }
1140
1141 s->dma_map_count += qiov->size;
1142
1143 assert(entries <= s->page_size / sizeof(uint64_t));
1144 switch (entries) {
1145 case 0:
1146 abort();
1147 case 1:
1148 cmd->dptr.prp1 = pagelist[0];
1149 cmd->dptr.prp2 = 0;
1150 break;
1151 case 2:
1152 cmd->dptr.prp1 = pagelist[0];
1153 cmd->dptr.prp2 = pagelist[1];
1154 break;
1155 default:
1156 cmd->dptr.prp1 = pagelist[0];
1157 cmd->dptr.prp2 = cpu_to_le64(req->prp_list_iova + sizeof(uint64_t));
1158 break;
1159 }
1160 trace_nvme_cmd_map_qiov(s, cmd, req, qiov, entries);
1161 for (i = 0; i < entries; ++i) {
1162 trace_nvme_cmd_map_qiov_pages(s, i, pagelist[i]);
1163 }
1164 return 0;
1165 fail:
1166 /* No need to unmap [0 - i) iovs even if we've failed, since we don't
1167 * increment s->dma_map_count. This is okay for fixed mapping memory areas
1168 * because they are already mapped before calling this function; for
1169 * temporary mappings, a later nvme_cmd_(un)map_qiov will reclaim by
1170 * calling qemu_vfio_dma_reset_temporary when necessary. */
1171 if (local_err) {
1172 error_reportf_err(local_err, "Cannot map buffer for DMA: ");
1173 }
1174 return r;
1175 }
1176
1177 typedef struct {
1178 Coroutine *co;
1179 bool skip_yield;
1180 int ret;
1181 } NVMeCoData;
1182
nvme_rw_cb(void * opaque,int ret)1183 static void nvme_rw_cb(void *opaque, int ret)
1184 {
1185 NVMeCoData *data = opaque;
1186
1187 data->ret = ret;
1188
1189 if (data->co == qemu_coroutine_self()) {
1190 /*
1191 * Fast path: We are inside of the request coroutine (through
1192 * nvme_submit_command, nvme_deferred_fn, nvme_process_completion).
1193 * We can set data->skip_yield here to keep the coroutine from
1194 * yielding, and then we don't need to schedule a BH to wake it.
1195 */
1196 data->skip_yield = true;
1197 } else {
1198 /*
1199 * Safe to call: The case where we run in the request coroutine is
1200 * handled above, so we must be independent of it; and without
1201 * skip_yield set, the coroutine will yield.
1202 * No need to release NVMeQueuePair.lock (we are called without it
1203 * held). (Note: If we enter the coroutine here, @data will
1204 * probably be dangling once aio_co_wake() returns.)
1205 */
1206 aio_co_wake(data->co);
1207 }
1208 }
1209
nvme_co_prw_aligned(BlockDriverState * bs,uint64_t offset,uint64_t bytes,QEMUIOVector * qiov,bool is_write,int flags)1210 static coroutine_fn int nvme_co_prw_aligned(BlockDriverState *bs,
1211 uint64_t offset, uint64_t bytes,
1212 QEMUIOVector *qiov,
1213 bool is_write,
1214 int flags)
1215 {
1216 int r;
1217 BDRVNVMeState *s = bs->opaque;
1218 NVMeQueuePair *ioq = s->queues[INDEX_IO(0)];
1219 NVMeRequest *req;
1220
1221 uint32_t cdw12 = (((bytes >> s->blkshift) - 1) & 0xFFFF) |
1222 (flags & BDRV_REQ_FUA ? 1 << 30 : 0);
1223 NvmeCmd cmd = {
1224 .opcode = is_write ? NVME_CMD_WRITE : NVME_CMD_READ,
1225 .nsid = cpu_to_le32(s->nsid),
1226 .cdw10 = cpu_to_le32((offset >> s->blkshift) & 0xFFFFFFFF),
1227 .cdw11 = cpu_to_le32(((offset >> s->blkshift) >> 32) & 0xFFFFFFFF),
1228 .cdw12 = cpu_to_le32(cdw12),
1229 };
1230 NVMeCoData data = {
1231 .co = qemu_coroutine_self(),
1232 .ret = -EINPROGRESS,
1233 };
1234
1235 trace_nvme_prw_aligned(s, is_write, offset, bytes, flags, qiov->niov);
1236 assert(s->queue_count > 1);
1237 req = nvme_get_free_req(ioq);
1238 assert(req);
1239
1240 qemu_co_mutex_lock(&s->dma_map_lock);
1241 r = nvme_cmd_map_qiov(bs, &cmd, req, qiov);
1242 qemu_co_mutex_unlock(&s->dma_map_lock);
1243 if (r) {
1244 nvme_put_free_req_and_wake(ioq, req);
1245 return r;
1246 }
1247 nvme_submit_command(ioq, req, &cmd, nvme_rw_cb, &data);
1248 if (!data.skip_yield) {
1249 qemu_coroutine_yield();
1250 }
1251
1252 qemu_co_mutex_lock(&s->dma_map_lock);
1253 r = nvme_cmd_unmap_qiov(bs, qiov);
1254 qemu_co_mutex_unlock(&s->dma_map_lock);
1255 if (r) {
1256 return r;
1257 }
1258
1259 trace_nvme_rw_done(s, is_write, offset, bytes, data.ret);
1260 return data.ret;
1261 }
1262
nvme_qiov_aligned(BlockDriverState * bs,const QEMUIOVector * qiov)1263 static inline bool nvme_qiov_aligned(BlockDriverState *bs,
1264 const QEMUIOVector *qiov)
1265 {
1266 int i;
1267 BDRVNVMeState *s = bs->opaque;
1268
1269 for (i = 0; i < qiov->niov; ++i) {
1270 if (!QEMU_PTR_IS_ALIGNED(qiov->iov[i].iov_base,
1271 qemu_real_host_page_size()) ||
1272 !QEMU_IS_ALIGNED(qiov->iov[i].iov_len, qemu_real_host_page_size())) {
1273 trace_nvme_qiov_unaligned(qiov, i, qiov->iov[i].iov_base,
1274 qiov->iov[i].iov_len, s->page_size);
1275 return false;
1276 }
1277 }
1278 return true;
1279 }
1280
nvme_co_prw(BlockDriverState * bs,uint64_t offset,uint64_t bytes,QEMUIOVector * qiov,bool is_write,int flags)1281 static coroutine_fn int nvme_co_prw(BlockDriverState *bs,
1282 uint64_t offset, uint64_t bytes,
1283 QEMUIOVector *qiov, bool is_write,
1284 int flags)
1285 {
1286 BDRVNVMeState *s = bs->opaque;
1287 int r;
1288 QEMU_AUTO_VFREE uint8_t *buf = NULL;
1289 QEMUIOVector local_qiov;
1290 size_t len = QEMU_ALIGN_UP(bytes, qemu_real_host_page_size());
1291 assert(QEMU_IS_ALIGNED(offset, s->page_size));
1292 assert(QEMU_IS_ALIGNED(bytes, s->page_size));
1293 assert(bytes <= s->max_transfer);
1294 if (nvme_qiov_aligned(bs, qiov)) {
1295 s->stats.aligned_accesses++;
1296 return nvme_co_prw_aligned(bs, offset, bytes, qiov, is_write, flags);
1297 }
1298 s->stats.unaligned_accesses++;
1299 trace_nvme_prw_buffered(s, offset, bytes, qiov->niov, is_write);
1300 buf = qemu_try_memalign(qemu_real_host_page_size(), len);
1301
1302 if (!buf) {
1303 return -ENOMEM;
1304 }
1305 qemu_iovec_init(&local_qiov, 1);
1306 if (is_write) {
1307 qemu_iovec_to_buf(qiov, 0, buf, bytes);
1308 }
1309 qemu_iovec_add(&local_qiov, buf, bytes);
1310 r = nvme_co_prw_aligned(bs, offset, bytes, &local_qiov, is_write, flags);
1311 qemu_iovec_destroy(&local_qiov);
1312 if (!r && !is_write) {
1313 qemu_iovec_from_buf(qiov, 0, buf, bytes);
1314 }
1315 return r;
1316 }
1317
nvme_co_preadv(BlockDriverState * bs,int64_t offset,int64_t bytes,QEMUIOVector * qiov,BdrvRequestFlags flags)1318 static coroutine_fn int nvme_co_preadv(BlockDriverState *bs,
1319 int64_t offset, int64_t bytes,
1320 QEMUIOVector *qiov,
1321 BdrvRequestFlags flags)
1322 {
1323 return nvme_co_prw(bs, offset, bytes, qiov, false, flags);
1324 }
1325
nvme_co_pwritev(BlockDriverState * bs,int64_t offset,int64_t bytes,QEMUIOVector * qiov,BdrvRequestFlags flags)1326 static coroutine_fn int nvme_co_pwritev(BlockDriverState *bs,
1327 int64_t offset, int64_t bytes,
1328 QEMUIOVector *qiov,
1329 BdrvRequestFlags flags)
1330 {
1331 return nvme_co_prw(bs, offset, bytes, qiov, true, flags);
1332 }
1333
nvme_co_flush(BlockDriverState * bs)1334 static coroutine_fn int nvme_co_flush(BlockDriverState *bs)
1335 {
1336 BDRVNVMeState *s = bs->opaque;
1337 NVMeQueuePair *ioq = s->queues[INDEX_IO(0)];
1338 NVMeRequest *req;
1339 NvmeCmd cmd = {
1340 .opcode = NVME_CMD_FLUSH,
1341 .nsid = cpu_to_le32(s->nsid),
1342 };
1343 NVMeCoData data = {
1344 .co = qemu_coroutine_self(),
1345 .ret = -EINPROGRESS,
1346 };
1347
1348 assert(s->queue_count > 1);
1349 req = nvme_get_free_req(ioq);
1350 assert(req);
1351 nvme_submit_command(ioq, req, &cmd, nvme_rw_cb, &data);
1352 if (!data.skip_yield) {
1353 qemu_coroutine_yield();
1354 }
1355
1356 return data.ret;
1357 }
1358
1359
nvme_co_pwrite_zeroes(BlockDriverState * bs,int64_t offset,int64_t bytes,BdrvRequestFlags flags)1360 static coroutine_fn int nvme_co_pwrite_zeroes(BlockDriverState *bs,
1361 int64_t offset,
1362 int64_t bytes,
1363 BdrvRequestFlags flags)
1364 {
1365 BDRVNVMeState *s = bs->opaque;
1366 NVMeQueuePair *ioq = s->queues[INDEX_IO(0)];
1367 NVMeRequest *req;
1368 uint32_t cdw12;
1369
1370 if (!s->supports_write_zeroes) {
1371 return -ENOTSUP;
1372 }
1373
1374 if (bytes == 0) {
1375 return 0;
1376 }
1377
1378 cdw12 = ((bytes >> s->blkshift) - 1) & 0xFFFF;
1379 /*
1380 * We should not lose information. pwrite_zeroes_alignment and
1381 * max_pwrite_zeroes guarantees it.
1382 */
1383 assert(((cdw12 + 1) << s->blkshift) == bytes);
1384
1385 NvmeCmd cmd = {
1386 .opcode = NVME_CMD_WRITE_ZEROES,
1387 .nsid = cpu_to_le32(s->nsid),
1388 .cdw10 = cpu_to_le32((offset >> s->blkshift) & 0xFFFFFFFF),
1389 .cdw11 = cpu_to_le32(((offset >> s->blkshift) >> 32) & 0xFFFFFFFF),
1390 };
1391
1392 NVMeCoData data = {
1393 .co = qemu_coroutine_self(),
1394 .ret = -EINPROGRESS,
1395 };
1396
1397 if (flags & BDRV_REQ_MAY_UNMAP) {
1398 cdw12 |= (1 << 25);
1399 }
1400
1401 if (flags & BDRV_REQ_FUA) {
1402 cdw12 |= (1 << 30);
1403 }
1404
1405 cmd.cdw12 = cpu_to_le32(cdw12);
1406
1407 trace_nvme_write_zeroes(s, offset, bytes, flags);
1408 assert(s->queue_count > 1);
1409 req = nvme_get_free_req(ioq);
1410 assert(req);
1411
1412 nvme_submit_command(ioq, req, &cmd, nvme_rw_cb, &data);
1413 if (!data.skip_yield) {
1414 qemu_coroutine_yield();
1415 }
1416
1417 trace_nvme_rw_done(s, true, offset, bytes, data.ret);
1418 return data.ret;
1419 }
1420
1421
nvme_co_pdiscard(BlockDriverState * bs,int64_t offset,int64_t bytes)1422 static int coroutine_fn nvme_co_pdiscard(BlockDriverState *bs,
1423 int64_t offset,
1424 int64_t bytes)
1425 {
1426 BDRVNVMeState *s = bs->opaque;
1427 NVMeQueuePair *ioq = s->queues[INDEX_IO(0)];
1428 NVMeRequest *req;
1429 QEMU_AUTO_VFREE NvmeDsmRange *buf = NULL;
1430 QEMUIOVector local_qiov;
1431 int ret;
1432
1433 NvmeCmd cmd = {
1434 .opcode = NVME_CMD_DSM,
1435 .nsid = cpu_to_le32(s->nsid),
1436 .cdw10 = cpu_to_le32(0), /*number of ranges - 0 based*/
1437 .cdw11 = cpu_to_le32(1 << 2), /*deallocate bit*/
1438 };
1439
1440 NVMeCoData data = {
1441 .co = qemu_coroutine_self(),
1442 .ret = -EINPROGRESS,
1443 };
1444
1445 if (!s->supports_discard) {
1446 return -ENOTSUP;
1447 }
1448
1449 assert(s->queue_count > 1);
1450
1451 /*
1452 * Filling the @buf requires @offset and @bytes to satisfy restrictions
1453 * defined in nvme_refresh_limits().
1454 */
1455 assert(QEMU_IS_ALIGNED(bytes, 1UL << s->blkshift));
1456 assert(QEMU_IS_ALIGNED(offset, 1UL << s->blkshift));
1457 assert((bytes >> s->blkshift) <= UINT32_MAX);
1458
1459 buf = qemu_try_memalign(s->page_size, s->page_size);
1460 if (!buf) {
1461 return -ENOMEM;
1462 }
1463 memset(buf, 0, s->page_size);
1464 buf->nlb = cpu_to_le32(bytes >> s->blkshift);
1465 buf->slba = cpu_to_le64(offset >> s->blkshift);
1466 buf->cattr = 0;
1467
1468 qemu_iovec_init(&local_qiov, 1);
1469 qemu_iovec_add(&local_qiov, buf, 4096);
1470
1471 req = nvme_get_free_req(ioq);
1472 assert(req);
1473
1474 qemu_co_mutex_lock(&s->dma_map_lock);
1475 ret = nvme_cmd_map_qiov(bs, &cmd, req, &local_qiov);
1476 qemu_co_mutex_unlock(&s->dma_map_lock);
1477
1478 if (ret) {
1479 nvme_put_free_req_and_wake(ioq, req);
1480 goto out;
1481 }
1482
1483 trace_nvme_dsm(s, offset, bytes);
1484
1485 nvme_submit_command(ioq, req, &cmd, nvme_rw_cb, &data);
1486 if (!data.skip_yield) {
1487 qemu_coroutine_yield();
1488 }
1489
1490 qemu_co_mutex_lock(&s->dma_map_lock);
1491 ret = nvme_cmd_unmap_qiov(bs, &local_qiov);
1492 qemu_co_mutex_unlock(&s->dma_map_lock);
1493
1494 if (ret) {
1495 goto out;
1496 }
1497
1498 ret = data.ret;
1499 trace_nvme_dsm_done(s, offset, bytes, ret);
1500 out:
1501 qemu_iovec_destroy(&local_qiov);
1502 return ret;
1503
1504 }
1505
nvme_co_truncate(BlockDriverState * bs,int64_t offset,bool exact,PreallocMode prealloc,BdrvRequestFlags flags,Error ** errp)1506 static int coroutine_fn nvme_co_truncate(BlockDriverState *bs, int64_t offset,
1507 bool exact, PreallocMode prealloc,
1508 BdrvRequestFlags flags, Error **errp)
1509 {
1510 int64_t cur_length;
1511
1512 if (prealloc != PREALLOC_MODE_OFF) {
1513 error_setg(errp, "Unsupported preallocation mode '%s'",
1514 PreallocMode_str(prealloc));
1515 return -ENOTSUP;
1516 }
1517
1518 cur_length = nvme_co_getlength(bs);
1519 if (offset != cur_length && exact) {
1520 error_setg(errp, "Cannot resize NVMe devices");
1521 return -ENOTSUP;
1522 } else if (offset > cur_length) {
1523 error_setg(errp, "Cannot grow NVMe devices");
1524 return -EINVAL;
1525 }
1526
1527 return 0;
1528 }
1529
nvme_reopen_prepare(BDRVReopenState * reopen_state,BlockReopenQueue * queue,Error ** errp)1530 static int nvme_reopen_prepare(BDRVReopenState *reopen_state,
1531 BlockReopenQueue *queue, Error **errp)
1532 {
1533 return 0;
1534 }
1535
nvme_refresh_filename(BlockDriverState * bs)1536 static void nvme_refresh_filename(BlockDriverState *bs)
1537 {
1538 BDRVNVMeState *s = bs->opaque;
1539
1540 snprintf(bs->exact_filename, sizeof(bs->exact_filename), "nvme://%s/%i",
1541 s->device, s->nsid);
1542 }
1543
nvme_refresh_limits(BlockDriverState * bs,Error ** errp)1544 static void nvme_refresh_limits(BlockDriverState *bs, Error **errp)
1545 {
1546 BDRVNVMeState *s = bs->opaque;
1547
1548 bs->bl.opt_mem_alignment = s->page_size;
1549 bs->bl.request_alignment = s->page_size;
1550 bs->bl.max_transfer = s->max_transfer;
1551
1552 /*
1553 * Look at nvme_co_pwrite_zeroes: after shift and decrement we should get
1554 * at most 0xFFFF
1555 */
1556 bs->bl.max_pwrite_zeroes = 1ULL << (s->blkshift + 16);
1557 bs->bl.pwrite_zeroes_alignment = MAX(bs->bl.request_alignment,
1558 1UL << s->blkshift);
1559
1560 bs->bl.max_pdiscard = (uint64_t)UINT32_MAX << s->blkshift;
1561 bs->bl.pdiscard_alignment = MAX(bs->bl.request_alignment,
1562 1UL << s->blkshift);
1563 }
1564
nvme_detach_aio_context(BlockDriverState * bs)1565 static void nvme_detach_aio_context(BlockDriverState *bs)
1566 {
1567 BDRVNVMeState *s = bs->opaque;
1568
1569 for (unsigned i = 0; i < s->queue_count; i++) {
1570 NVMeQueuePair *q = s->queues[i];
1571
1572 qemu_bh_delete(q->completion_bh);
1573 q->completion_bh = NULL;
1574 }
1575
1576 aio_set_event_notifier(bdrv_get_aio_context(bs),
1577 &s->irq_notifier[MSIX_SHARED_IRQ_IDX],
1578 NULL, NULL, NULL);
1579 }
1580
nvme_attach_aio_context(BlockDriverState * bs,AioContext * new_context)1581 static void nvme_attach_aio_context(BlockDriverState *bs,
1582 AioContext *new_context)
1583 {
1584 BDRVNVMeState *s = bs->opaque;
1585
1586 s->aio_context = new_context;
1587 aio_set_event_notifier(new_context, &s->irq_notifier[MSIX_SHARED_IRQ_IDX],
1588 nvme_handle_event, nvme_poll_cb,
1589 nvme_poll_ready);
1590
1591 for (unsigned i = 0; i < s->queue_count; i++) {
1592 NVMeQueuePair *q = s->queues[i];
1593
1594 q->completion_bh =
1595 aio_bh_new(new_context, nvme_process_completion_bh, q);
1596 }
1597 }
1598
nvme_register_buf(BlockDriverState * bs,void * host,size_t size,Error ** errp)1599 static bool nvme_register_buf(BlockDriverState *bs, void *host, size_t size,
1600 Error **errp)
1601 {
1602 int ret;
1603 BDRVNVMeState *s = bs->opaque;
1604
1605 /*
1606 * FIXME: we may run out of IOVA addresses after repeated
1607 * bdrv_register_buf/bdrv_unregister_buf, because nvme_vfio_dma_unmap
1608 * doesn't reclaim addresses for fixed mappings.
1609 */
1610 ret = qemu_vfio_dma_map(s->vfio, host, size, false, NULL, errp);
1611 return ret == 0;
1612 }
1613
nvme_unregister_buf(BlockDriverState * bs,void * host,size_t size)1614 static void nvme_unregister_buf(BlockDriverState *bs, void *host, size_t size)
1615 {
1616 BDRVNVMeState *s = bs->opaque;
1617
1618 qemu_vfio_dma_unmap(s->vfio, host);
1619 }
1620
nvme_get_specific_stats(BlockDriverState * bs)1621 static BlockStatsSpecific *nvme_get_specific_stats(BlockDriverState *bs)
1622 {
1623 BlockStatsSpecific *stats = g_new(BlockStatsSpecific, 1);
1624 BDRVNVMeState *s = bs->opaque;
1625
1626 stats->driver = BLOCKDEV_DRIVER_NVME;
1627 stats->u.nvme = (BlockStatsSpecificNvme) {
1628 .completion_errors = s->stats.completion_errors,
1629 .aligned_accesses = s->stats.aligned_accesses,
1630 .unaligned_accesses = s->stats.unaligned_accesses,
1631 };
1632
1633 return stats;
1634 }
1635
1636 static const char *const nvme_strong_runtime_opts[] = {
1637 NVME_BLOCK_OPT_DEVICE,
1638 NVME_BLOCK_OPT_NAMESPACE,
1639
1640 NULL
1641 };
1642
1643 static BlockDriver bdrv_nvme = {
1644 .format_name = "nvme",
1645 .protocol_name = "nvme",
1646 .instance_size = sizeof(BDRVNVMeState),
1647
1648 .bdrv_co_create_opts = bdrv_co_create_opts_simple,
1649 .create_opts = &bdrv_create_opts_simple,
1650
1651 .bdrv_parse_filename = nvme_parse_filename,
1652 .bdrv_open = nvme_open,
1653 .bdrv_close = nvme_close,
1654 .bdrv_co_getlength = nvme_co_getlength,
1655 .bdrv_probe_blocksizes = nvme_probe_blocksizes,
1656 .bdrv_co_truncate = nvme_co_truncate,
1657
1658 .bdrv_co_preadv = nvme_co_preadv,
1659 .bdrv_co_pwritev = nvme_co_pwritev,
1660
1661 .bdrv_co_pwrite_zeroes = nvme_co_pwrite_zeroes,
1662 .bdrv_co_pdiscard = nvme_co_pdiscard,
1663
1664 .bdrv_co_flush_to_disk = nvme_co_flush,
1665 .bdrv_reopen_prepare = nvme_reopen_prepare,
1666
1667 .bdrv_refresh_filename = nvme_refresh_filename,
1668 .bdrv_refresh_limits = nvme_refresh_limits,
1669 .strong_runtime_opts = nvme_strong_runtime_opts,
1670 .bdrv_get_specific_stats = nvme_get_specific_stats,
1671
1672 .bdrv_detach_aio_context = nvme_detach_aio_context,
1673 .bdrv_attach_aio_context = nvme_attach_aio_context,
1674
1675 .bdrv_register_buf = nvme_register_buf,
1676 .bdrv_unregister_buf = nvme_unregister_buf,
1677 };
1678
bdrv_nvme_init(void)1679 static void bdrv_nvme_init(void)
1680 {
1681 bdrv_register(&bdrv_nvme);
1682 }
1683
1684 block_init(bdrv_nvme_init);
1685