1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2019-2020 NVIDIA CORPORATION.  All rights reserved.
3 
4 #include <linux/bitfield.h>
5 #include <linux/delay.h>
6 #include <linux/of.h>
7 #include <linux/platform_device.h>
8 #include <linux/slab.h>
9 
10 #include <soc/tegra/mc.h>
11 
12 #include "arm-smmu.h"
13 
14 /*
15  * Tegra194 has three ARM MMU-500 Instances.
16  * Two of them are used together and must be programmed identically for
17  * interleaved IOVA accesses across them and translates accesses from
18  * non-isochronous HW devices.
19  * Third one is used for translating accesses from isochronous HW devices.
20  *
21  * In addition, the SMMU driver needs to coordinate with the memory controller
22  * driver to ensure that the right SID override is programmed for any given
23  * memory client. This is necessary to allow for use-case such as seamlessly
24  * handing over the display controller configuration from the firmware to the
25  * kernel.
26  *
27  * This implementation supports programming of the two instances that must
28  * be programmed identically and takes care of invoking the memory controller
29  * driver for SID override programming after devices have been attached to an
30  * SMMU instance.
31  */
32 #define MAX_SMMU_INSTANCES 2
33 
34 struct nvidia_smmu {
35 	struct arm_smmu_device smmu;
36 	void __iomem *bases[MAX_SMMU_INSTANCES];
37 	unsigned int num_instances;
38 	struct tegra_mc *mc;
39 };
40 
to_nvidia_smmu(struct arm_smmu_device * smmu)41 static inline struct nvidia_smmu *to_nvidia_smmu(struct arm_smmu_device *smmu)
42 {
43 	return container_of(smmu, struct nvidia_smmu, smmu);
44 }
45 
nvidia_smmu_page(struct arm_smmu_device * smmu,unsigned int inst,int page)46 static inline void __iomem *nvidia_smmu_page(struct arm_smmu_device *smmu,
47 					     unsigned int inst, int page)
48 {
49 	struct nvidia_smmu *nvidia_smmu;
50 
51 	nvidia_smmu = container_of(smmu, struct nvidia_smmu, smmu);
52 	return nvidia_smmu->bases[inst] + (page << smmu->pgshift);
53 }
54 
nvidia_smmu_read_reg(struct arm_smmu_device * smmu,int page,int offset)55 static u32 nvidia_smmu_read_reg(struct arm_smmu_device *smmu,
56 				int page, int offset)
57 {
58 	void __iomem *reg = nvidia_smmu_page(smmu, 0, page) + offset;
59 
60 	return readl_relaxed(reg);
61 }
62 
nvidia_smmu_write_reg(struct arm_smmu_device * smmu,int page,int offset,u32 val)63 static void nvidia_smmu_write_reg(struct arm_smmu_device *smmu,
64 				  int page, int offset, u32 val)
65 {
66 	struct nvidia_smmu *nvidia = to_nvidia_smmu(smmu);
67 	unsigned int i;
68 
69 	for (i = 0; i < nvidia->num_instances; i++) {
70 		void __iomem *reg = nvidia_smmu_page(smmu, i, page) + offset;
71 
72 		writel_relaxed(val, reg);
73 	}
74 }
75 
nvidia_smmu_read_reg64(struct arm_smmu_device * smmu,int page,int offset)76 static u64 nvidia_smmu_read_reg64(struct arm_smmu_device *smmu,
77 				  int page, int offset)
78 {
79 	void __iomem *reg = nvidia_smmu_page(smmu, 0, page) + offset;
80 
81 	return readq_relaxed(reg);
82 }
83 
nvidia_smmu_write_reg64(struct arm_smmu_device * smmu,int page,int offset,u64 val)84 static void nvidia_smmu_write_reg64(struct arm_smmu_device *smmu,
85 				    int page, int offset, u64 val)
86 {
87 	struct nvidia_smmu *nvidia = to_nvidia_smmu(smmu);
88 	unsigned int i;
89 
90 	for (i = 0; i < nvidia->num_instances; i++) {
91 		void __iomem *reg = nvidia_smmu_page(smmu, i, page) + offset;
92 
93 		writeq_relaxed(val, reg);
94 	}
95 }
96 
nvidia_smmu_tlb_sync(struct arm_smmu_device * smmu,int page,int sync,int status)97 static void nvidia_smmu_tlb_sync(struct arm_smmu_device *smmu, int page,
98 				 int sync, int status)
99 {
100 	struct nvidia_smmu *nvidia = to_nvidia_smmu(smmu);
101 	unsigned int delay;
102 
103 	arm_smmu_writel(smmu, page, sync, 0);
104 
105 	for (delay = 1; delay < TLB_LOOP_TIMEOUT; delay *= 2) {
106 		unsigned int spin_cnt;
107 
108 		for (spin_cnt = TLB_SPIN_COUNT; spin_cnt > 0; spin_cnt--) {
109 			u32 val = 0;
110 			unsigned int i;
111 
112 			for (i = 0; i < nvidia->num_instances; i++) {
113 				void __iomem *reg;
114 
115 				reg = nvidia_smmu_page(smmu, i, page) + status;
116 				val |= readl_relaxed(reg);
117 			}
118 
119 			if (!(val & ARM_SMMU_sTLBGSTATUS_GSACTIVE))
120 				return;
121 
122 			cpu_relax();
123 		}
124 
125 		udelay(delay);
126 	}
127 
128 	dev_err_ratelimited(smmu->dev,
129 			    "TLB sync timed out -- SMMU may be deadlocked\n");
130 }
131 
nvidia_smmu_reset(struct arm_smmu_device * smmu)132 static int nvidia_smmu_reset(struct arm_smmu_device *smmu)
133 {
134 	struct nvidia_smmu *nvidia = to_nvidia_smmu(smmu);
135 	unsigned int i;
136 
137 	for (i = 0; i < nvidia->num_instances; i++) {
138 		u32 val;
139 		void __iomem *reg = nvidia_smmu_page(smmu, i, ARM_SMMU_GR0) +
140 				    ARM_SMMU_GR0_sGFSR;
141 
142 		/* clear global FSR */
143 		val = readl_relaxed(reg);
144 		writel_relaxed(val, reg);
145 	}
146 
147 	return 0;
148 }
149 
nvidia_smmu_global_fault_inst(int irq,struct arm_smmu_device * smmu,int inst)150 static irqreturn_t nvidia_smmu_global_fault_inst(int irq,
151 						 struct arm_smmu_device *smmu,
152 						 int inst)
153 {
154 	u32 gfsr, gfsynr0, gfsynr1, gfsynr2;
155 	void __iomem *gr0_base = nvidia_smmu_page(smmu, inst, 0);
156 
157 	gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR);
158 	if (!gfsr)
159 		return IRQ_NONE;
160 
161 	gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0);
162 	gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1);
163 	gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2);
164 
165 	dev_err_ratelimited(smmu->dev,
166 			    "Unexpected global fault, this could be serious\n");
167 	dev_err_ratelimited(smmu->dev,
168 			    "\tGFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x\n",
169 			    gfsr, gfsynr0, gfsynr1, gfsynr2);
170 
171 	writel_relaxed(gfsr, gr0_base + ARM_SMMU_GR0_sGFSR);
172 	return IRQ_HANDLED;
173 }
174 
nvidia_smmu_global_fault(int irq,void * dev)175 static irqreturn_t nvidia_smmu_global_fault(int irq, void *dev)
176 {
177 	unsigned int inst;
178 	irqreturn_t ret = IRQ_NONE;
179 	struct arm_smmu_device *smmu = dev;
180 	struct nvidia_smmu *nvidia = to_nvidia_smmu(smmu);
181 
182 	for (inst = 0; inst < nvidia->num_instances; inst++) {
183 		irqreturn_t irq_ret;
184 
185 		irq_ret = nvidia_smmu_global_fault_inst(irq, smmu, inst);
186 		if (irq_ret == IRQ_HANDLED)
187 			ret = IRQ_HANDLED;
188 	}
189 
190 	return ret;
191 }
192 
nvidia_smmu_context_fault_bank(int irq,struct arm_smmu_device * smmu,int idx,int inst)193 static irqreturn_t nvidia_smmu_context_fault_bank(int irq,
194 						  struct arm_smmu_device *smmu,
195 						  int idx, int inst)
196 {
197 	u32 fsr, fsynr, cbfrsynra;
198 	unsigned long iova;
199 	void __iomem *gr1_base = nvidia_smmu_page(smmu, inst, 1);
200 	void __iomem *cb_base = nvidia_smmu_page(smmu, inst, smmu->numpage + idx);
201 
202 	fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR);
203 	if (!(fsr & ARM_SMMU_FSR_FAULT))
204 		return IRQ_NONE;
205 
206 	fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
207 	iova = readq_relaxed(cb_base + ARM_SMMU_CB_FAR);
208 	cbfrsynra = readl_relaxed(gr1_base + ARM_SMMU_GR1_CBFRSYNRA(idx));
209 
210 	dev_err_ratelimited(smmu->dev,
211 			    "Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n",
212 			    fsr, iova, fsynr, cbfrsynra, idx);
213 
214 	writel_relaxed(fsr, cb_base + ARM_SMMU_CB_FSR);
215 	return IRQ_HANDLED;
216 }
217 
nvidia_smmu_context_fault(int irq,void * dev)218 static irqreturn_t nvidia_smmu_context_fault(int irq, void *dev)
219 {
220 	int idx;
221 	unsigned int inst;
222 	irqreturn_t ret = IRQ_NONE;
223 	struct arm_smmu_device *smmu;
224 	struct iommu_domain *domain = dev;
225 	struct arm_smmu_domain *smmu_domain;
226 	struct nvidia_smmu *nvidia;
227 
228 	smmu_domain = container_of(domain, struct arm_smmu_domain, domain);
229 	smmu = smmu_domain->smmu;
230 	nvidia = to_nvidia_smmu(smmu);
231 
232 	for (inst = 0; inst < nvidia->num_instances; inst++) {
233 		irqreturn_t irq_ret;
234 
235 		/*
236 		 * Interrupt line is shared between all contexts.
237 		 * Check for faults across all contexts.
238 		 */
239 		for (idx = 0; idx < smmu->num_context_banks; idx++) {
240 			irq_ret = nvidia_smmu_context_fault_bank(irq, smmu,
241 								 idx, inst);
242 			if (irq_ret == IRQ_HANDLED)
243 				ret = IRQ_HANDLED;
244 		}
245 	}
246 
247 	return ret;
248 }
249 
nvidia_smmu_probe_finalize(struct arm_smmu_device * smmu,struct device * dev)250 static void nvidia_smmu_probe_finalize(struct arm_smmu_device *smmu, struct device *dev)
251 {
252 	struct nvidia_smmu *nvidia = to_nvidia_smmu(smmu);
253 	int err;
254 
255 	err = tegra_mc_probe_device(nvidia->mc, dev);
256 	if (err < 0)
257 		dev_err(smmu->dev, "memory controller probe failed for %s: %d\n",
258 			dev_name(dev), err);
259 }
260 
nvidia_smmu_init_context(struct arm_smmu_domain * smmu_domain,struct io_pgtable_cfg * pgtbl_cfg,struct device * dev)261 static int nvidia_smmu_init_context(struct arm_smmu_domain *smmu_domain,
262 				    struct io_pgtable_cfg *pgtbl_cfg,
263 				    struct device *dev)
264 {
265 	struct arm_smmu_device *smmu = smmu_domain->smmu;
266 	const struct device_node *np = smmu->dev->of_node;
267 
268 	/*
269 	 * Tegra194 and Tegra234 SoCs have the erratum that causes walk cache
270 	 * entries to not be invalidated correctly. The problem is that the walk
271 	 * cache index generated for IOVA is not same across translation and
272 	 * invalidation requests. This is leading to page faults when PMD entry
273 	 * is released during unmap and populated with new PTE table during
274 	 * subsequent map request. Disabling large page mappings avoids the
275 	 * release of PMD entry and avoid translations seeing stale PMD entry in
276 	 * walk cache.
277 	 * Fix this by limiting the page mappings to PAGE_SIZE on Tegra194 and
278 	 * Tegra234.
279 	 */
280 	if (of_device_is_compatible(np, "nvidia,tegra234-smmu") ||
281 	    of_device_is_compatible(np, "nvidia,tegra194-smmu")) {
282 		smmu->pgsize_bitmap = PAGE_SIZE;
283 		pgtbl_cfg->pgsize_bitmap = smmu->pgsize_bitmap;
284 	}
285 
286 	return 0;
287 }
288 
289 static const struct arm_smmu_impl nvidia_smmu_impl = {
290 	.read_reg = nvidia_smmu_read_reg,
291 	.write_reg = nvidia_smmu_write_reg,
292 	.read_reg64 = nvidia_smmu_read_reg64,
293 	.write_reg64 = nvidia_smmu_write_reg64,
294 	.reset = nvidia_smmu_reset,
295 	.tlb_sync = nvidia_smmu_tlb_sync,
296 	.global_fault = nvidia_smmu_global_fault,
297 	.context_fault = nvidia_smmu_context_fault,
298 	.probe_finalize = nvidia_smmu_probe_finalize,
299 	.init_context = nvidia_smmu_init_context,
300 };
301 
302 static const struct arm_smmu_impl nvidia_smmu_single_impl = {
303 	.probe_finalize = nvidia_smmu_probe_finalize,
304 	.init_context = nvidia_smmu_init_context,
305 };
306 
nvidia_smmu_impl_init(struct arm_smmu_device * smmu)307 struct arm_smmu_device *nvidia_smmu_impl_init(struct arm_smmu_device *smmu)
308 {
309 	struct resource *res;
310 	struct device *dev = smmu->dev;
311 	struct nvidia_smmu *nvidia_smmu;
312 	struct platform_device *pdev = to_platform_device(dev);
313 	unsigned int i;
314 
315 	nvidia_smmu = devm_krealloc(dev, smmu, sizeof(*nvidia_smmu), GFP_KERNEL);
316 	if (!nvidia_smmu)
317 		return ERR_PTR(-ENOMEM);
318 
319 	nvidia_smmu->mc = devm_tegra_memory_controller_get(dev);
320 	if (IS_ERR(nvidia_smmu->mc))
321 		return ERR_CAST(nvidia_smmu->mc);
322 
323 	/* Instance 0 is ioremapped by arm-smmu.c. */
324 	nvidia_smmu->bases[0] = smmu->base;
325 	nvidia_smmu->num_instances++;
326 
327 	for (i = 1; i < MAX_SMMU_INSTANCES; i++) {
328 		res = platform_get_resource(pdev, IORESOURCE_MEM, i);
329 		if (!res)
330 			break;
331 
332 		nvidia_smmu->bases[i] = devm_ioremap_resource(dev, res);
333 		if (IS_ERR(nvidia_smmu->bases[i]))
334 			return ERR_CAST(nvidia_smmu->bases[i]);
335 
336 		nvidia_smmu->num_instances++;
337 	}
338 
339 	if (nvidia_smmu->num_instances == 1)
340 		nvidia_smmu->smmu.impl = &nvidia_smmu_single_impl;
341 	else
342 		nvidia_smmu->smmu.impl = &nvidia_smmu_impl;
343 
344 	return &nvidia_smmu->smmu;
345 }
346