1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Novatek NT36523 DriverIC panels driver
4  *
5  * Copyright (c) 2022, 2023 Jianhua Lu <lujianhua000@gmail.com>
6  */
7 
8 #include <linux/backlight.h>
9 #include <linux/delay.h>
10 #include <linux/gpio/consumer.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/of_graph.h>
14 #include <linux/regulator/consumer.h>
15 
16 #include <video/mipi_display.h>
17 
18 #include <drm/drm_connector.h>
19 #include <drm/drm_crtc.h>
20 #include <drm/drm_mipi_dsi.h>
21 #include <drm/drm_modes.h>
22 #include <drm/drm_panel.h>
23 
24 #define DSI_NUM_MIN 1
25 
26 #define mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, cmd, seq...)        \
27 		do {                                                 \
28 			mipi_dsi_dcs_write_seq(dsi0, cmd, seq);      \
29 			mipi_dsi_dcs_write_seq(dsi1, cmd, seq);      \
30 		} while (0)
31 
32 struct panel_info {
33 	struct drm_panel panel;
34 	struct mipi_dsi_device *dsi[2];
35 	const struct panel_desc *desc;
36 	enum drm_panel_orientation orientation;
37 
38 	struct gpio_desc *reset_gpio;
39 	struct backlight_device *backlight;
40 	struct regulator *vddio;
41 
42 	bool prepared;
43 };
44 
45 struct panel_desc {
46 	unsigned int width_mm;
47 	unsigned int height_mm;
48 
49 	unsigned int bpc;
50 	unsigned int lanes;
51 	unsigned long mode_flags;
52 	enum mipi_dsi_pixel_format format;
53 
54 	const struct drm_display_mode *modes;
55 	unsigned int num_modes;
56 	const struct mipi_dsi_device_info dsi_info;
57 	int (*init_sequence)(struct panel_info *pinfo);
58 
59 	bool is_dual_dsi;
60 	bool has_dcs_backlight;
61 };
62 
to_panel_info(struct drm_panel * panel)63 static inline struct panel_info *to_panel_info(struct drm_panel *panel)
64 {
65 	return container_of(panel, struct panel_info, panel);
66 }
67 
elish_boe_init_sequence(struct panel_info * pinfo)68 static int elish_boe_init_sequence(struct panel_info *pinfo)
69 {
70 	struct mipi_dsi_device *dsi0 = pinfo->dsi[0];
71 	struct mipi_dsi_device *dsi1 = pinfo->dsi[1];
72 	/* No datasheet, so write magic init sequence directly */
73 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x10);
74 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
75 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xb9, 0x05);
76 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x20);
77 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
78 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x18, 0x40);
79 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x10);
80 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
81 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xb9, 0x02);
82 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x23);
83 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
84 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x00, 0x80);
85 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x01, 0x84);
86 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x05, 0x2d);
87 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x06, 0x00);
88 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x07, 0x00);
89 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x08, 0x01);
90 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x09, 0x45);
91 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x11, 0x02);
92 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x12, 0x80);
93 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x15, 0x83);
94 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x16, 0x0c);
95 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x29, 0x0a);
96 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x30, 0xff);
97 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x31, 0xfe);
98 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x32, 0xfd);
99 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x33, 0xfb);
100 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x34, 0xf8);
101 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x35, 0xf5);
102 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x36, 0xf3);
103 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x37, 0xf2);
104 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x38, 0xf2);
105 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x39, 0xf2);
106 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x3a, 0xef);
107 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x3b, 0xec);
108 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x3d, 0xe9);
109 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x3f, 0xe5);
110 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x40, 0xe5);
111 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x41, 0xe5);
112 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x2a, 0x13);
113 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x45, 0xff);
114 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x46, 0xf4);
115 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x47, 0xe7);
116 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x48, 0xda);
117 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x49, 0xcd);
118 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x4a, 0xc0);
119 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x4b, 0xb3);
120 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x4c, 0xb2);
121 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x4d, 0xb2);
122 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x4e, 0xb2);
123 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x4f, 0x99);
124 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x50, 0x80);
125 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x51, 0x68);
126 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x52, 0x66);
127 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x53, 0x66);
128 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x54, 0x66);
129 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x2b, 0x0e);
130 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x58, 0xff);
131 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x59, 0xfb);
132 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x5a, 0xf7);
133 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x5b, 0xf3);
134 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x5c, 0xef);
135 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x5d, 0xe3);
136 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x5e, 0xda);
137 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x5f, 0xd8);
138 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x60, 0xd8);
139 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x61, 0xd8);
140 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x62, 0xcb);
141 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x63, 0xbf);
142 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x64, 0xb3);
143 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x65, 0xb2);
144 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x66, 0xb2);
145 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x67, 0xb2);
146 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x2a);
147 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
148 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x25, 0x47);
149 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x30, 0x47);
150 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x39, 0x47);
151 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x26);
152 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
153 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x19, 0x10);
154 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x1a, 0xe0);
155 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x1b, 0x10);
156 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x1c, 0x00);
157 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x2a, 0x10);
158 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x2b, 0xe0);
159 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x10);
160 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
161 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0xf0);
162 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
163 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x84, 0x08);
164 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x85, 0x0c);
165 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x20);
166 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
167 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x51, 0x00);
168 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x25);
169 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
170 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x91, 0x1f);
171 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x92, 0x0f);
172 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x93, 0x01);
173 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x94, 0x18);
174 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x95, 0x03);
175 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x96, 0x01);
176 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x10);
177 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xb0, 0x01);
178 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x25);
179 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
180 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x19, 0x1f);
181 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x1b, 0x1b);
182 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x24);
183 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
184 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xb8, 0x28);
185 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x27);
186 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
187 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xd0, 0x31);
188 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xd1, 0x20);
189 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xd2, 0x30);
190 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xd4, 0x08);
191 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xde, 0x80);
192 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xdf, 0x02);
193 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x26);
194 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
195 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x00, 0x81);
196 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x01, 0xb0);
197 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x22);
198 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
199 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x9f, 0x50);
200 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x6f, 0x01);
201 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x70, 0x11);
202 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x73, 0x01);
203 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x74, 0x49);
204 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x76, 0x01);
205 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x77, 0x49);
206 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xa0, 0x3f);
207 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xa9, 0x50);
208 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xaa, 0x28);
209 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xab, 0x28);
210 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xad, 0x10);
211 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xb8, 0x00);
212 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xb9, 0x49);
213 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xba, 0x49);
214 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xbb, 0x49);
215 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xbe, 0x04);
216 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xbf, 0x49);
217 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xc0, 0x04);
218 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xc1, 0x59);
219 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xc2, 0x00);
220 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xc5, 0x00);
221 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xc6, 0x01);
222 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xc7, 0x48);
223 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xca, 0x43);
224 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xcb, 0x3c);
225 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xce, 0x00);
226 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xcf, 0x43);
227 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xd0, 0x3c);
228 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xd3, 0x43);
229 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xd4, 0x3c);
230 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xd7, 0x00);
231 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xdc, 0x43);
232 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xdd, 0x3c);
233 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xe1, 0x43);
234 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xe2, 0x3c);
235 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xf2, 0x00);
236 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xf3, 0x01);
237 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xf4, 0x48);
238 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x25);
239 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
240 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x13, 0x01);
241 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x14, 0x23);
242 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xbc, 0x01);
243 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xbd, 0x23);
244 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x2a);
245 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
246 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x97, 0x3c);
247 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x98, 0x02);
248 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x99, 0x95);
249 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x9a, 0x03);
250 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x9b, 0x00);
251 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x9c, 0x0b);
252 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x9d, 0x0a);
253 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x9e, 0x90);
254 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x22);
255 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
256 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x9f, 0x50);
257 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x23);
258 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
259 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xa3, 0x50);
260 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0xe0);
261 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
262 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x14, 0x60);
263 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x16, 0xc0);
264 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x4f, 0x02);
265 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0xf0);
266 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
267 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x3a, 0x08);
268 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0xd0);
269 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
270 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x02, 0xaf);
271 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x09, 0xee);
272 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x1c, 0x99);
273 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x1d, 0x09);
274 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x10);
275 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
276 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x51, 0x0f, 0xff);
277 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x53, 0x2c);
278 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x35, 0x00);
279 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xbb, 0x13);
280 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x3b, 0x03, 0xac, 0x1a, 0x04, 0x04);
281 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x11);
282 	msleep(70);
283 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x29);
284 
285 	return 0;
286 }
287 
elish_csot_init_sequence(struct panel_info * pinfo)288 static int elish_csot_init_sequence(struct panel_info *pinfo)
289 {
290 	struct mipi_dsi_device *dsi0 = pinfo->dsi[0];
291 	struct mipi_dsi_device *dsi1 = pinfo->dsi[1];
292 	/* No datasheet, so write magic init sequence directly */
293 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x10);
294 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
295 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xb9, 0x05);
296 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x20);
297 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
298 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x18, 0x40);
299 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x10);
300 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
301 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xb9, 0x02);
302 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0xd0);
303 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
304 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x02, 0xaf);
305 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x00, 0x30);
306 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x09, 0xee);
307 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x1c, 0x99);
308 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x1d, 0x09);
309 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0xf0);
310 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
311 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x3a, 0x08);
312 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0xe0);
313 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
314 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x4f, 0x02);
315 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x20);
316 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
317 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x58, 0x40);
318 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x10);
319 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
320 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x35, 0x00);
321 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x23);
322 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
323 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x00, 0x80);
324 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x01, 0x84);
325 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x05, 0x2d);
326 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x06, 0x00);
327 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x07, 0x00);
328 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x08, 0x01);
329 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x09, 0x45);
330 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x11, 0x02);
331 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x12, 0x80);
332 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x15, 0x83);
333 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x16, 0x0c);
334 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x29, 0x0a);
335 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x30, 0xff);
336 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x31, 0xfe);
337 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x32, 0xfd);
338 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x33, 0xfb);
339 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x34, 0xf8);
340 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x35, 0xf5);
341 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x36, 0xf3);
342 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x37, 0xf2);
343 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x38, 0xf2);
344 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x39, 0xf2);
345 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x3a, 0xef);
346 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x3b, 0xec);
347 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x3d, 0xe9);
348 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x3f, 0xe5);
349 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x40, 0xe5);
350 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x41, 0xe5);
351 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x2a, 0x13);
352 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x45, 0xff);
353 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x46, 0xf4);
354 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x47, 0xe7);
355 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x48, 0xda);
356 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x49, 0xcd);
357 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x4a, 0xc0);
358 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x4b, 0xb3);
359 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x4c, 0xb2);
360 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x4d, 0xb2);
361 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x4e, 0xb2);
362 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x4f, 0x99);
363 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x50, 0x80);
364 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x51, 0x68);
365 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x52, 0x66);
366 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x53, 0x66);
367 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x54, 0x66);
368 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x2b, 0x0e);
369 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x58, 0xff);
370 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x59, 0xfb);
371 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x5a, 0xf7);
372 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x5b, 0xf3);
373 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x5c, 0xef);
374 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x5d, 0xe3);
375 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x5e, 0xda);
376 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x5f, 0xd8);
377 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x60, 0xd8);
378 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x61, 0xd8);
379 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x62, 0xcb);
380 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x63, 0xbf);
381 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x64, 0xb3);
382 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x65, 0xb2);
383 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x66, 0xb2);
384 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x67, 0xb2);
385 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x10);
386 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
387 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x51, 0x0f, 0xff);
388 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x53, 0x2c);
389 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x55, 0x00);
390 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xbb, 0x13);
391 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x3b, 0x03, 0xac, 0x1a, 0x04, 0x04);
392 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x2a);
393 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
394 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x25, 0x46);
395 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x30, 0x46);
396 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x39, 0x46);
397 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x26);
398 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
399 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x01, 0xb0);
400 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x19, 0x10);
401 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x1a, 0xe0);
402 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x1b, 0x10);
403 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x1c, 0x00);
404 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x2a, 0x10);
405 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x2b, 0xe0);
406 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0xf0);
407 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
408 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x84, 0x08);
409 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x85, 0x0c);
410 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x20);
411 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
412 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x51, 0x00);
413 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x25);
414 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
415 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x91, 0x1f);
416 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x92, 0x0f);
417 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x93, 0x01);
418 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x94, 0x18);
419 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x95, 0x03);
420 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x96, 0x01);
421 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x10);
422 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xb0, 0x01);
423 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x25);
424 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
425 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x19, 0x1f);
426 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x1b, 0x1b);
427 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x24);
428 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
429 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xb8, 0x28);
430 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x27);
431 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
432 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xd0, 0x31);
433 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xd1, 0x20);
434 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xd4, 0x08);
435 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xde, 0x80);
436 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xdf, 0x02);
437 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x26);
438 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
439 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x00, 0x81);
440 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x01, 0xb0);
441 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x22);
442 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
443 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x6f, 0x01);
444 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x70, 0x11);
445 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x73, 0x01);
446 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x74, 0x4d);
447 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xa0, 0x3f);
448 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xa9, 0x50);
449 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xaa, 0x28);
450 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xab, 0x28);
451 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xad, 0x10);
452 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xb8, 0x00);
453 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xb9, 0x4b);
454 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xba, 0x96);
455 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xbb, 0x4b);
456 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xbe, 0x07);
457 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xbf, 0x4b);
458 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xc0, 0x07);
459 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xc1, 0x5c);
460 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xc2, 0x00);
461 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xc5, 0x00);
462 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xc6, 0x3f);
463 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xc7, 0x00);
464 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xca, 0x08);
465 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xcb, 0x40);
466 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xce, 0x00);
467 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xcf, 0x08);
468 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xd0, 0x40);
469 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xd3, 0x08);
470 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xd4, 0x40);
471 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x25);
472 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
473 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xbc, 0x01);
474 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xbd, 0x1c);
475 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x2a);
476 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
477 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x9a, 0x03);
478 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x10);
479 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x11);
480 	msleep(70);
481 	mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x29);
482 
483 	return 0;
484 }
485 
j606f_boe_init_sequence(struct panel_info * pinfo)486 static int j606f_boe_init_sequence(struct panel_info *pinfo)
487 {
488 	struct mipi_dsi_device *dsi = pinfo->dsi[0];
489 	struct device *dev = &dsi->dev;
490 	int ret;
491 
492 	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x20);
493 	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
494 	mipi_dsi_dcs_write_seq(dsi, 0x05, 0xd9);
495 	mipi_dsi_dcs_write_seq(dsi, 0x07, 0x78);
496 	mipi_dsi_dcs_write_seq(dsi, 0x08, 0x5a);
497 	mipi_dsi_dcs_write_seq(dsi, 0x0d, 0x63);
498 	mipi_dsi_dcs_write_seq(dsi, 0x0e, 0x91);
499 	mipi_dsi_dcs_write_seq(dsi, 0x0f, 0x73);
500 	mipi_dsi_dcs_write_seq(dsi, 0x95, 0xeb);
501 	mipi_dsi_dcs_write_seq(dsi, 0x96, 0xeb);
502 	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_PARTIAL_ROWS, 0x11);
503 	mipi_dsi_dcs_write_seq(dsi, 0x6d, 0x66);
504 	mipi_dsi_dcs_write_seq(dsi, 0x75, 0xa2);
505 	mipi_dsi_dcs_write_seq(dsi, 0x77, 0xb3);
506 	mipi_dsi_dcs_write_seq(dsi, 0xb0, 0x00, 0x08, 0x00, 0x23, 0x00, 0x4d, 0x00, 0x6d, 0x00,
507 			       0x89, 0x00, 0xa1, 0x00, 0xb6, 0x00, 0xc9);
508 	mipi_dsi_dcs_write_seq(dsi, 0xb1, 0x00, 0xda, 0x01, 0x13, 0x01, 0x3c, 0x01, 0x7e, 0x01,
509 			       0xab, 0x01, 0xf7, 0x02, 0x2f, 0x02, 0x31);
510 	mipi_dsi_dcs_write_seq(dsi, 0xb2, 0x02, 0x67, 0x02, 0xa6, 0x02, 0xd1, 0x03, 0x08, 0x03,
511 			       0x2e, 0x03, 0x5b, 0x03, 0x6b, 0x03, 0x7b);
512 	mipi_dsi_dcs_write_seq(dsi, 0xb3, 0x03, 0x8e, 0x03, 0xa2, 0x03, 0xb7, 0x03, 0xe7, 0x03,
513 			       0xfd, 0x03, 0xff);
514 	mipi_dsi_dcs_write_seq(dsi, 0xb4, 0x00, 0x08, 0x00, 0x23, 0x00, 0x4d, 0x00, 0x6d, 0x00,
515 			       0x89, 0x00, 0xa1, 0x00, 0xb6, 0x00, 0xc9);
516 	mipi_dsi_dcs_write_seq(dsi, 0xb5, 0x00, 0xda, 0x01, 0x13, 0x01, 0x3c, 0x01, 0x7e, 0x01,
517 			       0xab, 0x01, 0xf7, 0x02, 0x2f, 0x02, 0x31);
518 	mipi_dsi_dcs_write_seq(dsi, 0xb6, 0x02, 0x67, 0x02, 0xa6, 0x02, 0xd1, 0x03, 0x08, 0x03,
519 			       0x2e, 0x03, 0x5b, 0x03, 0x6b, 0x03, 0x7b);
520 	mipi_dsi_dcs_write_seq(dsi, 0xb7, 0x03, 0x8e, 0x03, 0xa2, 0x03, 0xb7, 0x03, 0xe7, 0x03,
521 			       0xfd, 0x03, 0xff);
522 	mipi_dsi_dcs_write_seq(dsi, 0xb8, 0x00, 0x08, 0x00, 0x23, 0x00, 0x4d, 0x00, 0x6d, 0x00,
523 			       0x89, 0x00, 0xa1, 0x00, 0xb6, 0x00, 0xc9);
524 	mipi_dsi_dcs_write_seq(dsi, 0xb9, 0x00, 0xda, 0x01, 0x13, 0x01, 0x3c, 0x01, 0x7e, 0x01,
525 			       0xab, 0x01, 0xf7, 0x02, 0x2f, 0x02, 0x31);
526 	mipi_dsi_dcs_write_seq(dsi, 0xba, 0x02, 0x67, 0x02, 0xa6, 0x02, 0xd1, 0x03, 0x08, 0x03,
527 			       0x2e, 0x03, 0x5b, 0x03, 0x6b, 0x03, 0x7b);
528 	mipi_dsi_dcs_write_seq(dsi, 0xbb, 0x03, 0x8e, 0x03, 0xa2, 0x03, 0xb7, 0x03, 0xe7, 0x03,
529 			       0xfd, 0x03, 0xff);
530 	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x21);
531 	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
532 	mipi_dsi_dcs_write_seq(dsi, 0xb0, 0x00, 0x00, 0x00, 0x1b, 0x00, 0x45, 0x00, 0x65, 0x00,
533 			       0x81, 0x00, 0x99, 0x00, 0xae, 0x00, 0xc1);
534 	mipi_dsi_dcs_write_seq(dsi, 0xb1, 0x00, 0xd2, 0x01, 0x0b, 0x01, 0x34, 0x01, 0x76, 0x01,
535 			       0xa3, 0x01, 0xef, 0x02, 0x27, 0x02, 0x29);
536 	mipi_dsi_dcs_write_seq(dsi, 0xb2, 0x02, 0x5f, 0x02, 0x9e, 0x02, 0xc9, 0x03, 0x00, 0x03,
537 			       0x26, 0x03, 0x53, 0x03, 0x63, 0x03, 0x73);
538 	mipi_dsi_dcs_write_seq(dsi, 0xb3, 0x03, 0x86, 0x03, 0x9a, 0x03, 0xaf, 0x03, 0xdf, 0x03,
539 			       0xf5, 0x03, 0xf7);
540 	mipi_dsi_dcs_write_seq(dsi, 0xb4, 0x00, 0x00, 0x00, 0x1b, 0x00, 0x45, 0x00, 0x65, 0x00,
541 			       0x81, 0x00, 0x99, 0x00, 0xae, 0x00, 0xc1);
542 	mipi_dsi_dcs_write_seq(dsi, 0xb5, 0x00, 0xd2, 0x01, 0x0b, 0x01, 0x34, 0x01, 0x76, 0x01,
543 			       0xa3, 0x01, 0xef, 0x02, 0x27, 0x02, 0x29);
544 	mipi_dsi_dcs_write_seq(dsi, 0xb6, 0x02, 0x5f, 0x02, 0x9e, 0x02, 0xc9, 0x03, 0x00, 0x03,
545 			       0x26, 0x03, 0x53, 0x03, 0x63, 0x03, 0x73);
546 	mipi_dsi_dcs_write_seq(dsi, 0xb7, 0x03, 0x86, 0x03, 0x9a, 0x03, 0xaf, 0x03, 0xdf, 0x03,
547 			       0xf5, 0x03, 0xf7);
548 	mipi_dsi_dcs_write_seq(dsi, 0xb8, 0x00, 0x00, 0x00, 0x1b, 0x00, 0x45, 0x00, 0x65, 0x00,
549 			       0x81, 0x00, 0x99, 0x00, 0xae, 0x00, 0xc1);
550 	mipi_dsi_dcs_write_seq(dsi, 0xb9, 0x00, 0xd2, 0x01, 0x0b, 0x01, 0x34, 0x01, 0x76, 0x01,
551 			       0xa3, 0x01, 0xef, 0x02, 0x27, 0x02, 0x29);
552 	mipi_dsi_dcs_write_seq(dsi, 0xba, 0x02, 0x5f, 0x02, 0x9e, 0x02, 0xc9, 0x03, 0x00, 0x03,
553 			       0x26, 0x03, 0x53, 0x03, 0x63, 0x03, 0x73);
554 	mipi_dsi_dcs_write_seq(dsi, 0xbb, 0x03, 0x86, 0x03, 0x9a, 0x03, 0xaf, 0x03, 0xdf, 0x03,
555 			       0xf5, 0x03, 0xf7);
556 	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x23);
557 	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
558 	mipi_dsi_dcs_write_seq(dsi, 0x00, 0x80);
559 	mipi_dsi_dcs_write_seq(dsi, 0x07, 0x00);
560 	mipi_dsi_dcs_write_seq(dsi, 0x11, 0x01);
561 	mipi_dsi_dcs_write_seq(dsi, 0x12, 0x77);
562 	mipi_dsi_dcs_write_seq(dsi, 0x15, 0x07);
563 	mipi_dsi_dcs_write_seq(dsi, 0x16, 0x07);
564 	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x24);
565 	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
566 	mipi_dsi_dcs_write_seq(dsi, 0x00, 0x00);
567 	mipi_dsi_dcs_write_seq(dsi, 0x01, 0x00);
568 	mipi_dsi_dcs_write_seq(dsi, 0x02, 0x1c);
569 	mipi_dsi_dcs_write_seq(dsi, 0x03, 0x1c);
570 	mipi_dsi_dcs_write_seq(dsi, 0x04, 0x1d);
571 	mipi_dsi_dcs_write_seq(dsi, 0x05, 0x1d);
572 	mipi_dsi_dcs_write_seq(dsi, 0x06, 0x04);
573 	mipi_dsi_dcs_write_seq(dsi, 0x07, 0x04);
574 	mipi_dsi_dcs_write_seq(dsi, 0x08, 0x0f);
575 	mipi_dsi_dcs_write_seq(dsi, 0x09, 0x0f);
576 	mipi_dsi_dcs_write_seq(dsi, 0x0a, 0x0e);
577 	mipi_dsi_dcs_write_seq(dsi, 0x0b, 0x0e);
578 	mipi_dsi_dcs_write_seq(dsi, 0x0c, 0x0d);
579 	mipi_dsi_dcs_write_seq(dsi, 0x0d, 0x0d);
580 	mipi_dsi_dcs_write_seq(dsi, 0x0e, 0x0c);
581 	mipi_dsi_dcs_write_seq(dsi, 0x0f, 0x0c);
582 	mipi_dsi_dcs_write_seq(dsi, 0x10, 0x08);
583 	mipi_dsi_dcs_write_seq(dsi, 0x11, 0x08);
584 	mipi_dsi_dcs_write_seq(dsi, 0x12, 0x00);
585 	mipi_dsi_dcs_write_seq(dsi, 0x13, 0x00);
586 	mipi_dsi_dcs_write_seq(dsi, 0x14, 0x00);
587 	mipi_dsi_dcs_write_seq(dsi, 0x15, 0x00);
588 	mipi_dsi_dcs_write_seq(dsi, 0x16, 0x00);
589 	mipi_dsi_dcs_write_seq(dsi, 0x17, 0x00);
590 	mipi_dsi_dcs_write_seq(dsi, 0x18, 0x1c);
591 	mipi_dsi_dcs_write_seq(dsi, 0x19, 0x1c);
592 	mipi_dsi_dcs_write_seq(dsi, 0x1a, 0x1d);
593 	mipi_dsi_dcs_write_seq(dsi, 0x1b, 0x1d);
594 	mipi_dsi_dcs_write_seq(dsi, 0x1c, 0x04);
595 	mipi_dsi_dcs_write_seq(dsi, 0x1d, 0x04);
596 	mipi_dsi_dcs_write_seq(dsi, 0x1e, 0x0f);
597 	mipi_dsi_dcs_write_seq(dsi, 0x1f, 0x0f);
598 	mipi_dsi_dcs_write_seq(dsi, 0x20, 0x0e);
599 	mipi_dsi_dcs_write_seq(dsi, 0x21, 0x0e);
600 	mipi_dsi_dcs_write_seq(dsi, 0x22, 0x0d);
601 	mipi_dsi_dcs_write_seq(dsi, 0x23, 0x0d);
602 	mipi_dsi_dcs_write_seq(dsi, 0x24, 0x0c);
603 	mipi_dsi_dcs_write_seq(dsi, 0x25, 0x0c);
604 	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_GAMMA_CURVE, 0x08);
605 	mipi_dsi_dcs_write_seq(dsi, 0x27, 0x08);
606 	mipi_dsi_dcs_write_seq(dsi, 0x28, 0x00);
607 	mipi_dsi_dcs_write_seq(dsi, 0x29, 0x00);
608 	mipi_dsi_dcs_write_seq(dsi, 0x2a, 0x00);
609 	mipi_dsi_dcs_write_seq(dsi, 0x2b, 0x00);
610 	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_LUT, 0x20);
611 	mipi_dsi_dcs_write_seq(dsi, 0x2f, 0x0a);
612 	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_PARTIAL_ROWS, 0x44);
613 	mipi_dsi_dcs_write_seq(dsi, 0x33, 0x0c);
614 	mipi_dsi_dcs_write_seq(dsi, 0x34, 0x32);
615 	mipi_dsi_dcs_write_seq(dsi, 0x37, 0x44);
616 	mipi_dsi_dcs_write_seq(dsi, 0x38, 0x40);
617 	mipi_dsi_dcs_write_seq(dsi, 0x39, 0x00);
618 
619 	ret = mipi_dsi_dcs_set_pixel_format(dsi, 0x9a);
620 	if (ret < 0) {
621 		dev_err(dev, "Failed to set pixel format: %d\n", ret);
622 		return ret;
623 	}
624 
625 	mipi_dsi_dcs_write_seq(dsi, 0x3b, 0xa0);
626 	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_3D_CONTROL, 0x42);
627 	mipi_dsi_dcs_write_seq(dsi, 0x3f, 0x06);
628 	mipi_dsi_dcs_write_seq(dsi, 0x43, 0x06);
629 	mipi_dsi_dcs_write_seq(dsi, 0x47, 0x66);
630 	mipi_dsi_dcs_write_seq(dsi, 0x4a, 0x9a);
631 	mipi_dsi_dcs_write_seq(dsi, 0x4b, 0xa0);
632 	mipi_dsi_dcs_write_seq(dsi, 0x4c, 0x91);
633 	mipi_dsi_dcs_write_seq(dsi, 0x4d, 0x21);
634 	mipi_dsi_dcs_write_seq(dsi, 0x4e, 0x43);
635 
636 	ret = mipi_dsi_dcs_set_display_brightness(dsi, 18);
637 	if (ret < 0) {
638 		dev_err(dev, "Failed to set display brightness: %d\n", ret);
639 		return ret;
640 	}
641 
642 	mipi_dsi_dcs_write_seq(dsi, 0x52, 0x34);
643 	mipi_dsi_dcs_write_seq(dsi, 0x55, 0x82, 0x02);
644 	mipi_dsi_dcs_write_seq(dsi, 0x56, 0x04);
645 	mipi_dsi_dcs_write_seq(dsi, 0x58, 0x21);
646 	mipi_dsi_dcs_write_seq(dsi, 0x59, 0x30);
647 	mipi_dsi_dcs_write_seq(dsi, 0x5a, 0xba);
648 	mipi_dsi_dcs_write_seq(dsi, 0x5b, 0xa0);
649 	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_CABC_MIN_BRIGHTNESS, 0x00, 0x06);
650 	mipi_dsi_dcs_write_seq(dsi, 0x5f, 0x00);
651 	mipi_dsi_dcs_write_seq(dsi, 0x65, 0x82);
652 	mipi_dsi_dcs_write_seq(dsi, 0x7e, 0x20);
653 	mipi_dsi_dcs_write_seq(dsi, 0x7f, 0x3c);
654 	mipi_dsi_dcs_write_seq(dsi, 0x82, 0x04);
655 	mipi_dsi_dcs_write_seq(dsi, 0x97, 0xc0);
656 	mipi_dsi_dcs_write_seq(dsi, 0xb6,
657 			       0x05, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05,
658 			       0x05, 0x00, 0x00);
659 	mipi_dsi_dcs_write_seq(dsi, 0x92, 0xc4);
660 	mipi_dsi_dcs_write_seq(dsi, 0x93, 0x1a);
661 	mipi_dsi_dcs_write_seq(dsi, 0x94, 0x5f);
662 	mipi_dsi_dcs_write_seq(dsi, 0xd7, 0x55);
663 	mipi_dsi_dcs_write_seq(dsi, 0xda, 0x0a);
664 	mipi_dsi_dcs_write_seq(dsi, 0xde, 0x08);
665 	mipi_dsi_dcs_write_seq(dsi, 0xdb, 0x05);
666 	mipi_dsi_dcs_write_seq(dsi, 0xdc, 0xc4);
667 	mipi_dsi_dcs_write_seq(dsi, 0xdd, 0x22);
668 	mipi_dsi_dcs_write_seq(dsi, 0xdf, 0x05);
669 	mipi_dsi_dcs_write_seq(dsi, 0xe0, 0xc4);
670 	mipi_dsi_dcs_write_seq(dsi, 0xe1, 0x05);
671 	mipi_dsi_dcs_write_seq(dsi, 0xe2, 0xc4);
672 	mipi_dsi_dcs_write_seq(dsi, 0xe3, 0x05);
673 	mipi_dsi_dcs_write_seq(dsi, 0xe4, 0xc4);
674 	mipi_dsi_dcs_write_seq(dsi, 0xe5, 0x05);
675 	mipi_dsi_dcs_write_seq(dsi, 0xe6, 0xc4);
676 	mipi_dsi_dcs_write_seq(dsi, 0x5c, 0x88);
677 	mipi_dsi_dcs_write_seq(dsi, 0x5d, 0x08);
678 	mipi_dsi_dcs_write_seq(dsi, 0x8d, 0x88);
679 	mipi_dsi_dcs_write_seq(dsi, 0x8e, 0x08);
680 	mipi_dsi_dcs_write_seq(dsi, 0xb5, 0x90);
681 	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x25);
682 	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
683 	mipi_dsi_dcs_write_seq(dsi, 0x05, 0x00);
684 	mipi_dsi_dcs_write_seq(dsi, 0x19, 0x07);
685 	mipi_dsi_dcs_write_seq(dsi, 0x1f, 0xba);
686 	mipi_dsi_dcs_write_seq(dsi, 0x20, 0xa0);
687 	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_GAMMA_CURVE, 0xba);
688 	mipi_dsi_dcs_write_seq(dsi, 0x27, 0xa0);
689 	mipi_dsi_dcs_write_seq(dsi, 0x33, 0xba);
690 	mipi_dsi_dcs_write_seq(dsi, 0x34, 0xa0);
691 	mipi_dsi_dcs_write_seq(dsi, 0x3f, 0xe0);
692 	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_VSYNC_TIMING, 0x00);
693 	mipi_dsi_dcs_write_seq(dsi, 0x44, 0x00);
694 	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_GET_SCANLINE, 0x40);
695 	mipi_dsi_dcs_write_seq(dsi, 0x48, 0xba);
696 	mipi_dsi_dcs_write_seq(dsi, 0x49, 0xa0);
697 	mipi_dsi_dcs_write_seq(dsi, 0x5b, 0x00);
698 	mipi_dsi_dcs_write_seq(dsi, 0x5c, 0x00);
699 	mipi_dsi_dcs_write_seq(dsi, 0x5d, 0x00);
700 	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_CABC_MIN_BRIGHTNESS, 0xd0);
701 	mipi_dsi_dcs_write_seq(dsi, 0x61, 0xba);
702 	mipi_dsi_dcs_write_seq(dsi, 0x62, 0xa0);
703 	mipi_dsi_dcs_write_seq(dsi, 0xf1, 0x10);
704 	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x2a);
705 	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
706 	mipi_dsi_dcs_write_seq(dsi, 0x64, 0x16);
707 	mipi_dsi_dcs_write_seq(dsi, 0x67, 0x16);
708 	mipi_dsi_dcs_write_seq(dsi, 0x6a, 0x16);
709 	mipi_dsi_dcs_write_seq(dsi, 0x70, 0x30);
710 	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_READ_PPS_START, 0xf3);
711 	mipi_dsi_dcs_write_seq(dsi, 0xa3, 0xff);
712 	mipi_dsi_dcs_write_seq(dsi, 0xa4, 0xff);
713 	mipi_dsi_dcs_write_seq(dsi, 0xa5, 0xff);
714 	mipi_dsi_dcs_write_seq(dsi, 0xd6, 0x08);
715 	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x26);
716 	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
717 	mipi_dsi_dcs_write_seq(dsi, 0x00, 0xa1);
718 	mipi_dsi_dcs_write_seq(dsi, 0x0a, 0xf2);
719 	mipi_dsi_dcs_write_seq(dsi, 0x04, 0x28);
720 	mipi_dsi_dcs_write_seq(dsi, 0x06, 0x30);
721 	mipi_dsi_dcs_write_seq(dsi, 0x0c, 0x13);
722 	mipi_dsi_dcs_write_seq(dsi, 0x0d, 0x0a);
723 	mipi_dsi_dcs_write_seq(dsi, 0x0f, 0x0a);
724 	mipi_dsi_dcs_write_seq(dsi, 0x11, 0x00);
725 	mipi_dsi_dcs_write_seq(dsi, 0x12, 0x50);
726 	mipi_dsi_dcs_write_seq(dsi, 0x13, 0x51);
727 	mipi_dsi_dcs_write_seq(dsi, 0x14, 0x65);
728 	mipi_dsi_dcs_write_seq(dsi, 0x15, 0x00);
729 	mipi_dsi_dcs_write_seq(dsi, 0x16, 0x10);
730 	mipi_dsi_dcs_write_seq(dsi, 0x17, 0xa0);
731 	mipi_dsi_dcs_write_seq(dsi, 0x18, 0x86);
732 	mipi_dsi_dcs_write_seq(dsi, 0x19, 0x11);
733 	mipi_dsi_dcs_write_seq(dsi, 0x1a, 0x7b);
734 	mipi_dsi_dcs_write_seq(dsi, 0x1b, 0x10);
735 	mipi_dsi_dcs_write_seq(dsi, 0x1c, 0xbb);
736 	mipi_dsi_dcs_write_seq(dsi, 0x22, 0x00);
737 	mipi_dsi_dcs_write_seq(dsi, 0x23, 0x00);
738 	mipi_dsi_dcs_write_seq(dsi, 0x2a, 0x11);
739 	mipi_dsi_dcs_write_seq(dsi, 0x2b, 0x7b);
740 	mipi_dsi_dcs_write_seq(dsi, 0x1d, 0x00);
741 	mipi_dsi_dcs_write_seq(dsi, 0x1e, 0xc3);
742 	mipi_dsi_dcs_write_seq(dsi, 0x1f, 0xc3);
743 	mipi_dsi_dcs_write_seq(dsi, 0x24, 0x00);
744 	mipi_dsi_dcs_write_seq(dsi, 0x25, 0xc3);
745 	mipi_dsi_dcs_write_seq(dsi, 0x2f, 0x05);
746 	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_PARTIAL_ROWS, 0xc3);
747 	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_PARTIAL_COLUMNS, 0x00);
748 	mipi_dsi_dcs_write_seq(dsi, 0x32, 0xc3);
749 	mipi_dsi_dcs_write_seq(dsi, 0x39, 0x00);
750 
751 	ret = mipi_dsi_dcs_set_pixel_format(dsi, 0xc3);
752 	if (ret < 0) {
753 		dev_err(dev, "Failed to set pixel format: %d\n", ret);
754 		return ret;
755 	}
756 
757 	mipi_dsi_dcs_write_seq(dsi, 0x20, 0x01);
758 	mipi_dsi_dcs_write_seq(dsi, 0x33, 0x11);
759 	mipi_dsi_dcs_write_seq(dsi, 0x34, 0x78);
760 	mipi_dsi_dcs_write_seq(dsi, 0x35, 0x16);
761 	mipi_dsi_dcs_write_seq(dsi, 0xc8, 0x04);
762 	mipi_dsi_dcs_write_seq(dsi, 0xc9, 0x82);
763 	mipi_dsi_dcs_write_seq(dsi, 0xca, 0x4e);
764 	mipi_dsi_dcs_write_seq(dsi, 0xcb, 0x00);
765 	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_READ_PPS_CONTINUE, 0x4c);
766 	mipi_dsi_dcs_write_seq(dsi, 0xaa, 0x47);
767 	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x27);
768 	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
769 	mipi_dsi_dcs_write_seq(dsi, 0x56, 0x06);
770 	mipi_dsi_dcs_write_seq(dsi, 0x58, 0x80);
771 	mipi_dsi_dcs_write_seq(dsi, 0x59, 0x53);
772 	mipi_dsi_dcs_write_seq(dsi, 0x5a, 0x00);
773 	mipi_dsi_dcs_write_seq(dsi, 0x5b, 0x14);
774 	mipi_dsi_dcs_write_seq(dsi, 0x5c, 0x00);
775 	mipi_dsi_dcs_write_seq(dsi, 0x5d, 0x01);
776 	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_CABC_MIN_BRIGHTNESS, 0x20);
777 	mipi_dsi_dcs_write_seq(dsi, 0x5f, 0x10);
778 	mipi_dsi_dcs_write_seq(dsi, 0x60, 0x00);
779 	mipi_dsi_dcs_write_seq(dsi, 0x61, 0x1d);
780 	mipi_dsi_dcs_write_seq(dsi, 0x62, 0x00);
781 	mipi_dsi_dcs_write_seq(dsi, 0x63, 0x01);
782 	mipi_dsi_dcs_write_seq(dsi, 0x64, 0x24);
783 	mipi_dsi_dcs_write_seq(dsi, 0x65, 0x1c);
784 	mipi_dsi_dcs_write_seq(dsi, 0x66, 0x00);
785 	mipi_dsi_dcs_write_seq(dsi, 0x67, 0x01);
786 	mipi_dsi_dcs_write_seq(dsi, 0x68, 0x25);
787 	mipi_dsi_dcs_write_seq(dsi, 0x00, 0x00);
788 	mipi_dsi_dcs_write_seq(dsi, 0x78, 0x00);
789 	mipi_dsi_dcs_write_seq(dsi, 0xc3, 0x00);
790 	mipi_dsi_dcs_write_seq(dsi, 0xd1, 0x24);
791 	mipi_dsi_dcs_write_seq(dsi, 0xd2, 0x30);
792 	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x2a);
793 	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
794 	mipi_dsi_dcs_write_seq(dsi, 0x22, 0x2f);
795 	mipi_dsi_dcs_write_seq(dsi, 0x23, 0x08);
796 	mipi_dsi_dcs_write_seq(dsi, 0x24, 0x00);
797 	mipi_dsi_dcs_write_seq(dsi, 0x25, 0xc3);
798 	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_GAMMA_CURVE, 0xf8);
799 	mipi_dsi_dcs_write_seq(dsi, 0x27, 0x00);
800 	mipi_dsi_dcs_write_seq(dsi, 0x28, 0x1a);
801 	mipi_dsi_dcs_write_seq(dsi, 0x29, 0x00);
802 	mipi_dsi_dcs_write_seq(dsi, 0x2a, 0x1a);
803 	mipi_dsi_dcs_write_seq(dsi, 0x2b, 0x00);
804 	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_LUT, 0x1a);
805 	mipi_dsi_dcs_write_seq(dsi, 0xff, 0xe0);
806 	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
807 	mipi_dsi_dcs_write_seq(dsi, 0x14, 0x60);
808 	mipi_dsi_dcs_write_seq(dsi, 0x16, 0xc0);
809 	mipi_dsi_dcs_write_seq(dsi, 0xff, 0xf0);
810 	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
811 
812 	ret = mipi_dsi_dcs_set_pixel_format(dsi, 0x08);
813 	if (ret < 0) {
814 		dev_err(dev, "Failed to set pixel format: %d\n", ret);
815 		return ret;
816 	}
817 
818 	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x24);
819 	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
820 
821 	ret = mipi_dsi_dcs_set_pixel_format(dsi, 0x5d);
822 	if (ret < 0) {
823 		dev_err(dev, "Failed to set pixel format: %d\n", ret);
824 		return ret;
825 	}
826 
827 	mipi_dsi_dcs_write_seq(dsi, 0x3b, 0x60);
828 	mipi_dsi_dcs_write_seq(dsi, 0x4a, 0x5d);
829 	mipi_dsi_dcs_write_seq(dsi, 0x4b, 0x60);
830 	mipi_dsi_dcs_write_seq(dsi, 0x5a, 0x70);
831 	mipi_dsi_dcs_write_seq(dsi, 0x5b, 0x60);
832 	mipi_dsi_dcs_write_seq(dsi, 0x91, 0x44);
833 	mipi_dsi_dcs_write_seq(dsi, 0x92, 0x75);
834 	mipi_dsi_dcs_write_seq(dsi, 0xdb, 0x05);
835 	mipi_dsi_dcs_write_seq(dsi, 0xdc, 0x75);
836 	mipi_dsi_dcs_write_seq(dsi, 0xdd, 0x22);
837 	mipi_dsi_dcs_write_seq(dsi, 0xdf, 0x05);
838 	mipi_dsi_dcs_write_seq(dsi, 0xe0, 0x75);
839 	mipi_dsi_dcs_write_seq(dsi, 0xe1, 0x05);
840 	mipi_dsi_dcs_write_seq(dsi, 0xe2, 0x75);
841 	mipi_dsi_dcs_write_seq(dsi, 0xe3, 0x05);
842 	mipi_dsi_dcs_write_seq(dsi, 0xe4, 0x75);
843 	mipi_dsi_dcs_write_seq(dsi, 0xe5, 0x05);
844 	mipi_dsi_dcs_write_seq(dsi, 0xe6, 0x75);
845 	mipi_dsi_dcs_write_seq(dsi, 0x5c, 0x00);
846 	mipi_dsi_dcs_write_seq(dsi, 0x5d, 0x00);
847 	mipi_dsi_dcs_write_seq(dsi, 0x8d, 0x00);
848 	mipi_dsi_dcs_write_seq(dsi, 0x8e, 0x00);
849 	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x25);
850 	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
851 	mipi_dsi_dcs_write_seq(dsi, 0x1f, 0x70);
852 	mipi_dsi_dcs_write_seq(dsi, 0x20, 0x60);
853 	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_GAMMA_CURVE, 0x70);
854 	mipi_dsi_dcs_write_seq(dsi, 0x27, 0x60);
855 	mipi_dsi_dcs_write_seq(dsi, 0x33, 0x70);
856 	mipi_dsi_dcs_write_seq(dsi, 0x34, 0x60);
857 	mipi_dsi_dcs_write_seq(dsi, 0x48, 0x70);
858 	mipi_dsi_dcs_write_seq(dsi, 0x49, 0x60);
859 	mipi_dsi_dcs_write_seq(dsi, 0x5b, 0x00);
860 	mipi_dsi_dcs_write_seq(dsi, 0x61, 0x70);
861 	mipi_dsi_dcs_write_seq(dsi, 0x62, 0x60);
862 	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x26);
863 	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
864 	mipi_dsi_dcs_write_seq(dsi, 0x02, 0x31);
865 	mipi_dsi_dcs_write_seq(dsi, 0x19, 0x0a);
866 	mipi_dsi_dcs_write_seq(dsi, 0x1a, 0x7f);
867 	mipi_dsi_dcs_write_seq(dsi, 0x1b, 0x0a);
868 	mipi_dsi_dcs_write_seq(dsi, 0x1c, 0x0c);
869 	mipi_dsi_dcs_write_seq(dsi, 0x2a, 0x0a);
870 	mipi_dsi_dcs_write_seq(dsi, 0x2b, 0x7f);
871 	mipi_dsi_dcs_write_seq(dsi, 0x1e, 0x75);
872 	mipi_dsi_dcs_write_seq(dsi, 0x1f, 0x75);
873 	mipi_dsi_dcs_write_seq(dsi, 0x25, 0x75);
874 	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_PARTIAL_ROWS, 0x75);
875 	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_PARTIAL_COLUMNS, 0x05);
876 	mipi_dsi_dcs_write_seq(dsi, 0x32, 0x8d);
877 
878 	ret = mipi_dsi_dcs_set_pixel_format(dsi, 0x75);
879 	if (ret < 0) {
880 		dev_err(dev, "Failed to set pixel format: %d\n", ret);
881 		return ret;
882 	}
883 
884 	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x2a);
885 	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
886 	mipi_dsi_dcs_write_seq(dsi, 0x25, 0x75);
887 	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x10);
888 	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
889 	mipi_dsi_dcs_write_seq(dsi, 0xb9, 0x01);
890 	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x20);
891 	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
892 	mipi_dsi_dcs_write_seq(dsi, 0x18, 0x40);
893 	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x10);
894 	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
895 	mipi_dsi_dcs_write_seq(dsi, 0xb9, 0x02);
896 
897 	ret = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
898 	if (ret < 0) {
899 		dev_err(dev, "Failed to set tear on: %d\n", ret);
900 		return ret;
901 	}
902 
903 	mipi_dsi_dcs_write_seq(dsi, 0xbb, 0x13);
904 	mipi_dsi_dcs_write_seq(dsi, 0x3b, 0x03, 0x5f, 0x1a, 0x04, 0x04);
905 	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x10);
906 	usleep_range(10000, 11000);
907 	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
908 
909 	ret = mipi_dsi_dcs_set_display_brightness(dsi, 0);
910 	if (ret < 0) {
911 		dev_err(dev, "Failed to set display brightness: %d\n", ret);
912 		return ret;
913 	}
914 
915 	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x2c);
916 	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_POWER_SAVE, 0x00);
917 	mipi_dsi_dcs_write_seq(dsi, 0x68, 0x05, 0x01);
918 
919 	ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
920 	if (ret < 0) {
921 		dev_err(dev, "Failed to exit sleep mode: %d\n", ret);
922 		return ret;
923 	}
924 	msleep(100);
925 
926 	ret = mipi_dsi_dcs_set_display_on(dsi);
927 	if (ret < 0) {
928 		dev_err(dev, "Failed to set display on: %d\n", ret);
929 		return ret;
930 	}
931 	msleep(30);
932 
933 	return 0;
934 }
935 
936 static const struct drm_display_mode elish_boe_modes[] = {
937 	{
938 		.clock = (1600 + 60 + 8 + 60) * (2560 + 26 + 4 + 168) * 120 / 1000,
939 		.hdisplay = 1600,
940 		.hsync_start = 1600 + 60,
941 		.hsync_end = 1600 + 60 + 8,
942 		.htotal = 1600 + 60 + 8 + 60,
943 		.vdisplay = 2560,
944 		.vsync_start = 2560 + 26,
945 		.vsync_end = 2560 + 26 + 4,
946 		.vtotal = 2560 + 26 + 4 + 168,
947 	},
948 };
949 
950 static const struct drm_display_mode elish_csot_modes[] = {
951 	{
952 		.clock = (1600 + 200 + 40 + 52) * (2560 + 26 + 4 + 168) * 120 / 1000,
953 		.hdisplay = 1600,
954 		.hsync_start = 1600 + 200,
955 		.hsync_end = 1600 + 200 + 40,
956 		.htotal = 1600 + 200 + 40 + 52,
957 		.vdisplay = 2560,
958 		.vsync_start = 2560 + 26,
959 		.vsync_end = 2560 + 26 + 4,
960 		.vtotal = 2560 + 26 + 4 + 168,
961 	},
962 };
963 
964 static const struct drm_display_mode j606f_boe_modes[] = {
965 	{
966 		.clock = (1200 + 58 + 2 + 60) * (2000 + 26 + 2 + 93) * 60 / 1000,
967 		.hdisplay = 1200,
968 		.hsync_start = 1200 + 58,
969 		.hsync_end = 1200 + 58 + 2,
970 		.htotal = 1200 + 58 + 2 + 60,
971 		.vdisplay = 2000,
972 		.vsync_start = 2000 + 26,
973 		.vsync_end = 2000 + 26 + 2,
974 		.vtotal = 2000 + 26 + 2 + 93,
975 		.width_mm = 143,
976 		.height_mm = 235,
977 	},
978 };
979 
980 static const struct panel_desc elish_boe_desc = {
981 	.modes = elish_boe_modes,
982 	.num_modes = ARRAY_SIZE(elish_boe_modes),
983 	.dsi_info = {
984 		.type = "BOE-elish",
985 		.channel = 0,
986 		.node = NULL,
987 	},
988 	.width_mm = 127,
989 	.height_mm = 203,
990 	.bpc = 8,
991 	.lanes = 3,
992 	.format = MIPI_DSI_FMT_RGB888,
993 	.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS | MIPI_DSI_MODE_LPM,
994 	.init_sequence = elish_boe_init_sequence,
995 	.is_dual_dsi = true,
996 };
997 
998 static const struct panel_desc elish_csot_desc = {
999 	.modes = elish_csot_modes,
1000 	.num_modes = ARRAY_SIZE(elish_csot_modes),
1001 	.dsi_info = {
1002 		.type = "CSOT-elish",
1003 		.channel = 0,
1004 		.node = NULL,
1005 	},
1006 	.width_mm = 127,
1007 	.height_mm = 203,
1008 	.bpc = 8,
1009 	.lanes = 3,
1010 	.format = MIPI_DSI_FMT_RGB888,
1011 	.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS | MIPI_DSI_MODE_LPM,
1012 	.init_sequence = elish_csot_init_sequence,
1013 	.is_dual_dsi = true,
1014 };
1015 
1016 static const struct panel_desc j606f_boe_desc = {
1017 	.modes = j606f_boe_modes,
1018 	.num_modes = ARRAY_SIZE(j606f_boe_modes),
1019 	.width_mm = 143,
1020 	.height_mm = 235,
1021 	.bpc = 8,
1022 	.lanes = 4,
1023 	.format = MIPI_DSI_FMT_RGB888,
1024 	.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
1025 		      MIPI_DSI_CLOCK_NON_CONTINUOUS | MIPI_DSI_MODE_LPM,
1026 	.init_sequence = j606f_boe_init_sequence,
1027 	.has_dcs_backlight = true,
1028 };
1029 
nt36523_reset(struct panel_info * pinfo)1030 static void nt36523_reset(struct panel_info *pinfo)
1031 {
1032 	gpiod_set_value_cansleep(pinfo->reset_gpio, 1);
1033 	usleep_range(12000, 13000);
1034 	gpiod_set_value_cansleep(pinfo->reset_gpio, 0);
1035 	usleep_range(12000, 13000);
1036 	gpiod_set_value_cansleep(pinfo->reset_gpio, 1);
1037 	usleep_range(12000, 13000);
1038 	gpiod_set_value_cansleep(pinfo->reset_gpio, 0);
1039 	usleep_range(12000, 13000);
1040 }
1041 
nt36523_prepare(struct drm_panel * panel)1042 static int nt36523_prepare(struct drm_panel *panel)
1043 {
1044 	struct panel_info *pinfo = to_panel_info(panel);
1045 	int ret;
1046 
1047 	if (pinfo->prepared)
1048 		return 0;
1049 
1050 	ret = regulator_enable(pinfo->vddio);
1051 	if (ret) {
1052 		dev_err(panel->dev, "failed to enable vddio regulator: %d\n", ret);
1053 		return ret;
1054 	}
1055 
1056 	nt36523_reset(pinfo);
1057 
1058 	ret = pinfo->desc->init_sequence(pinfo);
1059 	if (ret < 0) {
1060 		regulator_disable(pinfo->vddio);
1061 		dev_err(panel->dev, "failed to initialize panel: %d\n", ret);
1062 		return ret;
1063 	}
1064 
1065 	pinfo->prepared = true;
1066 
1067 	return 0;
1068 }
1069 
nt36523_disable(struct drm_panel * panel)1070 static int nt36523_disable(struct drm_panel *panel)
1071 {
1072 	struct panel_info *pinfo = to_panel_info(panel);
1073 	int i, ret;
1074 
1075 	for (i = 0; i < DSI_NUM_MIN + pinfo->desc->is_dual_dsi; i++) {
1076 		ret = mipi_dsi_dcs_set_display_off(pinfo->dsi[i]);
1077 		if (ret < 0)
1078 			dev_err(&pinfo->dsi[i]->dev, "failed to set display off: %d\n", ret);
1079 	}
1080 
1081 	for (i = 0; i < DSI_NUM_MIN + pinfo->desc->is_dual_dsi; i++) {
1082 		ret = mipi_dsi_dcs_enter_sleep_mode(pinfo->dsi[i]);
1083 		if (ret < 0)
1084 			dev_err(&pinfo->dsi[i]->dev, "failed to enter sleep mode: %d\n", ret);
1085 	}
1086 
1087 	msleep(70);
1088 
1089 	return 0;
1090 }
1091 
nt36523_unprepare(struct drm_panel * panel)1092 static int nt36523_unprepare(struct drm_panel *panel)
1093 {
1094 	struct panel_info *pinfo = to_panel_info(panel);
1095 
1096 	if (!pinfo->prepared)
1097 		return 0;
1098 
1099 	gpiod_set_value_cansleep(pinfo->reset_gpio, 1);
1100 	regulator_disable(pinfo->vddio);
1101 
1102 	pinfo->prepared = false;
1103 
1104 	return 0;
1105 }
1106 
nt36523_remove(struct mipi_dsi_device * dsi)1107 static void nt36523_remove(struct mipi_dsi_device *dsi)
1108 {
1109 	struct panel_info *pinfo = mipi_dsi_get_drvdata(dsi);
1110 	int ret;
1111 
1112 	ret = mipi_dsi_detach(pinfo->dsi[0]);
1113 	if (ret < 0)
1114 		dev_err(&dsi->dev, "failed to detach from DSI0 host: %d\n", ret);
1115 
1116 	if (pinfo->desc->is_dual_dsi) {
1117 		ret = mipi_dsi_detach(pinfo->dsi[1]);
1118 		if (ret < 0)
1119 			dev_err(&pinfo->dsi[1]->dev, "failed to detach from DSI1 host: %d\n", ret);
1120 		mipi_dsi_device_unregister(pinfo->dsi[1]);
1121 	}
1122 
1123 	drm_panel_remove(&pinfo->panel);
1124 }
1125 
nt36523_get_modes(struct drm_panel * panel,struct drm_connector * connector)1126 static int nt36523_get_modes(struct drm_panel *panel,
1127 			       struct drm_connector *connector)
1128 {
1129 	struct panel_info *pinfo = to_panel_info(panel);
1130 	int i;
1131 
1132 	for (i = 0; i < pinfo->desc->num_modes; i++) {
1133 		const struct drm_display_mode *m = &pinfo->desc->modes[i];
1134 		struct drm_display_mode *mode;
1135 
1136 		mode = drm_mode_duplicate(connector->dev, m);
1137 		if (!mode) {
1138 			dev_err(panel->dev, "failed to add mode %ux%u@%u\n",
1139 				m->hdisplay, m->vdisplay, drm_mode_vrefresh(m));
1140 			return -ENOMEM;
1141 		}
1142 
1143 		mode->type = DRM_MODE_TYPE_DRIVER;
1144 		if (i == 0)
1145 			mode->type |= DRM_MODE_TYPE_PREFERRED;
1146 
1147 		drm_mode_set_name(mode);
1148 		drm_mode_probed_add(connector, mode);
1149 	}
1150 
1151 	connector->display_info.width_mm = pinfo->desc->width_mm;
1152 	connector->display_info.height_mm = pinfo->desc->height_mm;
1153 	connector->display_info.bpc = pinfo->desc->bpc;
1154 
1155 	return pinfo->desc->num_modes;
1156 }
1157 
nt36523_get_orientation(struct drm_panel * panel)1158 static enum drm_panel_orientation nt36523_get_orientation(struct drm_panel *panel)
1159 {
1160 	struct panel_info *pinfo = to_panel_info(panel);
1161 
1162 	return pinfo->orientation;
1163 }
1164 
1165 static const struct drm_panel_funcs nt36523_panel_funcs = {
1166 	.disable = nt36523_disable,
1167 	.prepare = nt36523_prepare,
1168 	.unprepare = nt36523_unprepare,
1169 	.get_modes = nt36523_get_modes,
1170 	.get_orientation = nt36523_get_orientation,
1171 };
1172 
nt36523_bl_update_status(struct backlight_device * bl)1173 static int nt36523_bl_update_status(struct backlight_device *bl)
1174 {
1175 	struct mipi_dsi_device *dsi = bl_get_data(bl);
1176 	u16 brightness = backlight_get_brightness(bl);
1177 	int ret;
1178 
1179 	dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
1180 
1181 	ret = mipi_dsi_dcs_set_display_brightness_large(dsi, brightness);
1182 	if (ret < 0)
1183 		return ret;
1184 
1185 	dsi->mode_flags |= MIPI_DSI_MODE_LPM;
1186 
1187 	return 0;
1188 }
1189 
nt36523_bl_get_brightness(struct backlight_device * bl)1190 static int nt36523_bl_get_brightness(struct backlight_device *bl)
1191 {
1192 	struct mipi_dsi_device *dsi = bl_get_data(bl);
1193 	u16 brightness;
1194 	int ret;
1195 
1196 	dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
1197 
1198 	ret = mipi_dsi_dcs_get_display_brightness_large(dsi, &brightness);
1199 	if (ret < 0)
1200 		return ret;
1201 
1202 	dsi->mode_flags |= MIPI_DSI_MODE_LPM;
1203 
1204 	return brightness;
1205 }
1206 
1207 static const struct backlight_ops nt36523_bl_ops = {
1208 	.update_status = nt36523_bl_update_status,
1209 	.get_brightness = nt36523_bl_get_brightness,
1210 };
1211 
nt36523_create_backlight(struct mipi_dsi_device * dsi)1212 static struct backlight_device *nt36523_create_backlight(struct mipi_dsi_device *dsi)
1213 {
1214 	struct device *dev = &dsi->dev;
1215 	const struct backlight_properties props = {
1216 		.type = BACKLIGHT_RAW,
1217 		.brightness = 512,
1218 		.max_brightness = 4095,
1219 		.scale = BACKLIGHT_SCALE_NON_LINEAR,
1220 	};
1221 
1222 	return devm_backlight_device_register(dev, dev_name(dev), dev, dsi,
1223 					      &nt36523_bl_ops, &props);
1224 }
1225 
nt36523_probe(struct mipi_dsi_device * dsi)1226 static int nt36523_probe(struct mipi_dsi_device *dsi)
1227 {
1228 	struct device *dev = &dsi->dev;
1229 	struct device_node *dsi1;
1230 	struct mipi_dsi_host *dsi1_host;
1231 	struct panel_info *pinfo;
1232 	const struct mipi_dsi_device_info *info;
1233 	int i, ret;
1234 
1235 	pinfo = devm_kzalloc(dev, sizeof(*pinfo), GFP_KERNEL);
1236 	if (!pinfo)
1237 		return -ENOMEM;
1238 
1239 	pinfo->vddio = devm_regulator_get(dev, "vddio");
1240 	if (IS_ERR(pinfo->vddio))
1241 		return dev_err_probe(dev, PTR_ERR(pinfo->vddio), "failed to get vddio regulator\n");
1242 
1243 	pinfo->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
1244 	if (IS_ERR(pinfo->reset_gpio))
1245 		return dev_err_probe(dev, PTR_ERR(pinfo->reset_gpio), "failed to get reset gpio\n");
1246 
1247 	pinfo->desc = of_device_get_match_data(dev);
1248 	if (!pinfo->desc)
1249 		return -ENODEV;
1250 
1251 	/* If the panel is dual dsi, register DSI1 */
1252 	if (pinfo->desc->is_dual_dsi) {
1253 		info = &pinfo->desc->dsi_info;
1254 
1255 		dsi1 = of_graph_get_remote_node(dsi->dev.of_node, 1, -1);
1256 		if (!dsi1) {
1257 			dev_err(dev, "cannot get secondary DSI node.\n");
1258 			return -ENODEV;
1259 		}
1260 
1261 		dsi1_host = of_find_mipi_dsi_host_by_node(dsi1);
1262 		of_node_put(dsi1);
1263 		if (!dsi1_host)
1264 			return dev_err_probe(dev, -EPROBE_DEFER, "cannot get secondary DSI host\n");
1265 
1266 		pinfo->dsi[1] = mipi_dsi_device_register_full(dsi1_host, info);
1267 		if (IS_ERR(pinfo->dsi[1])) {
1268 			dev_err(dev, "cannot get secondary DSI device\n");
1269 			return PTR_ERR(pinfo->dsi[1]);
1270 		}
1271 	}
1272 
1273 	pinfo->dsi[0] = dsi;
1274 	mipi_dsi_set_drvdata(dsi, pinfo);
1275 	drm_panel_init(&pinfo->panel, dev, &nt36523_panel_funcs, DRM_MODE_CONNECTOR_DSI);
1276 
1277 	ret = of_drm_get_panel_orientation(dev->of_node, &pinfo->orientation);
1278 	if (ret < 0) {
1279 		dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, ret);
1280 		return ret;
1281 	}
1282 
1283 	if (pinfo->desc->has_dcs_backlight) {
1284 		pinfo->panel.backlight = nt36523_create_backlight(dsi);
1285 		if (IS_ERR(pinfo->panel.backlight))
1286 			return dev_err_probe(dev, PTR_ERR(pinfo->panel.backlight),
1287 					     "Failed to create backlight\n");
1288 	} else {
1289 		ret = drm_panel_of_backlight(&pinfo->panel);
1290 		if (ret)
1291 			return dev_err_probe(dev, ret, "Failed to get backlight\n");
1292 	}
1293 
1294 	drm_panel_add(&pinfo->panel);
1295 
1296 	for (i = 0; i < DSI_NUM_MIN + pinfo->desc->is_dual_dsi; i++) {
1297 		pinfo->dsi[i]->lanes = pinfo->desc->lanes;
1298 		pinfo->dsi[i]->format = pinfo->desc->format;
1299 		pinfo->dsi[i]->mode_flags = pinfo->desc->mode_flags;
1300 
1301 		ret = mipi_dsi_attach(pinfo->dsi[i]);
1302 		if (ret < 0)
1303 			return dev_err_probe(dev, ret, "cannot attach to DSI%d host.\n", i);
1304 	}
1305 
1306 	return 0;
1307 }
1308 
1309 static const struct of_device_id nt36523_of_match[] = {
1310 	{
1311 		.compatible = "lenovo,j606f-boe-nt36523w",
1312 		.data = &j606f_boe_desc,
1313 	},
1314 	{
1315 		.compatible = "xiaomi,elish-boe-nt36523",
1316 		.data = &elish_boe_desc,
1317 	},
1318 	{
1319 		.compatible = "xiaomi,elish-csot-nt36523",
1320 		.data = &elish_csot_desc,
1321 	},
1322 	{},
1323 };
1324 MODULE_DEVICE_TABLE(of, nt36523_of_match);
1325 
1326 static struct mipi_dsi_driver nt36523_driver = {
1327 	.probe = nt36523_probe,
1328 	.remove = nt36523_remove,
1329 	.driver = {
1330 		.name = "panel-novatek-nt36523",
1331 		.of_match_table = nt36523_of_match,
1332 	},
1333 };
1334 module_mipi_dsi_driver(nt36523_driver);
1335 
1336 MODULE_AUTHOR("Jianhua Lu <lujianhua000@gmail.com>");
1337 MODULE_DESCRIPTION("DRM driver for Novatek NT36523 based MIPI DSI panels");
1338 MODULE_LICENSE("GPL");
1339