1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
4 * Copyright (C) 2014 Marek Vasut <marex@denx.de>
5 */
6
7 #include <common.h>
8 #include <dm.h>
9 #include <errno.h>
10 #include <usb.h>
11 #include <malloc.h>
12 #include <memalign.h>
13 #include <phys2bus.h>
14 #include <usbroothubdes.h>
15 #include <wait_bit.h>
16 #include <asm/io.h>
17 #include <power/regulator.h>
18 #include <reset.h>
19
20 #include "dwc2.h"
21
22 /* Use only HC channel 0. */
23 #define DWC2_HC_CHANNEL 0
24
25 #define DWC2_STATUS_BUF_SIZE 64
26 #define DWC2_DATA_BUF_SIZE (CONFIG_USB_DWC2_BUFFER_SIZE * 1024)
27
28 #define MAX_DEVICE 16
29 #define MAX_ENDPOINT 16
30
31 struct dwc2_priv {
32 #if CONFIG_IS_ENABLED(DM_USB)
33 uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
34 uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
35 #ifdef CONFIG_DM_REGULATOR
36 struct udevice *vbus_supply;
37 #endif
38 #else
39 uint8_t *aligned_buffer;
40 uint8_t *status_buffer;
41 #endif
42 u8 in_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
43 u8 out_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
44 struct dwc2_core_regs *regs;
45 int root_hub_devnum;
46 bool ext_vbus;
47 /*
48 * The hnp/srp capability must be disabled if the platform
49 * does't support hnp/srp. Otherwise the force mode can't work.
50 */
51 bool hnp_srp_disable;
52 bool oc_disable;
53
54 struct reset_ctl_bulk resets;
55 };
56
57 #if !CONFIG_IS_ENABLED(DM_USB)
58 /* We need cacheline-aligned buffers for DMA transfers and dcache support */
59 DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE,
60 ARCH_DMA_MINALIGN);
61 DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE,
62 ARCH_DMA_MINALIGN);
63
64 static struct dwc2_priv local;
65 #endif
66
67 /*
68 * DWC2 IP interface
69 */
70
71 /*
72 * Initializes the FSLSPClkSel field of the HCFG register
73 * depending on the PHY type.
74 */
init_fslspclksel(struct dwc2_core_regs * regs)75 static void init_fslspclksel(struct dwc2_core_regs *regs)
76 {
77 uint32_t phyclk;
78
79 #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
80 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
81 #else
82 /* High speed PHY running at full speed or high speed */
83 phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
84 #endif
85
86 #ifdef CONFIG_DWC2_ULPI_FS_LS
87 uint32_t hwcfg2 = readl(®s->ghwcfg2);
88 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
89 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
90 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
91 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
92
93 if (hval == 2 && fval == 1)
94 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
95 #endif
96
97 clrsetbits_le32(®s->host_regs.hcfg,
98 DWC2_HCFG_FSLSPCLKSEL_MASK,
99 phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET);
100 }
101
102 /*
103 * Flush a Tx FIFO.
104 *
105 * @param regs Programming view of DWC_otg controller.
106 * @param num Tx FIFO to flush.
107 */
dwc_otg_flush_tx_fifo(struct dwc2_core_regs * regs,const int num)108 static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
109 {
110 int ret;
111
112 writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
113 ®s->grstctl);
114 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_TXFFLSH,
115 false, 1000, false);
116 if (ret)
117 dev_info(dev, "%s: Timeout!\n", __func__);
118
119 /* Wait for 3 PHY Clocks */
120 udelay(1);
121 }
122
123 /*
124 * Flush Rx FIFO.
125 *
126 * @param regs Programming view of DWC_otg controller.
127 */
dwc_otg_flush_rx_fifo(struct dwc2_core_regs * regs)128 static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs)
129 {
130 int ret;
131
132 writel(DWC2_GRSTCTL_RXFFLSH, ®s->grstctl);
133 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_RXFFLSH,
134 false, 1000, false);
135 if (ret)
136 dev_info(dev, "%s: Timeout!\n", __func__);
137
138 /* Wait for 3 PHY Clocks */
139 udelay(1);
140 }
141
142 /*
143 * Do core a soft reset of the core. Be careful with this because it
144 * resets all the internal state machines of the core.
145 */
dwc_otg_core_reset(struct dwc2_core_regs * regs)146 static void dwc_otg_core_reset(struct dwc2_core_regs *regs)
147 {
148 int ret;
149
150 /* Wait for AHB master IDLE state. */
151 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_AHBIDLE,
152 true, 1000, false);
153 if (ret)
154 dev_info(dev, "%s: Timeout!\n", __func__);
155
156 /* Core Soft Reset */
157 writel(DWC2_GRSTCTL_CSFTRST, ®s->grstctl);
158 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_CSFTRST,
159 false, 1000, false);
160 if (ret)
161 dev_info(dev, "%s: Timeout!\n", __func__);
162
163 /*
164 * Wait for core to come out of reset.
165 * NOTE: This long sleep is _very_ important, otherwise the core will
166 * not stay in host mode after a connector ID change!
167 */
168 mdelay(100);
169 }
170
171 #if CONFIG_IS_ENABLED(DM_USB) && defined(CONFIG_DM_REGULATOR)
dwc_vbus_supply_init(struct udevice * dev)172 static int dwc_vbus_supply_init(struct udevice *dev)
173 {
174 struct dwc2_priv *priv = dev_get_priv(dev);
175 int ret;
176
177 ret = device_get_supply_regulator(dev, "vbus-supply",
178 &priv->vbus_supply);
179 if (ret) {
180 debug("%s: No vbus supply\n", dev->name);
181 return 0;
182 }
183
184 ret = regulator_set_enable(priv->vbus_supply, true);
185 if (ret) {
186 dev_err(dev, "Error enabling vbus supply\n");
187 return ret;
188 }
189
190 return 0;
191 }
192
dwc_vbus_supply_exit(struct udevice * dev)193 static int dwc_vbus_supply_exit(struct udevice *dev)
194 {
195 struct dwc2_priv *priv = dev_get_priv(dev);
196 int ret;
197
198 if (priv->vbus_supply) {
199 ret = regulator_set_enable(priv->vbus_supply, false);
200 if (ret) {
201 dev_err(dev, "Error disabling vbus supply\n");
202 return ret;
203 }
204 }
205
206 return 0;
207 }
208 #else
dwc_vbus_supply_init(struct udevice * dev)209 static int dwc_vbus_supply_init(struct udevice *dev)
210 {
211 return 0;
212 }
213
214 #if CONFIG_IS_ENABLED(DM_USB)
dwc_vbus_supply_exit(struct udevice * dev)215 static int dwc_vbus_supply_exit(struct udevice *dev)
216 {
217 return 0;
218 }
219 #endif
220 #endif
221
222 /*
223 * This function initializes the DWC_otg controller registers for
224 * host mode.
225 *
226 * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
227 * request queues. Host channels are reset to ensure that they are ready for
228 * performing transfers.
229 *
230 * @param dev USB Device (NULL if driver model is not being used)
231 * @param regs Programming view of DWC_otg controller
232 *
233 */
dwc_otg_core_host_init(struct udevice * dev,struct dwc2_core_regs * regs)234 static void dwc_otg_core_host_init(struct udevice *dev,
235 struct dwc2_core_regs *regs)
236 {
237 uint32_t nptxfifosize = 0;
238 uint32_t ptxfifosize = 0;
239 uint32_t hprt0 = 0;
240 int i, ret, num_channels;
241
242 /* Restart the Phy Clock */
243 writel(0, ®s->pcgcctl);
244
245 /* Initialize Host Configuration Register */
246 init_fslspclksel(regs);
247 #ifdef CONFIG_DWC2_DFLT_SPEED_FULL
248 setbits_le32(®s->host_regs.hcfg, DWC2_HCFG_FSLSSUPP);
249 #endif
250
251 /* Configure data FIFO sizes */
252 #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
253 if (readl(®s->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) {
254 /* Rx FIFO */
255 writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, ®s->grxfsiz);
256
257 /* Non-periodic Tx FIFO */
258 nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
259 DWC2_FIFOSIZE_DEPTH_OFFSET;
260 nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE <<
261 DWC2_FIFOSIZE_STARTADDR_OFFSET;
262 writel(nptxfifosize, ®s->gnptxfsiz);
263
264 /* Periodic Tx FIFO */
265 ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE <<
266 DWC2_FIFOSIZE_DEPTH_OFFSET;
267 ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE +
268 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
269 DWC2_FIFOSIZE_STARTADDR_OFFSET;
270 writel(ptxfifosize, ®s->hptxfsiz);
271 }
272 #endif
273
274 /* Clear Host Set HNP Enable in the OTG Control Register */
275 clrbits_le32(®s->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN);
276
277 /* Make sure the FIFOs are flushed. */
278 dwc_otg_flush_tx_fifo(regs, 0x10); /* All Tx FIFOs */
279 dwc_otg_flush_rx_fifo(regs);
280
281 /* Flush out any leftover queued requests. */
282 num_channels = readl(®s->ghwcfg2);
283 num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK;
284 num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET;
285 num_channels += 1;
286
287 for (i = 0; i < num_channels; i++)
288 clrsetbits_le32(®s->hc_regs[i].hcchar,
289 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR,
290 DWC2_HCCHAR_CHDIS);
291
292 /* Halt all channels to put them into a known state. */
293 for (i = 0; i < num_channels; i++) {
294 clrsetbits_le32(®s->hc_regs[i].hcchar,
295 DWC2_HCCHAR_EPDIR,
296 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
297 ret = wait_for_bit_le32(®s->hc_regs[i].hcchar,
298 DWC2_HCCHAR_CHEN, false, 1000, false);
299 if (ret)
300 dev_info("%s: Timeout!\n", __func__);
301 }
302
303 /* Turn on the vbus power. */
304 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) {
305 hprt0 = readl(®s->hprt0);
306 hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET);
307 hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG);
308 if (!(hprt0 & DWC2_HPRT0_PRTPWR)) {
309 hprt0 |= DWC2_HPRT0_PRTPWR;
310 writel(hprt0, ®s->hprt0);
311 }
312 }
313
314 if (dev)
315 dwc_vbus_supply_init(dev);
316 }
317
318 /*
319 * This function initializes the DWC_otg controller registers and
320 * prepares the core for device mode or host mode operation.
321 *
322 * @param regs Programming view of the DWC_otg controller
323 */
dwc_otg_core_init(struct dwc2_priv * priv)324 static void dwc_otg_core_init(struct dwc2_priv *priv)
325 {
326 struct dwc2_core_regs *regs = priv->regs;
327 uint32_t ahbcfg = 0;
328 uint32_t usbcfg = 0;
329 uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
330
331 /* Common Initialization */
332 usbcfg = readl(®s->gusbcfg);
333
334 /* Program the ULPI External VBUS bit if needed */
335 if (priv->ext_vbus) {
336 usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
337 if (!priv->oc_disable) {
338 usbcfg |= DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR |
339 DWC2_GUSBCFG_INDICATOR_PASSTHROUGH;
340 }
341 } else {
342 usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
343 }
344
345 /* Set external TS Dline pulsing */
346 #ifdef CONFIG_DWC2_TS_DLINE
347 usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
348 #else
349 usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
350 #endif
351 writel(usbcfg, ®s->gusbcfg);
352
353 /* Reset the Controller */
354 dwc_otg_core_reset(regs);
355
356 /*
357 * This programming sequence needs to happen in FS mode before
358 * any other programming occurs
359 */
360 #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \
361 (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
362 /* If FS mode with FS PHY */
363 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_PHYSEL);
364
365 /* Reset after a PHY select */
366 dwc_otg_core_reset(regs);
367
368 /*
369 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.
370 * Also do this on HNP Dev/Host mode switches (done in dev_init
371 * and host_init).
372 */
373 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
374 init_fslspclksel(regs);
375
376 #ifdef CONFIG_DWC2_I2C_ENABLE
377 /* Program GUSBCFG.OtgUtmifsSel to I2C */
378 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL);
379
380 /* Program GI2CCTL.I2CEn */
381 clrsetbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN |
382 DWC2_GI2CCTL_I2CDEVADDR_MASK,
383 1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET);
384 setbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN);
385 #endif
386
387 #else
388 /* High speed PHY. */
389
390 /*
391 * HS PHY parameters. These parameters are preserved during
392 * soft reset so only program the first time. Do a soft reset
393 * immediately after setting phyif.
394 */
395 usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
396 usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
397
398 if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */
399 #ifdef CONFIG_DWC2_PHY_ULPI_DDR
400 usbcfg |= DWC2_GUSBCFG_DDRSEL;
401 #else
402 usbcfg &= ~DWC2_GUSBCFG_DDRSEL;
403 #endif
404 } else { /* UTMI+ interface */
405 #if (CONFIG_DWC2_UTMI_WIDTH == 16)
406 usbcfg |= DWC2_GUSBCFG_PHYIF;
407 #endif
408 }
409
410 writel(usbcfg, ®s->gusbcfg);
411
412 /* Reset after setting the PHY parameters */
413 dwc_otg_core_reset(regs);
414 #endif
415
416 usbcfg = readl(®s->gusbcfg);
417 usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
418 #ifdef CONFIG_DWC2_ULPI_FS_LS
419 uint32_t hwcfg2 = readl(®s->ghwcfg2);
420 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
421 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
422 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
423 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
424 if (hval == 2 && fval == 1) {
425 usbcfg |= DWC2_GUSBCFG_ULPI_FSLS;
426 usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M;
427 }
428 #endif
429 if (priv->hnp_srp_disable)
430 usbcfg |= DWC2_GUSBCFG_FORCEHOSTMODE;
431
432 writel(usbcfg, ®s->gusbcfg);
433
434 /* Program the GAHBCFG Register. */
435 switch (readl(®s->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) {
436 case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY:
437 break;
438 case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA:
439 while (brst_sz > 1) {
440 ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET);
441 ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK;
442 brst_sz >>= 1;
443 }
444
445 #ifdef CONFIG_DWC2_DMA_ENABLE
446 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
447 #endif
448 break;
449
450 case DWC2_HWCFG2_ARCHITECTURE_INT_DMA:
451 ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
452 #ifdef CONFIG_DWC2_DMA_ENABLE
453 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
454 #endif
455 break;
456 }
457
458 writel(ahbcfg, ®s->gahbcfg);
459
460 /* Program the capabilities in GUSBCFG Register */
461 usbcfg = 0;
462
463 if (!priv->hnp_srp_disable)
464 usbcfg |= DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP;
465 #ifdef CONFIG_DWC2_IC_USB_CAP
466 usbcfg |= DWC2_GUSBCFG_IC_USB_CAP;
467 #endif
468
469 setbits_le32(®s->gusbcfg, usbcfg);
470 }
471
472 /*
473 * Prepares a host channel for transferring packets to/from a specific
474 * endpoint. The HCCHARn register is set up with the characteristics specified
475 * in _hc. Host channel interrupts that may need to be serviced while this
476 * transfer is in progress are enabled.
477 *
478 * @param regs Programming view of DWC_otg controller
479 * @param hc Information needed to initialize the host channel
480 */
dwc_otg_hc_init(struct dwc2_core_regs * regs,uint8_t hc_num,struct usb_device * dev,uint8_t dev_addr,uint8_t ep_num,uint8_t ep_is_in,uint8_t ep_type,uint16_t max_packet)481 static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
482 struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num,
483 uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet)
484 {
485 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[hc_num];
486 uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) |
487 (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) |
488 (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) |
489 (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) |
490 (max_packet << DWC2_HCCHAR_MPS_OFFSET);
491
492 if (dev->speed == USB_SPEED_LOW)
493 hcchar |= DWC2_HCCHAR_LSPDDEV;
494
495 /*
496 * Program the HCCHARn register with the endpoint characteristics
497 * for the current transfer.
498 */
499 writel(hcchar, &hc_regs->hcchar);
500
501 /* Program the HCSPLIT register, default to no SPLIT */
502 writel(0, &hc_regs->hcsplt);
503 }
504
dwc_otg_hc_init_split(struct dwc2_hc_regs * hc_regs,uint8_t hub_devnum,uint8_t hub_port)505 static void dwc_otg_hc_init_split(struct dwc2_hc_regs *hc_regs,
506 uint8_t hub_devnum, uint8_t hub_port)
507 {
508 uint32_t hcsplt = 0;
509
510 hcsplt = DWC2_HCSPLT_SPLTENA;
511 hcsplt |= hub_devnum << DWC2_HCSPLT_HUBADDR_OFFSET;
512 hcsplt |= hub_port << DWC2_HCSPLT_PRTADDR_OFFSET;
513
514 /* Program the HCSPLIT register for SPLITs */
515 writel(hcsplt, &hc_regs->hcsplt);
516 }
517
518 /*
519 * DWC2 to USB API interface
520 */
521 /* Direction: In ; Request: Status */
dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs * regs,struct usb_device * dev,void * buffer,int txlen,struct devrequest * cmd)522 static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs,
523 struct usb_device *dev, void *buffer,
524 int txlen, struct devrequest *cmd)
525 {
526 uint32_t hprt0 = 0;
527 uint32_t port_status = 0;
528 uint32_t port_change = 0;
529 int len = 0;
530 int stat = 0;
531
532 switch (cmd->requesttype & ~USB_DIR_IN) {
533 case 0:
534 *(uint16_t *)buffer = cpu_to_le16(1);
535 len = 2;
536 break;
537 case USB_RECIP_INTERFACE:
538 case USB_RECIP_ENDPOINT:
539 *(uint16_t *)buffer = cpu_to_le16(0);
540 len = 2;
541 break;
542 case USB_TYPE_CLASS:
543 *(uint32_t *)buffer = cpu_to_le32(0);
544 len = 4;
545 break;
546 case USB_RECIP_OTHER | USB_TYPE_CLASS:
547 hprt0 = readl(®s->hprt0);
548 if (hprt0 & DWC2_HPRT0_PRTCONNSTS)
549 port_status |= USB_PORT_STAT_CONNECTION;
550 if (hprt0 & DWC2_HPRT0_PRTENA)
551 port_status |= USB_PORT_STAT_ENABLE;
552 if (hprt0 & DWC2_HPRT0_PRTSUSP)
553 port_status |= USB_PORT_STAT_SUSPEND;
554 if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT)
555 port_status |= USB_PORT_STAT_OVERCURRENT;
556 if (hprt0 & DWC2_HPRT0_PRTRST)
557 port_status |= USB_PORT_STAT_RESET;
558 if (hprt0 & DWC2_HPRT0_PRTPWR)
559 port_status |= USB_PORT_STAT_POWER;
560
561 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW)
562 port_status |= USB_PORT_STAT_LOW_SPEED;
563 else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
564 DWC2_HPRT0_PRTSPD_HIGH)
565 port_status |= USB_PORT_STAT_HIGH_SPEED;
566
567 if (hprt0 & DWC2_HPRT0_PRTENCHNG)
568 port_change |= USB_PORT_STAT_C_ENABLE;
569 if (hprt0 & DWC2_HPRT0_PRTCONNDET)
570 port_change |= USB_PORT_STAT_C_CONNECTION;
571 if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG)
572 port_change |= USB_PORT_STAT_C_OVERCURRENT;
573
574 *(uint32_t *)buffer = cpu_to_le32(port_status |
575 (port_change << 16));
576 len = 4;
577 break;
578 default:
579 puts("unsupported root hub command\n");
580 stat = USB_ST_STALLED;
581 }
582
583 dev->act_len = min(len, txlen);
584 dev->status = stat;
585
586 return stat;
587 }
588
589 /* Direction: In ; Request: Descriptor */
dwc_otg_submit_rh_msg_in_descriptor(struct usb_device * dev,void * buffer,int txlen,struct devrequest * cmd)590 static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev,
591 void *buffer, int txlen,
592 struct devrequest *cmd)
593 {
594 unsigned char data[32];
595 uint32_t dsc;
596 int len = 0;
597 int stat = 0;
598 uint16_t wValue = cpu_to_le16(cmd->value);
599 uint16_t wLength = cpu_to_le16(cmd->length);
600
601 switch (cmd->requesttype & ~USB_DIR_IN) {
602 case 0:
603 switch (wValue & 0xff00) {
604 case 0x0100: /* device descriptor */
605 len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength);
606 memcpy(buffer, root_hub_dev_des, len);
607 break;
608 case 0x0200: /* configuration descriptor */
609 len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength);
610 memcpy(buffer, root_hub_config_des, len);
611 break;
612 case 0x0300: /* string descriptors */
613 switch (wValue & 0xff) {
614 case 0x00:
615 len = min3(txlen, (int)sizeof(root_hub_str_index0),
616 (int)wLength);
617 memcpy(buffer, root_hub_str_index0, len);
618 break;
619 case 0x01:
620 len = min3(txlen, (int)sizeof(root_hub_str_index1),
621 (int)wLength);
622 memcpy(buffer, root_hub_str_index1, len);
623 break;
624 }
625 break;
626 default:
627 stat = USB_ST_STALLED;
628 }
629 break;
630
631 case USB_TYPE_CLASS:
632 /* Root port config, set 1 port and nothing else. */
633 dsc = 0x00000001;
634
635 data[0] = 9; /* min length; */
636 data[1] = 0x29;
637 data[2] = dsc & RH_A_NDP;
638 data[3] = 0;
639 if (dsc & RH_A_PSM)
640 data[3] |= 0x1;
641 if (dsc & RH_A_NOCP)
642 data[3] |= 0x10;
643 else if (dsc & RH_A_OCPM)
644 data[3] |= 0x8;
645
646 /* corresponds to data[4-7] */
647 data[5] = (dsc & RH_A_POTPGT) >> 24;
648 data[7] = dsc & RH_B_DR;
649 if (data[2] < 7) {
650 data[8] = 0xff;
651 } else {
652 data[0] += 2;
653 data[8] = (dsc & RH_B_DR) >> 8;
654 data[9] = 0xff;
655 data[10] = data[9];
656 }
657
658 len = min3(txlen, (int)data[0], (int)wLength);
659 memcpy(buffer, data, len);
660 break;
661 default:
662 puts("unsupported root hub command\n");
663 stat = USB_ST_STALLED;
664 }
665
666 dev->act_len = min(len, txlen);
667 dev->status = stat;
668
669 return stat;
670 }
671
672 /* Direction: In ; Request: Configuration */
dwc_otg_submit_rh_msg_in_configuration(struct usb_device * dev,void * buffer,int txlen,struct devrequest * cmd)673 static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev,
674 void *buffer, int txlen,
675 struct devrequest *cmd)
676 {
677 int len = 0;
678 int stat = 0;
679
680 switch (cmd->requesttype & ~USB_DIR_IN) {
681 case 0:
682 *(uint8_t *)buffer = 0x01;
683 len = 1;
684 break;
685 default:
686 puts("unsupported root hub command\n");
687 stat = USB_ST_STALLED;
688 }
689
690 dev->act_len = min(len, txlen);
691 dev->status = stat;
692
693 return stat;
694 }
695
696 /* Direction: In */
dwc_otg_submit_rh_msg_in(struct dwc2_priv * priv,struct usb_device * dev,void * buffer,int txlen,struct devrequest * cmd)697 static int dwc_otg_submit_rh_msg_in(struct dwc2_priv *priv,
698 struct usb_device *dev, void *buffer,
699 int txlen, struct devrequest *cmd)
700 {
701 switch (cmd->request) {
702 case USB_REQ_GET_STATUS:
703 return dwc_otg_submit_rh_msg_in_status(priv->regs, dev, buffer,
704 txlen, cmd);
705 case USB_REQ_GET_DESCRIPTOR:
706 return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer,
707 txlen, cmd);
708 case USB_REQ_GET_CONFIGURATION:
709 return dwc_otg_submit_rh_msg_in_configuration(dev, buffer,
710 txlen, cmd);
711 default:
712 puts("unsupported root hub command\n");
713 return USB_ST_STALLED;
714 }
715 }
716
717 /* Direction: Out */
dwc_otg_submit_rh_msg_out(struct dwc2_priv * priv,struct usb_device * dev,void * buffer,int txlen,struct devrequest * cmd)718 static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv,
719 struct usb_device *dev,
720 void *buffer, int txlen,
721 struct devrequest *cmd)
722 {
723 struct dwc2_core_regs *regs = priv->regs;
724 int len = 0;
725 int stat = 0;
726 uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8);
727 uint16_t wValue = cpu_to_le16(cmd->value);
728
729 switch (bmrtype_breq & ~USB_DIR_IN) {
730 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT:
731 case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS:
732 break;
733
734 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
735 switch (wValue) {
736 case USB_PORT_FEAT_C_CONNECTION:
737 setbits_le32(®s->hprt0, DWC2_HPRT0_PRTCONNDET);
738 break;
739 }
740 break;
741
742 case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
743 switch (wValue) {
744 case USB_PORT_FEAT_SUSPEND:
745 break;
746
747 case USB_PORT_FEAT_RESET:
748 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
749 DWC2_HPRT0_PRTCONNDET |
750 DWC2_HPRT0_PRTENCHNG |
751 DWC2_HPRT0_PRTOVRCURRCHNG,
752 DWC2_HPRT0_PRTRST);
753 mdelay(50);
754 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTRST);
755 break;
756
757 case USB_PORT_FEAT_POWER:
758 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
759 DWC2_HPRT0_PRTCONNDET |
760 DWC2_HPRT0_PRTENCHNG |
761 DWC2_HPRT0_PRTOVRCURRCHNG,
762 DWC2_HPRT0_PRTRST);
763 break;
764
765 case USB_PORT_FEAT_ENABLE:
766 break;
767 }
768 break;
769 case (USB_REQ_SET_ADDRESS << 8):
770 priv->root_hub_devnum = wValue;
771 break;
772 case (USB_REQ_SET_CONFIGURATION << 8):
773 break;
774 default:
775 puts("unsupported root hub command\n");
776 stat = USB_ST_STALLED;
777 }
778
779 len = min(len, txlen);
780
781 dev->act_len = len;
782 dev->status = stat;
783
784 return stat;
785 }
786
dwc_otg_submit_rh_msg(struct dwc2_priv * priv,struct usb_device * dev,unsigned long pipe,void * buffer,int txlen,struct devrequest * cmd)787 static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev,
788 unsigned long pipe, void *buffer, int txlen,
789 struct devrequest *cmd)
790 {
791 int stat = 0;
792
793 if (usb_pipeint(pipe)) {
794 puts("Root-Hub submit IRQ: NOT implemented\n");
795 return 0;
796 }
797
798 if (cmd->requesttype & USB_DIR_IN)
799 stat = dwc_otg_submit_rh_msg_in(priv, dev, buffer, txlen, cmd);
800 else
801 stat = dwc_otg_submit_rh_msg_out(priv, dev, buffer, txlen, cmd);
802
803 mdelay(1);
804
805 return stat;
806 }
807
wait_for_chhltd(struct dwc2_hc_regs * hc_regs,uint32_t * sub,u8 * toggle)808 int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, u8 *toggle)
809 {
810 int ret;
811 uint32_t hcint, hctsiz;
812
813 ret = wait_for_bit_le32(&hc_regs->hcint, DWC2_HCINT_CHHLTD, true,
814 2000, false);
815 if (ret)
816 return ret;
817
818 hcint = readl(&hc_regs->hcint);
819 hctsiz = readl(&hc_regs->hctsiz);
820 *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >>
821 DWC2_HCTSIZ_XFERSIZE_OFFSET;
822 *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET;
823
824 debug("%s: HCINT=%08x sub=%u toggle=%d\n", __func__, hcint, *sub,
825 *toggle);
826
827 if (hcint & DWC2_HCINT_XFERCOMP)
828 return 0;
829
830 if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN))
831 return -EAGAIN;
832
833 debug("%s: Error (HCINT=%08x)\n", __func__, hcint);
834 return -EINVAL;
835 }
836
837 static int dwc2_eptype[] = {
838 DWC2_HCCHAR_EPTYPE_ISOC,
839 DWC2_HCCHAR_EPTYPE_INTR,
840 DWC2_HCCHAR_EPTYPE_CONTROL,
841 DWC2_HCCHAR_EPTYPE_BULK,
842 };
843
transfer_chunk(struct dwc2_hc_regs * hc_regs,void * aligned_buffer,u8 * pid,int in,void * buffer,int num_packets,int xfer_len,int * actual_len,int odd_frame)844 static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer,
845 u8 *pid, int in, void *buffer, int num_packets,
846 int xfer_len, int *actual_len, int odd_frame)
847 {
848 int ret = 0;
849 uint32_t sub;
850
851 debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
852 *pid, xfer_len, num_packets);
853
854 writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
855 (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
856 (*pid << DWC2_HCTSIZ_PID_OFFSET),
857 &hc_regs->hctsiz);
858
859 if (xfer_len) {
860 if (in) {
861 invalidate_dcache_range(
862 (uintptr_t)aligned_buffer,
863 (uintptr_t)aligned_buffer +
864 roundup(xfer_len, ARCH_DMA_MINALIGN));
865 } else {
866 memcpy(aligned_buffer, buffer, xfer_len);
867 flush_dcache_range(
868 (uintptr_t)aligned_buffer,
869 (uintptr_t)aligned_buffer +
870 roundup(xfer_len, ARCH_DMA_MINALIGN));
871 }
872 }
873
874 writel(phys_to_bus((unsigned long)aligned_buffer), &hc_regs->hcdma);
875
876 /* Clear old interrupt conditions for this host channel. */
877 writel(0x3fff, &hc_regs->hcint);
878
879 /* Set host channel enable after all other setup is complete. */
880 clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
881 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS |
882 DWC2_HCCHAR_ODDFRM,
883 (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
884 (odd_frame << DWC2_HCCHAR_ODDFRM_OFFSET) |
885 DWC2_HCCHAR_CHEN);
886
887 ret = wait_for_chhltd(hc_regs, &sub, pid);
888 if (ret < 0)
889 return ret;
890
891 if (in) {
892 xfer_len -= sub;
893
894 invalidate_dcache_range((unsigned long)aligned_buffer,
895 (unsigned long)aligned_buffer +
896 roundup(xfer_len, ARCH_DMA_MINALIGN));
897
898 memcpy(buffer, aligned_buffer, xfer_len);
899 }
900 *actual_len = xfer_len;
901
902 return ret;
903 }
904
chunk_msg(struct dwc2_priv * priv,struct usb_device * dev,unsigned long pipe,u8 * pid,int in,void * buffer,int len)905 int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
906 unsigned long pipe, u8 *pid, int in, void *buffer, int len)
907 {
908 struct dwc2_core_regs *regs = priv->regs;
909 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[DWC2_HC_CHANNEL];
910 struct dwc2_host_regs *host_regs = ®s->host_regs;
911 int devnum = usb_pipedevice(pipe);
912 int ep = usb_pipeendpoint(pipe);
913 int max = usb_maxpacket(dev, pipe);
914 int eptype = dwc2_eptype[usb_pipetype(pipe)];
915 int done = 0;
916 int ret = 0;
917 int do_split = 0;
918 int complete_split = 0;
919 uint32_t xfer_len;
920 uint32_t num_packets;
921 int stop_transfer = 0;
922 uint32_t max_xfer_len;
923 int ssplit_frame_num = 0;
924
925 debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid,
926 in, len);
927
928 max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max;
929 if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
930 max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE;
931 if (max_xfer_len > DWC2_DATA_BUF_SIZE)
932 max_xfer_len = DWC2_DATA_BUF_SIZE;
933
934 /* Make sure that max_xfer_len is a multiple of max packet size. */
935 num_packets = max_xfer_len / max;
936 max_xfer_len = num_packets * max;
937
938 /* Initialize channel */
939 dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in,
940 eptype, max);
941
942 /* Check if the target is a FS/LS device behind a HS hub */
943 if (dev->speed != USB_SPEED_HIGH) {
944 uint8_t hub_addr;
945 uint8_t hub_port;
946 uint32_t hprt0 = readl(®s->hprt0);
947 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
948 DWC2_HPRT0_PRTSPD_HIGH) {
949 usb_find_usb2_hub_address_port(dev, &hub_addr,
950 &hub_port);
951 dwc_otg_hc_init_split(hc_regs, hub_addr, hub_port);
952
953 do_split = 1;
954 num_packets = 1;
955 max_xfer_len = max;
956 }
957 }
958
959 do {
960 int actual_len = 0;
961 uint32_t hcint;
962 int odd_frame = 0;
963 xfer_len = len - done;
964
965 if (xfer_len > max_xfer_len)
966 xfer_len = max_xfer_len;
967 else if (xfer_len > max)
968 num_packets = (xfer_len + max - 1) / max;
969 else
970 num_packets = 1;
971
972 if (complete_split)
973 setbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
974 else if (do_split)
975 clrbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
976
977 if (eptype == DWC2_HCCHAR_EPTYPE_INTR) {
978 int uframe_num = readl(&host_regs->hfnum);
979 if (!(uframe_num & 0x1))
980 odd_frame = 1;
981 }
982
983 ret = transfer_chunk(hc_regs, priv->aligned_buffer, pid,
984 in, (char *)buffer + done, num_packets,
985 xfer_len, &actual_len, odd_frame);
986
987 hcint = readl(&hc_regs->hcint);
988 if (complete_split) {
989 stop_transfer = 0;
990 if (hcint & DWC2_HCINT_NYET) {
991 ret = 0;
992 int frame_num = DWC2_HFNUM_MAX_FRNUM &
993 readl(&host_regs->hfnum);
994 if (((frame_num - ssplit_frame_num) &
995 DWC2_HFNUM_MAX_FRNUM) > 4)
996 ret = -EAGAIN;
997 } else
998 complete_split = 0;
999 } else if (do_split) {
1000 if (hcint & DWC2_HCINT_ACK) {
1001 ssplit_frame_num = DWC2_HFNUM_MAX_FRNUM &
1002 readl(&host_regs->hfnum);
1003 ret = 0;
1004 complete_split = 1;
1005 }
1006 }
1007
1008 if (ret)
1009 break;
1010
1011 if (actual_len < xfer_len)
1012 stop_transfer = 1;
1013
1014 done += actual_len;
1015
1016 /* Transactions are done when when either all data is transferred or
1017 * there is a short transfer. In case of a SPLIT make sure the CSPLIT
1018 * is executed.
1019 */
1020 } while (((done < len) && !stop_transfer) || complete_split);
1021
1022 writel(0, &hc_regs->hcintmsk);
1023 writel(0xFFFFFFFF, &hc_regs->hcint);
1024
1025 dev->status = 0;
1026 dev->act_len = done;
1027
1028 return ret;
1029 }
1030
1031 /* U-Boot USB transmission interface */
_submit_bulk_msg(struct dwc2_priv * priv,struct usb_device * dev,unsigned long pipe,void * buffer,int len)1032 int _submit_bulk_msg(struct dwc2_priv *priv, struct usb_device *dev,
1033 unsigned long pipe, void *buffer, int len)
1034 {
1035 int devnum = usb_pipedevice(pipe);
1036 int ep = usb_pipeendpoint(pipe);
1037 u8* pid;
1038
1039 if ((devnum >= MAX_DEVICE) || (devnum == priv->root_hub_devnum)) {
1040 dev->status = 0;
1041 return -EINVAL;
1042 }
1043
1044 if (usb_pipein(pipe))
1045 pid = &priv->in_data_toggle[devnum][ep];
1046 else
1047 pid = &priv->out_data_toggle[devnum][ep];
1048
1049 return chunk_msg(priv, dev, pipe, pid, usb_pipein(pipe), buffer, len);
1050 }
1051
_submit_control_msg(struct dwc2_priv * priv,struct usb_device * dev,unsigned long pipe,void * buffer,int len,struct devrequest * setup)1052 static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev,
1053 unsigned long pipe, void *buffer, int len,
1054 struct devrequest *setup)
1055 {
1056 int devnum = usb_pipedevice(pipe);
1057 int ret, act_len;
1058 u8 pid;
1059 /* For CONTROL endpoint pid should start with DATA1 */
1060 int status_direction;
1061
1062 if (devnum == priv->root_hub_devnum) {
1063 dev->status = 0;
1064 dev->speed = USB_SPEED_HIGH;
1065 return dwc_otg_submit_rh_msg(priv, dev, pipe, buffer, len,
1066 setup);
1067 }
1068
1069 /* SETUP stage */
1070 pid = DWC2_HC_PID_SETUP;
1071 do {
1072 ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8);
1073 } while (ret == -EAGAIN);
1074 if (ret)
1075 return ret;
1076
1077 /* DATA stage */
1078 act_len = 0;
1079 if (buffer) {
1080 pid = DWC2_HC_PID_DATA1;
1081 do {
1082 ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe),
1083 buffer, len);
1084 act_len += dev->act_len;
1085 buffer += dev->act_len;
1086 len -= dev->act_len;
1087 } while (ret == -EAGAIN);
1088 if (ret)
1089 return ret;
1090 status_direction = usb_pipeout(pipe);
1091 } else {
1092 /* No-data CONTROL always ends with an IN transaction */
1093 status_direction = 1;
1094 }
1095
1096 /* STATUS stage */
1097 pid = DWC2_HC_PID_DATA1;
1098 do {
1099 ret = chunk_msg(priv, dev, pipe, &pid, status_direction,
1100 priv->status_buffer, 0);
1101 } while (ret == -EAGAIN);
1102 if (ret)
1103 return ret;
1104
1105 dev->act_len = act_len;
1106
1107 return 0;
1108 }
1109
_submit_int_msg(struct dwc2_priv * priv,struct usb_device * dev,unsigned long pipe,void * buffer,int len,int interval)1110 int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev,
1111 unsigned long pipe, void *buffer, int len, int interval)
1112 {
1113 unsigned long timeout;
1114 int ret;
1115
1116 /* FIXME: what is interval? */
1117
1118 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
1119 for (;;) {
1120 if (get_timer(0) > timeout) {
1121 dev_err(dev, "Timeout poll on interrupt endpoint\n");
1122 return -ETIMEDOUT;
1123 }
1124 ret = _submit_bulk_msg(priv, dev, pipe, buffer, len);
1125 if (ret != -EAGAIN)
1126 return ret;
1127 }
1128 }
1129
dwc2_reset(struct udevice * dev)1130 static int dwc2_reset(struct udevice *dev)
1131 {
1132 int ret;
1133 struct dwc2_priv *priv = dev_get_priv(dev);
1134
1135 ret = reset_get_bulk(dev, &priv->resets);
1136 if (ret) {
1137 dev_warn(dev, "Can't get reset: %d\n", ret);
1138 /* Return 0 if error due to !CONFIG_DM_RESET and reset
1139 * DT property is not present.
1140 */
1141 if (ret == -ENOENT || ret == -ENOTSUPP)
1142 return 0;
1143 else
1144 return ret;
1145 }
1146
1147 ret = reset_deassert_bulk(&priv->resets);
1148 if (ret) {
1149 reset_release_bulk(&priv->resets);
1150 dev_err(dev, "Failed to reset: %d\n", ret);
1151 return ret;
1152 }
1153
1154 return 0;
1155 }
1156
dwc2_init_common(struct udevice * dev,struct dwc2_priv * priv)1157 static int dwc2_init_common(struct udevice *dev, struct dwc2_priv *priv)
1158 {
1159 struct dwc2_core_regs *regs = priv->regs;
1160 uint32_t snpsid;
1161 int i, j;
1162 int ret;
1163
1164 ret = dwc2_reset(dev);
1165 if (ret)
1166 return ret;
1167
1168 snpsid = readl(®s->gsnpsid);
1169 dev_info(dev, "Core Release: %x.%03x\n",
1170 snpsid >> 12 & 0xf, snpsid & 0xfff);
1171
1172 if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx &&
1173 (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) {
1174 dev_info(dev, "SNPSID invalid (not DWC2 OTG device): %08x\n",
1175 snpsid);
1176 return -ENODEV;
1177 }
1178
1179 #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
1180 priv->ext_vbus = 1;
1181 #else
1182 priv->ext_vbus = 0;
1183 #endif
1184
1185 dwc_otg_core_init(priv);
1186 dwc_otg_core_host_init(dev, regs);
1187
1188 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
1189 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1190 DWC2_HPRT0_PRTOVRCURRCHNG,
1191 DWC2_HPRT0_PRTRST);
1192 mdelay(50);
1193 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
1194 DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG |
1195 DWC2_HPRT0_PRTRST);
1196
1197 for (i = 0; i < MAX_DEVICE; i++) {
1198 for (j = 0; j < MAX_ENDPOINT; j++) {
1199 priv->in_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1200 priv->out_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1201 }
1202 }
1203
1204 /*
1205 * Add a 1 second delay here. This gives the host controller
1206 * a bit time before the comminucation with the USB devices
1207 * is started (the bus is scanned) and fixes the USB detection
1208 * problems with some problematic USB keys.
1209 */
1210 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
1211 mdelay(1000);
1212
1213 return 0;
1214 }
1215
dwc2_uninit_common(struct dwc2_core_regs * regs)1216 static void dwc2_uninit_common(struct dwc2_core_regs *regs)
1217 {
1218 /* Put everything in reset. */
1219 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
1220 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1221 DWC2_HPRT0_PRTOVRCURRCHNG,
1222 DWC2_HPRT0_PRTRST);
1223 }
1224
1225 #if !CONFIG_IS_ENABLED(DM_USB)
submit_control_msg(struct usb_device * dev,unsigned long pipe,void * buffer,int len,struct devrequest * setup)1226 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1227 int len, struct devrequest *setup)
1228 {
1229 return _submit_control_msg(&local, dev, pipe, buffer, len, setup);
1230 }
1231
submit_bulk_msg(struct usb_device * dev,unsigned long pipe,void * buffer,int len)1232 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1233 int len)
1234 {
1235 return _submit_bulk_msg(&local, dev, pipe, buffer, len);
1236 }
1237
submit_int_msg(struct usb_device * dev,unsigned long pipe,void * buffer,int len,int interval)1238 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1239 int len, int interval)
1240 {
1241 return _submit_int_msg(&local, dev, pipe, buffer, len, interval);
1242 }
1243
1244 /* U-Boot USB control interface */
usb_lowlevel_init(int index,enum usb_init_type init,void ** controller)1245 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1246 {
1247 struct dwc2_priv *priv = &local;
1248
1249 memset(priv, '\0', sizeof(*priv));
1250 priv->root_hub_devnum = 0;
1251 priv->regs = (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR;
1252 priv->aligned_buffer = aligned_buffer_addr;
1253 priv->status_buffer = status_buffer_addr;
1254
1255 /* board-dependant init */
1256 if (board_usb_init(index, USB_INIT_HOST))
1257 return -1;
1258
1259 return dwc2_init_common(NULL, priv);
1260 }
1261
usb_lowlevel_stop(int index)1262 int usb_lowlevel_stop(int index)
1263 {
1264 dwc2_uninit_common(local.regs);
1265
1266 return 0;
1267 }
1268 #endif
1269
1270 #if CONFIG_IS_ENABLED(DM_USB)
dwc2_submit_control_msg(struct udevice * dev,struct usb_device * udev,unsigned long pipe,void * buffer,int length,struct devrequest * setup)1271 static int dwc2_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1272 unsigned long pipe, void *buffer, int length,
1273 struct devrequest *setup)
1274 {
1275 struct dwc2_priv *priv = dev_get_priv(dev);
1276
1277 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1278 dev->name, udev, udev->dev->name, udev->portnr);
1279
1280 return _submit_control_msg(priv, udev, pipe, buffer, length, setup);
1281 }
1282
dwc2_submit_bulk_msg(struct udevice * dev,struct usb_device * udev,unsigned long pipe,void * buffer,int length)1283 static int dwc2_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1284 unsigned long pipe, void *buffer, int length)
1285 {
1286 struct dwc2_priv *priv = dev_get_priv(dev);
1287
1288 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1289
1290 return _submit_bulk_msg(priv, udev, pipe, buffer, length);
1291 }
1292
dwc2_submit_int_msg(struct udevice * dev,struct usb_device * udev,unsigned long pipe,void * buffer,int length,int interval)1293 static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1294 unsigned long pipe, void *buffer, int length,
1295 int interval)
1296 {
1297 struct dwc2_priv *priv = dev_get_priv(dev);
1298
1299 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1300
1301 return _submit_int_msg(priv, udev, pipe, buffer, length, interval);
1302 }
1303
dwc2_usb_ofdata_to_platdata(struct udevice * dev)1304 static int dwc2_usb_ofdata_to_platdata(struct udevice *dev)
1305 {
1306 struct dwc2_priv *priv = dev_get_priv(dev);
1307 fdt_addr_t addr;
1308
1309 addr = dev_read_addr(dev);
1310 if (addr == FDT_ADDR_T_NONE)
1311 return -EINVAL;
1312 priv->regs = (struct dwc2_core_regs *)addr;
1313
1314 priv->oc_disable = dev_read_bool(dev, "disable-over-current");
1315 priv->hnp_srp_disable = dev_read_bool(dev, "hnp-srp-disable");
1316
1317 return 0;
1318 }
1319
dwc2_usb_probe(struct udevice * dev)1320 static int dwc2_usb_probe(struct udevice *dev)
1321 {
1322 struct dwc2_priv *priv = dev_get_priv(dev);
1323 struct usb_bus_priv *bus_priv = dev_get_uclass_priv(dev);
1324
1325 bus_priv->desc_before_addr = true;
1326
1327 return dwc2_init_common(dev, priv);
1328 }
1329
dwc2_usb_remove(struct udevice * dev)1330 static int dwc2_usb_remove(struct udevice *dev)
1331 {
1332 struct dwc2_priv *priv = dev_get_priv(dev);
1333 int ret;
1334
1335 ret = dwc_vbus_supply_exit(dev);
1336 if (ret)
1337 return ret;
1338
1339 dwc2_uninit_common(priv->regs);
1340
1341 reset_release_bulk(&priv->resets);
1342
1343 return 0;
1344 }
1345
1346 struct dm_usb_ops dwc2_usb_ops = {
1347 .control = dwc2_submit_control_msg,
1348 .bulk = dwc2_submit_bulk_msg,
1349 .interrupt = dwc2_submit_int_msg,
1350 };
1351
1352 static const struct udevice_id dwc2_usb_ids[] = {
1353 { .compatible = "brcm,bcm2835-usb" },
1354 { .compatible = "brcm,bcm2708-usb" },
1355 { .compatible = "snps,dwc2" },
1356 { }
1357 };
1358
1359 U_BOOT_DRIVER(usb_dwc2) = {
1360 .name = "dwc2_usb",
1361 .id = UCLASS_USB,
1362 .of_match = dwc2_usb_ids,
1363 .ofdata_to_platdata = dwc2_usb_ofdata_to_platdata,
1364 .probe = dwc2_usb_probe,
1365 .remove = dwc2_usb_remove,
1366 .ops = &dwc2_usb_ops,
1367 .priv_auto_alloc_size = sizeof(struct dwc2_priv),
1368 .flags = DM_FLAG_ALLOC_PRIV_DMA,
1369 };
1370 #endif
1371