1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24 #include <nvif/push006c.h>
25
26 #include <nvif/class.h>
27 #include <nvif/cl0002.h>
28 #include <nvif/if0020.h>
29
30 #include "nouveau_drv.h"
31 #include "nouveau_dma.h"
32 #include "nouveau_bo.h"
33 #include "nouveau_chan.h"
34 #include "nouveau_fence.h"
35 #include "nouveau_abi16.h"
36 #include "nouveau_vmm.h"
37 #include "nouveau_svm.h"
38
39 MODULE_PARM_DESC(vram_pushbuf, "Create DMA push buffers in VRAM");
40 int nouveau_vram_pushbuf;
41 module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);
42
43 void
nouveau_channel_kill(struct nouveau_channel * chan)44 nouveau_channel_kill(struct nouveau_channel *chan)
45 {
46 atomic_set(&chan->killed, 1);
47 if (chan->fence)
48 nouveau_fence_context_kill(chan->fence, -ENODEV);
49 }
50
51 static int
nouveau_channel_killed(struct nvif_event * event,void * repv,u32 repc)52 nouveau_channel_killed(struct nvif_event *event, void *repv, u32 repc)
53 {
54 struct nouveau_channel *chan = container_of(event, typeof(*chan), kill);
55 struct nouveau_cli *cli = chan->cli;
56
57 NV_PRINTK(warn, cli, "channel %d killed!\n", chan->chid);
58
59 if (unlikely(!atomic_read(&chan->killed)))
60 nouveau_channel_kill(chan);
61
62 return NVIF_EVENT_DROP;
63 }
64
65 int
nouveau_channel_idle(struct nouveau_channel * chan)66 nouveau_channel_idle(struct nouveau_channel *chan)
67 {
68 if (likely(chan && chan->fence && !atomic_read(&chan->killed))) {
69 struct nouveau_cli *cli = chan->cli;
70 struct nouveau_fence *fence = NULL;
71 int ret;
72
73 ret = nouveau_fence_new(&fence, chan);
74 if (!ret) {
75 ret = nouveau_fence_wait(fence, false, false);
76 nouveau_fence_unref(&fence);
77 }
78
79 if (ret) {
80 NV_PRINTK(err, cli, "failed to idle channel %d [%s]\n",
81 chan->chid, nvxx_client(&cli->base)->name);
82 return ret;
83 }
84 }
85 return 0;
86 }
87
88 void
nouveau_channel_del(struct nouveau_channel ** pchan)89 nouveau_channel_del(struct nouveau_channel **pchan)
90 {
91 struct nouveau_channel *chan = *pchan;
92 if (chan) {
93 struct nouveau_cli *cli = (void *)chan->user.client;
94
95 if (chan->fence)
96 nouveau_fence(chan->drm)->context_del(chan);
97
98 if (cli)
99 nouveau_svmm_part(chan->vmm->svmm, chan->inst);
100
101 nvif_object_dtor(&chan->blit);
102 nvif_object_dtor(&chan->nvsw);
103 nvif_object_dtor(&chan->gart);
104 nvif_object_dtor(&chan->vram);
105 nvif_event_dtor(&chan->kill);
106 nvif_object_dtor(&chan->user);
107 nvif_mem_dtor(&chan->mem_userd);
108 nvif_object_dtor(&chan->push.ctxdma);
109 nouveau_vma_del(&chan->push.vma);
110 nouveau_bo_unmap(chan->push.buffer);
111 if (chan->push.buffer && chan->push.buffer->bo.pin_count)
112 nouveau_bo_unpin(chan->push.buffer);
113 nouveau_bo_ref(NULL, &chan->push.buffer);
114 kfree(chan);
115 }
116 *pchan = NULL;
117 }
118
119 static void
nouveau_channel_kick(struct nvif_push * push)120 nouveau_channel_kick(struct nvif_push *push)
121 {
122 struct nouveau_channel *chan = container_of(push, typeof(*chan), chan._push);
123 chan->dma.cur = chan->dma.cur + (chan->chan._push.cur - chan->chan._push.bgn);
124 FIRE_RING(chan);
125 chan->chan._push.bgn = chan->chan._push.cur;
126 }
127
128 static int
nouveau_channel_wait(struct nvif_push * push,u32 size)129 nouveau_channel_wait(struct nvif_push *push, u32 size)
130 {
131 struct nouveau_channel *chan = container_of(push, typeof(*chan), chan._push);
132 int ret;
133 chan->dma.cur = chan->dma.cur + (chan->chan._push.cur - chan->chan._push.bgn);
134 ret = RING_SPACE(chan, size);
135 if (ret == 0) {
136 chan->chan._push.bgn = chan->chan._push.mem.object.map.ptr;
137 chan->chan._push.bgn = chan->chan._push.bgn + chan->dma.cur;
138 chan->chan._push.cur = chan->chan._push.bgn;
139 chan->chan._push.end = chan->chan._push.bgn + size;
140 }
141 return ret;
142 }
143
144 static int
nouveau_channel_prep(struct nouveau_cli * cli,u32 size,struct nouveau_channel ** pchan)145 nouveau_channel_prep(struct nouveau_cli *cli,
146 u32 size, struct nouveau_channel **pchan)
147 {
148 struct nouveau_drm *drm = cli->drm;
149 struct nvif_device *device = &cli->device;
150 struct nv_dma_v0 args = {};
151 struct nouveau_channel *chan;
152 u32 target;
153 int ret;
154
155 chan = *pchan = kzalloc(sizeof(*chan), GFP_KERNEL);
156 if (!chan)
157 return -ENOMEM;
158
159 chan->cli = cli;
160 chan->device = device;
161 chan->drm = drm;
162 chan->vmm = nouveau_cli_vmm(cli);
163 atomic_set(&chan->killed, 0);
164
165 /* allocate memory for dma push buffer */
166 target = NOUVEAU_GEM_DOMAIN_GART | NOUVEAU_GEM_DOMAIN_COHERENT;
167 if (nouveau_vram_pushbuf)
168 target = NOUVEAU_GEM_DOMAIN_VRAM;
169
170 ret = nouveau_bo_new(cli, size, 0, target, 0, 0, NULL, NULL,
171 &chan->push.buffer);
172 if (ret == 0) {
173 ret = nouveau_bo_pin(chan->push.buffer, target, false);
174 if (ret == 0)
175 ret = nouveau_bo_map(chan->push.buffer);
176 }
177
178 if (ret) {
179 nouveau_channel_del(pchan);
180 return ret;
181 }
182
183 chan->chan._push.mem.object.parent = cli->base.object.parent;
184 chan->chan._push.mem.object.client = &cli->base;
185 chan->chan._push.mem.object.name = "chanPush";
186 chan->chan._push.mem.object.map.ptr = chan->push.buffer->kmap.virtual;
187 chan->chan._push.wait = nouveau_channel_wait;
188 chan->chan._push.kick = nouveau_channel_kick;
189 chan->chan.push = &chan->chan._push;
190
191 /* create dma object covering the *entire* memory space that the
192 * pushbuf lives in, this is because the GEM code requires that
193 * we be able to call out to other (indirect) push buffers
194 */
195 chan->push.addr = chan->push.buffer->offset;
196
197 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
198 ret = nouveau_vma_new(chan->push.buffer, chan->vmm,
199 &chan->push.vma);
200 if (ret) {
201 nouveau_channel_del(pchan);
202 return ret;
203 }
204
205 chan->push.addr = chan->push.vma->addr;
206
207 if (device->info.family >= NV_DEVICE_INFO_V0_FERMI)
208 return 0;
209
210 args.target = NV_DMA_V0_TARGET_VM;
211 args.access = NV_DMA_V0_ACCESS_VM;
212 args.start = 0;
213 args.limit = chan->vmm->vmm.limit - 1;
214 } else
215 if (chan->push.buffer->bo.resource->mem_type == TTM_PL_VRAM) {
216 if (device->info.family == NV_DEVICE_INFO_V0_TNT) {
217 /* nv04 vram pushbuf hack, retarget to its location in
218 * the framebuffer bar rather than direct vram access..
219 * nfi why this exists, it came from the -nv ddx.
220 */
221 args.target = NV_DMA_V0_TARGET_PCI;
222 args.access = NV_DMA_V0_ACCESS_RDWR;
223 args.start = nvxx_device(device)->func->
224 resource_addr(nvxx_device(device), 1);
225 args.limit = args.start + device->info.ram_user - 1;
226 } else {
227 args.target = NV_DMA_V0_TARGET_VRAM;
228 args.access = NV_DMA_V0_ACCESS_RDWR;
229 args.start = 0;
230 args.limit = device->info.ram_user - 1;
231 }
232 } else {
233 if (chan->drm->agp.bridge) {
234 args.target = NV_DMA_V0_TARGET_AGP;
235 args.access = NV_DMA_V0_ACCESS_RDWR;
236 args.start = chan->drm->agp.base;
237 args.limit = chan->drm->agp.base +
238 chan->drm->agp.size - 1;
239 } else {
240 args.target = NV_DMA_V0_TARGET_VM;
241 args.access = NV_DMA_V0_ACCESS_RDWR;
242 args.start = 0;
243 args.limit = chan->vmm->vmm.limit - 1;
244 }
245 }
246
247 ret = nvif_object_ctor(&device->object, "abi16PushCtxDma", 0,
248 NV_DMA_FROM_MEMORY, &args, sizeof(args),
249 &chan->push.ctxdma);
250 if (ret) {
251 nouveau_channel_del(pchan);
252 return ret;
253 }
254
255 return 0;
256 }
257
258 static int
nouveau_channel_ctor(struct nouveau_cli * cli,bool priv,u64 runm,struct nouveau_channel ** pchan)259 nouveau_channel_ctor(struct nouveau_cli *cli, bool priv, u64 runm,
260 struct nouveau_channel **pchan)
261 {
262 const struct nvif_mclass hosts[] = {
263 { AMPERE_CHANNEL_GPFIFO_B, 0 },
264 { AMPERE_CHANNEL_GPFIFO_A, 0 },
265 { TURING_CHANNEL_GPFIFO_A, 0 },
266 { VOLTA_CHANNEL_GPFIFO_A, 0 },
267 { PASCAL_CHANNEL_GPFIFO_A, 0 },
268 { MAXWELL_CHANNEL_GPFIFO_A, 0 },
269 { KEPLER_CHANNEL_GPFIFO_B, 0 },
270 { KEPLER_CHANNEL_GPFIFO_A, 0 },
271 { FERMI_CHANNEL_GPFIFO , 0 },
272 { G82_CHANNEL_GPFIFO , 0 },
273 { NV50_CHANNEL_GPFIFO , 0 },
274 { NV40_CHANNEL_DMA , 0 },
275 { NV17_CHANNEL_DMA , 0 },
276 { NV10_CHANNEL_DMA , 0 },
277 { NV03_CHANNEL_DMA , 0 },
278 {}
279 };
280 struct {
281 struct nvif_chan_v0 chan;
282 char name[TASK_COMM_LEN+16];
283 } args;
284 struct nvif_device *device = &cli->device;
285 struct nouveau_channel *chan;
286 const u64 plength = 0x10000;
287 const u64 ioffset = plength;
288 const u64 ilength = 0x02000;
289 char name[TASK_COMM_LEN];
290 int cid, ret;
291 u64 size;
292
293 cid = nvif_mclass(&device->object, hosts);
294 if (cid < 0)
295 return cid;
296
297 if (hosts[cid].oclass < NV50_CHANNEL_GPFIFO)
298 size = plength;
299 else
300 size = ioffset + ilength;
301
302 /* allocate dma push buffer */
303 ret = nouveau_channel_prep(cli, size, &chan);
304 *pchan = chan;
305 if (ret)
306 return ret;
307
308 /* create channel object */
309 args.chan.version = 0;
310 args.chan.namelen = sizeof(args.name);
311 args.chan.runlist = __ffs64(runm);
312 args.chan.runq = 0;
313 args.chan.priv = priv;
314 args.chan.devm = BIT(0);
315 if (hosts[cid].oclass < NV50_CHANNEL_GPFIFO) {
316 args.chan.vmm = 0;
317 args.chan.ctxdma = nvif_handle(&chan->push.ctxdma);
318 args.chan.offset = chan->push.addr;
319 args.chan.length = 0;
320 } else {
321 args.chan.vmm = nvif_handle(&chan->vmm->vmm.object);
322 if (hosts[cid].oclass < FERMI_CHANNEL_GPFIFO)
323 args.chan.ctxdma = nvif_handle(&chan->push.ctxdma);
324 else
325 args.chan.ctxdma = 0;
326 args.chan.offset = ioffset + chan->push.addr;
327 args.chan.length = ilength;
328 }
329 args.chan.huserd = 0;
330 args.chan.ouserd = 0;
331
332 /* allocate userd */
333 if (hosts[cid].oclass >= VOLTA_CHANNEL_GPFIFO_A) {
334 ret = nvif_mem_ctor(&cli->mmu, "abi16ChanUSERD", NVIF_CLASS_MEM_GF100,
335 NVIF_MEM_VRAM | NVIF_MEM_COHERENT | NVIF_MEM_MAPPABLE,
336 0, PAGE_SIZE, NULL, 0, &chan->mem_userd);
337 if (ret)
338 return ret;
339
340 args.chan.huserd = nvif_handle(&chan->mem_userd.object);
341 args.chan.ouserd = 0;
342
343 chan->userd = &chan->mem_userd.object;
344 } else {
345 chan->userd = &chan->user;
346 }
347
348 get_task_comm(name, current);
349 snprintf(args.name, sizeof(args.name), "%s[%d]", name, task_pid_nr(current));
350
351 ret = nvif_object_ctor(&device->object, "abi16ChanUser", 0, hosts[cid].oclass,
352 &args, sizeof(args), &chan->user);
353 if (ret) {
354 nouveau_channel_del(pchan);
355 return ret;
356 }
357
358 chan->runlist = args.chan.runlist;
359 chan->chid = args.chan.chid;
360 chan->inst = args.chan.inst;
361 chan->token = args.chan.token;
362 return 0;
363 }
364
365 static int
nouveau_channel_init(struct nouveau_channel * chan,u32 vram,u32 gart)366 nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart)
367 {
368 struct nvif_device *device = chan->device;
369 struct nouveau_drm *drm = chan->drm;
370 struct nv_dma_v0 args = {};
371 int ret, i;
372
373 ret = nvif_object_map(chan->userd, NULL, 0);
374 if (ret)
375 return ret;
376
377 if (chan->user.oclass >= FERMI_CHANNEL_GPFIFO) {
378 struct {
379 struct nvif_event_v0 base;
380 struct nvif_chan_event_v0 host;
381 } args;
382
383 args.host.version = 0;
384 args.host.type = NVIF_CHAN_EVENT_V0_KILLED;
385
386 ret = nvif_event_ctor(&chan->user, "abi16ChanKilled", chan->chid,
387 nouveau_channel_killed, false,
388 &args.base, sizeof(args), &chan->kill);
389 if (ret == 0)
390 ret = nvif_event_allow(&chan->kill);
391 if (ret) {
392 NV_ERROR(drm, "Failed to request channel kill "
393 "notification: %d\n", ret);
394 return ret;
395 }
396 }
397
398 /* allocate dma objects to cover all allowed vram, and gart */
399 if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
400 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
401 args.target = NV_DMA_V0_TARGET_VM;
402 args.access = NV_DMA_V0_ACCESS_VM;
403 args.start = 0;
404 args.limit = chan->vmm->vmm.limit - 1;
405 } else {
406 args.target = NV_DMA_V0_TARGET_VRAM;
407 args.access = NV_DMA_V0_ACCESS_RDWR;
408 args.start = 0;
409 args.limit = device->info.ram_user - 1;
410 }
411
412 ret = nvif_object_ctor(&chan->user, "abi16ChanVramCtxDma", vram,
413 NV_DMA_IN_MEMORY, &args, sizeof(args),
414 &chan->vram);
415 if (ret)
416 return ret;
417
418 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
419 args.target = NV_DMA_V0_TARGET_VM;
420 args.access = NV_DMA_V0_ACCESS_VM;
421 args.start = 0;
422 args.limit = chan->vmm->vmm.limit - 1;
423 } else
424 if (chan->drm->agp.bridge) {
425 args.target = NV_DMA_V0_TARGET_AGP;
426 args.access = NV_DMA_V0_ACCESS_RDWR;
427 args.start = chan->drm->agp.base;
428 args.limit = chan->drm->agp.base +
429 chan->drm->agp.size - 1;
430 } else {
431 args.target = NV_DMA_V0_TARGET_VM;
432 args.access = NV_DMA_V0_ACCESS_RDWR;
433 args.start = 0;
434 args.limit = chan->vmm->vmm.limit - 1;
435 }
436
437 ret = nvif_object_ctor(&chan->user, "abi16ChanGartCtxDma", gart,
438 NV_DMA_IN_MEMORY, &args, sizeof(args),
439 &chan->gart);
440 if (ret)
441 return ret;
442 }
443
444 /* initialise dma tracking parameters */
445 switch (chan->user.oclass) {
446 case NV03_CHANNEL_DMA:
447 case NV10_CHANNEL_DMA:
448 case NV17_CHANNEL_DMA:
449 case NV40_CHANNEL_DMA:
450 chan->user_put = 0x40;
451 chan->user_get = 0x44;
452 chan->dma.max = (0x10000 / 4) - 2;
453 break;
454 default:
455 chan->user_put = 0x40;
456 chan->user_get = 0x44;
457 chan->user_get_hi = 0x60;
458 chan->dma.ib_base = 0x10000 / 4;
459 chan->dma.ib_max = NV50_DMA_IB_MAX;
460 chan->dma.ib_put = 0;
461 chan->dma.ib_free = chan->dma.ib_max - chan->dma.ib_put;
462 chan->dma.max = chan->dma.ib_base;
463 break;
464 }
465
466 chan->dma.put = 0;
467 chan->dma.cur = chan->dma.put;
468 chan->dma.free = chan->dma.max - chan->dma.cur;
469
470 ret = PUSH_WAIT(chan->chan.push, NOUVEAU_DMA_SKIPS);
471 if (ret)
472 return ret;
473
474 for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
475 PUSH_DATA(chan->chan.push, 0x00000000);
476
477 /* allocate software object class (used for fences on <= nv05) */
478 if (device->info.family < NV_DEVICE_INFO_V0_CELSIUS) {
479 ret = nvif_object_ctor(&chan->user, "abi16NvswFence", 0x006e,
480 NVIF_CLASS_SW_NV04,
481 NULL, 0, &chan->nvsw);
482 if (ret)
483 return ret;
484
485 ret = PUSH_WAIT(chan->chan.push, 2);
486 if (ret)
487 return ret;
488
489 PUSH_NVSQ(chan->chan.push, NV_SW, 0x0000, chan->nvsw.handle);
490 PUSH_KICK(chan->chan.push);
491 }
492
493 /* initialise synchronisation */
494 return nouveau_fence(chan->drm)->context_new(chan);
495 }
496
497 int
nouveau_channel_new(struct nouveau_cli * cli,bool priv,u64 runm,u32 vram,u32 gart,struct nouveau_channel ** pchan)498 nouveau_channel_new(struct nouveau_cli *cli,
499 bool priv, u64 runm, u32 vram, u32 gart, struct nouveau_channel **pchan)
500 {
501 int ret;
502
503 ret = nouveau_channel_ctor(cli, priv, runm, pchan);
504 if (ret) {
505 NV_PRINTK(dbg, cli, "channel create, %d\n", ret);
506 return ret;
507 }
508
509 ret = nouveau_channel_init(*pchan, vram, gart);
510 if (ret) {
511 NV_PRINTK(err, cli, "channel failed to initialise, %d\n", ret);
512 nouveau_channel_del(pchan);
513 return ret;
514 }
515
516 ret = nouveau_svmm_join((*pchan)->vmm->svmm, (*pchan)->inst);
517 if (ret)
518 nouveau_channel_del(pchan);
519
520 return ret;
521 }
522
523 void
nouveau_channels_fini(struct nouveau_drm * drm)524 nouveau_channels_fini(struct nouveau_drm *drm)
525 {
526 kfree(drm->runl);
527 }
528
529 int
nouveau_channels_init(struct nouveau_drm * drm)530 nouveau_channels_init(struct nouveau_drm *drm)
531 {
532 struct {
533 struct nv_device_info_v1 m;
534 struct {
535 struct nv_device_info_v1_data channels;
536 struct nv_device_info_v1_data runlists;
537 } v;
538 } args = {
539 .m.version = 1,
540 .m.count = sizeof(args.v) / sizeof(args.v.channels),
541 .v.channels.mthd = NV_DEVICE_HOST_CHANNELS,
542 .v.runlists.mthd = NV_DEVICE_HOST_RUNLISTS,
543 };
544 struct nvif_object *device = &drm->client.device.object;
545 int ret, i;
546
547 ret = nvif_object_mthd(device, NV_DEVICE_V0_INFO, &args, sizeof(args));
548 if (ret ||
549 args.v.runlists.mthd == NV_DEVICE_INFO_INVALID || !args.v.runlists.data ||
550 args.v.channels.mthd == NV_DEVICE_INFO_INVALID)
551 return -ENODEV;
552
553 drm->chan_nr = drm->chan_total = args.v.channels.data;
554 drm->runl_nr = fls64(args.v.runlists.data);
555 drm->runl = kcalloc(drm->runl_nr, sizeof(*drm->runl), GFP_KERNEL);
556 if (!drm->runl)
557 return -ENOMEM;
558
559 if (drm->chan_nr == 0) {
560 for (i = 0; i < drm->runl_nr; i++) {
561 if (!(args.v.runlists.data & BIT(i)))
562 continue;
563
564 args.v.channels.mthd = NV_DEVICE_HOST_RUNLIST_CHANNELS;
565 args.v.channels.data = i;
566
567 ret = nvif_object_mthd(device, NV_DEVICE_V0_INFO, &args, sizeof(args));
568 if (ret || args.v.channels.mthd == NV_DEVICE_INFO_INVALID)
569 return -ENODEV;
570
571 drm->runl[i].chan_nr = args.v.channels.data;
572 drm->runl[i].chan_id_base = drm->chan_total;
573 drm->runl[i].context_base = dma_fence_context_alloc(drm->runl[i].chan_nr);
574
575 drm->chan_total += drm->runl[i].chan_nr;
576 }
577 } else {
578 drm->runl[0].context_base = dma_fence_context_alloc(drm->chan_nr);
579 for (i = 1; i < drm->runl_nr; i++)
580 drm->runl[i].context_base = drm->runl[0].context_base;
581
582 }
583
584 return 0;
585 }
586