1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright 2008-2016 Freescale Semiconductor, Inc.
4 * Copyright 2017-2018 NXP Semiconductor
5 */
6
7 #include <common.h>
8 #include <fsl_ddr_sdram.h>
9
10 #include <fsl_ddr.h>
11
12 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
13 static unsigned int
compute_cas_latency(const unsigned int ctrl_num,const dimm_params_t * dimm_params,common_timing_params_t * outpdimm,unsigned int number_of_dimms)14 compute_cas_latency(const unsigned int ctrl_num,
15 const dimm_params_t *dimm_params,
16 common_timing_params_t *outpdimm,
17 unsigned int number_of_dimms)
18 {
19 unsigned int i;
20 unsigned int common_caslat;
21 unsigned int caslat_actual;
22 unsigned int retry = 16;
23 unsigned int tmp = ~0;
24 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
25 #ifdef CONFIG_SYS_FSL_DDR3
26 const unsigned int taamax = 20000;
27 #else
28 const unsigned int taamax = 18000;
29 #endif
30
31 /* compute the common CAS latency supported between slots */
32 for (i = 0; i < number_of_dimms; i++) {
33 if (dimm_params[i].n_ranks)
34 tmp &= dimm_params[i].caslat_x;
35 }
36 common_caslat = tmp;
37
38 /* validate if the memory clk is in the range of dimms */
39 if (mclk_ps < outpdimm->tckmin_x_ps) {
40 printf("DDR clock (MCLK cycle %u ps) is faster than "
41 "the slowest DIMM(s) (tCKmin %u ps) can support.\n",
42 mclk_ps, outpdimm->tckmin_x_ps);
43 }
44 #ifdef CONFIG_SYS_FSL_DDR4
45 if (mclk_ps > outpdimm->tckmax_ps) {
46 printf("DDR clock (MCLK cycle %u ps) is slower than DIMM(s) (tCKmax %u ps) can support.\n",
47 mclk_ps, outpdimm->tckmax_ps);
48 }
49 #endif
50 /* determine the acutal cas latency */
51 caslat_actual = (outpdimm->taamin_ps + mclk_ps - 1) / mclk_ps;
52 /* check if the dimms support the CAS latency */
53 while (!(common_caslat & (1 << caslat_actual)) && retry > 0) {
54 caslat_actual++;
55 retry--;
56 }
57 /* once the caculation of caslat_actual is completed
58 * we must verify that this CAS latency value does not
59 * exceed tAAmax, which is 20 ns for all DDR3 speed grades,
60 * 18ns for all DDR4 speed grades.
61 */
62 if (caslat_actual * mclk_ps > taamax) {
63 printf("The chosen cas latency %d is too large\n",
64 caslat_actual);
65 }
66 outpdimm->lowest_common_spd_caslat = caslat_actual;
67 debug("lowest_common_spd_caslat is 0x%x\n", caslat_actual);
68
69 return 0;
70 }
71 #else /* for DDR1 and DDR2 */
72 static unsigned int
compute_cas_latency(const unsigned int ctrl_num,const dimm_params_t * dimm_params,common_timing_params_t * outpdimm,unsigned int number_of_dimms)73 compute_cas_latency(const unsigned int ctrl_num,
74 const dimm_params_t *dimm_params,
75 common_timing_params_t *outpdimm,
76 unsigned int number_of_dimms)
77 {
78 int i;
79 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
80 unsigned int lowest_good_caslat;
81 unsigned int not_ok;
82 unsigned int temp1, temp2;
83
84 debug("using mclk_ps = %u\n", mclk_ps);
85 if (mclk_ps > outpdimm->tckmax_ps) {
86 printf("Warning: DDR clock (%u ps) is slower than DIMM(s) (tCKmax %u ps)\n",
87 mclk_ps, outpdimm->tckmax_ps);
88 }
89
90 /*
91 * Compute a CAS latency suitable for all DIMMs
92 *
93 * Strategy for SPD-defined latencies: compute only
94 * CAS latency defined by all DIMMs.
95 */
96
97 /*
98 * Step 1: find CAS latency common to all DIMMs using bitwise
99 * operation.
100 */
101 temp1 = 0xFF;
102 for (i = 0; i < number_of_dimms; i++) {
103 if (dimm_params[i].n_ranks) {
104 temp2 = 0;
105 temp2 |= 1 << dimm_params[i].caslat_x;
106 temp2 |= 1 << dimm_params[i].caslat_x_minus_1;
107 temp2 |= 1 << dimm_params[i].caslat_x_minus_2;
108 /*
109 * If there was no entry for X-2 (X-1) in
110 * the SPD, then caslat_x_minus_2
111 * (caslat_x_minus_1) contains either 255 or
112 * 0xFFFFFFFF because that's what the glorious
113 * __ilog2 function returns for an input of 0.
114 * On 32-bit PowerPC, left shift counts with bit
115 * 26 set (that the value of 255 or 0xFFFFFFFF
116 * will have), cause the destination register to
117 * be 0. That is why this works.
118 */
119 temp1 &= temp2;
120 }
121 }
122
123 /*
124 * Step 2: check each common CAS latency against tCK of each
125 * DIMM's SPD.
126 */
127 lowest_good_caslat = 0;
128 temp2 = 0;
129 while (temp1) {
130 not_ok = 0;
131 temp2 = __ilog2(temp1);
132 debug("checking common caslat = %u\n", temp2);
133
134 /* Check if this CAS latency will work on all DIMMs at tCK. */
135 for (i = 0; i < number_of_dimms; i++) {
136 if (!dimm_params[i].n_ranks)
137 continue;
138
139 if (dimm_params[i].caslat_x == temp2) {
140 if (mclk_ps >= dimm_params[i].tckmin_x_ps) {
141 debug("CL = %u ok on DIMM %u at tCK=%u ps with tCKmin_X_ps of %u\n",
142 temp2, i, mclk_ps,
143 dimm_params[i].tckmin_x_ps);
144 continue;
145 } else {
146 not_ok++;
147 }
148 }
149
150 if (dimm_params[i].caslat_x_minus_1 == temp2) {
151 unsigned int tckmin_x_minus_1_ps
152 = dimm_params[i].tckmin_x_minus_1_ps;
153 if (mclk_ps >= tckmin_x_minus_1_ps) {
154 debug("CL = %u ok on DIMM %u at tCK=%u ps with tckmin_x_minus_1_ps of %u\n",
155 temp2, i, mclk_ps,
156 tckmin_x_minus_1_ps);
157 continue;
158 } else {
159 not_ok++;
160 }
161 }
162
163 if (dimm_params[i].caslat_x_minus_2 == temp2) {
164 unsigned int tckmin_x_minus_2_ps
165 = dimm_params[i].tckmin_x_minus_2_ps;
166 if (mclk_ps >= tckmin_x_minus_2_ps) {
167 debug("CL = %u ok on DIMM %u at tCK=%u ps with tckmin_x_minus_2_ps of %u\n",
168 temp2, i, mclk_ps,
169 tckmin_x_minus_2_ps);
170 continue;
171 } else {
172 not_ok++;
173 }
174 }
175 }
176
177 if (!not_ok)
178 lowest_good_caslat = temp2;
179
180 temp1 &= ~(1 << temp2);
181 }
182
183 debug("lowest common SPD-defined CAS latency = %u\n",
184 lowest_good_caslat);
185 outpdimm->lowest_common_spd_caslat = lowest_good_caslat;
186
187
188 /*
189 * Compute a common 'de-rated' CAS latency.
190 *
191 * The strategy here is to find the *highest* dereated cas latency
192 * with the assumption that all of the DIMMs will support a dereated
193 * CAS latency higher than or equal to their lowest dereated value.
194 */
195 temp1 = 0;
196 for (i = 0; i < number_of_dimms; i++)
197 temp1 = max(temp1, dimm_params[i].caslat_lowest_derated);
198
199 outpdimm->highest_common_derated_caslat = temp1;
200 debug("highest common dereated CAS latency = %u\n", temp1);
201
202 return 0;
203 }
204 #endif
205
206 /*
207 * compute_lowest_common_dimm_parameters()
208 *
209 * Determine the worst-case DIMM timing parameters from the set of DIMMs
210 * whose parameters have been computed into the array pointed to
211 * by dimm_params.
212 */
213 unsigned int
compute_lowest_common_dimm_parameters(const unsigned int ctrl_num,const dimm_params_t * dimm_params,common_timing_params_t * outpdimm,const unsigned int number_of_dimms)214 compute_lowest_common_dimm_parameters(const unsigned int ctrl_num,
215 const dimm_params_t *dimm_params,
216 common_timing_params_t *outpdimm,
217 const unsigned int number_of_dimms)
218 {
219 unsigned int i, j;
220
221 unsigned int tckmin_x_ps = 0;
222 unsigned int tckmax_ps = 0xFFFFFFFF;
223 unsigned int trcd_ps = 0;
224 unsigned int trp_ps = 0;
225 unsigned int tras_ps = 0;
226 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
227 unsigned int taamin_ps = 0;
228 #endif
229 #ifdef CONFIG_SYS_FSL_DDR4
230 unsigned int twr_ps = 15000;
231 unsigned int trfc1_ps = 0;
232 unsigned int trfc2_ps = 0;
233 unsigned int trfc4_ps = 0;
234 unsigned int trrds_ps = 0;
235 unsigned int trrdl_ps = 0;
236 unsigned int tccdl_ps = 0;
237 unsigned int trfc_slr_ps = 0;
238 #else
239 unsigned int twr_ps = 0;
240 unsigned int twtr_ps = 0;
241 unsigned int trfc_ps = 0;
242 unsigned int trrd_ps = 0;
243 unsigned int trtp_ps = 0;
244 #endif
245 unsigned int trc_ps = 0;
246 unsigned int refresh_rate_ps = 0;
247 unsigned int extended_op_srt = 1;
248 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
249 unsigned int tis_ps = 0;
250 unsigned int tih_ps = 0;
251 unsigned int tds_ps = 0;
252 unsigned int tdh_ps = 0;
253 unsigned int tdqsq_max_ps = 0;
254 unsigned int tqhs_ps = 0;
255 #endif
256 unsigned int temp1, temp2;
257 unsigned int additive_latency = 0;
258
259 temp1 = 0;
260 for (i = 0; i < number_of_dimms; i++) {
261 /*
262 * If there are no ranks on this DIMM,
263 * it probably doesn't exist, so skip it.
264 */
265 if (dimm_params[i].n_ranks == 0) {
266 temp1++;
267 continue;
268 }
269 if (dimm_params[i].n_ranks == 4 && i != 0) {
270 printf("Found Quad-rank DIMM in wrong bank, ignored."
271 " Software may not run as expected.\n");
272 temp1++;
273 continue;
274 }
275
276 /*
277 * check if quad-rank DIMM is plugged if
278 * CONFIG_CHIP_SELECT_QUAD_CAPABLE is not defined
279 * Only the board with proper design is capable
280 */
281 #ifndef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
282 if (dimm_params[i].n_ranks == 4 && \
283 CONFIG_CHIP_SELECTS_PER_CTRL/CONFIG_DIMM_SLOTS_PER_CTLR < 4) {
284 printf("Found Quad-rank DIMM, not able to support.");
285 temp1++;
286 continue;
287 }
288 #endif
289 /*
290 * Find minimum tckmax_ps to find fastest slow speed,
291 * i.e., this is the slowest the whole system can go.
292 */
293 tckmax_ps = min(tckmax_ps,
294 (unsigned int)dimm_params[i].tckmax_ps);
295 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
296 taamin_ps = max(taamin_ps,
297 (unsigned int)dimm_params[i].taa_ps);
298 #endif
299 tckmin_x_ps = max(tckmin_x_ps,
300 (unsigned int)dimm_params[i].tckmin_x_ps);
301 trcd_ps = max(trcd_ps, (unsigned int)dimm_params[i].trcd_ps);
302 trp_ps = max(trp_ps, (unsigned int)dimm_params[i].trp_ps);
303 tras_ps = max(tras_ps, (unsigned int)dimm_params[i].tras_ps);
304 #ifdef CONFIG_SYS_FSL_DDR4
305 trfc1_ps = max(trfc1_ps,
306 (unsigned int)dimm_params[i].trfc1_ps);
307 trfc2_ps = max(trfc2_ps,
308 (unsigned int)dimm_params[i].trfc2_ps);
309 trfc4_ps = max(trfc4_ps,
310 (unsigned int)dimm_params[i].trfc4_ps);
311 trrds_ps = max(trrds_ps,
312 (unsigned int)dimm_params[i].trrds_ps);
313 trrdl_ps = max(trrdl_ps,
314 (unsigned int)dimm_params[i].trrdl_ps);
315 tccdl_ps = max(tccdl_ps,
316 (unsigned int)dimm_params[i].tccdl_ps);
317 trfc_slr_ps = max(trfc_slr_ps,
318 (unsigned int)dimm_params[i].trfc_slr_ps);
319 #else
320 twr_ps = max(twr_ps, (unsigned int)dimm_params[i].twr_ps);
321 twtr_ps = max(twtr_ps, (unsigned int)dimm_params[i].twtr_ps);
322 trfc_ps = max(trfc_ps, (unsigned int)dimm_params[i].trfc_ps);
323 trrd_ps = max(trrd_ps, (unsigned int)dimm_params[i].trrd_ps);
324 trtp_ps = max(trtp_ps, (unsigned int)dimm_params[i].trtp_ps);
325 #endif
326 trc_ps = max(trc_ps, (unsigned int)dimm_params[i].trc_ps);
327 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
328 tis_ps = max(tis_ps, (unsigned int)dimm_params[i].tis_ps);
329 tih_ps = max(tih_ps, (unsigned int)dimm_params[i].tih_ps);
330 tds_ps = max(tds_ps, (unsigned int)dimm_params[i].tds_ps);
331 tdh_ps = max(tdh_ps, (unsigned int)dimm_params[i].tdh_ps);
332 tqhs_ps = max(tqhs_ps, (unsigned int)dimm_params[i].tqhs_ps);
333 /*
334 * Find maximum tdqsq_max_ps to find slowest.
335 *
336 * FIXME: is finding the slowest value the correct
337 * strategy for this parameter?
338 */
339 tdqsq_max_ps = max(tdqsq_max_ps,
340 (unsigned int)dimm_params[i].tdqsq_max_ps);
341 #endif
342 refresh_rate_ps = max(refresh_rate_ps,
343 (unsigned int)dimm_params[i].refresh_rate_ps);
344 /* extended_op_srt is either 0 or 1, 0 having priority */
345 extended_op_srt = min(extended_op_srt,
346 (unsigned int)dimm_params[i].extended_op_srt);
347 }
348
349 outpdimm->ndimms_present = number_of_dimms - temp1;
350
351 if (temp1 == number_of_dimms) {
352 debug("no dimms this memory controller\n");
353 return 0;
354 }
355
356 outpdimm->tckmin_x_ps = tckmin_x_ps;
357 outpdimm->tckmax_ps = tckmax_ps;
358 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
359 outpdimm->taamin_ps = taamin_ps;
360 #endif
361 outpdimm->trcd_ps = trcd_ps;
362 outpdimm->trp_ps = trp_ps;
363 outpdimm->tras_ps = tras_ps;
364 #ifdef CONFIG_SYS_FSL_DDR4
365 outpdimm->trfc1_ps = trfc1_ps;
366 outpdimm->trfc2_ps = trfc2_ps;
367 outpdimm->trfc4_ps = trfc4_ps;
368 outpdimm->trrds_ps = trrds_ps;
369 outpdimm->trrdl_ps = trrdl_ps;
370 outpdimm->tccdl_ps = tccdl_ps;
371 outpdimm->trfc_slr_ps = trfc_slr_ps;
372 #else
373 outpdimm->twtr_ps = twtr_ps;
374 outpdimm->trfc_ps = trfc_ps;
375 outpdimm->trrd_ps = trrd_ps;
376 outpdimm->trtp_ps = trtp_ps;
377 #endif
378 outpdimm->twr_ps = twr_ps;
379 outpdimm->trc_ps = trc_ps;
380 outpdimm->refresh_rate_ps = refresh_rate_ps;
381 outpdimm->extended_op_srt = extended_op_srt;
382 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
383 outpdimm->tis_ps = tis_ps;
384 outpdimm->tih_ps = tih_ps;
385 outpdimm->tds_ps = tds_ps;
386 outpdimm->tdh_ps = tdh_ps;
387 outpdimm->tdqsq_max_ps = tdqsq_max_ps;
388 outpdimm->tqhs_ps = tqhs_ps;
389 #endif
390
391 /* Determine common burst length for all DIMMs. */
392 temp1 = 0xff;
393 for (i = 0; i < number_of_dimms; i++) {
394 if (dimm_params[i].n_ranks) {
395 temp1 &= dimm_params[i].burst_lengths_bitmask;
396 }
397 }
398 outpdimm->all_dimms_burst_lengths_bitmask = temp1;
399
400 /* Determine if all DIMMs registered buffered. */
401 temp1 = temp2 = 0;
402 for (i = 0; i < number_of_dimms; i++) {
403 if (dimm_params[i].n_ranks) {
404 if (dimm_params[i].registered_dimm) {
405 temp1 = 1;
406 #ifndef CONFIG_SPL_BUILD
407 printf("Detected RDIMM %s\n",
408 dimm_params[i].mpart);
409 #endif
410 } else {
411 temp2 = 1;
412 #ifndef CONFIG_SPL_BUILD
413 printf("Detected UDIMM %s\n",
414 dimm_params[i].mpart);
415 #endif
416 }
417 }
418 }
419
420 outpdimm->all_dimms_registered = 0;
421 outpdimm->all_dimms_unbuffered = 0;
422 if (temp1 && !temp2) {
423 outpdimm->all_dimms_registered = 1;
424 } else if (!temp1 && temp2) {
425 outpdimm->all_dimms_unbuffered = 1;
426 } else {
427 printf("ERROR: Mix of registered buffered and unbuffered "
428 "DIMMs detected!\n");
429 }
430
431 temp1 = 0;
432 if (outpdimm->all_dimms_registered)
433 for (j = 0; j < 16; j++) {
434 outpdimm->rcw[j] = dimm_params[0].rcw[j];
435 for (i = 1; i < number_of_dimms; i++) {
436 if (!dimm_params[i].n_ranks)
437 continue;
438 if (dimm_params[i].rcw[j] != dimm_params[0].rcw[j]) {
439 temp1 = 1;
440 break;
441 }
442 }
443 }
444
445 if (temp1 != 0)
446 printf("ERROR: Mix different RDIMM detected!\n");
447
448 /* calculate cas latency for all DDR types */
449 if (compute_cas_latency(ctrl_num, dimm_params,
450 outpdimm, number_of_dimms))
451 return 1;
452
453 /* Determine if all DIMMs ECC capable. */
454 temp1 = 1;
455 for (i = 0; i < number_of_dimms; i++) {
456 if (dimm_params[i].n_ranks &&
457 !(dimm_params[i].edc_config & EDC_ECC)) {
458 temp1 = 0;
459 break;
460 }
461 }
462 if (temp1) {
463 debug("all DIMMs ECC capable\n");
464 } else {
465 debug("Warning: not all DIMMs ECC capable, cant enable ECC\n");
466 }
467 outpdimm->all_dimms_ecc_capable = temp1;
468
469 /*
470 * Compute additive latency.
471 *
472 * For DDR1, additive latency should be 0.
473 *
474 * For DDR2, with ODT enabled, use "a value" less than ACTTORW,
475 * which comes from Trcd, and also note that:
476 * add_lat + caslat must be >= 4
477 *
478 * For DDR3, we use the AL=0
479 *
480 * When to use additive latency for DDR2:
481 *
482 * I. Because you are using CL=3 and need to do ODT on writes and
483 * want functionality.
484 * 1. Are you going to use ODT? (Does your board not have
485 * additional termination circuitry for DQ, DQS, DQS_,
486 * DM, RDQS, RDQS_ for x4/x8 configs?)
487 * 2. If so, is your lowest supported CL going to be 3?
488 * 3. If so, then you must set AL=1 because
489 *
490 * WL >= 3 for ODT on writes
491 * RL = AL + CL
492 * WL = RL - 1
493 * ->
494 * WL = AL + CL - 1
495 * AL + CL - 1 >= 3
496 * AL + CL >= 4
497 * QED
498 *
499 * RL >= 3 for ODT on reads
500 * RL = AL + CL
501 *
502 * Since CL aren't usually less than 2, AL=0 is a minimum,
503 * so the WL-derived AL should be the -- FIXME?
504 *
505 * II. Because you are using auto-precharge globally and want to
506 * use additive latency (posted CAS) to get more bandwidth.
507 * 1. Are you going to use auto-precharge mode globally?
508 *
509 * Use addtivie latency and compute AL to be 1 cycle less than
510 * tRCD, i.e. the READ or WRITE command is in the cycle
511 * immediately following the ACTIVATE command..
512 *
513 * III. Because you feel like it or want to do some sort of
514 * degraded-performance experiment.
515 * 1. Do you just want to use additive latency because you feel
516 * like it?
517 *
518 * Validation: AL is less than tRCD, and within the other
519 * read-to-precharge constraints.
520 */
521
522 additive_latency = 0;
523
524 #if defined(CONFIG_SYS_FSL_DDR2)
525 if ((outpdimm->lowest_common_spd_caslat < 4) &&
526 (picos_to_mclk(ctrl_num, trcd_ps) >
527 outpdimm->lowest_common_spd_caslat)) {
528 additive_latency = picos_to_mclk(ctrl_num, trcd_ps) -
529 outpdimm->lowest_common_spd_caslat;
530 if (mclk_to_picos(ctrl_num, additive_latency) > trcd_ps) {
531 additive_latency = picos_to_mclk(ctrl_num, trcd_ps);
532 debug("setting additive_latency to %u because it was "
533 " greater than tRCD_ps\n", additive_latency);
534 }
535 }
536 #endif
537
538 /*
539 * Validate additive latency
540 *
541 * AL <= tRCD(min)
542 */
543 if (mclk_to_picos(ctrl_num, additive_latency) > trcd_ps) {
544 printf("Error: invalid additive latency exceeds tRCD(min).\n");
545 return 1;
546 }
547
548 /*
549 * RL = CL + AL; RL >= 3 for ODT_RD_CFG to be enabled
550 * WL = RL - 1; WL >= 3 for ODT_WL_CFG to be enabled
551 * ADD_LAT (the register) must be set to a value less
552 * than ACTTORW if WL = 1, then AL must be set to 1
553 * RD_TO_PRE (the register) must be set to a minimum
554 * tRTP + AL if AL is nonzero
555 */
556
557 /*
558 * Additive latency will be applied only if the memctl option to
559 * use it.
560 */
561 outpdimm->additive_latency = additive_latency;
562
563 debug("tCKmin_ps = %u\n", outpdimm->tckmin_x_ps);
564 debug("trcd_ps = %u\n", outpdimm->trcd_ps);
565 debug("trp_ps = %u\n", outpdimm->trp_ps);
566 debug("tras_ps = %u\n", outpdimm->tras_ps);
567 #ifdef CONFIG_SYS_FSL_DDR4
568 debug("trfc1_ps = %u\n", trfc1_ps);
569 debug("trfc2_ps = %u\n", trfc2_ps);
570 debug("trfc4_ps = %u\n", trfc4_ps);
571 debug("trrds_ps = %u\n", trrds_ps);
572 debug("trrdl_ps = %u\n", trrdl_ps);
573 debug("tccdl_ps = %u\n", tccdl_ps);
574 debug("trfc_slr_ps = %u\n", trfc_slr_ps);
575 #else
576 debug("twtr_ps = %u\n", outpdimm->twtr_ps);
577 debug("trfc_ps = %u\n", outpdimm->trfc_ps);
578 debug("trrd_ps = %u\n", outpdimm->trrd_ps);
579 #endif
580 debug("twr_ps = %u\n", outpdimm->twr_ps);
581 debug("trc_ps = %u\n", outpdimm->trc_ps);
582
583 return 0;
584 }
585